2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly enable_vpid
= 1;
53 module_param_named(vpid
, enable_vpid
, bool, 0444);
55 static int __read_mostly flexpriority_enabled
= 1;
56 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
58 static int __read_mostly enable_ept
= 1;
59 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
61 static int __read_mostly enable_unrestricted_guest
= 1;
62 module_param_named(unrestricted_guest
,
63 enable_unrestricted_guest
, bool, S_IRUGO
);
65 static int __read_mostly emulate_invalid_guest_state
= 0;
66 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
68 static int __read_mostly vmm_exclusive
= 1;
69 module_param(vmm_exclusive
, bool, S_IRUGO
);
71 static int __read_mostly yield_on_hlt
= 1;
72 module_param(yield_on_hlt
, bool, S_IRUGO
);
74 static int __read_mostly fasteoi
= 1;
75 module_param(fasteoi
, bool, S_IRUGO
);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested
= 0;
83 module_param(nested
, bool, S_IRUGO
);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
116 module_param(ple_gap
, int, S_IRUGO
);
118 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
119 module_param(ple_window
, int, S_IRUGO
);
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
139 struct list_head loaded_vmcss_on_cpu_link
;
142 struct shared_msr_entry
{
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 typedef u64 natural_width
;
162 struct __packed vmcs12
{
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
169 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding
[7]; /* room for future expansion */
175 u64 vm_exit_msr_store_addr
;
176 u64 vm_exit_msr_load_addr
;
177 u64 vm_entry_msr_load_addr
;
179 u64 virtual_apic_page_addr
;
180 u64 apic_access_addr
;
182 u64 guest_physical_address
;
183 u64 vmcs_link_pointer
;
184 u64 guest_ia32_debugctl
;
187 u64 guest_ia32_perf_global_ctrl
;
194 u64 host_ia32_perf_global_ctrl
;
195 u64 padding64
[8]; /* room for future expansion */
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
202 natural_width cr0_guest_host_mask
;
203 natural_width cr4_guest_host_mask
;
204 natural_width cr0_read_shadow
;
205 natural_width cr4_read_shadow
;
206 natural_width cr3_target_value0
;
207 natural_width cr3_target_value1
;
208 natural_width cr3_target_value2
;
209 natural_width cr3_target_value3
;
210 natural_width exit_qualification
;
211 natural_width guest_linear_address
;
212 natural_width guest_cr0
;
213 natural_width guest_cr3
;
214 natural_width guest_cr4
;
215 natural_width guest_es_base
;
216 natural_width guest_cs_base
;
217 natural_width guest_ss_base
;
218 natural_width guest_ds_base
;
219 natural_width guest_fs_base
;
220 natural_width guest_gs_base
;
221 natural_width guest_ldtr_base
;
222 natural_width guest_tr_base
;
223 natural_width guest_gdtr_base
;
224 natural_width guest_idtr_base
;
225 natural_width guest_dr7
;
226 natural_width guest_rsp
;
227 natural_width guest_rip
;
228 natural_width guest_rflags
;
229 natural_width guest_pending_dbg_exceptions
;
230 natural_width guest_sysenter_esp
;
231 natural_width guest_sysenter_eip
;
232 natural_width host_cr0
;
233 natural_width host_cr3
;
234 natural_width host_cr4
;
235 natural_width host_fs_base
;
236 natural_width host_gs_base
;
237 natural_width host_tr_base
;
238 natural_width host_gdtr_base
;
239 natural_width host_idtr_base
;
240 natural_width host_ia32_sysenter_esp
;
241 natural_width host_ia32_sysenter_eip
;
242 natural_width host_rsp
;
243 natural_width host_rip
;
244 natural_width paddingl
[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control
;
246 u32 cpu_based_vm_exec_control
;
247 u32 exception_bitmap
;
248 u32 page_fault_error_code_mask
;
249 u32 page_fault_error_code_match
;
250 u32 cr3_target_count
;
251 u32 vm_exit_controls
;
252 u32 vm_exit_msr_store_count
;
253 u32 vm_exit_msr_load_count
;
254 u32 vm_entry_controls
;
255 u32 vm_entry_msr_load_count
;
256 u32 vm_entry_intr_info_field
;
257 u32 vm_entry_exception_error_code
;
258 u32 vm_entry_instruction_len
;
260 u32 secondary_vm_exec_control
;
261 u32 vm_instruction_error
;
263 u32 vm_exit_intr_info
;
264 u32 vm_exit_intr_error_code
;
265 u32 idt_vectoring_info_field
;
266 u32 idt_vectoring_error_code
;
267 u32 vm_exit_instruction_len
;
268 u32 vmx_instruction_info
;
275 u32 guest_ldtr_limit
;
277 u32 guest_gdtr_limit
;
278 u32 guest_idtr_limit
;
279 u32 guest_es_ar_bytes
;
280 u32 guest_cs_ar_bytes
;
281 u32 guest_ss_ar_bytes
;
282 u32 guest_ds_ar_bytes
;
283 u32 guest_fs_ar_bytes
;
284 u32 guest_gs_ar_bytes
;
285 u32 guest_ldtr_ar_bytes
;
286 u32 guest_tr_ar_bytes
;
287 u32 guest_interruptibility_info
;
288 u32 guest_activity_state
;
289 u32 guest_sysenter_cs
;
290 u32 host_ia32_sysenter_cs
;
291 u32 padding32
[8]; /* room for future expansion */
292 u16 virtual_processor_id
;
293 u16 guest_es_selector
;
294 u16 guest_cs_selector
;
295 u16 guest_ss_selector
;
296 u16 guest_ds_selector
;
297 u16 guest_fs_selector
;
298 u16 guest_gs_selector
;
299 u16 guest_ldtr_selector
;
300 u16 guest_tr_selector
;
301 u16 host_es_selector
;
302 u16 host_cs_selector
;
303 u16 host_ss_selector
;
304 u16 host_ds_selector
;
305 u16 host_fs_selector
;
306 u16 host_gs_selector
;
307 u16 host_tr_selector
;
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 #define VMCS12_REVISION 0x11e57ed0
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
322 #define VMCS12_SIZE 0x1000
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct list_head list
;
328 struct loaded_vmcs vmcs02
;
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 /* Has the level1 guest done vmxon? */
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 /* The host-usable pointer to the above */
342 struct page
*current_vmcs12_page
;
343 struct vmcs12
*current_vmcs12
;
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool
;
348 u64 vmcs01_tsc_offset
;
349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending
;
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
355 struct page
*apic_access_page
;
359 struct kvm_vcpu vcpu
;
360 unsigned long host_rsp
;
363 bool nmi_known_unmasked
;
365 u32 idt_vectoring_info
;
367 struct shared_msr_entry
*guest_msrs
;
371 u64 msr_host_kernel_gs_base
;
372 u64 msr_guest_kernel_gs_base
;
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
379 struct loaded_vmcs vmcs01
;
380 struct loaded_vmcs
*loaded_vmcs
;
381 bool __launched
; /* temporary, used in vmx_vcpu_run */
382 struct msr_autoload
{
384 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
385 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
389 u16 fs_sel
, gs_sel
, ldt_sel
;
390 int gs_ldt_reload_needed
;
391 int fs_reload_needed
;
396 struct kvm_save_segment
{
401 } tr
, es
, ds
, fs
, gs
;
404 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg
[8];
408 bool emulation_required
;
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked
;
413 s64 vnmi_blocked_time
;
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested
;
422 enum segment_cache_field
{
431 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
433 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
441 static unsigned short vmcs_field_to_offset_table
[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
443 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
444 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
445 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
446 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
447 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
448 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
449 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
450 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
451 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
452 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
453 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
454 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
455 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
456 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
457 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
458 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
459 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
460 FIELD64(MSR_BITMAP
, msr_bitmap
),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
464 FIELD64(TSC_OFFSET
, tsc_offset
),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
466 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
467 FIELD64(EPT_POINTER
, ept_pointer
),
468 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
469 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
470 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
471 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
472 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
474 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
475 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
476 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
477 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
478 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
479 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
483 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
486 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
487 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
488 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
490 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
495 FIELD(TPR_THRESHOLD
, tpr_threshold
),
496 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
497 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
498 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
499 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
500 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
501 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
502 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
503 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
504 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
505 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
506 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
507 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
508 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
509 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
510 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
511 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
512 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
513 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
514 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
515 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
516 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
517 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
518 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
519 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
520 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
521 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
522 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
524 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
525 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
526 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
527 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
528 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
529 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
530 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
531 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
532 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
533 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
534 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
535 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
536 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
537 FIELD(GUEST_CR0
, guest_cr0
),
538 FIELD(GUEST_CR3
, guest_cr3
),
539 FIELD(GUEST_CR4
, guest_cr4
),
540 FIELD(GUEST_ES_BASE
, guest_es_base
),
541 FIELD(GUEST_CS_BASE
, guest_cs_base
),
542 FIELD(GUEST_SS_BASE
, guest_ss_base
),
543 FIELD(GUEST_DS_BASE
, guest_ds_base
),
544 FIELD(GUEST_FS_BASE
, guest_fs_base
),
545 FIELD(GUEST_GS_BASE
, guest_gs_base
),
546 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
547 FIELD(GUEST_TR_BASE
, guest_tr_base
),
548 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
549 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
550 FIELD(GUEST_DR7
, guest_dr7
),
551 FIELD(GUEST_RSP
, guest_rsp
),
552 FIELD(GUEST_RIP
, guest_rip
),
553 FIELD(GUEST_RFLAGS
, guest_rflags
),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
555 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
556 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
557 FIELD(HOST_CR0
, host_cr0
),
558 FIELD(HOST_CR3
, host_cr3
),
559 FIELD(HOST_CR4
, host_cr4
),
560 FIELD(HOST_FS_BASE
, host_fs_base
),
561 FIELD(HOST_GS_BASE
, host_gs_base
),
562 FIELD(HOST_TR_BASE
, host_tr_base
),
563 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
564 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
565 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
566 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
567 FIELD(HOST_RSP
, host_rsp
),
568 FIELD(HOST_RIP
, host_rip
),
570 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
572 static inline short vmcs_field_to_offset(unsigned long field
)
574 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
576 return vmcs_field_to_offset_table
[field
];
579 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
581 return to_vmx(vcpu
)->nested
.current_vmcs12
;
584 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
586 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
587 if (is_error_page(page
)) {
588 kvm_release_page_clean(page
);
594 static void nested_release_page(struct page
*page
)
596 kvm_release_page_dirty(page
);
599 static void nested_release_page_clean(struct page
*page
)
601 kvm_release_page_clean(page
);
604 static u64
construct_eptp(unsigned long root_hpa
);
605 static void kvm_cpu_vmxon(u64 addr
);
606 static void kvm_cpu_vmxoff(void);
607 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
608 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
610 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
611 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
617 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
619 static unsigned long *vmx_io_bitmap_a
;
620 static unsigned long *vmx_io_bitmap_b
;
621 static unsigned long *vmx_msr_bitmap_legacy
;
622 static unsigned long *vmx_msr_bitmap_longmode
;
624 static bool cpu_has_load_ia32_efer
;
626 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
627 static DEFINE_SPINLOCK(vmx_vpid_lock
);
629 static struct vmcs_config
{
633 u32 pin_based_exec_ctrl
;
634 u32 cpu_based_exec_ctrl
;
635 u32 cpu_based_2nd_exec_ctrl
;
640 static struct vmx_capability
{
645 #define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 static struct kvm_vmx_segment_field
{
658 } kvm_vmx_segment_fields
[] = {
659 VMX_SEGMENT_FIELD(CS
),
660 VMX_SEGMENT_FIELD(DS
),
661 VMX_SEGMENT_FIELD(ES
),
662 VMX_SEGMENT_FIELD(FS
),
663 VMX_SEGMENT_FIELD(GS
),
664 VMX_SEGMENT_FIELD(SS
),
665 VMX_SEGMENT_FIELD(TR
),
666 VMX_SEGMENT_FIELD(LDTR
),
669 static u64 host_efer
;
671 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675 * away by decrementing the array size.
677 static const u32 vmx_msr_index
[] = {
679 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
681 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
685 static inline bool is_page_fault(u32 intr_info
)
687 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
688 INTR_INFO_VALID_MASK
)) ==
689 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
692 static inline bool is_no_device(u32 intr_info
)
694 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
695 INTR_INFO_VALID_MASK
)) ==
696 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
699 static inline bool is_invalid_opcode(u32 intr_info
)
701 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
702 INTR_INFO_VALID_MASK
)) ==
703 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
706 static inline bool is_external_interrupt(u32 intr_info
)
708 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
709 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
712 static inline bool is_machine_check(u32 intr_info
)
714 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
715 INTR_INFO_VALID_MASK
)) ==
716 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
719 static inline bool cpu_has_vmx_msr_bitmap(void)
721 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
724 static inline bool cpu_has_vmx_tpr_shadow(void)
726 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
729 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
734 static inline bool cpu_has_secondary_exec_ctrls(void)
736 return vmcs_config
.cpu_based_exec_ctrl
&
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
742 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
746 static inline bool cpu_has_vmx_flexpriority(void)
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
752 static inline bool cpu_has_vmx_ept_execute_only(void)
754 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
759 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
762 static inline bool cpu_has_vmx_eptp_writeback(void)
764 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
767 static inline bool cpu_has_vmx_ept_2m_page(void)
769 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
772 static inline bool cpu_has_vmx_ept_1g_page(void)
774 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
777 static inline bool cpu_has_vmx_ept_4levels(void)
779 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
784 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
787 static inline bool cpu_has_vmx_invept_context(void)
789 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
792 static inline bool cpu_has_vmx_invept_global(void)
794 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
797 static inline bool cpu_has_vmx_invvpid_single(void)
799 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
802 static inline bool cpu_has_vmx_invvpid_global(void)
804 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
807 static inline bool cpu_has_vmx_ept(void)
809 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
810 SECONDARY_EXEC_ENABLE_EPT
;
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
815 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
816 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
819 static inline bool cpu_has_vmx_ple(void)
821 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
827 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
830 static inline bool cpu_has_vmx_vpid(void)
832 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
833 SECONDARY_EXEC_ENABLE_VPID
;
836 static inline bool cpu_has_vmx_rdtscp(void)
838 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
839 SECONDARY_EXEC_RDTSCP
;
842 static inline bool cpu_has_virtual_nmis(void)
844 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
849 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
850 SECONDARY_EXEC_WBINVD_EXITING
;
853 static inline bool report_flexpriority(void)
855 return flexpriority_enabled
;
858 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
860 return vmcs12
->cpu_based_vm_exec_control
& bit
;
863 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
865 return (vmcs12
->cpu_based_vm_exec_control
&
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
867 (vmcs12
->secondary_vm_exec_control
& bit
);
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
871 struct kvm_vcpu
*vcpu
)
873 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
876 static inline bool is_exception(u32 intr_info
)
878 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
879 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
882 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
883 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
884 struct vmcs12
*vmcs12
,
885 u32 reason
, unsigned long qualification
);
887 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
891 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
892 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
897 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
903 } operand
= { vpid
, 0, gva
};
905 asm volatile (__ex(ASM_VMX_INVVPID
)
906 /* CF==1 or ZF==1 --> rc = -1 */
908 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
911 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
915 } operand
= {eptp
, gpa
};
917 asm volatile (__ex(ASM_VMX_INVEPT
)
918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
923 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
927 i
= __find_msr_index(vmx
, msr
);
929 return &vmx
->guest_msrs
[i
];
933 static void vmcs_clear(struct vmcs
*vmcs
)
935 u64 phys_addr
= __pa(vmcs
);
938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
939 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
942 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
946 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
948 vmcs_clear(loaded_vmcs
->vmcs
);
949 loaded_vmcs
->cpu
= -1;
950 loaded_vmcs
->launched
= 0;
953 static void vmcs_load(struct vmcs
*vmcs
)
955 u64 phys_addr
= __pa(vmcs
);
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
959 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
962 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
966 static void __loaded_vmcs_clear(void *arg
)
968 struct loaded_vmcs
*loaded_vmcs
= arg
;
969 int cpu
= raw_smp_processor_id();
971 if (loaded_vmcs
->cpu
!= cpu
)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
974 per_cpu(current_vmcs
, cpu
) = NULL
;
975 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
976 loaded_vmcs_init(loaded_vmcs
);
979 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
981 if (loaded_vmcs
->cpu
!= -1)
982 smp_call_function_single(
983 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
995 static inline void vpid_sync_vcpu_global(void)
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1001 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1003 if (cpu_has_vmx_invvpid_single())
1004 vpid_sync_vcpu_single(vmx
);
1006 vpid_sync_vcpu_global();
1009 static inline void ept_sync_global(void)
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1015 static inline void ept_sync_context(u64 eptp
)
1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1025 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
1032 ept_sync_context(eptp
);
1036 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1038 unsigned long value
;
1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1041 : "=a"(value
) : "d"(field
) : "cc");
1045 static __always_inline u16
vmcs_read16(unsigned long field
)
1047 return vmcs_readl(field
);
1050 static __always_inline u32
vmcs_read32(unsigned long field
)
1052 return vmcs_readl(field
);
1055 static __always_inline u64
vmcs_read64(unsigned long field
)
1057 #ifdef CONFIG_X86_64
1058 return vmcs_readl(field
);
1060 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1064 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1066 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1067 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1071 static void vmcs_writel(unsigned long field
, unsigned long value
)
1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1076 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1077 if (unlikely(error
))
1078 vmwrite_error(field
, value
);
1081 static void vmcs_write16(unsigned long field
, u16 value
)
1083 vmcs_writel(field
, value
);
1086 static void vmcs_write32(unsigned long field
, u32 value
)
1088 vmcs_writel(field
, value
);
1091 static void vmcs_write64(unsigned long field
, u64 value
)
1093 vmcs_writel(field
, value
);
1094 #ifndef CONFIG_X86_64
1096 vmcs_writel(field
+1, value
>> 32);
1100 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1102 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1105 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1107 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1110 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1112 vmx
->segment_cache
.bitmask
= 0;
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1119 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1121 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1122 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1123 vmx
->segment_cache
.bitmask
= 0;
1125 ret
= vmx
->segment_cache
.bitmask
& mask
;
1126 vmx
->segment_cache
.bitmask
|= mask
;
1130 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1132 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1134 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1135 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1139 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1141 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1143 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1144 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1148 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1150 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1152 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1153 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1157 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1159 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1161 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1162 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1166 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1170 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1171 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1172 if ((vcpu
->guest_debug
&
1173 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1174 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1175 eb
|= 1u << BP_VECTOR
;
1176 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1179 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1180 if (vcpu
->fpu_active
)
1181 eb
&= ~(1u << NM_VECTOR
);
1183 /* When we are running a nested L2 guest and L1 specified for it a
1184 * certain exception bitmap, we must trap the same exceptions and pass
1185 * them to L1. When running L2, we will only handle the exceptions
1186 * specified above if L1 did not want them.
1188 if (is_guest_mode(vcpu
))
1189 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1191 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1194 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1197 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1199 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1205 for (i
= 0; i
< m
->nr
; ++i
)
1206 if (m
->guest
[i
].index
== msr
)
1212 m
->guest
[i
] = m
->guest
[m
->nr
];
1213 m
->host
[i
] = m
->host
[m
->nr
];
1214 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1218 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1219 u64 guest_val
, u64 host_val
)
1222 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1224 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1225 vmcs_write64(GUEST_IA32_EFER
, guest_val
);
1226 vmcs_write64(HOST_IA32_EFER
, host_val
);
1227 vmcs_set_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1228 vmcs_set_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1232 for (i
= 0; i
< m
->nr
; ++i
)
1233 if (m
->guest
[i
].index
== msr
)
1238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1239 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1242 m
->guest
[i
].index
= msr
;
1243 m
->guest
[i
].value
= guest_val
;
1244 m
->host
[i
].index
= msr
;
1245 m
->host
[i
].value
= host_val
;
1248 static void reload_tss(void)
1251 * VT restores TR but not its size. Useless.
1253 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1254 struct desc_struct
*descs
;
1256 descs
= (void *)gdt
->address
;
1257 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1261 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1266 guest_efer
= vmx
->vcpu
.arch
.efer
;
1269 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1272 ignore_bits
= EFER_NX
| EFER_SCE
;
1273 #ifdef CONFIG_X86_64
1274 ignore_bits
|= EFER_LMA
| EFER_LME
;
1275 /* SCE is meaningful only in long mode on Intel */
1276 if (guest_efer
& EFER_LMA
)
1277 ignore_bits
&= ~(u64
)EFER_SCE
;
1279 guest_efer
&= ~ignore_bits
;
1280 guest_efer
|= host_efer
& ignore_bits
;
1281 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1282 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1284 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1285 /* On ept, can't emulate nx, and must switch nx atomically */
1286 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1287 guest_efer
= vmx
->vcpu
.arch
.efer
;
1288 if (!(guest_efer
& EFER_LMA
))
1289 guest_efer
&= ~EFER_LME
;
1290 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1297 static unsigned long segment_base(u16 selector
)
1299 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1300 struct desc_struct
*d
;
1301 unsigned long table_base
;
1304 if (!(selector
& ~3))
1307 table_base
= gdt
->address
;
1309 if (selector
& 4) { /* from ldt */
1310 u16 ldt_selector
= kvm_read_ldt();
1312 if (!(ldt_selector
& ~3))
1315 table_base
= segment_base(ldt_selector
);
1317 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1318 v
= get_desc_base(d
);
1319 #ifdef CONFIG_X86_64
1320 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1321 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1326 static inline unsigned long kvm_read_tr_base(void)
1329 asm("str %0" : "=g"(tr
));
1330 return segment_base(tr
);
1333 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1335 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1338 if (vmx
->host_state
.loaded
)
1341 vmx
->host_state
.loaded
= 1;
1343 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1344 * allow segment selectors with cpl > 0 or ti == 1.
1346 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1347 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1348 savesegment(fs
, vmx
->host_state
.fs_sel
);
1349 if (!(vmx
->host_state
.fs_sel
& 7)) {
1350 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1351 vmx
->host_state
.fs_reload_needed
= 0;
1353 vmcs_write16(HOST_FS_SELECTOR
, 0);
1354 vmx
->host_state
.fs_reload_needed
= 1;
1356 savesegment(gs
, vmx
->host_state
.gs_sel
);
1357 if (!(vmx
->host_state
.gs_sel
& 7))
1358 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1360 vmcs_write16(HOST_GS_SELECTOR
, 0);
1361 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1364 #ifdef CONFIG_X86_64
1365 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1366 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1368 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1369 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1372 #ifdef CONFIG_X86_64
1373 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1374 if (is_long_mode(&vmx
->vcpu
))
1375 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1377 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1378 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1379 vmx
->guest_msrs
[i
].data
,
1380 vmx
->guest_msrs
[i
].mask
);
1383 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1385 if (!vmx
->host_state
.loaded
)
1388 ++vmx
->vcpu
.stat
.host_state_reload
;
1389 vmx
->host_state
.loaded
= 0;
1390 #ifdef CONFIG_X86_64
1391 if (is_long_mode(&vmx
->vcpu
))
1392 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1394 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1395 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1396 #ifdef CONFIG_X86_64
1397 load_gs_index(vmx
->host_state
.gs_sel
);
1399 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1402 if (vmx
->host_state
.fs_reload_needed
)
1403 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1405 #ifdef CONFIG_X86_64
1406 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1408 if (current_thread_info()->status
& TS_USEDFPU
)
1410 load_gdt(&__get_cpu_var(host_gdt
));
1413 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1416 __vmx_load_host_state(vmx
);
1421 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422 * vcpu mutex is already taken.
1424 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1426 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1427 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1430 kvm_cpu_vmxon(phys_addr
);
1431 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1432 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1434 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1435 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1436 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1439 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1440 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1441 unsigned long sysenter_esp
;
1443 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1444 local_irq_disable();
1445 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1446 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1450 * Linux uses per-cpu TSS and GDT, so set these when switching
1453 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1454 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1456 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1457 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1458 vmx
->loaded_vmcs
->cpu
= cpu
;
1462 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1464 __vmx_load_host_state(to_vmx(vcpu
));
1465 if (!vmm_exclusive
) {
1466 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1472 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1476 if (vcpu
->fpu_active
)
1478 vcpu
->fpu_active
= 1;
1479 cr0
= vmcs_readl(GUEST_CR0
);
1480 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1481 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1482 vmcs_writel(GUEST_CR0
, cr0
);
1483 update_exception_bitmap(vcpu
);
1484 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1485 if (is_guest_mode(vcpu
))
1486 vcpu
->arch
.cr0_guest_owned_bits
&=
1487 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1488 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1491 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1494 * Return the cr0 value that a nested guest would read. This is a combination
1495 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496 * its hypervisor (cr0_read_shadow).
1498 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1500 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1501 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1503 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1505 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1506 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1509 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1511 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512 * set this *before* calling this function.
1514 vmx_decache_cr0_guest_bits(vcpu
);
1515 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1516 update_exception_bitmap(vcpu
);
1517 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1518 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1519 if (is_guest_mode(vcpu
)) {
1521 * L1's specified read shadow might not contain the TS bit,
1522 * so now that we turned on shadowing of this bit, we need to
1523 * set this bit of the shadow. Like in nested_vmx_run we need
1524 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525 * up-to-date here because we just decached cr0.TS (and we'll
1526 * only update vmcs12->guest_cr0 on nested exit).
1528 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1529 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1530 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1531 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1533 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1536 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1538 unsigned long rflags
, save_rflags
;
1540 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1541 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1542 rflags
= vmcs_readl(GUEST_RFLAGS
);
1543 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1544 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1545 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1546 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1548 to_vmx(vcpu
)->rflags
= rflags
;
1550 return to_vmx(vcpu
)->rflags
;
1553 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1555 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1556 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1557 to_vmx(vcpu
)->rflags
= rflags
;
1558 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1559 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1560 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1562 vmcs_writel(GUEST_RFLAGS
, rflags
);
1565 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1567 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1570 if (interruptibility
& GUEST_INTR_STATE_STI
)
1571 ret
|= KVM_X86_SHADOW_INT_STI
;
1572 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1573 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1578 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1580 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1581 u32 interruptibility
= interruptibility_old
;
1583 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1585 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1586 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1587 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1588 interruptibility
|= GUEST_INTR_STATE_STI
;
1590 if ((interruptibility
!= interruptibility_old
))
1591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1594 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1598 rip
= kvm_rip_read(vcpu
);
1599 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1600 kvm_rip_write(vcpu
, rip
);
1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu
, 0);
1606 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1608 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1609 * explicitly skip the instruction because if the HLT state is set, then
1610 * the instruction is already executing and RIP has already been
1612 if (!yield_on_hlt
&&
1613 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1614 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1618 * KVM wants to inject page-faults which it got to the guest. This function
1619 * checks whether in a nested guest, we need to inject them to L1 or L2.
1620 * This function assumes it is called with the exit reason in vmcs02 being
1621 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1624 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1626 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1628 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629 if (!(vmcs12
->exception_bitmap
& PF_VECTOR
))
1632 nested_vmx_vmexit(vcpu
);
1636 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1637 bool has_error_code
, u32 error_code
,
1640 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1641 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1643 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1644 nested_pf_handled(vcpu
))
1647 if (has_error_code
) {
1648 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1649 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1652 if (vmx
->rmode
.vm86_active
) {
1654 if (kvm_exception_is_soft(nr
))
1655 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1656 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1657 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1661 if (kvm_exception_is_soft(nr
)) {
1662 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1663 vmx
->vcpu
.arch
.event_exit_inst_len
);
1664 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1666 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1668 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1669 vmx_clear_hlt(vcpu
);
1672 static bool vmx_rdtscp_supported(void)
1674 return cpu_has_vmx_rdtscp();
1678 * Swap MSR entry in host/guest MSR entry array.
1680 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1682 struct shared_msr_entry tmp
;
1684 tmp
= vmx
->guest_msrs
[to
];
1685 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1686 vmx
->guest_msrs
[from
] = tmp
;
1690 * Set up the vmcs to automatically save and restore system
1691 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1692 * mode, as fiddling with msrs is very expensive.
1694 static void setup_msrs(struct vcpu_vmx
*vmx
)
1696 int save_nmsrs
, index
;
1697 unsigned long *msr_bitmap
;
1699 vmx_load_host_state(vmx
);
1701 #ifdef CONFIG_X86_64
1702 if (is_long_mode(&vmx
->vcpu
)) {
1703 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1705 move_msr_up(vmx
, index
, save_nmsrs
++);
1706 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1708 move_msr_up(vmx
, index
, save_nmsrs
++);
1709 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1711 move_msr_up(vmx
, index
, save_nmsrs
++);
1712 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1713 if (index
>= 0 && vmx
->rdtscp_enabled
)
1714 move_msr_up(vmx
, index
, save_nmsrs
++);
1716 * MSR_STAR is only needed on long mode guests, and only
1717 * if efer.sce is enabled.
1719 index
= __find_msr_index(vmx
, MSR_STAR
);
1720 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1721 move_msr_up(vmx
, index
, save_nmsrs
++);
1724 index
= __find_msr_index(vmx
, MSR_EFER
);
1725 if (index
>= 0 && update_transition_efer(vmx
, index
))
1726 move_msr_up(vmx
, index
, save_nmsrs
++);
1728 vmx
->save_nmsrs
= save_nmsrs
;
1730 if (cpu_has_vmx_msr_bitmap()) {
1731 if (is_long_mode(&vmx
->vcpu
))
1732 msr_bitmap
= vmx_msr_bitmap_longmode
;
1734 msr_bitmap
= vmx_msr_bitmap_legacy
;
1736 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1741 * reads and returns guest's timestamp counter "register"
1742 * guest_tsc = host_tsc + tsc_offset -- 21.3
1744 static u64
guest_read_tsc(void)
1746 u64 host_tsc
, tsc_offset
;
1749 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1750 return host_tsc
+ tsc_offset
;
1754 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1755 * counter, even if a nested guest (L2) is currently running.
1757 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
)
1759 u64 host_tsc
, tsc_offset
;
1762 tsc_offset
= is_guest_mode(vcpu
) ?
1763 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1764 vmcs_read64(TSC_OFFSET
);
1765 return host_tsc
+ tsc_offset
;
1769 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1770 * ioctl. In this case the call-back should update internal vmx state to make
1771 * the changes effective.
1773 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
)
1775 /* Nothing to do here */
1779 * writes 'offset' into guest's timestamp counter offset register
1781 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1783 if (is_guest_mode(vcpu
)) {
1785 * We're here if L1 chose not to trap WRMSR to TSC. According
1786 * to the spec, this should set L1's TSC; The offset that L1
1787 * set for L2 remains unchanged, and still needs to be added
1788 * to the newly set TSC to get L2's TSC.
1790 struct vmcs12
*vmcs12
;
1791 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1792 /* recalculate vmcs02.TSC_OFFSET: */
1793 vmcs12
= get_vmcs12(vcpu
);
1794 vmcs_write64(TSC_OFFSET
, offset
+
1795 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1796 vmcs12
->tsc_offset
: 0));
1798 vmcs_write64(TSC_OFFSET
, offset
);
1802 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1804 u64 offset
= vmcs_read64(TSC_OFFSET
);
1805 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1806 if (is_guest_mode(vcpu
)) {
1807 /* Even when running L2, the adjustment needs to apply to L1 */
1808 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1812 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1814 return target_tsc
- native_read_tsc();
1817 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1819 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1820 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1824 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1825 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1826 * all guests if the "nested" module option is off, and can also be disabled
1827 * for a single guest by disabling its VMX cpuid bit.
1829 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1831 return nested
&& guest_cpuid_has_vmx(vcpu
);
1835 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1836 * returned for the various VMX controls MSRs when nested VMX is enabled.
1837 * The same values should also be used to verify that vmcs12 control fields are
1838 * valid during nested entry from L1 to L2.
1839 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1840 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1841 * bit in the high half is on if the corresponding bit in the control field
1842 * may be on. See also vmx_control_verify().
1843 * TODO: allow these variables to be modified (downgraded) by module options
1846 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1847 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1848 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1849 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1850 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1851 static __init
void nested_vmx_setup_ctls_msrs(void)
1854 * Note that as a general rule, the high half of the MSRs (bits in
1855 * the control fields which may be 1) should be initialized by the
1856 * intersection of the underlying hardware's MSR (i.e., features which
1857 * can be supported) and the list of features we want to expose -
1858 * because they are known to be properly supported in our code.
1859 * Also, usually, the low half of the MSRs (bits which must be 1) can
1860 * be set to 0, meaning that L1 may turn off any of these bits. The
1861 * reason is that if one of these bits is necessary, it will appear
1862 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1863 * fields of vmcs01 and vmcs02, will turn these bits off - and
1864 * nested_vmx_exit_handled() will not pass related exits to L1.
1865 * These rules have exceptions below.
1868 /* pin-based controls */
1870 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1871 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1873 nested_vmx_pinbased_ctls_low
= 0x16 ;
1874 nested_vmx_pinbased_ctls_high
= 0x16 |
1875 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1876 PIN_BASED_VIRTUAL_NMIS
;
1879 nested_vmx_exit_ctls_low
= 0;
1880 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1881 #ifdef CONFIG_X86_64
1882 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1884 nested_vmx_exit_ctls_high
= 0;
1887 /* entry controls */
1888 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1889 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1890 nested_vmx_entry_ctls_low
= 0;
1891 nested_vmx_entry_ctls_high
&=
1892 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1894 /* cpu-based controls */
1895 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1896 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1897 nested_vmx_procbased_ctls_low
= 0;
1898 nested_vmx_procbased_ctls_high
&=
1899 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1900 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1901 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1902 CPU_BASED_CR3_STORE_EXITING
|
1903 #ifdef CONFIG_X86_64
1904 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1906 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1907 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1908 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1910 * We can allow some features even when not supported by the
1911 * hardware. For example, L1 can specify an MSR bitmap - and we
1912 * can use it to avoid exits to L1 - even when L0 runs L2
1913 * without MSR bitmaps.
1915 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
1917 /* secondary cpu-based controls */
1918 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1919 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
1920 nested_vmx_secondary_ctls_low
= 0;
1921 nested_vmx_secondary_ctls_high
&=
1922 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1925 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
1928 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1930 return ((control
& high
) | low
) == control
;
1933 static inline u64
vmx_control_msr(u32 low
, u32 high
)
1935 return low
| ((u64
)high
<< 32);
1939 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1940 * also let it use VMX-specific MSRs.
1941 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1942 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1943 * like all other MSRs).
1945 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1947 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
1948 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
1950 * According to the spec, processors which do not support VMX
1951 * should throw a #GP(0) when VMX capability MSRs are read.
1953 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
1957 switch (msr_index
) {
1958 case MSR_IA32_FEATURE_CONTROL
:
1961 case MSR_IA32_VMX_BASIC
:
1963 * This MSR reports some information about VMX support. We
1964 * should return information about the VMX we emulate for the
1965 * guest, and the VMCS structure we give it - not about the
1966 * VMX support of the underlying hardware.
1968 *pdata
= VMCS12_REVISION
|
1969 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
1970 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
1972 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
1973 case MSR_IA32_VMX_PINBASED_CTLS
:
1974 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
1975 nested_vmx_pinbased_ctls_high
);
1977 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
1978 case MSR_IA32_VMX_PROCBASED_CTLS
:
1979 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
1980 nested_vmx_procbased_ctls_high
);
1982 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
1983 case MSR_IA32_VMX_EXIT_CTLS
:
1984 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
1985 nested_vmx_exit_ctls_high
);
1987 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
1988 case MSR_IA32_VMX_ENTRY_CTLS
:
1989 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
1990 nested_vmx_entry_ctls_high
);
1992 case MSR_IA32_VMX_MISC
:
1996 * These MSRs specify bits which the guest must keep fixed (on or off)
1997 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1998 * We picked the standard core2 setting.
2000 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2001 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2002 case MSR_IA32_VMX_CR0_FIXED0
:
2003 *pdata
= VMXON_CR0_ALWAYSON
;
2005 case MSR_IA32_VMX_CR0_FIXED1
:
2008 case MSR_IA32_VMX_CR4_FIXED0
:
2009 *pdata
= VMXON_CR4_ALWAYSON
;
2011 case MSR_IA32_VMX_CR4_FIXED1
:
2014 case MSR_IA32_VMX_VMCS_ENUM
:
2017 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2018 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2019 nested_vmx_secondary_ctls_high
);
2021 case MSR_IA32_VMX_EPT_VPID_CAP
:
2022 /* Currently, no nested ept or nested vpid */
2032 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2034 if (!nested_vmx_allowed(vcpu
))
2037 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2038 /* TODO: the right thing. */
2041 * No need to treat VMX capability MSRs specially: If we don't handle
2042 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2048 * Reads an msr value (of 'msr_index') into 'pdata'.
2049 * Returns 0 on success, non-0 otherwise.
2050 * Assumes vcpu_load() was already called.
2052 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2055 struct shared_msr_entry
*msr
;
2058 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2062 switch (msr_index
) {
2063 #ifdef CONFIG_X86_64
2065 data
= vmcs_readl(GUEST_FS_BASE
);
2068 data
= vmcs_readl(GUEST_GS_BASE
);
2070 case MSR_KERNEL_GS_BASE
:
2071 vmx_load_host_state(to_vmx(vcpu
));
2072 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2076 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2078 data
= guest_read_tsc();
2080 case MSR_IA32_SYSENTER_CS
:
2081 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2083 case MSR_IA32_SYSENTER_EIP
:
2084 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2086 case MSR_IA32_SYSENTER_ESP
:
2087 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2090 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2092 /* Otherwise falls through */
2094 vmx_load_host_state(to_vmx(vcpu
));
2095 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2097 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2099 vmx_load_host_state(to_vmx(vcpu
));
2103 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2111 * Writes msr value into into the appropriate "register".
2112 * Returns 0 on success, non-0 otherwise.
2113 * Assumes vcpu_load() was already called.
2115 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2117 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2118 struct shared_msr_entry
*msr
;
2121 switch (msr_index
) {
2123 vmx_load_host_state(vmx
);
2124 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2126 #ifdef CONFIG_X86_64
2128 vmx_segment_cache_clear(vmx
);
2129 vmcs_writel(GUEST_FS_BASE
, data
);
2132 vmx_segment_cache_clear(vmx
);
2133 vmcs_writel(GUEST_GS_BASE
, data
);
2135 case MSR_KERNEL_GS_BASE
:
2136 vmx_load_host_state(vmx
);
2137 vmx
->msr_guest_kernel_gs_base
= data
;
2140 case MSR_IA32_SYSENTER_CS
:
2141 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2143 case MSR_IA32_SYSENTER_EIP
:
2144 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2146 case MSR_IA32_SYSENTER_ESP
:
2147 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2150 kvm_write_tsc(vcpu
, data
);
2152 case MSR_IA32_CR_PAT
:
2153 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2154 vmcs_write64(GUEST_IA32_PAT
, data
);
2155 vcpu
->arch
.pat
= data
;
2158 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2161 if (!vmx
->rdtscp_enabled
)
2163 /* Check reserved bit, higher 32 bits should be zero */
2164 if ((data
>> 32) != 0)
2166 /* Otherwise falls through */
2168 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2170 msr
= find_msr_entry(vmx
, msr_index
);
2172 vmx_load_host_state(vmx
);
2176 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2182 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2184 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2187 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2190 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2192 case VCPU_EXREG_PDPTR
:
2194 ept_save_pdptrs(vcpu
);
2201 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
2203 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
2204 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
2206 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2208 update_exception_bitmap(vcpu
);
2211 static __init
int cpu_has_kvm_support(void)
2213 return cpu_has_vmx();
2216 static __init
int vmx_disabled_by_bios(void)
2220 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2221 if (msr
& FEATURE_CONTROL_LOCKED
) {
2222 /* launched w/ TXT and VMX disabled */
2223 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2226 /* launched w/o TXT and VMX only enabled w/ TXT */
2227 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2228 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2229 && !tboot_enabled()) {
2230 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2231 "activate TXT before enabling KVM\n");
2234 /* launched w/o TXT and VMX disabled */
2235 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2236 && !tboot_enabled())
2243 static void kvm_cpu_vmxon(u64 addr
)
2245 asm volatile (ASM_VMX_VMXON_RAX
2246 : : "a"(&addr
), "m"(addr
)
2250 static int hardware_enable(void *garbage
)
2252 int cpu
= raw_smp_processor_id();
2253 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2256 if (read_cr4() & X86_CR4_VMXE
)
2259 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2260 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2262 test_bits
= FEATURE_CONTROL_LOCKED
;
2263 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2264 if (tboot_enabled())
2265 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2267 if ((old
& test_bits
) != test_bits
) {
2268 /* enable and lock */
2269 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2271 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2273 if (vmm_exclusive
) {
2274 kvm_cpu_vmxon(phys_addr
);
2278 store_gdt(&__get_cpu_var(host_gdt
));
2283 static void vmclear_local_loaded_vmcss(void)
2285 int cpu
= raw_smp_processor_id();
2286 struct loaded_vmcs
*v
, *n
;
2288 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2289 loaded_vmcss_on_cpu_link
)
2290 __loaded_vmcs_clear(v
);
2294 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2297 static void kvm_cpu_vmxoff(void)
2299 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2302 static void hardware_disable(void *garbage
)
2304 if (vmm_exclusive
) {
2305 vmclear_local_loaded_vmcss();
2308 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2311 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2312 u32 msr
, u32
*result
)
2314 u32 vmx_msr_low
, vmx_msr_high
;
2315 u32 ctl
= ctl_min
| ctl_opt
;
2317 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2319 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2320 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2322 /* Ensure minimum (required) set of control bits are supported. */
2330 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2332 u32 vmx_msr_low
, vmx_msr_high
;
2334 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2335 return vmx_msr_high
& ctl
;
2338 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2340 u32 vmx_msr_low
, vmx_msr_high
;
2341 u32 min
, opt
, min2
, opt2
;
2342 u32 _pin_based_exec_control
= 0;
2343 u32 _cpu_based_exec_control
= 0;
2344 u32 _cpu_based_2nd_exec_control
= 0;
2345 u32 _vmexit_control
= 0;
2346 u32 _vmentry_control
= 0;
2348 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2349 opt
= PIN_BASED_VIRTUAL_NMIS
;
2350 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2351 &_pin_based_exec_control
) < 0)
2355 #ifdef CONFIG_X86_64
2356 CPU_BASED_CR8_LOAD_EXITING
|
2357 CPU_BASED_CR8_STORE_EXITING
|
2359 CPU_BASED_CR3_LOAD_EXITING
|
2360 CPU_BASED_CR3_STORE_EXITING
|
2361 CPU_BASED_USE_IO_BITMAPS
|
2362 CPU_BASED_MOV_DR_EXITING
|
2363 CPU_BASED_USE_TSC_OFFSETING
|
2364 CPU_BASED_MWAIT_EXITING
|
2365 CPU_BASED_MONITOR_EXITING
|
2366 CPU_BASED_INVLPG_EXITING
;
2369 min
|= CPU_BASED_HLT_EXITING
;
2371 opt
= CPU_BASED_TPR_SHADOW
|
2372 CPU_BASED_USE_MSR_BITMAPS
|
2373 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2374 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2375 &_cpu_based_exec_control
) < 0)
2377 #ifdef CONFIG_X86_64
2378 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2379 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2380 ~CPU_BASED_CR8_STORE_EXITING
;
2382 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2384 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2385 SECONDARY_EXEC_WBINVD_EXITING
|
2386 SECONDARY_EXEC_ENABLE_VPID
|
2387 SECONDARY_EXEC_ENABLE_EPT
|
2388 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2389 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2390 SECONDARY_EXEC_RDTSCP
;
2391 if (adjust_vmx_controls(min2
, opt2
,
2392 MSR_IA32_VMX_PROCBASED_CTLS2
,
2393 &_cpu_based_2nd_exec_control
) < 0)
2396 #ifndef CONFIG_X86_64
2397 if (!(_cpu_based_2nd_exec_control
&
2398 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2399 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2401 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2402 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2404 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2405 CPU_BASED_CR3_STORE_EXITING
|
2406 CPU_BASED_INVLPG_EXITING
);
2407 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2408 vmx_capability
.ept
, vmx_capability
.vpid
);
2412 #ifdef CONFIG_X86_64
2413 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2415 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2416 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2417 &_vmexit_control
) < 0)
2421 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2422 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2423 &_vmentry_control
) < 0)
2426 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2428 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2429 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2432 #ifdef CONFIG_X86_64
2433 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2434 if (vmx_msr_high
& (1u<<16))
2438 /* Require Write-Back (WB) memory type for VMCS accesses. */
2439 if (((vmx_msr_high
>> 18) & 15) != 6)
2442 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2443 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2444 vmcs_conf
->revision_id
= vmx_msr_low
;
2446 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2447 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2448 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2449 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2450 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2452 cpu_has_load_ia32_efer
=
2453 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2454 VM_ENTRY_LOAD_IA32_EFER
)
2455 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2456 VM_EXIT_LOAD_IA32_EFER
);
2461 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2463 int node
= cpu_to_node(cpu
);
2467 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2470 vmcs
= page_address(pages
);
2471 memset(vmcs
, 0, vmcs_config
.size
);
2472 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2476 static struct vmcs
*alloc_vmcs(void)
2478 return alloc_vmcs_cpu(raw_smp_processor_id());
2481 static void free_vmcs(struct vmcs
*vmcs
)
2483 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2487 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2489 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2491 if (!loaded_vmcs
->vmcs
)
2493 loaded_vmcs_clear(loaded_vmcs
);
2494 free_vmcs(loaded_vmcs
->vmcs
);
2495 loaded_vmcs
->vmcs
= NULL
;
2498 static void free_kvm_area(void)
2502 for_each_possible_cpu(cpu
) {
2503 free_vmcs(per_cpu(vmxarea
, cpu
));
2504 per_cpu(vmxarea
, cpu
) = NULL
;
2508 static __init
int alloc_kvm_area(void)
2512 for_each_possible_cpu(cpu
) {
2515 vmcs
= alloc_vmcs_cpu(cpu
);
2521 per_cpu(vmxarea
, cpu
) = vmcs
;
2526 static __init
int hardware_setup(void)
2528 if (setup_vmcs_config(&vmcs_config
) < 0)
2531 if (boot_cpu_has(X86_FEATURE_NX
))
2532 kvm_enable_efer_bits(EFER_NX
);
2534 if (!cpu_has_vmx_vpid())
2537 if (!cpu_has_vmx_ept() ||
2538 !cpu_has_vmx_ept_4levels()) {
2540 enable_unrestricted_guest
= 0;
2543 if (!cpu_has_vmx_unrestricted_guest())
2544 enable_unrestricted_guest
= 0;
2546 if (!cpu_has_vmx_flexpriority())
2547 flexpriority_enabled
= 0;
2549 if (!cpu_has_vmx_tpr_shadow())
2550 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2552 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2553 kvm_disable_largepages();
2555 if (!cpu_has_vmx_ple())
2559 nested_vmx_setup_ctls_msrs();
2561 return alloc_kvm_area();
2564 static __exit
void hardware_unsetup(void)
2569 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2571 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2573 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2574 vmcs_write16(sf
->selector
, save
->selector
);
2575 vmcs_writel(sf
->base
, save
->base
);
2576 vmcs_write32(sf
->limit
, save
->limit
);
2577 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2579 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2581 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2585 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2587 unsigned long flags
;
2588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2590 vmx
->emulation_required
= 1;
2591 vmx
->rmode
.vm86_active
= 0;
2593 vmx_segment_cache_clear(vmx
);
2595 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2596 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2597 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2598 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2600 flags
= vmcs_readl(GUEST_RFLAGS
);
2601 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2602 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2603 vmcs_writel(GUEST_RFLAGS
, flags
);
2605 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2606 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2608 update_exception_bitmap(vcpu
);
2610 if (emulate_invalid_guest_state
)
2613 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2614 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2615 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2616 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2618 vmx_segment_cache_clear(vmx
);
2620 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2621 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2623 vmcs_write16(GUEST_CS_SELECTOR
,
2624 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2625 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2628 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2630 if (!kvm
->arch
.tss_addr
) {
2631 struct kvm_memslots
*slots
;
2634 slots
= kvm_memslots(kvm
);
2635 base_gfn
= slots
->memslots
[0].base_gfn
+
2636 kvm
->memslots
->memslots
[0].npages
- 3;
2637 return base_gfn
<< PAGE_SHIFT
;
2639 return kvm
->arch
.tss_addr
;
2642 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2644 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2646 save
->selector
= vmcs_read16(sf
->selector
);
2647 save
->base
= vmcs_readl(sf
->base
);
2648 save
->limit
= vmcs_read32(sf
->limit
);
2649 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2650 vmcs_write16(sf
->selector
, save
->base
>> 4);
2651 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2652 vmcs_write32(sf
->limit
, 0xffff);
2653 vmcs_write32(sf
->ar_bytes
, 0xf3);
2654 if (save
->base
& 0xf)
2655 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2656 " aligned when entering protected mode (seg=%d)",
2660 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2662 unsigned long flags
;
2663 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2665 if (enable_unrestricted_guest
)
2668 vmx
->emulation_required
= 1;
2669 vmx
->rmode
.vm86_active
= 1;
2672 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2673 * vcpu. Call it here with phys address pointing 16M below 4G.
2675 if (!vcpu
->kvm
->arch
.tss_addr
) {
2676 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2677 "called before entering vcpu\n");
2678 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2679 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2680 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2683 vmx_segment_cache_clear(vmx
);
2685 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2686 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2687 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2689 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2690 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2692 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2693 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2695 flags
= vmcs_readl(GUEST_RFLAGS
);
2696 vmx
->rmode
.save_rflags
= flags
;
2698 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2700 vmcs_writel(GUEST_RFLAGS
, flags
);
2701 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2702 update_exception_bitmap(vcpu
);
2704 if (emulate_invalid_guest_state
)
2705 goto continue_rmode
;
2707 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
2708 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
2709 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
2711 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
2712 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
2713 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
2714 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
2715 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
2717 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2718 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2719 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2720 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2723 kvm_mmu_reset_context(vcpu
);
2726 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2729 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2735 * Force kernel_gs_base reloading before EFER changes, as control
2736 * of this msr depends on is_long_mode().
2738 vmx_load_host_state(to_vmx(vcpu
));
2739 vcpu
->arch
.efer
= efer
;
2740 if (efer
& EFER_LMA
) {
2741 vmcs_write32(VM_ENTRY_CONTROLS
,
2742 vmcs_read32(VM_ENTRY_CONTROLS
) |
2743 VM_ENTRY_IA32E_MODE
);
2746 vmcs_write32(VM_ENTRY_CONTROLS
,
2747 vmcs_read32(VM_ENTRY_CONTROLS
) &
2748 ~VM_ENTRY_IA32E_MODE
);
2750 msr
->data
= efer
& ~EFER_LME
;
2755 #ifdef CONFIG_X86_64
2757 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2761 vmx_segment_cache_clear(to_vmx(vcpu
));
2763 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2764 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2765 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2767 vmcs_write32(GUEST_TR_AR_BYTES
,
2768 (guest_tr_ar
& ~AR_TYPE_MASK
)
2769 | AR_TYPE_BUSY_64_TSS
);
2771 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2774 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2776 vmcs_write32(VM_ENTRY_CONTROLS
,
2777 vmcs_read32(VM_ENTRY_CONTROLS
)
2778 & ~VM_ENTRY_IA32E_MODE
);
2779 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2784 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2786 vpid_sync_context(to_vmx(vcpu
));
2788 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2790 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2794 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2796 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2798 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2799 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2802 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2804 if (enable_ept
&& is_paging(vcpu
))
2805 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2806 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2809 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2811 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2813 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2814 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2817 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2819 if (!test_bit(VCPU_EXREG_PDPTR
,
2820 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2823 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2824 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2825 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2826 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2827 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2831 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2833 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2834 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2835 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2836 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2837 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2840 __set_bit(VCPU_EXREG_PDPTR
,
2841 (unsigned long *)&vcpu
->arch
.regs_avail
);
2842 __set_bit(VCPU_EXREG_PDPTR
,
2843 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2846 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2848 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2850 struct kvm_vcpu
*vcpu
)
2852 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2853 vmx_decache_cr3(vcpu
);
2854 if (!(cr0
& X86_CR0_PG
)) {
2855 /* From paging/starting to nonpaging */
2856 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2857 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2858 (CPU_BASED_CR3_LOAD_EXITING
|
2859 CPU_BASED_CR3_STORE_EXITING
));
2860 vcpu
->arch
.cr0
= cr0
;
2861 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2862 } else if (!is_paging(vcpu
)) {
2863 /* From nonpaging to paging */
2864 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2865 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
2866 ~(CPU_BASED_CR3_LOAD_EXITING
|
2867 CPU_BASED_CR3_STORE_EXITING
));
2868 vcpu
->arch
.cr0
= cr0
;
2869 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2872 if (!(cr0
& X86_CR0_WP
))
2873 *hw_cr0
&= ~X86_CR0_WP
;
2876 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2878 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2879 unsigned long hw_cr0
;
2881 if (enable_unrestricted_guest
)
2882 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
2883 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
2885 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
2887 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
2890 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
2893 #ifdef CONFIG_X86_64
2894 if (vcpu
->arch
.efer
& EFER_LME
) {
2895 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
2897 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
2903 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
2905 if (!vcpu
->fpu_active
)
2906 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
2908 vmcs_writel(CR0_READ_SHADOW
, cr0
);
2909 vmcs_writel(GUEST_CR0
, hw_cr0
);
2910 vcpu
->arch
.cr0
= cr0
;
2911 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2914 static u64
construct_eptp(unsigned long root_hpa
)
2918 /* TODO write the value reading from MSR */
2919 eptp
= VMX_EPT_DEFAULT_MT
|
2920 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
2921 eptp
|= (root_hpa
& PAGE_MASK
);
2926 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
2928 unsigned long guest_cr3
;
2933 eptp
= construct_eptp(cr3
);
2934 vmcs_write64(EPT_POINTER
, eptp
);
2935 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
2936 vcpu
->kvm
->arch
.ept_identity_map_addr
;
2937 ept_load_pdptrs(vcpu
);
2940 vmx_flush_tlb(vcpu
);
2941 vmcs_writel(GUEST_CR3
, guest_cr3
);
2944 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2946 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
2947 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
2949 if (cr4
& X86_CR4_VMXE
) {
2951 * To use VMXON (and later other VMX instructions), a guest
2952 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2953 * So basically the check on whether to allow nested VMX
2956 if (!nested_vmx_allowed(vcpu
))
2958 } else if (to_vmx(vcpu
)->nested
.vmxon
)
2961 vcpu
->arch
.cr4
= cr4
;
2963 if (!is_paging(vcpu
)) {
2964 hw_cr4
&= ~X86_CR4_PAE
;
2965 hw_cr4
|= X86_CR4_PSE
;
2966 } else if (!(cr4
& X86_CR4_PAE
)) {
2967 hw_cr4
&= ~X86_CR4_PAE
;
2971 vmcs_writel(CR4_READ_SHADOW
, cr4
);
2972 vmcs_writel(GUEST_CR4
, hw_cr4
);
2976 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2977 struct kvm_segment
*var
, int seg
)
2979 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2980 struct kvm_save_segment
*save
;
2983 if (vmx
->rmode
.vm86_active
2984 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
2985 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
2986 || seg
== VCPU_SREG_GS
)
2987 && !emulate_invalid_guest_state
) {
2989 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
2990 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
2991 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
2992 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
2993 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
2996 var
->selector
= save
->selector
;
2997 var
->base
= save
->base
;
2998 var
->limit
= save
->limit
;
3000 if (seg
== VCPU_SREG_TR
3001 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3002 goto use_saved_rmode_seg
;
3004 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3005 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3006 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3007 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3008 use_saved_rmode_seg
:
3009 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
3011 var
->type
= ar
& 15;
3012 var
->s
= (ar
>> 4) & 1;
3013 var
->dpl
= (ar
>> 5) & 3;
3014 var
->present
= (ar
>> 7) & 1;
3015 var
->avl
= (ar
>> 12) & 1;
3016 var
->l
= (ar
>> 13) & 1;
3017 var
->db
= (ar
>> 14) & 1;
3018 var
->g
= (ar
>> 15) & 1;
3019 var
->unusable
= (ar
>> 16) & 1;
3022 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3024 struct kvm_segment s
;
3026 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3027 vmx_get_segment(vcpu
, &s
, seg
);
3030 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3033 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3035 if (!is_protmode(vcpu
))
3038 if (!is_long_mode(vcpu
)
3039 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3042 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
3045 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3047 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3048 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3049 to_vmx(vcpu
)->cpl
= __vmx_get_cpl(vcpu
);
3051 return to_vmx(vcpu
)->cpl
;
3055 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3062 ar
= var
->type
& 15;
3063 ar
|= (var
->s
& 1) << 4;
3064 ar
|= (var
->dpl
& 3) << 5;
3065 ar
|= (var
->present
& 1) << 7;
3066 ar
|= (var
->avl
& 1) << 12;
3067 ar
|= (var
->l
& 1) << 13;
3068 ar
|= (var
->db
& 1) << 14;
3069 ar
|= (var
->g
& 1) << 15;
3071 if (ar
== 0) /* a 0 value means unusable */
3072 ar
= AR_UNUSABLE_MASK
;
3077 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3078 struct kvm_segment
*var
, int seg
)
3080 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3081 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3084 vmx_segment_cache_clear(vmx
);
3086 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
3087 vmcs_write16(sf
->selector
, var
->selector
);
3088 vmx
->rmode
.tr
.selector
= var
->selector
;
3089 vmx
->rmode
.tr
.base
= var
->base
;
3090 vmx
->rmode
.tr
.limit
= var
->limit
;
3091 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
3094 vmcs_writel(sf
->base
, var
->base
);
3095 vmcs_write32(sf
->limit
, var
->limit
);
3096 vmcs_write16(sf
->selector
, var
->selector
);
3097 if (vmx
->rmode
.vm86_active
&& var
->s
) {
3099 * Hack real-mode segments into vm86 compatibility.
3101 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
3102 vmcs_writel(sf
->base
, 0xf0000);
3105 ar
= vmx_segment_access_rights(var
);
3108 * Fix the "Accessed" bit in AR field of segment registers for older
3110 * IA32 arch specifies that at the time of processor reset the
3111 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3112 * is setting it to 0 in the usedland code. This causes invalid guest
3113 * state vmexit when "unrestricted guest" mode is turned on.
3114 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3115 * tree. Newer qemu binaries with that qemu fix would not need this
3118 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3119 ar
|= 0x1; /* Accessed */
3121 vmcs_write32(sf
->ar_bytes
, ar
);
3122 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3125 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3127 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3129 *db
= (ar
>> 14) & 1;
3130 *l
= (ar
>> 13) & 1;
3133 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3135 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3136 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3139 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3141 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3142 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3145 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3147 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3148 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3151 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3153 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3154 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3157 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3159 struct kvm_segment var
;
3162 vmx_get_segment(vcpu
, &var
, seg
);
3163 ar
= vmx_segment_access_rights(&var
);
3165 if (var
.base
!= (var
.selector
<< 4))
3167 if (var
.limit
!= 0xffff)
3175 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3177 struct kvm_segment cs
;
3178 unsigned int cs_rpl
;
3180 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3181 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3185 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3189 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3190 if (cs
.dpl
> cs_rpl
)
3193 if (cs
.dpl
!= cs_rpl
)
3199 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3203 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3205 struct kvm_segment ss
;
3206 unsigned int ss_rpl
;
3208 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3209 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3213 if (ss
.type
!= 3 && ss
.type
!= 7)
3217 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3225 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3227 struct kvm_segment var
;
3230 vmx_get_segment(vcpu
, &var
, seg
);
3231 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3239 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3240 if (var
.dpl
< rpl
) /* DPL < RPL */
3244 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3250 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3252 struct kvm_segment tr
;
3254 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3258 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3260 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3268 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3270 struct kvm_segment ldtr
;
3272 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3276 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3286 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3288 struct kvm_segment cs
, ss
;
3290 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3291 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3293 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3294 (ss
.selector
& SELECTOR_RPL_MASK
));
3298 * Check if guest state is valid. Returns true if valid, false if
3300 * We assume that registers are always usable
3302 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3304 /* real mode guest state checks */
3305 if (!is_protmode(vcpu
)) {
3306 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3308 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3310 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3312 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3314 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3316 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3319 /* protected mode guest state checks */
3320 if (!cs_ss_rpl_check(vcpu
))
3322 if (!code_segment_valid(vcpu
))
3324 if (!stack_segment_valid(vcpu
))
3326 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3328 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3330 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3332 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3334 if (!tr_valid(vcpu
))
3336 if (!ldtr_valid(vcpu
))
3340 * - Add checks on RIP
3341 * - Add checks on RFLAGS
3347 static int init_rmode_tss(struct kvm
*kvm
)
3351 int r
, idx
, ret
= 0;
3353 idx
= srcu_read_lock(&kvm
->srcu
);
3354 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3355 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3358 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3359 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3360 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3363 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3366 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3370 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3371 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3378 srcu_read_unlock(&kvm
->srcu
, idx
);
3382 static int init_rmode_identity_map(struct kvm
*kvm
)
3385 pfn_t identity_map_pfn
;
3390 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3391 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3392 "haven't been allocated!\n");
3395 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3398 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3399 idx
= srcu_read_lock(&kvm
->srcu
);
3400 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3403 /* Set up identity-mapping pagetable for EPT in real mode */
3404 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3405 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3406 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3407 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3408 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3412 kvm
->arch
.ept_identity_pagetable_done
= true;
3415 srcu_read_unlock(&kvm
->srcu
, idx
);
3419 static void seg_setup(int seg
)
3421 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3424 vmcs_write16(sf
->selector
, 0);
3425 vmcs_writel(sf
->base
, 0);
3426 vmcs_write32(sf
->limit
, 0xffff);
3427 if (enable_unrestricted_guest
) {
3429 if (seg
== VCPU_SREG_CS
)
3430 ar
|= 0x08; /* code segment */
3434 vmcs_write32(sf
->ar_bytes
, ar
);
3437 static int alloc_apic_access_page(struct kvm
*kvm
)
3439 struct kvm_userspace_memory_region kvm_userspace_mem
;
3442 mutex_lock(&kvm
->slots_lock
);
3443 if (kvm
->arch
.apic_access_page
)
3445 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3446 kvm_userspace_mem
.flags
= 0;
3447 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3448 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3449 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3453 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3455 mutex_unlock(&kvm
->slots_lock
);
3459 static int alloc_identity_pagetable(struct kvm
*kvm
)
3461 struct kvm_userspace_memory_region kvm_userspace_mem
;
3464 mutex_lock(&kvm
->slots_lock
);
3465 if (kvm
->arch
.ept_identity_pagetable
)
3467 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3468 kvm_userspace_mem
.flags
= 0;
3469 kvm_userspace_mem
.guest_phys_addr
=
3470 kvm
->arch
.ept_identity_map_addr
;
3471 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3472 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3476 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3477 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3479 mutex_unlock(&kvm
->slots_lock
);
3483 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3490 spin_lock(&vmx_vpid_lock
);
3491 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3492 if (vpid
< VMX_NR_VPIDS
) {
3494 __set_bit(vpid
, vmx_vpid_bitmap
);
3496 spin_unlock(&vmx_vpid_lock
);
3499 static void free_vpid(struct vcpu_vmx
*vmx
)
3503 spin_lock(&vmx_vpid_lock
);
3505 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3506 spin_unlock(&vmx_vpid_lock
);
3509 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3511 int f
= sizeof(unsigned long);
3513 if (!cpu_has_vmx_msr_bitmap())
3517 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3518 * have the write-low and read-high bitmap offsets the wrong way round.
3519 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3521 if (msr
<= 0x1fff) {
3522 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3523 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3524 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3526 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3527 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3531 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3534 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3535 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3539 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3540 * will not change in the lifetime of the guest.
3541 * Note that host-state that does change is set elsewhere. E.g., host-state
3542 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3544 static void vmx_set_constant_host_state(void)
3550 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3551 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3552 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3554 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3555 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3556 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3557 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3558 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3560 native_store_idt(&dt
);
3561 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3563 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl
));
3564 vmcs_writel(HOST_RIP
, tmpl
); /* 22.2.5 */
3566 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3567 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3568 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3569 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3571 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3572 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3573 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3577 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3579 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3581 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3582 if (is_guest_mode(&vmx
->vcpu
))
3583 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3584 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3585 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3588 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3590 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3591 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3592 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3593 #ifdef CONFIG_X86_64
3594 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3595 CPU_BASED_CR8_LOAD_EXITING
;
3599 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3600 CPU_BASED_CR3_LOAD_EXITING
|
3601 CPU_BASED_INVLPG_EXITING
;
3602 return exec_control
;
3605 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3607 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3608 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3609 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3611 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3613 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3614 enable_unrestricted_guest
= 0;
3616 if (!enable_unrestricted_guest
)
3617 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3619 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3620 return exec_control
;
3623 static void ept_set_mmio_spte_mask(void)
3626 * EPT Misconfigurations can be generated if the value of bits 2:0
3627 * of an EPT paging-structure entry is 110b (write/execute).
3628 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3631 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
3635 * Sets up the vmcs for emulated real mode.
3637 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3639 #ifdef CONFIG_X86_64
3645 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3646 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3648 if (cpu_has_vmx_msr_bitmap())
3649 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3651 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3654 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3655 vmcs_config
.pin_based_exec_ctrl
);
3657 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
3659 if (cpu_has_secondary_exec_ctrls()) {
3660 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
3661 vmx_secondary_exec_control(vmx
));
3665 vmcs_write32(PLE_GAP
, ple_gap
);
3666 vmcs_write32(PLE_WINDOW
, ple_window
);
3669 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
3670 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
3671 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3673 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3674 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3675 vmx_set_constant_host_state();
3676 #ifdef CONFIG_X86_64
3677 rdmsrl(MSR_FS_BASE
, a
);
3678 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3679 rdmsrl(MSR_GS_BASE
, a
);
3680 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3682 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3683 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3686 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3687 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3688 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3690 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3692 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3693 u32 msr_low
, msr_high
;
3695 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3696 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3697 /* Write the default value follow host pat */
3698 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3699 /* Keep arch.pat sync with GUEST_IA32_PAT */
3700 vmx
->vcpu
.arch
.pat
= host_pat
;
3703 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3704 u32 index
= vmx_msr_index
[i
];
3705 u32 data_low
, data_high
;
3708 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3710 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3712 vmx
->guest_msrs
[j
].index
= i
;
3713 vmx
->guest_msrs
[j
].data
= 0;
3714 vmx
->guest_msrs
[j
].mask
= -1ull;
3718 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3720 /* 22.2.1, 20.8.1 */
3721 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3723 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3724 set_cr4_guest_host_mask(vmx
);
3726 kvm_write_tsc(&vmx
->vcpu
, 0);
3731 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3737 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3739 vmx
->rmode
.vm86_active
= 0;
3741 vmx
->soft_vnmi_blocked
= 0;
3743 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3744 kvm_set_cr8(&vmx
->vcpu
, 0);
3745 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3746 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3747 msr
|= MSR_IA32_APICBASE_BSP
;
3748 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3750 ret
= fx_init(&vmx
->vcpu
);
3754 vmx_segment_cache_clear(vmx
);
3756 seg_setup(VCPU_SREG_CS
);
3758 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3759 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3761 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3762 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3763 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3765 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3766 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3769 seg_setup(VCPU_SREG_DS
);
3770 seg_setup(VCPU_SREG_ES
);
3771 seg_setup(VCPU_SREG_FS
);
3772 seg_setup(VCPU_SREG_GS
);
3773 seg_setup(VCPU_SREG_SS
);
3775 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3776 vmcs_writel(GUEST_TR_BASE
, 0);
3777 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3778 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3780 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3781 vmcs_writel(GUEST_LDTR_BASE
, 0);
3782 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3783 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3785 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3786 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3787 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3789 vmcs_writel(GUEST_RFLAGS
, 0x02);
3790 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3791 kvm_rip_write(vcpu
, 0xfff0);
3793 kvm_rip_write(vcpu
, 0);
3794 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3796 vmcs_writel(GUEST_DR7
, 0x400);
3798 vmcs_writel(GUEST_GDTR_BASE
, 0);
3799 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3801 vmcs_writel(GUEST_IDTR_BASE
, 0);
3802 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3804 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3805 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3806 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3808 /* Special registers */
3809 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
3813 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
3815 if (cpu_has_vmx_tpr_shadow()) {
3816 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
3817 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
3818 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
3819 __pa(vmx
->vcpu
.arch
.apic
->regs
));
3820 vmcs_write32(TPR_THRESHOLD
, 0);
3823 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3824 vmcs_write64(APIC_ACCESS_ADDR
,
3825 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
3828 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
3830 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
3831 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
3832 vmx_set_cr4(&vmx
->vcpu
, 0);
3833 vmx_set_efer(&vmx
->vcpu
, 0);
3834 vmx_fpu_activate(&vmx
->vcpu
);
3835 update_exception_bitmap(&vmx
->vcpu
);
3837 vpid_sync_context(vmx
);
3841 /* HACK: Don't enable emulation on guest boot/reset */
3842 vmx
->emulation_required
= 0;
3849 * In nested virtualization, check if L1 asked to exit on external interrupts.
3850 * For most existing hypervisors, this will always return true.
3852 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
3854 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
3855 PIN_BASED_EXT_INTR_MASK
;
3858 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3860 u32 cpu_based_vm_exec_control
;
3861 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
3862 /* We can get here when nested_run_pending caused
3863 * vmx_interrupt_allowed() to return false. In this case, do
3864 * nothing - the interrupt will be injected later.
3868 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3869 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
3870 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3873 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3875 u32 cpu_based_vm_exec_control
;
3877 if (!cpu_has_virtual_nmis()) {
3878 enable_irq_window(vcpu
);
3882 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
3883 enable_irq_window(vcpu
);
3886 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3887 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
3888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3891 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
3893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3895 int irq
= vcpu
->arch
.interrupt
.nr
;
3897 trace_kvm_inj_virq(irq
);
3899 ++vcpu
->stat
.irq_injections
;
3900 if (vmx
->rmode
.vm86_active
) {
3902 if (vcpu
->arch
.interrupt
.soft
)
3903 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
3904 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
3905 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3908 intr
= irq
| INTR_INFO_VALID_MASK
;
3909 if (vcpu
->arch
.interrupt
.soft
) {
3910 intr
|= INTR_TYPE_SOFT_INTR
;
3911 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
3912 vmx
->vcpu
.arch
.event_exit_inst_len
);
3914 intr
|= INTR_TYPE_EXT_INTR
;
3915 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
3916 vmx_clear_hlt(vcpu
);
3919 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
3921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3923 if (is_guest_mode(vcpu
))
3926 if (!cpu_has_virtual_nmis()) {
3928 * Tracking the NMI-blocked state in software is built upon
3929 * finding the next open IRQ window. This, in turn, depends on
3930 * well-behaving guests: They have to keep IRQs disabled at
3931 * least as long as the NMI handler runs. Otherwise we may
3932 * cause NMI nesting, maybe breaking the guest. But as this is
3933 * highly unlikely, we can live with the residual risk.
3935 vmx
->soft_vnmi_blocked
= 1;
3936 vmx
->vnmi_blocked_time
= 0;
3939 ++vcpu
->stat
.nmi_injections
;
3940 vmx
->nmi_known_unmasked
= false;
3941 if (vmx
->rmode
.vm86_active
) {
3942 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
3943 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3946 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
3947 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
3948 vmx_clear_hlt(vcpu
);
3951 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
3953 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
3956 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3957 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
3958 | GUEST_INTR_STATE_NMI
));
3961 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3963 if (!cpu_has_virtual_nmis())
3964 return to_vmx(vcpu
)->soft_vnmi_blocked
;
3965 if (to_vmx(vcpu
)->nmi_known_unmasked
)
3967 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
3970 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3974 if (!cpu_has_virtual_nmis()) {
3975 if (vmx
->soft_vnmi_blocked
!= masked
) {
3976 vmx
->soft_vnmi_blocked
= masked
;
3977 vmx
->vnmi_blocked_time
= 0;
3980 vmx
->nmi_known_unmasked
= !masked
;
3982 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3983 GUEST_INTR_STATE_NMI
);
3985 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3986 GUEST_INTR_STATE_NMI
);
3990 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3992 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
3993 struct vmcs12
*vmcs12
;
3994 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
3996 nested_vmx_vmexit(vcpu
);
3997 vmcs12
= get_vmcs12(vcpu
);
3998 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
3999 vmcs12
->vm_exit_intr_info
= 0;
4000 /* fall through to normal code, but now in L1, not L2 */
4003 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4004 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4005 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4008 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4011 struct kvm_userspace_memory_region tss_mem
= {
4012 .slot
= TSS_PRIVATE_MEMSLOT
,
4013 .guest_phys_addr
= addr
,
4014 .memory_size
= PAGE_SIZE
* 3,
4018 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
4021 kvm
->arch
.tss_addr
= addr
;
4022 if (!init_rmode_tss(kvm
))
4028 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4029 int vec
, u32 err_code
)
4032 * Instruction with address size override prefix opcode 0x67
4033 * Cause the #SS fault with 0 error code in VM86 mode.
4035 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
4036 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
4039 * Forward all other exceptions that are valid in real mode.
4040 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4041 * the required debugging infrastructure rework.
4045 if (vcpu
->guest_debug
&
4046 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4048 kvm_queue_exception(vcpu
, vec
);
4052 * Update instruction length as we may reinject the exception
4053 * from user space while in guest debugging mode.
4055 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4056 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4057 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4068 kvm_queue_exception(vcpu
, vec
);
4075 * Trigger machine check on the host. We assume all the MSRs are already set up
4076 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4077 * We pass a fake environment to the machine check handler because we want
4078 * the guest to be always treated like user space, no matter what context
4079 * it used internally.
4081 static void kvm_machine_check(void)
4083 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4084 struct pt_regs regs
= {
4085 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4086 .flags
= X86_EFLAGS_IF
,
4089 do_machine_check(®s
, 0);
4093 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4095 /* already handled by vcpu_run */
4099 static int handle_exception(struct kvm_vcpu
*vcpu
)
4101 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4102 struct kvm_run
*kvm_run
= vcpu
->run
;
4103 u32 intr_info
, ex_no
, error_code
;
4104 unsigned long cr2
, rip
, dr6
;
4106 enum emulation_result er
;
4108 vect_info
= vmx
->idt_vectoring_info
;
4109 intr_info
= vmx
->exit_intr_info
;
4111 if (is_machine_check(intr_info
))
4112 return handle_machine_check(vcpu
);
4114 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4115 !is_page_fault(intr_info
)) {
4116 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4117 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4118 vcpu
->run
->internal
.ndata
= 2;
4119 vcpu
->run
->internal
.data
[0] = vect_info
;
4120 vcpu
->run
->internal
.data
[1] = intr_info
;
4124 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4125 return 1; /* already handled by vmx_vcpu_run() */
4127 if (is_no_device(intr_info
)) {
4128 vmx_fpu_activate(vcpu
);
4132 if (is_invalid_opcode(intr_info
)) {
4133 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4134 if (er
!= EMULATE_DONE
)
4135 kvm_queue_exception(vcpu
, UD_VECTOR
);
4140 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4141 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4142 if (is_page_fault(intr_info
)) {
4143 /* EPT won't cause page fault directly */
4145 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4146 trace_kvm_page_fault(cr2
, error_code
);
4148 if (kvm_event_needs_reinjection(vcpu
))
4149 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4150 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4153 if (vmx
->rmode
.vm86_active
&&
4154 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
4156 if (vcpu
->arch
.halt_request
) {
4157 vcpu
->arch
.halt_request
= 0;
4158 return kvm_emulate_halt(vcpu
);
4163 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4166 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4167 if (!(vcpu
->guest_debug
&
4168 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4169 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4170 kvm_queue_exception(vcpu
, DB_VECTOR
);
4173 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4174 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4178 * Update instruction length as we may reinject #BP from
4179 * user space while in guest debugging mode. Reading it for
4180 * #DB as well causes no harm, it is not used in that case.
4182 vmx
->vcpu
.arch
.event_exit_inst_len
=
4183 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4184 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4185 rip
= kvm_rip_read(vcpu
);
4186 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4187 kvm_run
->debug
.arch
.exception
= ex_no
;
4190 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4191 kvm_run
->ex
.exception
= ex_no
;
4192 kvm_run
->ex
.error_code
= error_code
;
4198 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4200 ++vcpu
->stat
.irq_exits
;
4204 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4206 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4210 static int handle_io(struct kvm_vcpu
*vcpu
)
4212 unsigned long exit_qualification
;
4213 int size
, in
, string
;
4216 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4217 string
= (exit_qualification
& 16) != 0;
4218 in
= (exit_qualification
& 8) != 0;
4220 ++vcpu
->stat
.io_exits
;
4223 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4225 port
= exit_qualification
>> 16;
4226 size
= (exit_qualification
& 7) + 1;
4227 skip_emulated_instruction(vcpu
);
4229 return kvm_fast_pio_out(vcpu
, size
, port
);
4233 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4236 * Patch in the VMCALL instruction:
4238 hypercall
[0] = 0x0f;
4239 hypercall
[1] = 0x01;
4240 hypercall
[2] = 0xc1;
4243 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4244 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4246 if (to_vmx(vcpu
)->nested
.vmxon
&&
4247 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4250 if (is_guest_mode(vcpu
)) {
4252 * We get here when L2 changed cr0 in a way that did not change
4253 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4254 * but did change L0 shadowed bits. This can currently happen
4255 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4256 * loading) while pretending to allow the guest to change it.
4258 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4259 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4261 vmcs_writel(CR0_READ_SHADOW
, val
);
4264 return kvm_set_cr0(vcpu
, val
);
4267 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4269 if (is_guest_mode(vcpu
)) {
4270 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4271 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4273 vmcs_writel(CR4_READ_SHADOW
, val
);
4276 return kvm_set_cr4(vcpu
, val
);
4279 /* called to set cr0 as approriate for clts instruction exit. */
4280 static void handle_clts(struct kvm_vcpu
*vcpu
)
4282 if (is_guest_mode(vcpu
)) {
4284 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4285 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4286 * just pretend it's off (also in arch.cr0 for fpu_activate).
4288 vmcs_writel(CR0_READ_SHADOW
,
4289 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4290 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4292 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4295 static int handle_cr(struct kvm_vcpu
*vcpu
)
4297 unsigned long exit_qualification
, val
;
4302 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4303 cr
= exit_qualification
& 15;
4304 reg
= (exit_qualification
>> 8) & 15;
4305 switch ((exit_qualification
>> 4) & 3) {
4306 case 0: /* mov to cr */
4307 val
= kvm_register_read(vcpu
, reg
);
4308 trace_kvm_cr_write(cr
, val
);
4311 err
= handle_set_cr0(vcpu
, val
);
4312 kvm_complete_insn_gp(vcpu
, err
);
4315 err
= kvm_set_cr3(vcpu
, val
);
4316 kvm_complete_insn_gp(vcpu
, err
);
4319 err
= handle_set_cr4(vcpu
, val
);
4320 kvm_complete_insn_gp(vcpu
, err
);
4323 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4324 u8 cr8
= kvm_register_read(vcpu
, reg
);
4325 err
= kvm_set_cr8(vcpu
, cr8
);
4326 kvm_complete_insn_gp(vcpu
, err
);
4327 if (irqchip_in_kernel(vcpu
->kvm
))
4329 if (cr8_prev
<= cr8
)
4331 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4338 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4339 skip_emulated_instruction(vcpu
);
4340 vmx_fpu_activate(vcpu
);
4342 case 1: /*mov from cr*/
4345 val
= kvm_read_cr3(vcpu
);
4346 kvm_register_write(vcpu
, reg
, val
);
4347 trace_kvm_cr_read(cr
, val
);
4348 skip_emulated_instruction(vcpu
);
4351 val
= kvm_get_cr8(vcpu
);
4352 kvm_register_write(vcpu
, reg
, val
);
4353 trace_kvm_cr_read(cr
, val
);
4354 skip_emulated_instruction(vcpu
);
4359 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4360 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4361 kvm_lmsw(vcpu
, val
);
4363 skip_emulated_instruction(vcpu
);
4368 vcpu
->run
->exit_reason
= 0;
4369 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4370 (int)(exit_qualification
>> 4) & 3, cr
);
4374 static int handle_dr(struct kvm_vcpu
*vcpu
)
4376 unsigned long exit_qualification
;
4379 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4380 if (!kvm_require_cpl(vcpu
, 0))
4382 dr
= vmcs_readl(GUEST_DR7
);
4385 * As the vm-exit takes precedence over the debug trap, we
4386 * need to emulate the latter, either for the host or the
4387 * guest debugging itself.
4389 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4390 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4391 vcpu
->run
->debug
.arch
.dr7
= dr
;
4392 vcpu
->run
->debug
.arch
.pc
=
4393 vmcs_readl(GUEST_CS_BASE
) +
4394 vmcs_readl(GUEST_RIP
);
4395 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4396 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4399 vcpu
->arch
.dr7
&= ~DR7_GD
;
4400 vcpu
->arch
.dr6
|= DR6_BD
;
4401 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4402 kvm_queue_exception(vcpu
, DB_VECTOR
);
4407 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4408 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4409 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4410 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4412 if (!kvm_get_dr(vcpu
, dr
, &val
))
4413 kvm_register_write(vcpu
, reg
, val
);
4415 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4416 skip_emulated_instruction(vcpu
);
4420 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4422 vmcs_writel(GUEST_DR7
, val
);
4425 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4427 kvm_emulate_cpuid(vcpu
);
4431 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4433 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4436 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4437 trace_kvm_msr_read_ex(ecx
);
4438 kvm_inject_gp(vcpu
, 0);
4442 trace_kvm_msr_read(ecx
, data
);
4444 /* FIXME: handling of bits 32:63 of rax, rdx */
4445 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4446 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4447 skip_emulated_instruction(vcpu
);
4451 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4453 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4454 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4455 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4457 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
4458 trace_kvm_msr_write_ex(ecx
, data
);
4459 kvm_inject_gp(vcpu
, 0);
4463 trace_kvm_msr_write(ecx
, data
);
4464 skip_emulated_instruction(vcpu
);
4468 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4470 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4474 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4476 u32 cpu_based_vm_exec_control
;
4478 /* clear pending irq */
4479 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4480 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4481 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4483 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4485 ++vcpu
->stat
.irq_window_exits
;
4488 * If the user space waits to inject interrupts, exit as soon as
4491 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4492 vcpu
->run
->request_interrupt_window
&&
4493 !kvm_cpu_has_interrupt(vcpu
)) {
4494 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4500 static int handle_halt(struct kvm_vcpu
*vcpu
)
4502 skip_emulated_instruction(vcpu
);
4503 return kvm_emulate_halt(vcpu
);
4506 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4508 skip_emulated_instruction(vcpu
);
4509 kvm_emulate_hypercall(vcpu
);
4513 static int handle_invd(struct kvm_vcpu
*vcpu
)
4515 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4518 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4520 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4522 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4523 skip_emulated_instruction(vcpu
);
4527 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4529 skip_emulated_instruction(vcpu
);
4530 kvm_emulate_wbinvd(vcpu
);
4534 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4536 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4537 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4539 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4540 skip_emulated_instruction(vcpu
);
4544 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4546 if (likely(fasteoi
)) {
4547 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4548 int access_type
, offset
;
4550 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4551 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4553 * Sane guest uses MOV to write EOI, with written value
4554 * not cared. So make a short-circuit here by avoiding
4555 * heavy instruction emulation.
4557 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4558 (offset
== APIC_EOI
)) {
4559 kvm_lapic_set_eoi(vcpu
);
4560 skip_emulated_instruction(vcpu
);
4564 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4567 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4569 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4570 unsigned long exit_qualification
;
4571 bool has_error_code
= false;
4574 int reason
, type
, idt_v
;
4576 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4577 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4579 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4581 reason
= (u32
)exit_qualification
>> 30;
4582 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4584 case INTR_TYPE_NMI_INTR
:
4585 vcpu
->arch
.nmi_injected
= false;
4586 vmx_set_nmi_mask(vcpu
, true);
4588 case INTR_TYPE_EXT_INTR
:
4589 case INTR_TYPE_SOFT_INTR
:
4590 kvm_clear_interrupt_queue(vcpu
);
4592 case INTR_TYPE_HARD_EXCEPTION
:
4593 if (vmx
->idt_vectoring_info
&
4594 VECTORING_INFO_DELIVER_CODE_MASK
) {
4595 has_error_code
= true;
4597 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4600 case INTR_TYPE_SOFT_EXCEPTION
:
4601 kvm_clear_exception_queue(vcpu
);
4607 tss_selector
= exit_qualification
;
4609 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4610 type
!= INTR_TYPE_EXT_INTR
&&
4611 type
!= INTR_TYPE_NMI_INTR
))
4612 skip_emulated_instruction(vcpu
);
4614 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
4615 has_error_code
, error_code
) == EMULATE_FAIL
) {
4616 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4617 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4618 vcpu
->run
->internal
.ndata
= 0;
4622 /* clear all local breakpoint enable flags */
4623 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4626 * TODO: What about debug traps on tss switch?
4627 * Are we supposed to inject them and update dr6?
4633 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4635 unsigned long exit_qualification
;
4639 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4641 if (exit_qualification
& (1 << 6)) {
4642 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4646 gla_validity
= (exit_qualification
>> 7) & 0x3;
4647 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4648 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4649 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4650 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4651 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4652 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4653 (long unsigned int)exit_qualification
);
4654 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4655 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4659 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4660 trace_kvm_page_fault(gpa
, exit_qualification
);
4661 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
4664 static u64
ept_rsvd_mask(u64 spte
, int level
)
4669 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4670 mask
|= (1ULL << i
);
4673 /* bits 7:3 reserved */
4675 else if (level
== 2) {
4676 if (spte
& (1ULL << 7))
4677 /* 2MB ref, bits 20:12 reserved */
4680 /* bits 6:3 reserved */
4687 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4690 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4692 /* 010b (write-only) */
4693 WARN_ON((spte
& 0x7) == 0x2);
4695 /* 110b (write/execute) */
4696 WARN_ON((spte
& 0x7) == 0x6);
4698 /* 100b (execute-only) and value not supported by logical processor */
4699 if (!cpu_has_vmx_ept_execute_only())
4700 WARN_ON((spte
& 0x7) == 0x4);
4704 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4706 if (rsvd_bits
!= 0) {
4707 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4708 __func__
, rsvd_bits
);
4712 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4713 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4715 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4716 ept_mem_type
== 7) {
4717 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4718 __func__
, ept_mem_type
);
4725 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4728 int nr_sptes
, i
, ret
;
4731 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4733 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
4734 if (likely(ret
== 1))
4735 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
4740 /* It is the real ept misconfig */
4741 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4742 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4744 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4746 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4747 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4749 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4750 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4755 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4757 u32 cpu_based_vm_exec_control
;
4759 /* clear pending NMI */
4760 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4761 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4762 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4763 ++vcpu
->stat
.nmi_window_exits
;
4764 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4769 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4772 enum emulation_result err
= EMULATE_DONE
;
4775 bool intr_window_requested
;
4777 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4778 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4780 while (!guest_state_valid(vcpu
)) {
4781 if (intr_window_requested
4782 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
4783 return handle_interrupt_window(&vmx
->vcpu
);
4785 err
= emulate_instruction(vcpu
, 0);
4787 if (err
== EMULATE_DO_MMIO
) {
4792 if (err
!= EMULATE_DONE
)
4795 if (signal_pending(current
))
4801 vmx
->emulation_required
= 0;
4807 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4808 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4810 static int handle_pause(struct kvm_vcpu
*vcpu
)
4812 skip_emulated_instruction(vcpu
);
4813 kvm_vcpu_on_spin(vcpu
);
4818 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
4820 kvm_queue_exception(vcpu
, UD_VECTOR
);
4825 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4826 * We could reuse a single VMCS for all the L2 guests, but we also want the
4827 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4828 * allows keeping them loaded on the processor, and in the future will allow
4829 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4830 * every entry if they never change.
4831 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4832 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4834 * The following functions allocate and free a vmcs02 in this pool.
4837 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4838 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
4840 struct vmcs02_list
*item
;
4841 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4842 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
4843 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4844 return &item
->vmcs02
;
4847 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
4848 /* Recycle the least recently used VMCS. */
4849 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
4850 struct vmcs02_list
, list
);
4851 item
->vmptr
= vmx
->nested
.current_vmptr
;
4852 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4853 return &item
->vmcs02
;
4856 /* Create a new VMCS */
4857 item
= (struct vmcs02_list
*)
4858 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
4861 item
->vmcs02
.vmcs
= alloc_vmcs();
4862 if (!item
->vmcs02
.vmcs
) {
4866 loaded_vmcs_init(&item
->vmcs02
);
4867 item
->vmptr
= vmx
->nested
.current_vmptr
;
4868 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
4869 vmx
->nested
.vmcs02_num
++;
4870 return &item
->vmcs02
;
4873 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4874 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
4876 struct vmcs02_list
*item
;
4877 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4878 if (item
->vmptr
== vmptr
) {
4879 free_loaded_vmcs(&item
->vmcs02
);
4880 list_del(&item
->list
);
4882 vmx
->nested
.vmcs02_num
--;
4888 * Free all VMCSs saved for this vcpu, except the one pointed by
4889 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4890 * currently used, if running L2), and vmcs01 when running L2.
4892 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
4894 struct vmcs02_list
*item
, *n
;
4895 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
4896 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
4897 free_loaded_vmcs(&item
->vmcs02
);
4898 list_del(&item
->list
);
4901 vmx
->nested
.vmcs02_num
= 0;
4903 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
4904 free_loaded_vmcs(&vmx
->vmcs01
);
4908 * Emulate the VMXON instruction.
4909 * Currently, we just remember that VMX is active, and do not save or even
4910 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4911 * do not currently need to store anything in that guest-allocated memory
4912 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4913 * argument is different from the VMXON pointer (which the spec says they do).
4915 static int handle_vmon(struct kvm_vcpu
*vcpu
)
4917 struct kvm_segment cs
;
4918 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4920 /* The Intel VMX Instruction Reference lists a bunch of bits that
4921 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4922 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4923 * Otherwise, we should fail with #UD. We test these now:
4925 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
4926 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
4927 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4928 kvm_queue_exception(vcpu
, UD_VECTOR
);
4932 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4933 if (is_long_mode(vcpu
) && !cs
.l
) {
4934 kvm_queue_exception(vcpu
, UD_VECTOR
);
4938 if (vmx_get_cpl(vcpu
)) {
4939 kvm_inject_gp(vcpu
, 0);
4943 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
4944 vmx
->nested
.vmcs02_num
= 0;
4946 vmx
->nested
.vmxon
= true;
4948 skip_emulated_instruction(vcpu
);
4953 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4954 * for running VMX instructions (except VMXON, whose prerequisites are
4955 * slightly different). It also specifies what exception to inject otherwise.
4957 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
4959 struct kvm_segment cs
;
4960 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4962 if (!vmx
->nested
.vmxon
) {
4963 kvm_queue_exception(vcpu
, UD_VECTOR
);
4967 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4968 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
4969 (is_long_mode(vcpu
) && !cs
.l
)) {
4970 kvm_queue_exception(vcpu
, UD_VECTOR
);
4974 if (vmx_get_cpl(vcpu
)) {
4975 kvm_inject_gp(vcpu
, 0);
4983 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4984 * just stops using VMX.
4986 static void free_nested(struct vcpu_vmx
*vmx
)
4988 if (!vmx
->nested
.vmxon
)
4990 vmx
->nested
.vmxon
= false;
4991 if (vmx
->nested
.current_vmptr
!= -1ull) {
4992 kunmap(vmx
->nested
.current_vmcs12_page
);
4993 nested_release_page(vmx
->nested
.current_vmcs12_page
);
4994 vmx
->nested
.current_vmptr
= -1ull;
4995 vmx
->nested
.current_vmcs12
= NULL
;
4997 /* Unpin physical memory we referred to in current vmcs02 */
4998 if (vmx
->nested
.apic_access_page
) {
4999 nested_release_page(vmx
->nested
.apic_access_page
);
5000 vmx
->nested
.apic_access_page
= 0;
5003 nested_free_all_saved_vmcss(vmx
);
5006 /* Emulate the VMXOFF instruction */
5007 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5009 if (!nested_vmx_check_permission(vcpu
))
5011 free_nested(to_vmx(vcpu
));
5012 skip_emulated_instruction(vcpu
);
5017 * Decode the memory-address operand of a vmx instruction, as recorded on an
5018 * exit caused by such an instruction (run by a guest hypervisor).
5019 * On success, returns 0. When the operand is invalid, returns 1 and throws
5022 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5023 unsigned long exit_qualification
,
5024 u32 vmx_instruction_info
, gva_t
*ret
)
5027 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5028 * Execution", on an exit, vmx_instruction_info holds most of the
5029 * addressing components of the operand. Only the displacement part
5030 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5031 * For how an actual address is calculated from all these components,
5032 * refer to Vol. 1, "Operand Addressing".
5034 int scaling
= vmx_instruction_info
& 3;
5035 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5036 bool is_reg
= vmx_instruction_info
& (1u << 10);
5037 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5038 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5039 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5040 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5041 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5044 kvm_queue_exception(vcpu
, UD_VECTOR
);
5048 /* Addr = segment_base + offset */
5049 /* offset = base + [index * scale] + displacement */
5050 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5052 *ret
+= kvm_register_read(vcpu
, base_reg
);
5054 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5055 *ret
+= exit_qualification
; /* holds the displacement */
5057 if (addr_size
== 1) /* 32 bit */
5061 * TODO: throw #GP (and return 1) in various cases that the VM*
5062 * instructions require it - e.g., offset beyond segment limit,
5063 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5064 * address, and so on. Currently these are not checked.
5070 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5071 * set the success or error code of an emulated VMX instruction, as specified
5072 * by Vol 2B, VMX Instruction Reference, "Conventions".
5074 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5076 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5077 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5078 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5081 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5083 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5084 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5085 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5089 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5090 u32 vm_instruction_error
)
5092 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5094 * failValid writes the error number to the current VMCS, which
5095 * can't be done there isn't a current VMCS.
5097 nested_vmx_failInvalid(vcpu
);
5100 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5101 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5102 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5104 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5107 /* Emulate the VMCLEAR instruction */
5108 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5110 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5113 struct vmcs12
*vmcs12
;
5115 struct x86_exception e
;
5117 if (!nested_vmx_check_permission(vcpu
))
5120 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5121 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5124 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5125 sizeof(vmptr
), &e
)) {
5126 kvm_inject_page_fault(vcpu
, &e
);
5130 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5131 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5132 skip_emulated_instruction(vcpu
);
5136 if (vmptr
== vmx
->nested
.current_vmptr
) {
5137 kunmap(vmx
->nested
.current_vmcs12_page
);
5138 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5139 vmx
->nested
.current_vmptr
= -1ull;
5140 vmx
->nested
.current_vmcs12
= NULL
;
5143 page
= nested_get_page(vcpu
, vmptr
);
5146 * For accurate processor emulation, VMCLEAR beyond available
5147 * physical memory should do nothing at all. However, it is
5148 * possible that a nested vmx bug, not a guest hypervisor bug,
5149 * resulted in this case, so let's shut down before doing any
5152 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5155 vmcs12
= kmap(page
);
5156 vmcs12
->launch_state
= 0;
5158 nested_release_page(page
);
5160 nested_free_vmcs02(vmx
, vmptr
);
5162 skip_emulated_instruction(vcpu
);
5163 nested_vmx_succeed(vcpu
);
5167 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5169 /* Emulate the VMLAUNCH instruction */
5170 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5172 return nested_vmx_run(vcpu
, true);
5175 /* Emulate the VMRESUME instruction */
5176 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5179 return nested_vmx_run(vcpu
, false);
5182 enum vmcs_field_type
{
5183 VMCS_FIELD_TYPE_U16
= 0,
5184 VMCS_FIELD_TYPE_U64
= 1,
5185 VMCS_FIELD_TYPE_U32
= 2,
5186 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5189 static inline int vmcs_field_type(unsigned long field
)
5191 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5192 return VMCS_FIELD_TYPE_U32
;
5193 return (field
>> 13) & 0x3 ;
5196 static inline int vmcs_field_readonly(unsigned long field
)
5198 return (((field
>> 10) & 0x3) == 1);
5202 * Read a vmcs12 field. Since these can have varying lengths and we return
5203 * one type, we chose the biggest type (u64) and zero-extend the return value
5204 * to that size. Note that the caller, handle_vmread, might need to use only
5205 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5206 * 64-bit fields are to be returned).
5208 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5209 unsigned long field
, u64
*ret
)
5211 short offset
= vmcs_field_to_offset(field
);
5217 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5219 switch (vmcs_field_type(field
)) {
5220 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5221 *ret
= *((natural_width
*)p
);
5223 case VMCS_FIELD_TYPE_U16
:
5226 case VMCS_FIELD_TYPE_U32
:
5229 case VMCS_FIELD_TYPE_U64
:
5233 return 0; /* can never happen. */
5238 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5239 * used before) all generate the same failure when it is missing.
5241 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5243 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5244 if (vmx
->nested
.current_vmptr
== -1ull) {
5245 nested_vmx_failInvalid(vcpu
);
5246 skip_emulated_instruction(vcpu
);
5252 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5254 unsigned long field
;
5256 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5257 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5260 if (!nested_vmx_check_permission(vcpu
) ||
5261 !nested_vmx_check_vmcs12(vcpu
))
5264 /* Decode instruction info and find the field to read */
5265 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5266 /* Read the field, zero-extended to a u64 field_value */
5267 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5268 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5269 skip_emulated_instruction(vcpu
);
5273 * Now copy part of this value to register or memory, as requested.
5274 * Note that the number of bits actually copied is 32 or 64 depending
5275 * on the guest's mode (32 or 64 bit), not on the given field's length.
5277 if (vmx_instruction_info
& (1u << 10)) {
5278 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5281 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5282 vmx_instruction_info
, &gva
))
5284 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5285 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5286 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5289 nested_vmx_succeed(vcpu
);
5290 skip_emulated_instruction(vcpu
);
5295 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5297 unsigned long field
;
5299 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5300 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5303 /* The value to write might be 32 or 64 bits, depending on L1's long
5304 * mode, and eventually we need to write that into a field of several
5305 * possible lengths. The code below first zero-extends the value to 64
5306 * bit (field_value), and then copies only the approriate number of
5307 * bits into the vmcs12 field.
5309 u64 field_value
= 0;
5310 struct x86_exception e
;
5312 if (!nested_vmx_check_permission(vcpu
) ||
5313 !nested_vmx_check_vmcs12(vcpu
))
5316 if (vmx_instruction_info
& (1u << 10))
5317 field_value
= kvm_register_read(vcpu
,
5318 (((vmx_instruction_info
) >> 3) & 0xf));
5320 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5321 vmx_instruction_info
, &gva
))
5323 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5324 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5325 kvm_inject_page_fault(vcpu
, &e
);
5331 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5332 if (vmcs_field_readonly(field
)) {
5333 nested_vmx_failValid(vcpu
,
5334 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5335 skip_emulated_instruction(vcpu
);
5339 offset
= vmcs_field_to_offset(field
);
5341 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5342 skip_emulated_instruction(vcpu
);
5345 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5347 switch (vmcs_field_type(field
)) {
5348 case VMCS_FIELD_TYPE_U16
:
5349 *(u16
*)p
= field_value
;
5351 case VMCS_FIELD_TYPE_U32
:
5352 *(u32
*)p
= field_value
;
5354 case VMCS_FIELD_TYPE_U64
:
5355 *(u64
*)p
= field_value
;
5357 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5358 *(natural_width
*)p
= field_value
;
5361 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5362 skip_emulated_instruction(vcpu
);
5366 nested_vmx_succeed(vcpu
);
5367 skip_emulated_instruction(vcpu
);
5371 /* Emulate the VMPTRLD instruction */
5372 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5377 struct x86_exception e
;
5379 if (!nested_vmx_check_permission(vcpu
))
5382 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5383 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5386 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5387 sizeof(vmptr
), &e
)) {
5388 kvm_inject_page_fault(vcpu
, &e
);
5392 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5393 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5394 skip_emulated_instruction(vcpu
);
5398 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5399 struct vmcs12
*new_vmcs12
;
5401 page
= nested_get_page(vcpu
, vmptr
);
5403 nested_vmx_failInvalid(vcpu
);
5404 skip_emulated_instruction(vcpu
);
5407 new_vmcs12
= kmap(page
);
5408 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5410 nested_release_page_clean(page
);
5411 nested_vmx_failValid(vcpu
,
5412 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5413 skip_emulated_instruction(vcpu
);
5416 if (vmx
->nested
.current_vmptr
!= -1ull) {
5417 kunmap(vmx
->nested
.current_vmcs12_page
);
5418 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5421 vmx
->nested
.current_vmptr
= vmptr
;
5422 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5423 vmx
->nested
.current_vmcs12_page
= page
;
5426 nested_vmx_succeed(vcpu
);
5427 skip_emulated_instruction(vcpu
);
5431 /* Emulate the VMPTRST instruction */
5432 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5434 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5435 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5437 struct x86_exception e
;
5439 if (!nested_vmx_check_permission(vcpu
))
5442 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5443 vmx_instruction_info
, &vmcs_gva
))
5445 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5446 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5447 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5449 kvm_inject_page_fault(vcpu
, &e
);
5452 nested_vmx_succeed(vcpu
);
5453 skip_emulated_instruction(vcpu
);
5458 * The exit handlers return 1 if the exit was handled fully and guest execution
5459 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5460 * to be done to userspace and return 0.
5462 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5463 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5464 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5465 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5466 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5467 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5468 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5469 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5470 [EXIT_REASON_CPUID
] = handle_cpuid
,
5471 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5472 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5473 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5474 [EXIT_REASON_HLT
] = handle_halt
,
5475 [EXIT_REASON_INVD
] = handle_invd
,
5476 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5477 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5478 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5479 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5480 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5481 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5482 [EXIT_REASON_VMREAD
] = handle_vmread
,
5483 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5484 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5485 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5486 [EXIT_REASON_VMON
] = handle_vmon
,
5487 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5488 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5489 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5490 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5491 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5492 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5493 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5494 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5495 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5496 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5497 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5500 static const int kvm_vmx_max_exit_handlers
=
5501 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5504 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5505 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5506 * disinterest in the current event (read or write a specific MSR) by using an
5507 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5509 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5510 struct vmcs12
*vmcs12
, u32 exit_reason
)
5512 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5515 if (!nested_cpu_has(get_vmcs12(vcpu
), CPU_BASED_USE_MSR_BITMAPS
))
5519 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5520 * for the four combinations of read/write and low/high MSR numbers.
5521 * First we need to figure out which of the four to use:
5523 bitmap
= vmcs12
->msr_bitmap
;
5524 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5526 if (msr_index
>= 0xc0000000) {
5527 msr_index
-= 0xc0000000;
5531 /* Then read the msr_index'th bit from this bitmap: */
5532 if (msr_index
< 1024*8) {
5534 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5535 return 1 & (b
>> (msr_index
& 7));
5537 return 1; /* let L1 handle the wrong parameter */
5541 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5542 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5543 * intercept (via guest_host_mask etc.) the current event.
5545 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5546 struct vmcs12
*vmcs12
)
5548 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5549 int cr
= exit_qualification
& 15;
5550 int reg
= (exit_qualification
>> 8) & 15;
5551 unsigned long val
= kvm_register_read(vcpu
, reg
);
5553 switch ((exit_qualification
>> 4) & 3) {
5554 case 0: /* mov to cr */
5557 if (vmcs12
->cr0_guest_host_mask
&
5558 (val
^ vmcs12
->cr0_read_shadow
))
5562 if ((vmcs12
->cr3_target_count
>= 1 &&
5563 vmcs12
->cr3_target_value0
== val
) ||
5564 (vmcs12
->cr3_target_count
>= 2 &&
5565 vmcs12
->cr3_target_value1
== val
) ||
5566 (vmcs12
->cr3_target_count
>= 3 &&
5567 vmcs12
->cr3_target_value2
== val
) ||
5568 (vmcs12
->cr3_target_count
>= 4 &&
5569 vmcs12
->cr3_target_value3
== val
))
5571 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5575 if (vmcs12
->cr4_guest_host_mask
&
5576 (vmcs12
->cr4_read_shadow
^ val
))
5580 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5586 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5587 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5590 case 1: /* mov from cr */
5593 if (vmcs12
->cpu_based_vm_exec_control
&
5594 CPU_BASED_CR3_STORE_EXITING
)
5598 if (vmcs12
->cpu_based_vm_exec_control
&
5599 CPU_BASED_CR8_STORE_EXITING
)
5606 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5607 * cr0. Other attempted changes are ignored, with no exit.
5609 if (vmcs12
->cr0_guest_host_mask
& 0xe &
5610 (val
^ vmcs12
->cr0_read_shadow
))
5612 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
5613 !(vmcs12
->cr0_read_shadow
& 0x1) &&
5622 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5623 * should handle it ourselves in L0 (and then continue L2). Only call this
5624 * when in is_guest_mode (L2).
5626 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
5628 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5629 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5631 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5633 if (vmx
->nested
.nested_run_pending
)
5636 if (unlikely(vmx
->fail
)) {
5637 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
5638 vmcs_read32(VM_INSTRUCTION_ERROR
));
5642 switch (exit_reason
) {
5643 case EXIT_REASON_EXCEPTION_NMI
:
5644 if (!is_exception(intr_info
))
5646 else if (is_page_fault(intr_info
))
5648 return vmcs12
->exception_bitmap
&
5649 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
5650 case EXIT_REASON_EXTERNAL_INTERRUPT
:
5652 case EXIT_REASON_TRIPLE_FAULT
:
5654 case EXIT_REASON_PENDING_INTERRUPT
:
5655 case EXIT_REASON_NMI_WINDOW
:
5657 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5658 * (aka Interrupt Window Exiting) only when L1 turned it on,
5659 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5660 * Same for NMI Window Exiting.
5663 case EXIT_REASON_TASK_SWITCH
:
5665 case EXIT_REASON_CPUID
:
5667 case EXIT_REASON_HLT
:
5668 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
5669 case EXIT_REASON_INVD
:
5671 case EXIT_REASON_INVLPG
:
5672 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
5673 case EXIT_REASON_RDPMC
:
5674 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
5675 case EXIT_REASON_RDTSC
:
5676 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
5677 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
5678 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
5679 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
5680 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
5681 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
5683 * VMX instructions trap unconditionally. This allows L1 to
5684 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5687 case EXIT_REASON_CR_ACCESS
:
5688 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
5689 case EXIT_REASON_DR_ACCESS
:
5690 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
5691 case EXIT_REASON_IO_INSTRUCTION
:
5692 /* TODO: support IO bitmaps */
5694 case EXIT_REASON_MSR_READ
:
5695 case EXIT_REASON_MSR_WRITE
:
5696 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
5697 case EXIT_REASON_INVALID_STATE
:
5699 case EXIT_REASON_MWAIT_INSTRUCTION
:
5700 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
5701 case EXIT_REASON_MONITOR_INSTRUCTION
:
5702 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
5703 case EXIT_REASON_PAUSE_INSTRUCTION
:
5704 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
5705 nested_cpu_has2(vmcs12
,
5706 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
5707 case EXIT_REASON_MCE_DURING_VMENTRY
:
5709 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
5711 case EXIT_REASON_APIC_ACCESS
:
5712 return nested_cpu_has2(vmcs12
,
5713 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
5714 case EXIT_REASON_EPT_VIOLATION
:
5715 case EXIT_REASON_EPT_MISCONFIG
:
5717 case EXIT_REASON_WBINVD
:
5718 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
5719 case EXIT_REASON_XSETBV
:
5726 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
5728 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
5729 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
5733 * The guest has exited. See if we can fix it or if we need userspace
5736 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
5738 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5739 u32 exit_reason
= vmx
->exit_reason
;
5740 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5742 /* If guest state is invalid, start emulating */
5743 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5744 return handle_invalid_guest_state(vcpu
);
5747 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5748 * we did not inject a still-pending event to L1 now because of
5749 * nested_run_pending, we need to re-enable this bit.
5751 if (vmx
->nested
.nested_run_pending
)
5752 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5754 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
5755 exit_reason
== EXIT_REASON_VMRESUME
))
5756 vmx
->nested
.nested_run_pending
= 1;
5758 vmx
->nested
.nested_run_pending
= 0;
5760 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
5761 nested_vmx_vmexit(vcpu
);
5765 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
5766 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5767 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5772 if (unlikely(vmx
->fail
)) {
5773 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5774 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5775 = vmcs_read32(VM_INSTRUCTION_ERROR
);
5779 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5780 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
5781 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
5782 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
5783 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
5784 "(0x%x) and exit reason is 0x%x\n",
5785 __func__
, vectoring_info
, exit_reason
);
5787 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
5788 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
5789 get_vmcs12(vcpu
), vcpu
)))) {
5790 if (vmx_interrupt_allowed(vcpu
)) {
5791 vmx
->soft_vnmi_blocked
= 0;
5792 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
5793 vcpu
->arch
.nmi_pending
) {
5795 * This CPU don't support us in finding the end of an
5796 * NMI-blocked window if the guest runs with IRQs
5797 * disabled. So we pull the trigger after 1 s of
5798 * futile waiting, but inform the user about this.
5800 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
5801 "state on VCPU %d after 1 s timeout\n",
5802 __func__
, vcpu
->vcpu_id
);
5803 vmx
->soft_vnmi_blocked
= 0;
5807 if (exit_reason
< kvm_vmx_max_exit_handlers
5808 && kvm_vmx_exit_handlers
[exit_reason
])
5809 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
5811 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5812 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
5817 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5819 if (irr
== -1 || tpr
< irr
) {
5820 vmcs_write32(TPR_THRESHOLD
, 0);
5824 vmcs_write32(TPR_THRESHOLD
, irr
);
5827 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
5831 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
5832 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
5835 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5836 exit_intr_info
= vmx
->exit_intr_info
;
5838 /* Handle machine checks before interrupts are enabled */
5839 if (is_machine_check(exit_intr_info
))
5840 kvm_machine_check();
5842 /* We need to handle NMIs before interrupts are enabled */
5843 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
5844 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
5845 kvm_before_handle_nmi(&vmx
->vcpu
);
5847 kvm_after_handle_nmi(&vmx
->vcpu
);
5851 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
5856 bool idtv_info_valid
;
5858 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5860 if (cpu_has_virtual_nmis()) {
5861 if (vmx
->nmi_known_unmasked
)
5864 * Can't use vmx->exit_intr_info since we're not sure what
5865 * the exit reason is.
5867 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5868 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
5869 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
5871 * SDM 3: 27.7.1.2 (September 2008)
5872 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5873 * a guest IRET fault.
5874 * SDM 3: 23.2.2 (September 2008)
5875 * Bit 12 is undefined in any of the following cases:
5876 * If the VM exit sets the valid bit in the IDT-vectoring
5877 * information field.
5878 * If the VM exit is due to a double fault.
5880 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
5881 vector
!= DF_VECTOR
&& !idtv_info_valid
)
5882 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5883 GUEST_INTR_STATE_NMI
);
5885 vmx
->nmi_known_unmasked
=
5886 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
5887 & GUEST_INTR_STATE_NMI
);
5888 } else if (unlikely(vmx
->soft_vnmi_blocked
))
5889 vmx
->vnmi_blocked_time
+=
5890 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
5893 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
5894 u32 idt_vectoring_info
,
5895 int instr_len_field
,
5896 int error_code_field
)
5900 bool idtv_info_valid
;
5902 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5904 vmx
->vcpu
.arch
.nmi_injected
= false;
5905 kvm_clear_exception_queue(&vmx
->vcpu
);
5906 kvm_clear_interrupt_queue(&vmx
->vcpu
);
5908 if (!idtv_info_valid
)
5911 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5913 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
5914 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
5917 case INTR_TYPE_NMI_INTR
:
5918 vmx
->vcpu
.arch
.nmi_injected
= true;
5920 * SDM 3: 27.7.1.2 (September 2008)
5921 * Clear bit "block by NMI" before VM entry if a NMI
5924 vmx_set_nmi_mask(&vmx
->vcpu
, false);
5926 case INTR_TYPE_SOFT_EXCEPTION
:
5927 vmx
->vcpu
.arch
.event_exit_inst_len
=
5928 vmcs_read32(instr_len_field
);
5930 case INTR_TYPE_HARD_EXCEPTION
:
5931 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
5932 u32 err
= vmcs_read32(error_code_field
);
5933 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
5935 kvm_queue_exception(&vmx
->vcpu
, vector
);
5937 case INTR_TYPE_SOFT_INTR
:
5938 vmx
->vcpu
.arch
.event_exit_inst_len
=
5939 vmcs_read32(instr_len_field
);
5941 case INTR_TYPE_EXT_INTR
:
5942 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
5943 type
== INTR_TYPE_SOFT_INTR
);
5950 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
5952 if (is_guest_mode(&vmx
->vcpu
))
5954 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
5955 VM_EXIT_INSTRUCTION_LEN
,
5956 IDT_VECTORING_ERROR_CODE
);
5959 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
5961 if (is_guest_mode(vcpu
))
5963 __vmx_complete_interrupts(to_vmx(vcpu
),
5964 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
5965 VM_ENTRY_INSTRUCTION_LEN
,
5966 VM_ENTRY_EXCEPTION_ERROR_CODE
);
5968 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
5971 #ifdef CONFIG_X86_64
5979 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
5981 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5983 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
5984 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5985 if (vmcs12
->idt_vectoring_info_field
&
5986 VECTORING_INFO_VALID_MASK
) {
5987 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5988 vmcs12
->idt_vectoring_info_field
);
5989 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5990 vmcs12
->vm_exit_instruction_len
);
5991 if (vmcs12
->idt_vectoring_info_field
&
5992 VECTORING_INFO_DELIVER_CODE_MASK
)
5993 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
5994 vmcs12
->idt_vectoring_error_code
);
5998 /* Record the guest's net vcpu time for enforced NMI injections. */
5999 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6000 vmx
->entry_time
= ktime_get();
6002 /* Don't enter VMX if guest state is invalid, let the exit handler
6003 start emulation until we arrive back to a valid state */
6004 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
6007 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6008 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6009 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6010 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6012 /* When single-stepping over STI and MOV SS, we must clear the
6013 * corresponding interruptibility bits in the guest state. Otherwise
6014 * vmentry fails as it then expects bit 14 (BS) in pending debug
6015 * exceptions being set, but that's not correct for the guest debugging
6017 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6018 vmx_set_interrupt_shadow(vcpu
, 0);
6020 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6022 /* Store host registers */
6023 "push %%"R
"dx; push %%"R
"bp;"
6024 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
6026 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
6028 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
6029 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6031 /* Reload cr2 if changed */
6032 "mov %c[cr2](%0), %%"R
"ax \n\t"
6033 "mov %%cr2, %%"R
"dx \n\t"
6034 "cmp %%"R
"ax, %%"R
"dx \n\t"
6036 "mov %%"R
"ax, %%cr2 \n\t"
6038 /* Check if vmlaunch of vmresume is needed */
6039 "cmpl $0, %c[launched](%0) \n\t"
6040 /* Load guest registers. Don't clobber flags. */
6041 "mov %c[rax](%0), %%"R
"ax \n\t"
6042 "mov %c[rbx](%0), %%"R
"bx \n\t"
6043 "mov %c[rdx](%0), %%"R
"dx \n\t"
6044 "mov %c[rsi](%0), %%"R
"si \n\t"
6045 "mov %c[rdi](%0), %%"R
"di \n\t"
6046 "mov %c[rbp](%0), %%"R
"bp \n\t"
6047 #ifdef CONFIG_X86_64
6048 "mov %c[r8](%0), %%r8 \n\t"
6049 "mov %c[r9](%0), %%r9 \n\t"
6050 "mov %c[r10](%0), %%r10 \n\t"
6051 "mov %c[r11](%0), %%r11 \n\t"
6052 "mov %c[r12](%0), %%r12 \n\t"
6053 "mov %c[r13](%0), %%r13 \n\t"
6054 "mov %c[r14](%0), %%r14 \n\t"
6055 "mov %c[r15](%0), %%r15 \n\t"
6057 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
6059 /* Enter guest mode */
6060 "jne .Llaunched \n\t"
6061 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6062 "jmp .Lkvm_vmx_return \n\t"
6063 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6064 ".Lkvm_vmx_return: "
6065 /* Save guest registers, load host registers, keep flags */
6066 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
6068 "mov %%"R
"ax, %c[rax](%0) \n\t"
6069 "mov %%"R
"bx, %c[rbx](%0) \n\t"
6070 "pop"Q
" %c[rcx](%0) \n\t"
6071 "mov %%"R
"dx, %c[rdx](%0) \n\t"
6072 "mov %%"R
"si, %c[rsi](%0) \n\t"
6073 "mov %%"R
"di, %c[rdi](%0) \n\t"
6074 "mov %%"R
"bp, %c[rbp](%0) \n\t"
6075 #ifdef CONFIG_X86_64
6076 "mov %%r8, %c[r8](%0) \n\t"
6077 "mov %%r9, %c[r9](%0) \n\t"
6078 "mov %%r10, %c[r10](%0) \n\t"
6079 "mov %%r11, %c[r11](%0) \n\t"
6080 "mov %%r12, %c[r12](%0) \n\t"
6081 "mov %%r13, %c[r13](%0) \n\t"
6082 "mov %%r14, %c[r14](%0) \n\t"
6083 "mov %%r15, %c[r15](%0) \n\t"
6085 "mov %%cr2, %%"R
"ax \n\t"
6086 "mov %%"R
"ax, %c[cr2](%0) \n\t"
6088 "pop %%"R
"bp; pop %%"R
"dx \n\t"
6089 "setbe %c[fail](%0) \n\t"
6090 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6091 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6092 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6093 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6094 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6095 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6096 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6097 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6098 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6099 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6100 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6101 #ifdef CONFIG_X86_64
6102 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6103 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6104 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6105 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6106 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6107 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6108 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6109 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6111 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6112 [wordsize
]"i"(sizeof(ulong
))
6114 , R
"ax", R
"bx", R
"di", R
"si"
6115 #ifdef CONFIG_X86_64
6116 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6120 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6121 | (1 << VCPU_EXREG_RFLAGS
)
6122 | (1 << VCPU_EXREG_CPL
)
6123 | (1 << VCPU_EXREG_PDPTR
)
6124 | (1 << VCPU_EXREG_SEGMENTS
)
6125 | (1 << VCPU_EXREG_CR3
));
6126 vcpu
->arch
.regs_dirty
= 0;
6128 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6130 if (is_guest_mode(vcpu
)) {
6131 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6132 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6133 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6134 vmcs12
->idt_vectoring_error_code
=
6135 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6136 vmcs12
->vm_exit_instruction_len
=
6137 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6141 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
6142 vmx
->loaded_vmcs
->launched
= 1;
6144 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6145 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6147 vmx_complete_atomic_exit(vmx
);
6148 vmx_recover_nmi_blocking(vmx
);
6149 vmx_complete_interrupts(vmx
);
6155 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6157 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6161 free_loaded_vmcs(vmx
->loaded_vmcs
);
6162 kfree(vmx
->guest_msrs
);
6163 kvm_vcpu_uninit(vcpu
);
6164 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6167 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6170 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6174 return ERR_PTR(-ENOMEM
);
6178 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6182 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6184 if (!vmx
->guest_msrs
) {
6188 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6189 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6190 if (!vmx
->loaded_vmcs
->vmcs
)
6193 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6194 loaded_vmcs_init(vmx
->loaded_vmcs
);
6199 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6200 vmx
->vcpu
.cpu
= cpu
;
6201 err
= vmx_vcpu_setup(vmx
);
6202 vmx_vcpu_put(&vmx
->vcpu
);
6206 if (vm_need_virtualize_apic_accesses(kvm
))
6207 err
= alloc_apic_access_page(kvm
);
6212 if (!kvm
->arch
.ept_identity_map_addr
)
6213 kvm
->arch
.ept_identity_map_addr
=
6214 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6216 if (alloc_identity_pagetable(kvm
) != 0)
6218 if (!init_rmode_identity_map(kvm
))
6222 vmx
->nested
.current_vmptr
= -1ull;
6223 vmx
->nested
.current_vmcs12
= NULL
;
6228 free_vmcs(vmx
->loaded_vmcs
->vmcs
);
6230 kfree(vmx
->guest_msrs
);
6232 kvm_vcpu_uninit(&vmx
->vcpu
);
6235 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6236 return ERR_PTR(err
);
6239 static void __init
vmx_check_processor_compat(void *rtn
)
6241 struct vmcs_config vmcs_conf
;
6244 if (setup_vmcs_config(&vmcs_conf
) < 0)
6246 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6247 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6248 smp_processor_id());
6253 static int get_ept_level(void)
6255 return VMX_EPT_DEFAULT_GAW
+ 1;
6258 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6262 /* For VT-d and EPT combination
6263 * 1. MMIO: always map as UC
6265 * a. VT-d without snooping control feature: can't guarantee the
6266 * result, try to trust guest.
6267 * b. VT-d with snooping control feature: snooping control feature of
6268 * VT-d engine can guarantee the cache correctness. Just set it
6269 * to WB to keep consistent with host. So the same as item 3.
6270 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6271 * consistent with host MTRR
6274 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6275 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6276 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6277 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6278 VMX_EPT_MT_EPTE_SHIFT
;
6280 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6286 static int vmx_get_lpage_level(void)
6288 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6289 return PT_DIRECTORY_LEVEL
;
6291 /* For shadow and EPT supported 1GB page */
6292 return PT_PDPE_LEVEL
;
6295 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6297 struct kvm_cpuid_entry2
*best
;
6298 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6301 vmx
->rdtscp_enabled
= false;
6302 if (vmx_rdtscp_supported()) {
6303 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6304 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6305 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6306 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6307 vmx
->rdtscp_enabled
= true;
6309 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6310 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6317 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6319 if (func
== 1 && nested
)
6320 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6324 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6325 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6326 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6327 * guest in a way that will both be appropriate to L1's requests, and our
6328 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6329 * function also has additional necessary side-effects, like setting various
6330 * vcpu->arch fields.
6332 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6337 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6338 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6339 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6340 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6341 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6342 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6343 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6344 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6345 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6346 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6347 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6348 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6349 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6350 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6351 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6352 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6353 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6354 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6355 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6356 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6357 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6358 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6359 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6360 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6361 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6362 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6363 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6364 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6365 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6366 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6367 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6368 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6369 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6370 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6371 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6372 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6374 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6375 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6376 vmcs12
->vm_entry_intr_info_field
);
6377 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6378 vmcs12
->vm_entry_exception_error_code
);
6379 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6380 vmcs12
->vm_entry_instruction_len
);
6381 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6382 vmcs12
->guest_interruptibility_info
);
6383 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6384 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6385 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6386 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6387 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6388 vmcs12
->guest_pending_dbg_exceptions
);
6389 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6390 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6392 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6394 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6395 (vmcs_config
.pin_based_exec_ctrl
|
6396 vmcs12
->pin_based_vm_exec_control
));
6399 * Whether page-faults are trapped is determined by a combination of
6400 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6401 * If enable_ept, L0 doesn't care about page faults and we should
6402 * set all of these to L1's desires. However, if !enable_ept, L0 does
6403 * care about (at least some) page faults, and because it is not easy
6404 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6405 * to exit on each and every L2 page fault. This is done by setting
6406 * MASK=MATCH=0 and (see below) EB.PF=1.
6407 * Note that below we don't need special code to set EB.PF beyond the
6408 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6409 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6410 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6412 * A problem with this approach (when !enable_ept) is that L1 may be
6413 * injected with more page faults than it asked for. This could have
6414 * caused problems, but in practice existing hypervisors don't care.
6415 * To fix this, we will need to emulate the PFEC checking (on the L1
6416 * page tables), using walk_addr(), when injecting PFs to L1.
6418 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6419 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6420 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6421 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6423 if (cpu_has_secondary_exec_ctrls()) {
6424 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6425 if (!vmx
->rdtscp_enabled
)
6426 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6427 /* Take the following fields only from vmcs12 */
6428 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6429 if (nested_cpu_has(vmcs12
,
6430 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6431 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6433 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6435 * Translate L1 physical address to host physical
6436 * address for vmcs02. Keep the page pinned, so this
6437 * physical address remains valid. We keep a reference
6438 * to it so we can release it later.
6440 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6441 nested_release_page(vmx
->nested
.apic_access_page
);
6442 vmx
->nested
.apic_access_page
=
6443 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6445 * If translation failed, no matter: This feature asks
6446 * to exit when accessing the given address, and if it
6447 * can never be accessed, this feature won't do
6450 if (!vmx
->nested
.apic_access_page
)
6452 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6454 vmcs_write64(APIC_ACCESS_ADDR
,
6455 page_to_phys(vmx
->nested
.apic_access_page
));
6458 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6463 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6464 * Some constant fields are set here by vmx_set_constant_host_state().
6465 * Other fields are different per CPU, and will be set later when
6466 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6468 vmx_set_constant_host_state();
6471 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6472 * entry, but only if the current (host) sp changed from the value
6473 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6474 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6475 * here we just force the write to happen on entry.
6479 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
6480 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
6481 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6482 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6483 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
6485 * Merging of IO and MSR bitmaps not currently supported.
6486 * Rather, exit every time.
6488 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
6489 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
6490 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
6492 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
6494 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6495 * bitwise-or of what L1 wants to trap for L2, and what we want to
6496 * trap. Note that CR0.TS also needs updating - we do this later.
6498 update_exception_bitmap(vcpu
);
6499 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
6500 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6502 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6503 vmcs_write32(VM_EXIT_CONTROLS
,
6504 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
6505 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
6506 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
6508 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
6509 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
6510 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6511 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6514 set_cr4_guest_host_mask(vmx
);
6516 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
6517 vmcs_write64(TSC_OFFSET
,
6518 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
6520 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6524 * Trivially support vpid by letting L2s share their parent
6525 * L1's vpid. TODO: move to a more elaborate solution, giving
6526 * each L2 its own vpid and exposing the vpid feature to L1.
6528 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6529 vmx_flush_tlb(vcpu
);
6532 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
6533 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
6534 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
6535 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6537 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6538 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6539 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6542 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6543 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6544 * The CR0_READ_SHADOW is what L2 should have expected to read given
6545 * the specifications by L1; It's not enough to take
6546 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6547 * have more bits than L1 expected.
6549 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
6550 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
6552 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
6553 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
6555 /* shadow page tables on either EPT or shadow page tables */
6556 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
6557 kvm_mmu_reset_context(vcpu
);
6559 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
6560 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
6564 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6565 * for running an L2 nested guest.
6567 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
6569 struct vmcs12
*vmcs12
;
6570 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6572 struct loaded_vmcs
*vmcs02
;
6574 if (!nested_vmx_check_permission(vcpu
) ||
6575 !nested_vmx_check_vmcs12(vcpu
))
6578 skip_emulated_instruction(vcpu
);
6579 vmcs12
= get_vmcs12(vcpu
);
6582 * The nested entry process starts with enforcing various prerequisites
6583 * on vmcs12 as required by the Intel SDM, and act appropriately when
6584 * they fail: As the SDM explains, some conditions should cause the
6585 * instruction to fail, while others will cause the instruction to seem
6586 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6587 * To speed up the normal (success) code path, we should avoid checking
6588 * for misconfigurations which will anyway be caught by the processor
6589 * when using the merged vmcs02.
6591 if (vmcs12
->launch_state
== launch
) {
6592 nested_vmx_failValid(vcpu
,
6593 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6594 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
6598 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
6599 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
6600 /*TODO: Also verify bits beyond physical address width are 0*/
6601 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6605 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
6606 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
6607 /*TODO: Also verify bits beyond physical address width are 0*/
6608 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6612 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
6613 vmcs12
->vm_exit_msr_load_count
> 0 ||
6614 vmcs12
->vm_exit_msr_store_count
> 0) {
6615 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6617 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6621 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
6622 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
6623 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
6624 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
6625 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
6626 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
6627 !vmx_control_verify(vmcs12
->vm_exit_controls
,
6628 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
6629 !vmx_control_verify(vmcs12
->vm_entry_controls
,
6630 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
6632 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6636 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6637 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6638 nested_vmx_failValid(vcpu
,
6639 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
6643 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6644 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6645 nested_vmx_entry_failure(vcpu
, vmcs12
,
6646 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
6649 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
6650 nested_vmx_entry_failure(vcpu
, vmcs12
,
6651 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
6656 * We're finally done with prerequisite checking, and can start with
6660 vmcs02
= nested_get_current_vmcs02(vmx
);
6664 enter_guest_mode(vcpu
);
6666 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
6669 vmx
->loaded_vmcs
= vmcs02
;
6671 vmx_vcpu_load(vcpu
, cpu
);
6675 vmcs12
->launch_state
= 1;
6677 prepare_vmcs02(vcpu
, vmcs12
);
6680 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6681 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6682 * returned as far as L1 is concerned. It will only return (and set
6683 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6689 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6690 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6691 * This function returns the new value we should put in vmcs12.guest_cr0.
6692 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6693 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6694 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6695 * didn't trap the bit, because if L1 did, so would L0).
6696 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6697 * been modified by L2, and L1 knows it. So just leave the old value of
6698 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6699 * isn't relevant, because if L0 traps this bit it can set it to anything.
6700 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6701 * changed these bits, and therefore they need to be updated, but L0
6702 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6703 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6705 static inline unsigned long
6706 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6709 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
6710 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
6711 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
6712 vcpu
->arch
.cr0_guest_owned_bits
));
6715 static inline unsigned long
6716 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6719 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
6720 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
6721 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
6722 vcpu
->arch
.cr4_guest_owned_bits
));
6726 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6727 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6728 * and this function updates it to reflect the changes to the guest state while
6729 * L2 was running (and perhaps made some exits which were handled directly by L0
6730 * without going back to L1), and to reflect the exit reason.
6731 * Note that we do not have to copy here all VMCS fields, just those that
6732 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6733 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6734 * which already writes to vmcs12 directly.
6736 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6738 /* update guest state fields: */
6739 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
6740 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
6742 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
6743 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
6744 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
6745 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
6747 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
6748 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
6749 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
6750 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
6751 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
6752 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
6753 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
6754 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
6755 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
6756 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
6757 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
6758 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
6759 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
6760 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
6761 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
6762 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
6763 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
6764 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
6765 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
6766 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
6767 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
6768 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
6769 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
6770 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
6771 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
6772 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
6773 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
6774 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
6775 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
6776 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
6777 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
6778 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
6779 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
6780 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
6781 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
6782 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
6784 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
6785 vmcs12
->guest_interruptibility_info
=
6786 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
6787 vmcs12
->guest_pending_dbg_exceptions
=
6788 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
6790 /* TODO: These cannot have changed unless we have MSR bitmaps and
6791 * the relevant bit asks not to trap the change */
6792 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
6793 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
6794 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
6795 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
6796 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
6797 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
6799 /* update exit information fields: */
6801 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6802 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6804 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6805 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6806 vmcs12
->idt_vectoring_info_field
=
6807 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6808 vmcs12
->idt_vectoring_error_code
=
6809 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6810 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6811 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6813 /* clear vm-entry fields which are to be cleared on exit */
6814 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
6815 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
6819 * A part of what we need to when the nested L2 guest exits and we want to
6820 * run its L1 parent, is to reset L1's guest state to the host state specified
6822 * This function is to be called not only on normal nested exit, but also on
6823 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6824 * Failures During or After Loading Guest State").
6825 * This function should be called when the active VMCS is L1's (vmcs01).
6827 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6829 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
6830 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
6831 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
6832 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6834 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6835 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6837 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
6838 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
6840 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6841 * actually changed, because it depends on the current state of
6842 * fpu_active (which may have changed).
6843 * Note that vmx_set_cr0 refers to efer set above.
6845 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
6847 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6848 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6849 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6851 update_exception_bitmap(vcpu
);
6852 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
6853 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6856 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6857 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6859 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
6860 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
6862 /* shadow page tables on either EPT or shadow page tables */
6863 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
6864 kvm_mmu_reset_context(vcpu
);
6868 * Trivially support vpid by letting L2s share their parent
6869 * L1's vpid. TODO: move to a more elaborate solution, giving
6870 * each L2 its own vpid and exposing the vpid feature to L1.
6872 vmx_flush_tlb(vcpu
);
6876 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
6877 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
6878 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
6879 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
6880 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
6881 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
6882 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
6883 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
6884 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
6885 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
6886 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
6887 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
6888 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
6889 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
6890 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
6892 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
6893 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
6894 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
6895 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
6896 vmcs12
->host_ia32_perf_global_ctrl
);
6900 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6901 * and modify vmcs12 to make it see what it would expect to see there if
6902 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6904 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
6906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6908 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6910 leave_guest_mode(vcpu
);
6911 prepare_vmcs12(vcpu
, vmcs12
);
6914 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6916 vmx_vcpu_load(vcpu
, cpu
);
6920 /* if no vmcs02 cache requested, remove the one we used */
6921 if (VMCS02_POOL_SIZE
== 0)
6922 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
6924 load_vmcs12_host_state(vcpu
, vmcs12
);
6926 /* Update TSC_OFFSET if TSC was changed while L2 ran */
6927 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6929 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6932 /* Unpin physical memory we referred to in vmcs02 */
6933 if (vmx
->nested
.apic_access_page
) {
6934 nested_release_page(vmx
->nested
.apic_access_page
);
6935 vmx
->nested
.apic_access_page
= 0;
6939 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6940 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6941 * success or failure flag accordingly.
6943 if (unlikely(vmx
->fail
)) {
6945 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
6947 nested_vmx_succeed(vcpu
);
6951 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6952 * 23.7 "VM-entry failures during or after loading guest state" (this also
6953 * lists the acceptable exit-reason and exit-qualification parameters).
6954 * It should only be called before L2 actually succeeded to run, and when
6955 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6957 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
6958 struct vmcs12
*vmcs12
,
6959 u32 reason
, unsigned long qualification
)
6961 load_vmcs12_host_state(vcpu
, vmcs12
);
6962 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
6963 vmcs12
->exit_qualification
= qualification
;
6964 nested_vmx_succeed(vcpu
);
6967 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
6968 struct x86_instruction_info
*info
,
6969 enum x86_intercept_stage stage
)
6971 return X86EMUL_CONTINUE
;
6974 static struct kvm_x86_ops vmx_x86_ops
= {
6975 .cpu_has_kvm_support
= cpu_has_kvm_support
,
6976 .disabled_by_bios
= vmx_disabled_by_bios
,
6977 .hardware_setup
= hardware_setup
,
6978 .hardware_unsetup
= hardware_unsetup
,
6979 .check_processor_compatibility
= vmx_check_processor_compat
,
6980 .hardware_enable
= hardware_enable
,
6981 .hardware_disable
= hardware_disable
,
6982 .cpu_has_accelerated_tpr
= report_flexpriority
,
6984 .vcpu_create
= vmx_create_vcpu
,
6985 .vcpu_free
= vmx_free_vcpu
,
6986 .vcpu_reset
= vmx_vcpu_reset
,
6988 .prepare_guest_switch
= vmx_save_host_state
,
6989 .vcpu_load
= vmx_vcpu_load
,
6990 .vcpu_put
= vmx_vcpu_put
,
6992 .set_guest_debug
= set_guest_debug
,
6993 .get_msr
= vmx_get_msr
,
6994 .set_msr
= vmx_set_msr
,
6995 .get_segment_base
= vmx_get_segment_base
,
6996 .get_segment
= vmx_get_segment
,
6997 .set_segment
= vmx_set_segment
,
6998 .get_cpl
= vmx_get_cpl
,
6999 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7000 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7001 .decache_cr3
= vmx_decache_cr3
,
7002 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7003 .set_cr0
= vmx_set_cr0
,
7004 .set_cr3
= vmx_set_cr3
,
7005 .set_cr4
= vmx_set_cr4
,
7006 .set_efer
= vmx_set_efer
,
7007 .get_idt
= vmx_get_idt
,
7008 .set_idt
= vmx_set_idt
,
7009 .get_gdt
= vmx_get_gdt
,
7010 .set_gdt
= vmx_set_gdt
,
7011 .set_dr7
= vmx_set_dr7
,
7012 .cache_reg
= vmx_cache_reg
,
7013 .get_rflags
= vmx_get_rflags
,
7014 .set_rflags
= vmx_set_rflags
,
7015 .fpu_activate
= vmx_fpu_activate
,
7016 .fpu_deactivate
= vmx_fpu_deactivate
,
7018 .tlb_flush
= vmx_flush_tlb
,
7020 .run
= vmx_vcpu_run
,
7021 .handle_exit
= vmx_handle_exit
,
7022 .skip_emulated_instruction
= skip_emulated_instruction
,
7023 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7024 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7025 .patch_hypercall
= vmx_patch_hypercall
,
7026 .set_irq
= vmx_inject_irq
,
7027 .set_nmi
= vmx_inject_nmi
,
7028 .queue_exception
= vmx_queue_exception
,
7029 .cancel_injection
= vmx_cancel_injection
,
7030 .interrupt_allowed
= vmx_interrupt_allowed
,
7031 .nmi_allowed
= vmx_nmi_allowed
,
7032 .get_nmi_mask
= vmx_get_nmi_mask
,
7033 .set_nmi_mask
= vmx_set_nmi_mask
,
7034 .enable_nmi_window
= enable_nmi_window
,
7035 .enable_irq_window
= enable_irq_window
,
7036 .update_cr8_intercept
= update_cr8_intercept
,
7038 .set_tss_addr
= vmx_set_tss_addr
,
7039 .get_tdp_level
= get_ept_level
,
7040 .get_mt_mask
= vmx_get_mt_mask
,
7042 .get_exit_info
= vmx_get_exit_info
,
7044 .get_lpage_level
= vmx_get_lpage_level
,
7046 .cpuid_update
= vmx_cpuid_update
,
7048 .rdtscp_supported
= vmx_rdtscp_supported
,
7050 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7052 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7054 .set_tsc_khz
= vmx_set_tsc_khz
,
7055 .write_tsc_offset
= vmx_write_tsc_offset
,
7056 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7057 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7058 .read_l1_tsc
= vmx_read_l1_tsc
,
7060 .set_tdp_cr3
= vmx_set_cr3
,
7062 .check_intercept
= vmx_check_intercept
,
7065 static int __init
vmx_init(void)
7069 rdmsrl_safe(MSR_EFER
, &host_efer
);
7071 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7072 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7074 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7075 if (!vmx_io_bitmap_a
)
7078 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7079 if (!vmx_io_bitmap_b
) {
7084 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7085 if (!vmx_msr_bitmap_legacy
) {
7090 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7091 if (!vmx_msr_bitmap_longmode
) {
7097 * Allow direct access to the PC debug port (it is often used for I/O
7098 * delays, but the vmexits simply slow things down).
7100 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7101 clear_bit(0x80, vmx_io_bitmap_a
);
7103 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7105 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7106 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7108 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7110 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7111 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7115 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7116 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7117 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7118 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7119 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7120 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7123 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7124 VMX_EPT_EXECUTABLE_MASK
);
7125 ept_set_mmio_spte_mask();
7133 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7135 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7137 free_page((unsigned long)vmx_io_bitmap_b
);
7139 free_page((unsigned long)vmx_io_bitmap_a
);
7143 static void __exit
vmx_exit(void)
7145 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7146 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7147 free_page((unsigned long)vmx_io_bitmap_b
);
7148 free_page((unsigned long)vmx_io_bitmap_a
);
7153 module_init(vmx_init
)
7154 module_exit(vmx_exit
)