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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / gpu / drm / radeon / r600_cs.c
blob0a2e023c15570ffdbd8c78280ac84123b6b17034
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
49 u32 sq_config;
50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8];
56 struct radeon_bo *cb_color_tile_bo[8];
57 u32 cb_color_info[8];
58 u32 cb_color_size_idx[8];
59 u32 cb_target_mask;
60 u32 cb_shader_mask;
61 u32 cb_color_size[8];
62 u32 vgt_strmout_en;
63 u32 vgt_strmout_buffer_en;
64 u32 db_depth_control;
65 u32 db_depth_info;
66 u32 db_depth_size_idx;
67 u32 db_depth_view;
68 u32 db_depth_size;
69 u32 db_offset;
70 struct radeon_bo *db_bo;
71 u64 db_bo_mc;
72 };
73
74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 }
77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 }
79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
82
83 struct gpu_formats {
84 unsigned blockwidth;
85 unsigned blockheight;
86 unsigned blocksize;
87 unsigned valid_color;
88 enum radeon_family min_family;
89 };
90
91 static const struct gpu_formats color_formats_table[] = {
92 /* 8 bit */
93 FMT_8_BIT(V_038004_COLOR_8, 1),
94 FMT_8_BIT(V_038004_COLOR_4_4, 1),
95 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
96 FMT_8_BIT(V_038004_FMT_1, 0),
97
98 /* 16-bit */
99 FMT_16_BIT(V_038004_COLOR_16, 1),
100 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
101 FMT_16_BIT(V_038004_COLOR_8_8, 1),
102 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
103 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
104 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
105 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
106 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
107
108 /* 24-bit */
109 FMT_24_BIT(V_038004_FMT_8_8_8),
110
111 /* 32-bit */
112 FMT_32_BIT(V_038004_COLOR_32, 1),
113 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
114 FMT_32_BIT(V_038004_COLOR_16_16, 1),
115 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
116 FMT_32_BIT(V_038004_COLOR_8_24, 1),
117 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
118 FMT_32_BIT(V_038004_COLOR_24_8, 1),
119 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
120 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
121 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
122 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
123 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
124 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
125 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
126 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
127 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
128 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
129 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
130
131 /* 48-bit */
132 FMT_48_BIT(V_038004_FMT_16_16_16),
133 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
134
135 /* 64-bit */
136 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
137 FMT_64_BIT(V_038004_COLOR_32_32, 1),
138 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
139 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
140 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
141
142 FMT_96_BIT(V_038004_FMT_32_32_32),
143 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
144
145 /* 128-bit */
146 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
147 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
148
149 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
150 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
151
152 /* block compressed formats */
153 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
154 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
155 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
156 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
157 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
158 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
159 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
160
161 /* The other Evergreen formats */
162 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
163 };
164
165 static bool fmt_is_valid_color(u32 format)
166 {
167 if (format >= ARRAY_SIZE(color_formats_table))
168 return false;
169
170 if (color_formats_table[format].valid_color)
171 return true;
172
173 return false;
174 }
175
176 static bool fmt_is_valid_texture(u32 format, enum radeon_family family)
177 {
178 if (format >= ARRAY_SIZE(color_formats_table))
179 return false;
180
181 if (family < color_formats_table[format].min_family)
182 return false;
183
184 if (color_formats_table[format].blockwidth > 0)
185 return true;
186
187 return false;
188 }
189
190 static int fmt_get_blocksize(u32 format)
191 {
192 if (format >= ARRAY_SIZE(color_formats_table))
193 return 0;
194
195 return color_formats_table[format].blocksize;
196 }
197
198 static int fmt_get_nblocksx(u32 format, u32 w)
199 {
200 unsigned bw;
201
202 if (format >= ARRAY_SIZE(color_formats_table))
203 return 0;
204
205 bw = color_formats_table[format].blockwidth;
206 if (bw == 0)
207 return 0;
208
209 return (w + bw - 1) / bw;
210 }
211
212 static int fmt_get_nblocksy(u32 format, u32 h)
213 {
214 unsigned bh;
215
216 if (format >= ARRAY_SIZE(color_formats_table))
217 return 0;
218
219 bh = color_formats_table[format].blockheight;
220 if (bh == 0)
221 return 0;
222
223 return (h + bh - 1) / bh;
224 }
225
226 struct array_mode_checker {
227 int array_mode;
228 u32 group_size;
229 u32 nbanks;
230 u32 npipes;
231 u32 nsamples;
232 u32 blocksize;
233 };
234
235 /* returns alignment in pixels for pitch/height/depth and bytes for base */
236 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
237 u32 *pitch_align,
238 u32 *height_align,
239 u32 *depth_align,
240 u64 *base_align)
241 {
242 u32 tile_width = 8;
243 u32 tile_height = 8;
244 u32 macro_tile_width = values->nbanks;
245 u32 macro_tile_height = values->npipes;
246 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
247 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
248
249 switch (values->array_mode) {
250 case ARRAY_LINEAR_GENERAL:
251 /* technically tile_width/_height for pitch/height */
252 *pitch_align = 1; /* tile_width */
253 *height_align = 1; /* tile_height */
254 *depth_align = 1;
255 *base_align = 1;
256 break;
257 case ARRAY_LINEAR_ALIGNED:
258 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
259 *height_align = tile_height;
260 *depth_align = 1;
261 *base_align = values->group_size;
262 break;
263 case ARRAY_1D_TILED_THIN1:
264 *pitch_align = max((u32)tile_width,
265 (u32)(values->group_size /
266 (tile_height * values->blocksize * values->nsamples)));
267 *height_align = tile_height;
268 *depth_align = 1;
269 *base_align = values->group_size;
270 break;
271 case ARRAY_2D_TILED_THIN1:
272 *pitch_align = max((u32)macro_tile_width,
273 (u32)(((values->group_size / tile_height) /
274 (values->blocksize * values->nsamples)) *
275 values->nbanks)) * tile_width;
276 *height_align = macro_tile_height * tile_height;
277 *depth_align = 1;
278 *base_align = max(macro_tile_bytes,
279 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
280 break;
281 default:
282 return -EINVAL;
283 }
284
285 return 0;
286 }
287
288 static void r600_cs_track_init(struct r600_cs_track *track)
289 {
290 int i;
291
292 /* assume DX9 mode */
293 track->sq_config = DX9_CONSTS;
294 for (i = 0; i < 8; i++) {
295 track->cb_color_base_last[i] = 0;
296 track->cb_color_size[i] = 0;
297 track->cb_color_size_idx[i] = 0;
298 track->cb_color_info[i] = 0;
299 track->cb_color_bo[i] = NULL;
300 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
301 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
302 }
303 track->cb_target_mask = 0xFFFFFFFF;
304 track->cb_shader_mask = 0xFFFFFFFF;
305 track->db_bo = NULL;
306 track->db_bo_mc = 0xFFFFFFFF;
307 /* assume the biggest format and that htile is enabled */
308 track->db_depth_info = 7 | (1 << 25);
309 track->db_depth_view = 0xFFFFC000;
310 track->db_depth_size = 0xFFFFFFFF;
311 track->db_depth_size_idx = 0;
312 track->db_depth_control = 0xFFFFFFFF;
313 }
314
315 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
316 {
317 struct r600_cs_track *track = p->track;
318 u32 slice_tile_max, size, tmp;
319 u32 height, height_align, pitch, pitch_align, depth_align;
320 u64 base_offset, base_align;
321 struct array_mode_checker array_check;
322 volatile u32 *ib = p->ib->ptr;
323 unsigned array_mode;
324 u32 format;
325 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
326 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
327 return -EINVAL;
328 }
329 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
330 format = G_0280A0_FORMAT(track->cb_color_info[i]);
331 if (!fmt_is_valid_color(format)) {
332 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
333 __func__, __LINE__, format,
334 i, track->cb_color_info[i]);
335 return -EINVAL;
336 }
337 /* pitch in pixels */
338 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
339 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
340 slice_tile_max *= 64;
341 height = slice_tile_max / pitch;
342 if (height > 8192)
343 height = 8192;
344 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
345
346 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
347 array_check.array_mode = array_mode;
348 array_check.group_size = track->group_size;
349 array_check.nbanks = track->nbanks;
350 array_check.npipes = track->npipes;
351 array_check.nsamples = track->nsamples;
352 array_check.blocksize = fmt_get_blocksize(format);
353 if (r600_get_array_mode_alignment(&array_check,
354 &pitch_align, &height_align, &depth_align, &base_align)) {
355 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
356 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
357 track->cb_color_info[i]);
358 return -EINVAL;
359 }
360 switch (array_mode) {
361 case V_0280A0_ARRAY_LINEAR_GENERAL:
362 break;
363 case V_0280A0_ARRAY_LINEAR_ALIGNED:
364 break;
365 case V_0280A0_ARRAY_1D_TILED_THIN1:
366 /* avoid breaking userspace */
367 if (height > 7)
368 height &= ~0x7;
369 break;
370 case V_0280A0_ARRAY_2D_TILED_THIN1:
371 break;
372 default:
373 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
374 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
375 track->cb_color_info[i]);
376 return -EINVAL;
377 }
378
379 if (!IS_ALIGNED(pitch, pitch_align)) {
380 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
381 __func__, __LINE__, pitch, pitch_align, array_mode);
382 return -EINVAL;
383 }
384 if (!IS_ALIGNED(height, height_align)) {
385 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
386 __func__, __LINE__, height, height_align, array_mode);
387 return -EINVAL;
388 }
389 if (!IS_ALIGNED(base_offset, base_align)) {
390 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
391 base_offset, base_align, array_mode);
392 return -EINVAL;
393 }
394
395 /* check offset */
396 tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
397 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
398 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
399 /* the initial DDX does bad things with the CB size occasionally */
400 /* it rounds up height too far for slice tile max but the BO is smaller */
401 /* r600c,g also seem to flush at bad times in some apps resulting in
402 * bogus values here. So for linear just allow anything to avoid breaking
403 * broken userspace.
404 */
405 } else {
406 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i,
407 array_mode,
408 track->cb_color_bo_offset[i], tmp,
409 radeon_bo_size(track->cb_color_bo[i]));
410 return -EINVAL;
411 }
412 }
413 /* limit max tile */
414 tmp = (height * pitch) >> 6;
415 if (tmp < slice_tile_max)
416 slice_tile_max = tmp;
417 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
418 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
419 ib[track->cb_color_size_idx[i]] = tmp;
420 return 0;
421 }
422
423 static int r600_cs_track_check(struct radeon_cs_parser *p)
424 {
425 struct r600_cs_track *track = p->track;
426 u32 tmp;
427 int r, i;
428 volatile u32 *ib = p->ib->ptr;
429
430 /* on legacy kernel we don't perform advanced check */
431 if (p->rdev == NULL)
432 return 0;
433 /* we don't support out buffer yet */
434 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
435 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
436 return -EINVAL;
437 }
438 /* check that we have a cb for each enabled target, we don't check
439 * shader_mask because it seems mesa isn't always setting it :(
440 */
441 tmp = track->cb_target_mask;
442 for (i = 0; i < 8; i++) {
443 if ((tmp >> (i * 4)) & 0xF) {
444 /* at least one component is enabled */
445 if (track->cb_color_bo[i] == NULL) {
446 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
447 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
448 return -EINVAL;
449 }
450 /* perform rewrite of CB_COLOR[0-7]_SIZE */
451 r = r600_cs_track_validate_cb(p, i);
452 if (r)
453 return r;
454 }
455 }
456 /* Check depth buffer */
457 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
458 G_028800_Z_ENABLE(track->db_depth_control)) {
459 u32 nviews, bpe, ntiles, size, slice_tile_max;
460 u32 height, height_align, pitch, pitch_align, depth_align;
461 u64 base_offset, base_align;
462 struct array_mode_checker array_check;
463 int array_mode;
464
465 if (track->db_bo == NULL) {
466 dev_warn(p->dev, "z/stencil with no depth buffer\n");
467 return -EINVAL;
468 }
469 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
470 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
471 return -EINVAL;
472 }
473 switch (G_028010_FORMAT(track->db_depth_info)) {
474 case V_028010_DEPTH_16:
475 bpe = 2;
476 break;
477 case V_028010_DEPTH_X8_24:
478 case V_028010_DEPTH_8_24:
479 case V_028010_DEPTH_X8_24_FLOAT:
480 case V_028010_DEPTH_8_24_FLOAT:
481 case V_028010_DEPTH_32_FLOAT:
482 bpe = 4;
483 break;
484 case V_028010_DEPTH_X24_8_32_FLOAT:
485 bpe = 8;
486 break;
487 default:
488 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
489 return -EINVAL;
490 }
491 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
492 if (!track->db_depth_size_idx) {
493 dev_warn(p->dev, "z/stencil buffer size not set\n");
494 return -EINVAL;
495 }
496 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
497 tmp = (tmp / bpe) >> 6;
498 if (!tmp) {
499 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
500 track->db_depth_size, bpe, track->db_offset,
501 radeon_bo_size(track->db_bo));
502 return -EINVAL;
503 }
504 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
505 } else {
506 size = radeon_bo_size(track->db_bo);
507 /* pitch in pixels */
508 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
509 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
510 slice_tile_max *= 64;
511 height = slice_tile_max / pitch;
512 if (height > 8192)
513 height = 8192;
514 base_offset = track->db_bo_mc + track->db_offset;
515 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
516 array_check.array_mode = array_mode;
517 array_check.group_size = track->group_size;
518 array_check.nbanks = track->nbanks;
519 array_check.npipes = track->npipes;
520 array_check.nsamples = track->nsamples;
521 array_check.blocksize = bpe;
522 if (r600_get_array_mode_alignment(&array_check,
523 &pitch_align, &height_align, &depth_align, &base_align)) {
524 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
525 G_028010_ARRAY_MODE(track->db_depth_info),
526 track->db_depth_info);
527 return -EINVAL;
528 }
529 switch (array_mode) {
530 case V_028010_ARRAY_1D_TILED_THIN1:
531 /* don't break userspace */
532 height &= ~0x7;
533 break;
534 case V_028010_ARRAY_2D_TILED_THIN1:
535 break;
536 default:
537 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
538 G_028010_ARRAY_MODE(track->db_depth_info),
539 track->db_depth_info);
540 return -EINVAL;
541 }
542
543 if (!IS_ALIGNED(pitch, pitch_align)) {
544 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
545 __func__, __LINE__, pitch, pitch_align, array_mode);
546 return -EINVAL;
547 }
548 if (!IS_ALIGNED(height, height_align)) {
549 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
550 __func__, __LINE__, height, height_align, array_mode);
551 return -EINVAL;
552 }
553 if (!IS_ALIGNED(base_offset, base_align)) {
554 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
555 base_offset, base_align, array_mode);
556 return -EINVAL;
557 }
558
559 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
560 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
561 tmp = ntiles * bpe * 64 * nviews;
562 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
563 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
564 array_mode,
565 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 }
570 }
571 return 0;
572 }
573
574 /**
575 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
576 * @parser: parser structure holding parsing context.
577 * @pkt: where to store packet informations
578 *
579 * Assume that chunk_ib_index is properly set. Will return -EINVAL
580 * if packet is bigger than remaining ib size. or if packets is unknown.
581 **/
582 int r600_cs_packet_parse(struct radeon_cs_parser *p,
583 struct radeon_cs_packet *pkt,
584 unsigned idx)
585 {
586 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
587 uint32_t header;
588
589 if (idx >= ib_chunk->length_dw) {
590 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
591 idx, ib_chunk->length_dw);
592 return -EINVAL;
593 }
594 header = radeon_get_ib_value(p, idx);
595 pkt->idx = idx;
596 pkt->type = CP_PACKET_GET_TYPE(header);
597 pkt->count = CP_PACKET_GET_COUNT(header);
598 pkt->one_reg_wr = 0;
599 switch (pkt->type) {
600 case PACKET_TYPE0:
601 pkt->reg = CP_PACKET0_GET_REG(header);
602 break;
603 case PACKET_TYPE3:
604 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
605 break;
606 case PACKET_TYPE2:
607 pkt->count = -1;
608 break;
609 default:
610 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
611 return -EINVAL;
612 }
613 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
614 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
615 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
616 return -EINVAL;
617 }
618 return 0;
619 }
620
621 /**
622 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
623 * @parser: parser structure holding parsing context.
624 * @data: pointer to relocation data
625 * @offset_start: starting offset
626 * @offset_mask: offset mask (to align start offset on)
627 * @reloc: reloc informations
628 *
629 * Check next packet is relocation packet3, do bo validation and compute
630 * GPU offset using the provided start.
631 **/
632 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
633 struct radeon_cs_reloc **cs_reloc)
634 {
635 struct radeon_cs_chunk *relocs_chunk;
636 struct radeon_cs_packet p3reloc;
637 unsigned idx;
638 int r;
639
640 if (p->chunk_relocs_idx == -1) {
641 DRM_ERROR("No relocation chunk !\n");
642 return -EINVAL;
643 }
644 *cs_reloc = NULL;
645 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
646 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
647 if (r) {
648 return r;
649 }
650 p->idx += p3reloc.count + 2;
651 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
652 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
653 p3reloc.idx);
654 return -EINVAL;
655 }
656 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
657 if (idx >= relocs_chunk->length_dw) {
658 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
659 idx, relocs_chunk->length_dw);
660 return -EINVAL;
661 }
662 /* FIXME: we assume reloc size is 4 dwords */
663 *cs_reloc = p->relocs_ptr[(idx / 4)];
664 return 0;
665 }
666
667 /**
668 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
669 * @parser: parser structure holding parsing context.
670 * @data: pointer to relocation data
671 * @offset_start: starting offset
672 * @offset_mask: offset mask (to align start offset on)
673 * @reloc: reloc informations
674 *
675 * Check next packet is relocation packet3, do bo validation and compute
676 * GPU offset using the provided start.
677 **/
678 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
679 struct radeon_cs_reloc **cs_reloc)
680 {
681 struct radeon_cs_chunk *relocs_chunk;
682 struct radeon_cs_packet p3reloc;
683 unsigned idx;
684 int r;
685
686 if (p->chunk_relocs_idx == -1) {
687 DRM_ERROR("No relocation chunk !\n");
688 return -EINVAL;
689 }
690 *cs_reloc = NULL;
691 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
692 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
693 if (r) {
694 return r;
695 }
696 p->idx += p3reloc.count + 2;
697 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
698 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
699 p3reloc.idx);
700 return -EINVAL;
701 }
702 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
703 if (idx >= relocs_chunk->length_dw) {
704 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
705 idx, relocs_chunk->length_dw);
706 return -EINVAL;
707 }
708 *cs_reloc = p->relocs;
709 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
710 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
711 return 0;
712 }
713
714 /**
715 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
716 * @parser: parser structure holding parsing context.
717 *
718 * Check next packet is relocation packet3, do bo validation and compute
719 * GPU offset using the provided start.
720 **/
721 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
722 {
723 struct radeon_cs_packet p3reloc;
724 int r;
725
726 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
727 if (r) {
728 return 0;
729 }
730 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
731 return 0;
732 }
733 return 1;
734 }
735
736 /**
737 * r600_cs_packet_next_vline() - parse userspace VLINE packet
738 * @parser: parser structure holding parsing context.
739 *
740 * Userspace sends a special sequence for VLINE waits.
741 * PACKET0 - VLINE_START_END + value
742 * PACKET3 - WAIT_REG_MEM poll vline status reg
743 * RELOC (P3) - crtc_id in reloc.
744 *
745 * This function parses this and relocates the VLINE START END
746 * and WAIT_REG_MEM packets to the correct crtc.
747 * It also detects a switched off crtc and nulls out the
748 * wait in that case.
749 */
750 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
751 {
752 struct drm_mode_object *obj;
753 struct drm_crtc *crtc;
754 struct radeon_crtc *radeon_crtc;
755 struct radeon_cs_packet p3reloc, wait_reg_mem;
756 int crtc_id;
757 int r;
758 uint32_t header, h_idx, reg, wait_reg_mem_info;
759 volatile uint32_t *ib;
760
761 ib = p->ib->ptr;
762
763 /* parse the WAIT_REG_MEM */
764 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
765 if (r)
766 return r;
767
768 /* check its a WAIT_REG_MEM */
769 if (wait_reg_mem.type != PACKET_TYPE3 ||
770 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
771 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
772 return -EINVAL;
773 }
774
775 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
776 /* bit 4 is reg (0) or mem (1) */
777 if (wait_reg_mem_info & 0x10) {
778 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
779 return -EINVAL;
780 }
781 /* waiting for value to be equal */
782 if ((wait_reg_mem_info & 0x7) != 0x3) {
783 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
784 return -EINVAL;
785 }
786 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
787 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
788 return -EINVAL;
789 }
790
791 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
792 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
793 return -EINVAL;
794 }
795
796 /* jump over the NOP */
797 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
798 if (r)
799 return r;
800
801 h_idx = p->idx - 2;
802 p->idx += wait_reg_mem.count + 2;
803 p->idx += p3reloc.count + 2;
804
805 header = radeon_get_ib_value(p, h_idx);
806 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
807 reg = CP_PACKET0_GET_REG(header);
808
809 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
810 if (!obj) {
811 DRM_ERROR("cannot find crtc %d\n", crtc_id);
812 return -EINVAL;
813 }
814 crtc = obj_to_crtc(obj);
815 radeon_crtc = to_radeon_crtc(crtc);
816 crtc_id = radeon_crtc->crtc_id;
817
818 if (!crtc->enabled) {
819 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
820 ib[h_idx + 2] = PACKET2(0);
821 ib[h_idx + 3] = PACKET2(0);
822 ib[h_idx + 4] = PACKET2(0);
823 ib[h_idx + 5] = PACKET2(0);
824 ib[h_idx + 6] = PACKET2(0);
825 ib[h_idx + 7] = PACKET2(0);
826 ib[h_idx + 8] = PACKET2(0);
827 } else if (crtc_id == 1) {
828 switch (reg) {
829 case AVIVO_D1MODE_VLINE_START_END:
830 header &= ~R600_CP_PACKET0_REG_MASK;
831 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
832 break;
833 default:
834 DRM_ERROR("unknown crtc reloc\n");
835 return -EINVAL;
836 }
837 ib[h_idx] = header;
838 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
839 }
840
841 return 0;
842 }
843
844 static int r600_packet0_check(struct radeon_cs_parser *p,
845 struct radeon_cs_packet *pkt,
846 unsigned idx, unsigned reg)
847 {
848 int r;
849
850 switch (reg) {
851 case AVIVO_D1MODE_VLINE_START_END:
852 r = r600_cs_packet_parse_vline(p);
853 if (r) {
854 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
855 idx, reg);
856 return r;
857 }
858 break;
859 default:
860 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
861 reg, idx);
862 return -EINVAL;
863 }
864 return 0;
865 }
866
867 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
868 struct radeon_cs_packet *pkt)
869 {
870 unsigned reg, i;
871 unsigned idx;
872 int r;
873
874 idx = pkt->idx + 1;
875 reg = pkt->reg;
876 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
877 r = r600_packet0_check(p, pkt, idx, reg);
878 if (r) {
879 return r;
880 }
881 }
882 return 0;
883 }
884
885 /**
886 * r600_cs_check_reg() - check if register is authorized or not
887 * @parser: parser structure holding parsing context
888 * @reg: register we are testing
889 * @idx: index into the cs buffer
890 *
891 * This function will test against r600_reg_safe_bm and return 0
892 * if register is safe. If register is not flag as safe this function
893 * will test it against a list of register needind special handling.
894 */
895 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
896 {
897 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
898 struct radeon_cs_reloc *reloc;
899 u32 m, i, tmp, *ib;
900 int r;
901
902 i = (reg >> 7);
903 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
904 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
905 return -EINVAL;
906 }
907 m = 1 << ((reg >> 2) & 31);
908 if (!(r600_reg_safe_bm[i] & m))
909 return 0;
910 ib = p->ib->ptr;
911 switch (reg) {
912 /* force following reg to 0 in an attempt to disable out buffer
913 * which will need us to better understand how it works to perform
914 * security check on it (Jerome)
915 */
916 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
917 case R_008C44_SQ_ESGS_RING_SIZE:
918 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
919 case R_008C54_SQ_ESTMP_RING_SIZE:
920 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
921 case R_008C74_SQ_FBUF_RING_SIZE:
922 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
923 case R_008C5C_SQ_GSTMP_RING_SIZE:
924 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
925 case R_008C4C_SQ_GSVS_RING_SIZE:
926 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
927 case R_008C6C_SQ_PSTMP_RING_SIZE:
928 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
929 case R_008C7C_SQ_REDUC_RING_SIZE:
930 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
931 case R_008C64_SQ_VSTMP_RING_SIZE:
932 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
933 /* get value to populate the IB don't remove */
934 tmp =radeon_get_ib_value(p, idx);
935 ib[idx] = 0;
936 break;
937 case SQ_CONFIG:
938 track->sq_config = radeon_get_ib_value(p, idx);
939 break;
940 case R_028800_DB_DEPTH_CONTROL:
941 track->db_depth_control = radeon_get_ib_value(p, idx);
942 break;
943 case R_028010_DB_DEPTH_INFO:
944 if (r600_cs_packet_next_is_pkt3_nop(p)) {
945 r = r600_cs_packet_next_reloc(p, &reloc);
946 if (r) {
947 dev_warn(p->dev, "bad SET_CONTEXT_REG "
948 "0x%04X\n", reg);
949 return -EINVAL;
950 }
951 track->db_depth_info = radeon_get_ib_value(p, idx);
952 ib[idx] &= C_028010_ARRAY_MODE;
953 track->db_depth_info &= C_028010_ARRAY_MODE;
954 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
955 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
956 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
957 } else {
958 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
959 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
960 }
961 } else
962 track->db_depth_info = radeon_get_ib_value(p, idx);
963 break;
964 case R_028004_DB_DEPTH_VIEW:
965 track->db_depth_view = radeon_get_ib_value(p, idx);
966 break;
967 case R_028000_DB_DEPTH_SIZE:
968 track->db_depth_size = radeon_get_ib_value(p, idx);
969 track->db_depth_size_idx = idx;
970 break;
971 case R_028AB0_VGT_STRMOUT_EN:
972 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
973 break;
974 case R_028B20_VGT_STRMOUT_BUFFER_EN:
975 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
976 break;
977 case R_028238_CB_TARGET_MASK:
978 track->cb_target_mask = radeon_get_ib_value(p, idx);
979 break;
980 case R_02823C_CB_SHADER_MASK:
981 track->cb_shader_mask = radeon_get_ib_value(p, idx);
982 break;
983 case R_028C04_PA_SC_AA_CONFIG:
984 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
985 track->nsamples = 1 << tmp;
986 break;
987 case R_0280A0_CB_COLOR0_INFO:
988 case R_0280A4_CB_COLOR1_INFO:
989 case R_0280A8_CB_COLOR2_INFO:
990 case R_0280AC_CB_COLOR3_INFO:
991 case R_0280B0_CB_COLOR4_INFO:
992 case R_0280B4_CB_COLOR5_INFO:
993 case R_0280B8_CB_COLOR6_INFO:
994 case R_0280BC_CB_COLOR7_INFO:
995 if (r600_cs_packet_next_is_pkt3_nop(p)) {
996 r = r600_cs_packet_next_reloc(p, &reloc);
997 if (r) {
998 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
999 return -EINVAL;
1000 }
1001 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1002 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1003 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1004 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1005 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1006 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1007 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1008 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1009 }
1010 } else {
1011 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1012 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1013 }
1014 break;
1015 case R_028060_CB_COLOR0_SIZE:
1016 case R_028064_CB_COLOR1_SIZE:
1017 case R_028068_CB_COLOR2_SIZE:
1018 case R_02806C_CB_COLOR3_SIZE:
1019 case R_028070_CB_COLOR4_SIZE:
1020 case R_028074_CB_COLOR5_SIZE:
1021 case R_028078_CB_COLOR6_SIZE:
1022 case R_02807C_CB_COLOR7_SIZE:
1023 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1024 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1025 track->cb_color_size_idx[tmp] = idx;
1026 break;
1027 /* This register were added late, there is userspace
1028 * which does provide relocation for those but set
1029 * 0 offset. In order to avoid breaking old userspace
1030 * we detect this and set address to point to last
1031 * CB_COLOR0_BASE, note that if userspace doesn't set
1032 * CB_COLOR0_BASE before this register we will report
1033 * error. Old userspace always set CB_COLOR0_BASE
1034 * before any of this.
1035 */
1036 case R_0280E0_CB_COLOR0_FRAG:
1037 case R_0280E4_CB_COLOR1_FRAG:
1038 case R_0280E8_CB_COLOR2_FRAG:
1039 case R_0280EC_CB_COLOR3_FRAG:
1040 case R_0280F0_CB_COLOR4_FRAG:
1041 case R_0280F4_CB_COLOR5_FRAG:
1042 case R_0280F8_CB_COLOR6_FRAG:
1043 case R_0280FC_CB_COLOR7_FRAG:
1044 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1045 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1046 if (!track->cb_color_base_last[tmp]) {
1047 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1048 return -EINVAL;
1049 }
1050 ib[idx] = track->cb_color_base_last[tmp];
1051 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1052 } else {
1053 r = r600_cs_packet_next_reloc(p, &reloc);
1054 if (r) {
1055 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1056 return -EINVAL;
1057 }
1058 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1059 track->cb_color_frag_bo[tmp] = reloc->robj;
1060 }
1061 break;
1062 case R_0280C0_CB_COLOR0_TILE:
1063 case R_0280C4_CB_COLOR1_TILE:
1064 case R_0280C8_CB_COLOR2_TILE:
1065 case R_0280CC_CB_COLOR3_TILE:
1066 case R_0280D0_CB_COLOR4_TILE:
1067 case R_0280D4_CB_COLOR5_TILE:
1068 case R_0280D8_CB_COLOR6_TILE:
1069 case R_0280DC_CB_COLOR7_TILE:
1070 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1071 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1072 if (!track->cb_color_base_last[tmp]) {
1073 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1074 return -EINVAL;
1075 }
1076 ib[idx] = track->cb_color_base_last[tmp];
1077 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1078 } else {
1079 r = r600_cs_packet_next_reloc(p, &reloc);
1080 if (r) {
1081 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1082 return -EINVAL;
1083 }
1084 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1085 track->cb_color_tile_bo[tmp] = reloc->robj;
1086 }
1087 break;
1088 case CB_COLOR0_BASE:
1089 case CB_COLOR1_BASE:
1090 case CB_COLOR2_BASE:
1091 case CB_COLOR3_BASE:
1092 case CB_COLOR4_BASE:
1093 case CB_COLOR5_BASE:
1094 case CB_COLOR6_BASE:
1095 case CB_COLOR7_BASE:
1096 r = r600_cs_packet_next_reloc(p, &reloc);
1097 if (r) {
1098 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1099 "0x%04X\n", reg);
1100 return -EINVAL;
1101 }
1102 tmp = (reg - CB_COLOR0_BASE) / 4;
1103 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1104 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1105 track->cb_color_base_last[tmp] = ib[idx];
1106 track->cb_color_bo[tmp] = reloc->robj;
1107 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1108 break;
1109 case DB_DEPTH_BASE:
1110 r = r600_cs_packet_next_reloc(p, &reloc);
1111 if (r) {
1112 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1113 "0x%04X\n", reg);
1114 return -EINVAL;
1115 }
1116 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1117 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1118 track->db_bo = reloc->robj;
1119 track->db_bo_mc = reloc->lobj.gpu_offset;
1120 break;
1121 case DB_HTILE_DATA_BASE:
1122 case SQ_PGM_START_FS:
1123 case SQ_PGM_START_ES:
1124 case SQ_PGM_START_VS:
1125 case SQ_PGM_START_GS:
1126 case SQ_PGM_START_PS:
1127 case SQ_ALU_CONST_CACHE_GS_0:
1128 case SQ_ALU_CONST_CACHE_GS_1:
1129 case SQ_ALU_CONST_CACHE_GS_2:
1130 case SQ_ALU_CONST_CACHE_GS_3:
1131 case SQ_ALU_CONST_CACHE_GS_4:
1132 case SQ_ALU_CONST_CACHE_GS_5:
1133 case SQ_ALU_CONST_CACHE_GS_6:
1134 case SQ_ALU_CONST_CACHE_GS_7:
1135 case SQ_ALU_CONST_CACHE_GS_8:
1136 case SQ_ALU_CONST_CACHE_GS_9:
1137 case SQ_ALU_CONST_CACHE_GS_10:
1138 case SQ_ALU_CONST_CACHE_GS_11:
1139 case SQ_ALU_CONST_CACHE_GS_12:
1140 case SQ_ALU_CONST_CACHE_GS_13:
1141 case SQ_ALU_CONST_CACHE_GS_14:
1142 case SQ_ALU_CONST_CACHE_GS_15:
1143 case SQ_ALU_CONST_CACHE_PS_0:
1144 case SQ_ALU_CONST_CACHE_PS_1:
1145 case SQ_ALU_CONST_CACHE_PS_2:
1146 case SQ_ALU_CONST_CACHE_PS_3:
1147 case SQ_ALU_CONST_CACHE_PS_4:
1148 case SQ_ALU_CONST_CACHE_PS_5:
1149 case SQ_ALU_CONST_CACHE_PS_6:
1150 case SQ_ALU_CONST_CACHE_PS_7:
1151 case SQ_ALU_CONST_CACHE_PS_8:
1152 case SQ_ALU_CONST_CACHE_PS_9:
1153 case SQ_ALU_CONST_CACHE_PS_10:
1154 case SQ_ALU_CONST_CACHE_PS_11:
1155 case SQ_ALU_CONST_CACHE_PS_12:
1156 case SQ_ALU_CONST_CACHE_PS_13:
1157 case SQ_ALU_CONST_CACHE_PS_14:
1158 case SQ_ALU_CONST_CACHE_PS_15:
1159 case SQ_ALU_CONST_CACHE_VS_0:
1160 case SQ_ALU_CONST_CACHE_VS_1:
1161 case SQ_ALU_CONST_CACHE_VS_2:
1162 case SQ_ALU_CONST_CACHE_VS_3:
1163 case SQ_ALU_CONST_CACHE_VS_4:
1164 case SQ_ALU_CONST_CACHE_VS_5:
1165 case SQ_ALU_CONST_CACHE_VS_6:
1166 case SQ_ALU_CONST_CACHE_VS_7:
1167 case SQ_ALU_CONST_CACHE_VS_8:
1168 case SQ_ALU_CONST_CACHE_VS_9:
1169 case SQ_ALU_CONST_CACHE_VS_10:
1170 case SQ_ALU_CONST_CACHE_VS_11:
1171 case SQ_ALU_CONST_CACHE_VS_12:
1172 case SQ_ALU_CONST_CACHE_VS_13:
1173 case SQ_ALU_CONST_CACHE_VS_14:
1174 case SQ_ALU_CONST_CACHE_VS_15:
1175 r = r600_cs_packet_next_reloc(p, &reloc);
1176 if (r) {
1177 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1178 "0x%04X\n", reg);
1179 return -EINVAL;
1180 }
1181 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1182 break;
1183 case SX_MEMORY_EXPORT_BASE:
1184 r = r600_cs_packet_next_reloc(p, &reloc);
1185 if (r) {
1186 dev_warn(p->dev, "bad SET_CONFIG_REG "
1187 "0x%04X\n", reg);
1188 return -EINVAL;
1189 }
1190 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1191 break;
1192 default:
1193 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1194 return -EINVAL;
1195 }
1196 return 0;
1197 }
1198
1199 static unsigned mip_minify(unsigned size, unsigned level)
1200 {
1201 unsigned val;
1202
1203 val = max(1U, size >> level);
1204 if (level > 0)
1205 val = roundup_pow_of_two(val);
1206 return val;
1207 }
1208
1209 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1210 unsigned w0, unsigned h0, unsigned d0, unsigned format,
1211 unsigned block_align, unsigned height_align, unsigned base_align,
1212 unsigned *l0_size, unsigned *mipmap_size)
1213 {
1214 unsigned offset, i, level;
1215 unsigned width, height, depth, size;
1216 unsigned blocksize;
1217 unsigned nbx, nby;
1218 unsigned nlevels = llevel - blevel + 1;
1219
1220 *l0_size = -1;
1221 blocksize = fmt_get_blocksize(format);
1222
1223 w0 = mip_minify(w0, 0);
1224 h0 = mip_minify(h0, 0);
1225 d0 = mip_minify(d0, 0);
1226 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1227 width = mip_minify(w0, i);
1228 nbx = fmt_get_nblocksx(format, width);
1229
1230 nbx = round_up(nbx, block_align);
1231
1232 height = mip_minify(h0, i);
1233 nby = fmt_get_nblocksy(format, height);
1234 nby = round_up(nby, height_align);
1235
1236 depth = mip_minify(d0, i);
1237
1238 size = nbx * nby * blocksize;
1239 if (nfaces)
1240 size *= nfaces;
1241 else
1242 size *= depth;
1243
1244 if (i == 0)
1245 *l0_size = size;
1246
1247 if (i == 0 || i == 1)
1248 offset = round_up(offset, base_align);
1249
1250 offset += size;
1251 }
1252 *mipmap_size = offset;
1253 if (llevel == 0)
1254 *mipmap_size = *l0_size;
1255 if (!blevel)
1256 *mipmap_size -= *l0_size;
1257 }
1258
1259 /**
1260 * r600_check_texture_resource() - check if register is authorized or not
1261 * @p: parser structure holding parsing context
1262 * @idx: index into the cs buffer
1263 * @texture: texture's bo structure
1264 * @mipmap: mipmap's bo structure
1265 *
1266 * This function will check that the resource has valid field and that
1267 * the texture and mipmap bo object are big enough to cover this resource.
1268 */
1269 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1270 struct radeon_bo *texture,
1271 struct radeon_bo *mipmap,
1272 u64 base_offset,
1273 u64 mip_offset,
1274 u32 tiling_flags)
1275 {
1276 struct r600_cs_track *track = p->track;
1277 u32 nfaces, llevel, blevel, w0, h0, d0;
1278 u32 word0, word1, l0_size, mipmap_size, word2, word3;
1279 u32 height_align, pitch, pitch_align, depth_align;
1280 u32 array, barray, larray;
1281 u64 base_align;
1282 struct array_mode_checker array_check;
1283 u32 format;
1284
1285 /* on legacy kernel we don't perform advanced check */
1286 if (p->rdev == NULL)
1287 return 0;
1288
1289 /* convert to bytes */
1290 base_offset <<= 8;
1291 mip_offset <<= 8;
1292
1293 word0 = radeon_get_ib_value(p, idx + 0);
1294 if (tiling_flags & RADEON_TILING_MACRO)
1295 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1296 else if (tiling_flags & RADEON_TILING_MICRO)
1297 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1298 word1 = radeon_get_ib_value(p, idx + 1);
1299 w0 = G_038000_TEX_WIDTH(word0) + 1;
1300 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1301 d0 = G_038004_TEX_DEPTH(word1);
1302 nfaces = 1;
1303 switch (G_038000_DIM(word0)) {
1304 case V_038000_SQ_TEX_DIM_1D:
1305 case V_038000_SQ_TEX_DIM_2D:
1306 case V_038000_SQ_TEX_DIM_3D:
1307 break;
1308 case V_038000_SQ_TEX_DIM_CUBEMAP:
1309 if (p->family >= CHIP_RV770)
1310 nfaces = 8;
1311 else
1312 nfaces = 6;
1313 break;
1314 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1315 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1316 array = 1;
1317 break;
1318 case V_038000_SQ_TEX_DIM_2D_MSAA:
1319 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1320 default:
1321 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1322 return -EINVAL;
1323 }
1324 format = G_038004_DATA_FORMAT(word1);
1325 if (!fmt_is_valid_texture(format, p->family)) {
1326 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1327 __func__, __LINE__, format);
1328 return -EINVAL;
1329 }
1330
1331 /* pitch in texels */
1332 pitch = (G_038000_PITCH(word0) + 1) * 8;
1333 array_check.array_mode = G_038000_TILE_MODE(word0);
1334 array_check.group_size = track->group_size;
1335 array_check.nbanks = track->nbanks;
1336 array_check.npipes = track->npipes;
1337 array_check.nsamples = 1;
1338 array_check.blocksize = fmt_get_blocksize(format);
1339 if (r600_get_array_mode_alignment(&array_check,
1340 &pitch_align, &height_align, &depth_align, &base_align)) {
1341 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1342 __func__, __LINE__, G_038000_TILE_MODE(word0));
1343 return -EINVAL;
1344 }
1345
1346 /* XXX check height as well... */
1347
1348 if (!IS_ALIGNED(pitch, pitch_align)) {
1349 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1350 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1351 return -EINVAL;
1352 }
1353 if (!IS_ALIGNED(base_offset, base_align)) {
1354 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1355 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1356 return -EINVAL;
1357 }
1358 if (!IS_ALIGNED(mip_offset, base_align)) {
1359 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1360 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1361 return -EINVAL;
1362 }
1363
1364 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1365 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1366
1367 word0 = radeon_get_ib_value(p, idx + 4);
1368 word1 = radeon_get_ib_value(p, idx + 5);
1369 blevel = G_038010_BASE_LEVEL(word0);
1370 llevel = G_038014_LAST_LEVEL(word1);
1371 if (array == 1) {
1372 barray = G_038014_BASE_ARRAY(word1);
1373 larray = G_038014_LAST_ARRAY(word1);
1374
1375 nfaces = larray - barray + 1;
1376 }
1377 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1378 pitch_align, height_align, base_align,
1379 &l0_size, &mipmap_size);
1380 /* using get ib will give us the offset into the texture bo */
1381 if ((l0_size + word2) > radeon_bo_size(texture)) {
1382 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1383 w0, h0, format, word2, l0_size, radeon_bo_size(texture));
1384 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1385 return -EINVAL;
1386 }
1387 /* using get ib will give us the offset into the mipmap bo */
1388 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1389 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1390 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1391 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1392 }
1393 return 0;
1394 }
1395
1396 static int r600_packet3_check(struct radeon_cs_parser *p,
1397 struct radeon_cs_packet *pkt)
1398 {
1399 struct radeon_cs_reloc *reloc;
1400 struct r600_cs_track *track;
1401 volatile u32 *ib;
1402 unsigned idx;
1403 unsigned i;
1404 unsigned start_reg, end_reg, reg;
1405 int r;
1406 u32 idx_value;
1407
1408 track = (struct r600_cs_track *)p->track;
1409 ib = p->ib->ptr;
1410 idx = pkt->idx + 1;
1411 idx_value = radeon_get_ib_value(p, idx);
1412
1413 switch (pkt->opcode) {
1414 case PACKET3_SET_PREDICATION:
1415 {
1416 int pred_op;
1417 int tmp;
1418 if (pkt->count != 1) {
1419 DRM_ERROR("bad SET PREDICATION\n");
1420 return -EINVAL;
1421 }
1422
1423 tmp = radeon_get_ib_value(p, idx + 1);
1424 pred_op = (tmp >> 16) & 0x7;
1425
1426 /* for the clear predicate operation */
1427 if (pred_op == 0)
1428 return 0;
1429
1430 if (pred_op > 2) {
1431 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1432 return -EINVAL;
1433 }
1434
1435 r = r600_cs_packet_next_reloc(p, &reloc);
1436 if (r) {
1437 DRM_ERROR("bad SET PREDICATION\n");
1438 return -EINVAL;
1439 }
1440
1441 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1442 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1443 }
1444 break;
1445
1446 case PACKET3_START_3D_CMDBUF:
1447 if (p->family >= CHIP_RV770 || pkt->count) {
1448 DRM_ERROR("bad START_3D\n");
1449 return -EINVAL;
1450 }
1451 break;
1452 case PACKET3_CONTEXT_CONTROL:
1453 if (pkt->count != 1) {
1454 DRM_ERROR("bad CONTEXT_CONTROL\n");
1455 return -EINVAL;
1456 }
1457 break;
1458 case PACKET3_INDEX_TYPE:
1459 case PACKET3_NUM_INSTANCES:
1460 if (pkt->count) {
1461 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1462 return -EINVAL;
1463 }
1464 break;
1465 case PACKET3_DRAW_INDEX:
1466 if (pkt->count != 3) {
1467 DRM_ERROR("bad DRAW_INDEX\n");
1468 return -EINVAL;
1469 }
1470 r = r600_cs_packet_next_reloc(p, &reloc);
1471 if (r) {
1472 DRM_ERROR("bad DRAW_INDEX\n");
1473 return -EINVAL;
1474 }
1475 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1476 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1477 r = r600_cs_track_check(p);
1478 if (r) {
1479 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1480 return r;
1481 }
1482 break;
1483 case PACKET3_DRAW_INDEX_AUTO:
1484 if (pkt->count != 1) {
1485 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1486 return -EINVAL;
1487 }
1488 r = r600_cs_track_check(p);
1489 if (r) {
1490 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1491 return r;
1492 }
1493 break;
1494 case PACKET3_DRAW_INDEX_IMMD_BE:
1495 case PACKET3_DRAW_INDEX_IMMD:
1496 if (pkt->count < 2) {
1497 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1498 return -EINVAL;
1499 }
1500 r = r600_cs_track_check(p);
1501 if (r) {
1502 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1503 return r;
1504 }
1505 break;
1506 case PACKET3_WAIT_REG_MEM:
1507 if (pkt->count != 5) {
1508 DRM_ERROR("bad WAIT_REG_MEM\n");
1509 return -EINVAL;
1510 }
1511 /* bit 4 is reg (0) or mem (1) */
1512 if (idx_value & 0x10) {
1513 r = r600_cs_packet_next_reloc(p, &reloc);
1514 if (r) {
1515 DRM_ERROR("bad WAIT_REG_MEM\n");
1516 return -EINVAL;
1517 }
1518 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1519 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1520 }
1521 break;
1522 case PACKET3_SURFACE_SYNC:
1523 if (pkt->count != 3) {
1524 DRM_ERROR("bad SURFACE_SYNC\n");
1525 return -EINVAL;
1526 }
1527 /* 0xffffffff/0x0 is flush all cache flag */
1528 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1529 radeon_get_ib_value(p, idx + 2) != 0) {
1530 r = r600_cs_packet_next_reloc(p, &reloc);
1531 if (r) {
1532 DRM_ERROR("bad SURFACE_SYNC\n");
1533 return -EINVAL;
1534 }
1535 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1536 }
1537 break;
1538 case PACKET3_EVENT_WRITE:
1539 if (pkt->count != 2 && pkt->count != 0) {
1540 DRM_ERROR("bad EVENT_WRITE\n");
1541 return -EINVAL;
1542 }
1543 if (pkt->count) {
1544 r = r600_cs_packet_next_reloc(p, &reloc);
1545 if (r) {
1546 DRM_ERROR("bad EVENT_WRITE\n");
1547 return -EINVAL;
1548 }
1549 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1550 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1551 }
1552 break;
1553 case PACKET3_EVENT_WRITE_EOP:
1554 if (pkt->count != 4) {
1555 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1556 return -EINVAL;
1557 }
1558 r = r600_cs_packet_next_reloc(p, &reloc);
1559 if (r) {
1560 DRM_ERROR("bad EVENT_WRITE\n");
1561 return -EINVAL;
1562 }
1563 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1564 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1565 break;
1566 case PACKET3_SET_CONFIG_REG:
1567 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1568 end_reg = 4 * pkt->count + start_reg - 4;
1569 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1570 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1571 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1572 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1573 return -EINVAL;
1574 }
1575 for (i = 0; i < pkt->count; i++) {
1576 reg = start_reg + (4 * i);
1577 r = r600_cs_check_reg(p, reg, idx+1+i);
1578 if (r)
1579 return r;
1580 }
1581 break;
1582 case PACKET3_SET_CONTEXT_REG:
1583 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1584 end_reg = 4 * pkt->count + start_reg - 4;
1585 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1586 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1587 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1588 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1589 return -EINVAL;
1590 }
1591 for (i = 0; i < pkt->count; i++) {
1592 reg = start_reg + (4 * i);
1593 r = r600_cs_check_reg(p, reg, idx+1+i);
1594 if (r)
1595 return r;
1596 }
1597 break;
1598 case PACKET3_SET_RESOURCE:
1599 if (pkt->count % 7) {
1600 DRM_ERROR("bad SET_RESOURCE\n");
1601 return -EINVAL;
1602 }
1603 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1604 end_reg = 4 * pkt->count + start_reg - 4;
1605 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1606 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1607 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1608 DRM_ERROR("bad SET_RESOURCE\n");
1609 return -EINVAL;
1610 }
1611 for (i = 0; i < (pkt->count / 7); i++) {
1612 struct radeon_bo *texture, *mipmap;
1613 u32 size, offset, base_offset, mip_offset;
1614
1615 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1616 case SQ_TEX_VTX_VALID_TEXTURE:
1617 /* tex base */
1618 r = r600_cs_packet_next_reloc(p, &reloc);
1619 if (r) {
1620 DRM_ERROR("bad SET_RESOURCE\n");
1621 return -EINVAL;
1622 }
1623 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1624 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1625 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1626 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1627 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1628 texture = reloc->robj;
1629 /* tex mip base */
1630 r = r600_cs_packet_next_reloc(p, &reloc);
1631 if (r) {
1632 DRM_ERROR("bad SET_RESOURCE\n");
1633 return -EINVAL;
1634 }
1635 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1636 mipmap = reloc->robj;
1637 r = r600_check_texture_resource(p, idx+(i*7)+1,
1638 texture, mipmap,
1639 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1640 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1641 reloc->lobj.tiling_flags);
1642 if (r)
1643 return r;
1644 ib[idx+1+(i*7)+2] += base_offset;
1645 ib[idx+1+(i*7)+3] += mip_offset;
1646 break;
1647 case SQ_TEX_VTX_VALID_BUFFER:
1648 /* vtx base */
1649 r = r600_cs_packet_next_reloc(p, &reloc);
1650 if (r) {
1651 DRM_ERROR("bad SET_RESOURCE\n");
1652 return -EINVAL;
1653 }
1654 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1655 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1656 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1657 /* force size to size of the buffer */
1658 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1659 size + offset, radeon_bo_size(reloc->robj));
1660 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1661 }
1662 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1663 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1664 break;
1665 case SQ_TEX_VTX_INVALID_TEXTURE:
1666 case SQ_TEX_VTX_INVALID_BUFFER:
1667 default:
1668 DRM_ERROR("bad SET_RESOURCE\n");
1669 return -EINVAL;
1670 }
1671 }
1672 break;
1673 case PACKET3_SET_ALU_CONST:
1674 if (track->sq_config & DX9_CONSTS) {
1675 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1676 end_reg = 4 * pkt->count + start_reg - 4;
1677 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1678 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1679 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1680 DRM_ERROR("bad SET_ALU_CONST\n");
1681 return -EINVAL;
1682 }
1683 }
1684 break;
1685 case PACKET3_SET_BOOL_CONST:
1686 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1687 end_reg = 4 * pkt->count + start_reg - 4;
1688 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1689 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1690 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1691 DRM_ERROR("bad SET_BOOL_CONST\n");
1692 return -EINVAL;
1693 }
1694 break;
1695 case PACKET3_SET_LOOP_CONST:
1696 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1697 end_reg = 4 * pkt->count + start_reg - 4;
1698 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1699 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1700 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1701 DRM_ERROR("bad SET_LOOP_CONST\n");
1702 return -EINVAL;
1703 }
1704 break;
1705 case PACKET3_SET_CTL_CONST:
1706 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1707 end_reg = 4 * pkt->count + start_reg - 4;
1708 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1709 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1710 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1711 DRM_ERROR("bad SET_CTL_CONST\n");
1712 return -EINVAL;
1713 }
1714 break;
1715 case PACKET3_SET_SAMPLER:
1716 if (pkt->count % 3) {
1717 DRM_ERROR("bad SET_SAMPLER\n");
1718 return -EINVAL;
1719 }
1720 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1721 end_reg = 4 * pkt->count + start_reg - 4;
1722 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1723 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1724 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1725 DRM_ERROR("bad SET_SAMPLER\n");
1726 return -EINVAL;
1727 }
1728 break;
1729 case PACKET3_SURFACE_BASE_UPDATE:
1730 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1731 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1732 return -EINVAL;
1733 }
1734 if (pkt->count) {
1735 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1736 return -EINVAL;
1737 }
1738 break;
1739 case PACKET3_NOP:
1740 break;
1741 default:
1742 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1743 return -EINVAL;
1744 }
1745 return 0;
1746 }
1747
1748 int r600_cs_parse(struct radeon_cs_parser *p)
1749 {
1750 struct radeon_cs_packet pkt;
1751 struct r600_cs_track *track;
1752 int r;
1753
1754 if (p->track == NULL) {
1755 /* initialize tracker, we are in kms */
1756 track = kzalloc(sizeof(*track), GFP_KERNEL);
1757 if (track == NULL)
1758 return -ENOMEM;
1759 r600_cs_track_init(track);
1760 if (p->rdev->family < CHIP_RV770) {
1761 track->npipes = p->rdev->config.r600.tiling_npipes;
1762 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1763 track->group_size = p->rdev->config.r600.tiling_group_size;
1764 } else if (p->rdev->family <= CHIP_RV740) {
1765 track->npipes = p->rdev->config.rv770.tiling_npipes;
1766 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1767 track->group_size = p->rdev->config.rv770.tiling_group_size;
1768 }
1769 p->track = track;
1770 }
1771 do {
1772 r = r600_cs_packet_parse(p, &pkt, p->idx);
1773 if (r) {
1774 kfree(p->track);
1775 p->track = NULL;
1776 return r;
1777 }
1778 p->idx += pkt.count + 2;
1779 switch (pkt.type) {
1780 case PACKET_TYPE0:
1781 r = r600_cs_parse_packet0(p, &pkt);
1782 break;
1783 case PACKET_TYPE2:
1784 break;
1785 case PACKET_TYPE3:
1786 r = r600_packet3_check(p, &pkt);
1787 break;
1788 default:
1789 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1790 kfree(p->track);
1791 p->track = NULL;
1792 return -EINVAL;
1793 }
1794 if (r) {
1795 kfree(p->track);
1796 p->track = NULL;
1797 return r;
1798 }
1799 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1800 #if 0
1801 for (r = 0; r < p->ib->length_dw; r++) {
1802 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1803 mdelay(1);
1804 }
1805 #endif
1806 kfree(p->track);
1807 p->track = NULL;
1808 return 0;
1809 }
1810
1811 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1812 {
1813 if (p->chunk_relocs_idx == -1) {
1814 return 0;
1815 }
1816 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1817 if (p->relocs == NULL) {
1818 return -ENOMEM;
1819 }
1820 return 0;
1821 }
1822
1823 /**
1824 * cs_parser_fini() - clean parser states
1825 * @parser: parser structure holding parsing context.
1826 * @error: error number
1827 *
1828 * If error is set than unvalidate buffer, otherwise just free memory
1829 * used by parsing context.
1830 **/
1831 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1832 {
1833 unsigned i;
1834
1835 kfree(parser->relocs);
1836 for (i = 0; i < parser->nchunks; i++) {
1837 kfree(parser->chunks[i].kdata);
1838 kfree(parser->chunks[i].kpage[0]);
1839 kfree(parser->chunks[i].kpage[1]);
1840 }
1841 kfree(parser->chunks);
1842 kfree(parser->chunks_array);
1843 }
1844
1845 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1846 unsigned family, u32 *ib, int *l)
1847 {
1848 struct radeon_cs_parser parser;
1849 struct radeon_cs_chunk *ib_chunk;
1850 struct radeon_ib fake_ib;
1851 struct r600_cs_track *track;
1852 int r;
1853
1854 /* initialize tracker */
1855 track = kzalloc(sizeof(*track), GFP_KERNEL);
1856 if (track == NULL)
1857 return -ENOMEM;
1858 r600_cs_track_init(track);
1859 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1860 /* initialize parser */
1861 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1862 parser.filp = filp;
1863 parser.dev = &dev->pdev->dev;
1864 parser.rdev = NULL;
1865 parser.family = family;
1866 parser.ib = &fake_ib;
1867 parser.track = track;
1868 fake_ib.ptr = ib;
1869 r = radeon_cs_parser_init(&parser, data);
1870 if (r) {
1871 DRM_ERROR("Failed to initialize parser !\n");
1872 r600_cs_parser_fini(&parser, r);
1873 return r;
1874 }
1875 r = r600_cs_parser_relocs_legacy(&parser);
1876 if (r) {
1877 DRM_ERROR("Failed to parse relocation !\n");
1878 r600_cs_parser_fini(&parser, r);
1879 return r;
1880 }
1881 /* Copy the packet into the IB, the parser will read from the
1882 * input memory (cached) and write to the IB (which can be
1883 * uncached). */
1884 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1885 parser.ib->length_dw = ib_chunk->length_dw;
1886 *l = parser.ib->length_dw;
1887 r = r600_cs_parse(&parser);
1888 if (r) {
1889 DRM_ERROR("Invalid command stream !\n");
1890 r600_cs_parser_fini(&parser, r);
1891 return r;
1892 }
1893 r = radeon_cs_finish_pages(&parser);
1894 if (r) {
1895 DRM_ERROR("Invalid command stream !\n");
1896 r600_cs_parser_fini(&parser, r);
1897 return r;
1898 }
1899 r600_cs_parser_fini(&parser, r);
1900 return r;
1901 }
1902
1903 void r600_cs_legacy_init(void)
1904 {
1905 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1906 }
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