drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "vmwgfx_drv.h"
  29 #include "drmP.h"
  30 #include "ttm/ttm_placement.h"
  31
  32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  33 {
  34         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  35         uint32_t fifo_min, hwversion;
  36
  37         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  38                 return false;
  39
  40         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  41         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  42                 return false;
  43
  44         hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
  45         if (hwversion == 0)
  46                 return false;
  47
  48         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  49                 return false;
  50
  51         /* Non-Screen Object path does not support surfaces */
  52         if (!dev_priv->sou_priv)
  53                 return false;
  54
  55         return true;
  56 }
  57
  58 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  59 {
  60         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  61         uint32_t caps;
  62
  63         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  64                 return false;
  65
  66         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  67         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  68                 return true;
  69
  70         return false;
  71 }
  72
  73 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  74 {
  75         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  76         uint32_t max;
  77         uint32_t min;
  78         uint32_t dummy;
  79
  80         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  81         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
  82         if (unlikely(fifo->static_buffer == NULL))
  83                 return -ENOMEM;
  84
  85         fifo->dynamic_buffer = NULL;
  86         fifo->reserved_size = 0;
  87         fifo->using_bounce_buffer = false;
  88
  89         mutex_init(&fifo->fifo_mutex);
  90         init_rwsem(&fifo->rwsem);
  91
  92         /*
  93          * Allow mapping the first page read-only to user-space.
  94          */
  95
  96         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
  97         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
  98         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
  99
 100         mutex_lock(&dev_priv->hw_mutex);
 101         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 102         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 103         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 104         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 105
 106         min = 4;
 107         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 108                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 109         min <<= 2;
 110
 111         if (min < PAGE_SIZE)
 112                 min = PAGE_SIZE;
 113
 114         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
 115         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
 116         wmb();
 117         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
 118         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
 119         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
 120         mb();
 121
 122         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 123         mutex_unlock(&dev_priv->hw_mutex);
 124
 125         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 126         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 127         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 128
 129         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 130                  (unsigned int) max,
 131                  (unsigned int) min,
 132                  (unsigned int) fifo->capabilities);
 133
 134         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 135         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
 136         vmw_marker_queue_init(&fifo->marker_queue);
 137         return vmw_fifo_send_fence(dev_priv, &dummy);
 138 }
 139
 140 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 141 {
 142         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 143
 144         mutex_lock(&dev_priv->hw_mutex);
 145
 146         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 147                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 148                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 149         }
 150
 151         mutex_unlock(&dev_priv->hw_mutex);
 152 }
 153
 154 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 155 {
 156         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 157
 158         mutex_lock(&dev_priv->hw_mutex);
 159
 160         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 161                 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 162
 163         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 164
 165         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 166                   dev_priv->config_done_state);
 167         vmw_write(dev_priv, SVGA_REG_ENABLE,
 168                   dev_priv->enable_state);
 169         vmw_write(dev_priv, SVGA_REG_TRACES,
 170                   dev_priv->traces_state);
 171
 172         mutex_unlock(&dev_priv->hw_mutex);
 173         vmw_marker_queue_takedown(&fifo->marker_queue);
 174
 175         if (likely(fifo->static_buffer != NULL)) {
 176                 vfree(fifo->static_buffer);
 177                 fifo->static_buffer = NULL;
 178         }
 179
 180         if (likely(fifo->dynamic_buffer != NULL)) {
 181                 vfree(fifo->dynamic_buffer);
 182                 fifo->dynamic_buffer = NULL;
 183         }
 184 }
 185
 186 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 187 {
 188         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 189         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 190         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 191         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 192         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 193
 194         return ((max - next_cmd) + (stop - min) <= bytes);
 195 }
 196
 197 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 198                                uint32_t bytes, bool interruptible,
 199                                unsigned long timeout)
 200 {
 201         int ret = 0;
 202         unsigned long end_jiffies = jiffies + timeout;
 203         DEFINE_WAIT(__wait);
 204
 205         DRM_INFO("Fifo wait noirq.\n");
 206
 207         for (;;) {
 208                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 209                                 (interruptible) ?
 210                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 211                 if (!vmw_fifo_is_full(dev_priv, bytes))
 212                         break;
 213                 if (time_after_eq(jiffies, end_jiffies)) {
 214                         ret = -EBUSY;
 215                         DRM_ERROR("SVGA device lockup.\n");
 216                         break;
 217                 }
 218                 schedule_timeout(1);
 219                 if (interruptible && signal_pending(current)) {
 220                         ret = -ERESTARTSYS;
 221                         break;
 222                 }
 223         }
 224         finish_wait(&dev_priv->fifo_queue, &__wait);
 225         wake_up_all(&dev_priv->fifo_queue);
 226         DRM_INFO("Fifo noirq exit.\n");
 227         return ret;
 228 }
 229
 230 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 231                          uint32_t bytes, bool interruptible,
 232                          unsigned long timeout)
 233 {
 234         long ret = 1L;
 235         unsigned long irq_flags;
 236
 237         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 238                 return 0;
 239
 240         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 241         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 242                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 243                                            interruptible, timeout);
 244
 245         mutex_lock(&dev_priv->hw_mutex);
 246         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 247                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 248                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 249                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 250                 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
 251                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 252                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 253         }
 254         mutex_unlock(&dev_priv->hw_mutex);
 255
 256         if (interruptible)
 257                 ret = wait_event_interruptible_timeout
 258                     (dev_priv->fifo_queue,
 259                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 260         else
 261                 ret = wait_event_timeout
 262                     (dev_priv->fifo_queue,
 263                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 264
 265         if (unlikely(ret == 0))
 266                 ret = -EBUSY;
 267         else if (likely(ret > 0))
 268                 ret = 0;
 269
 270         mutex_lock(&dev_priv->hw_mutex);
 271         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 272                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 273                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
 274                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 275                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 276         }
 277         mutex_unlock(&dev_priv->hw_mutex);
 278
 279         return ret;
 280 }
 281
 282 /**
 283  * Reserve @bytes number of bytes in the fifo.
 284  *
 285  * This function will return NULL (error) on two conditions:
 286  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 287  *   available fifo space.
 288  *
 289  * Returns:
 290  *   Pointer to the fifo, or null on error (possible hardware hang).
 291  */
 292 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
 293 {
 294         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 295         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 296         uint32_t max;
 297         uint32_t min;
 298         uint32_t next_cmd;
 299         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 300         int ret;
 301
 302         mutex_lock(&fifo_state->fifo_mutex);
 303         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 304         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 305         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 306
 307         if (unlikely(bytes >= (max - min)))
 308                 goto out_err;
 309
 310         BUG_ON(fifo_state->reserved_size != 0);
 311         BUG_ON(fifo_state->dynamic_buffer != NULL);
 312
 313         fifo_state->reserved_size = bytes;
 314
 315         while (1) {
 316                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 317                 bool need_bounce = false;
 318                 bool reserve_in_place = false;
 319
 320                 if (next_cmd >= stop) {
 321                         if (likely((next_cmd + bytes < max ||
 322                                     (next_cmd + bytes == max && stop > min))))
 323                                 reserve_in_place = true;
 324
 325                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 326                                 ret = vmw_fifo_wait(dev_priv, bytes,
 327                                                     false, 3 * HZ);
 328                                 if (unlikely(ret != 0))
 329                                         goto out_err;
 330                         } else
 331                                 need_bounce = true;
 332
 333                 } else {
 334
 335                         if (likely((next_cmd + bytes < stop)))
 336                                 reserve_in_place = true;
 337                         else {
 338                                 ret = vmw_fifo_wait(dev_priv, bytes,
 339                                                     false, 3 * HZ);
 340                                 if (unlikely(ret != 0))
 341                                         goto out_err;
 342                         }
 343                 }
 344
 345                 if (reserve_in_place) {
 346                         if (reserveable || bytes <= sizeof(uint32_t)) {
 347                                 fifo_state->using_bounce_buffer = false;
 348
 349                                 if (reserveable)
 350                                         iowrite32(bytes, fifo_mem +
 351                                                   SVGA_FIFO_RESERVED);
 352                                 return fifo_mem + (next_cmd >> 2);
 353                         } else {
 354                                 need_bounce = true;
 355                         }
 356                 }
 357
 358                 if (need_bounce) {
 359                         fifo_state->using_bounce_buffer = true;
 360                         if (bytes < fifo_state->static_buffer_size)
 361                                 return fifo_state->static_buffer;
 362                         else {
 363                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 364                                 return fifo_state->dynamic_buffer;
 365                         }
 366                 }
 367         }
 368 out_err:
 369         fifo_state->reserved_size = 0;
 370         mutex_unlock(&fifo_state->fifo_mutex);
 371         return NULL;
 372 }
 373
 374 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 375                               __le32 __iomem *fifo_mem,
 376                               uint32_t next_cmd,
 377                               uint32_t max, uint32_t min, uint32_t bytes)
 378 {
 379         uint32_t chunk_size = max - next_cmd;
 380         uint32_t rest;
 381         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 382             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 383
 384         if (bytes < chunk_size)
 385                 chunk_size = bytes;
 386
 387         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
 388         mb();
 389         memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 390         rest = bytes - chunk_size;
 391         if (rest)
 392                 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
 393                             rest);
 394 }
 395
 396 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 397                                __le32 __iomem *fifo_mem,
 398                                uint32_t next_cmd,
 399                                uint32_t max, uint32_t min, uint32_t bytes)
 400 {
 401         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 402             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 403
 404         while (bytes > 0) {
 405                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
 406                 next_cmd += sizeof(uint32_t);
 407                 if (unlikely(next_cmd == max))
 408                         next_cmd = min;
 409                 mb();
 410                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 411                 mb();
 412                 bytes -= sizeof(uint32_t);
 413         }
 414 }
 415
 416 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 417 {
 418         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 419         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 420         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 421         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 422         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 423         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 424
 425         BUG_ON((bytes & 3) != 0);
 426         BUG_ON(bytes > fifo_state->reserved_size);
 427
 428         fifo_state->reserved_size = 0;
 429
 430         if (fifo_state->using_bounce_buffer) {
 431                 if (reserveable)
 432                         vmw_fifo_res_copy(fifo_state, fifo_mem,
 433                                           next_cmd, max, min, bytes);
 434                 else
 435                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
 436                                            next_cmd, max, min, bytes);
 437
 438                 if (fifo_state->dynamic_buffer) {
 439                         vfree(fifo_state->dynamic_buffer);
 440                         fifo_state->dynamic_buffer = NULL;
 441                 }
 442
 443         }
 444
 445         down_write(&fifo_state->rwsem);
 446         if (fifo_state->using_bounce_buffer || reserveable) {
 447                 next_cmd += bytes;
 448                 if (next_cmd >= max)
 449                         next_cmd -= max - min;
 450                 mb();
 451                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 452         }
 453
 454         if (reserveable)
 455                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
 456         mb();
 457         up_write(&fifo_state->rwsem);
 458         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 459         mutex_unlock(&fifo_state->fifo_mutex);
 460 }
 461
 462 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 463 {
 464         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 465         struct svga_fifo_cmd_fence *cmd_fence;
 466         void *fm;
 467         int ret = 0;
 468         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 469
 470         fm = vmw_fifo_reserve(dev_priv, bytes);
 471         if (unlikely(fm == NULL)) {
 472                 *seqno = atomic_read(&dev_priv->marker_seq);
 473                 ret = -ENOMEM;
 474                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
 475                                         false, 3*HZ);
 476                 goto out_err;
 477         }
 478
 479         do {
 480                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
 481         } while (*seqno == 0);
 482
 483         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 484
 485                 /*
 486                  * Don't request hardware to send a fence. The
 487                  * waiting code in vmwgfx_irq.c will emulate this.
 488                  */
 489
 490                 vmw_fifo_commit(dev_priv, 0);
 491                 return 0;
 492         }
 493
 494         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
 495         cmd_fence = (struct svga_fifo_cmd_fence *)
 496             ((unsigned long)fm + sizeof(__le32));
 497
 498         iowrite32(*seqno, &cmd_fence->fence);
 499         vmw_fifo_commit(dev_priv, bytes);
 500         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
 501         vmw_update_seqno(dev_priv, fifo_state);
 502
 503 out_err:
 504         return ret;
 505 }
 506
 507 /**
 508  * vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
 509  *
 510  * @dev_priv: The device private structure.
 511  * @cid: The hardware context id used for the query.
 512  *
 513  * This function is used to emit a dummy occlusion query with
 514  * no primitives rendered between query begin and query end.
 515  * It's used to provide a query barrier, in order to know that when
 516  * this query is finished, all preceding queries are also finished.
 517  *
 518  * A Query results structure should have been initialized at the start
 519  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 520  * must also be either reserved or pinned when this function is called.
 521  *
 522  * Returns -ENOMEM on failure to reserve fifo space.
 523  */
 524 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
 525                               uint32_t cid)
 526 {
 527         /*
 528          * A query wait without a preceding query end will
 529          * actually finish all queries for this cid
 530          * without writing to the query result structure.
 531          */
 532
 533         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 534         struct {
 535                 SVGA3dCmdHeader header;
 536                 SVGA3dCmdWaitForQuery body;
 537         } *cmd;
 538
 539         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 540
 541         if (unlikely(cmd == NULL)) {
 542                 DRM_ERROR("Out of fifo space for dummy query.\n");
 543                 return -ENOMEM;
 544         }
 545
 546         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
 547         cmd->header.size = sizeof(cmd->body);
 548         cmd->body.cid = cid;
 549         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 550
 551         if (bo->mem.mem_type == TTM_PL_VRAM) {
 552                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
 553                 cmd->body.guestResult.offset = bo->offset;
 554         } else {
 555                 cmd->body.guestResult.gmrId = bo->mem.start;
 556                 cmd->body.guestResult.offset = 0;
 557         }
 558
 559         vmw_fifo_commit(dev_priv, sizeof(*cmd));
 560
 561         return 0;
 562 }