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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / i2c / busses / i2c-eg20t.c
blob8cebef49aeaca2b81a94b862387fb0be46dcdaa5
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/i2c.h>
24 #include <linux/fs.h>
25 #include <linux/io.h>
26 #include <linux/types.h>
27 #include <linux/interrupt.h>
28 #include <linux/jiffies.h>
29 #include <linux/pci.h>
30 #include <linux/mutex.h>
31 #include <linux/ktime.h>
32 #include <linux/slab.h>
33
34 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
35 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
36 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
37 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
38 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
39
40 #define PCH_I2CSADR 0x00 /* I2C slave address register */
41 #define PCH_I2CCTL 0x04 /* I2C control register */
42 #define PCH_I2CSR 0x08 /* I2C status register */
43 #define PCH_I2CDR 0x0C /* I2C data register */
44 #define PCH_I2CMON 0x10 /* I2C bus monitor register */
45 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
46 #define PCH_I2CMOD 0x18 /* I2C mode register */
47 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
48 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
49 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
50 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
51 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
52 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
53 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
54 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
55 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
56 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
57 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
58 #define PCH_I2CTMR 0x48 /* I2C timer register */
59 #define PCH_I2CSRST 0xFC /* I2C reset register */
60 #define PCH_I2CNF 0xF8 /* I2C noise filter register */
61
62 #define BUS_IDLE_TIMEOUT 20
63 #define PCH_I2CCTL_I2CMEN 0x0080
64 #define TEN_BIT_ADDR_DEFAULT 0xF000
65 #define TEN_BIT_ADDR_MASK 0xF0
66 #define PCH_START 0x0020
67 #define PCH_RESTART 0x0004
68 #define PCH_ESR_START 0x0001
69 #define PCH_BUFF_START 0x1
70 #define PCH_REPSTART 0x0004
71 #define PCH_ACK 0x0008
72 #define PCH_GETACK 0x0001
73 #define CLR_REG 0x0
74 #define I2C_RD 0x1
75 #define I2CMCF_BIT 0x0080
76 #define I2CMIF_BIT 0x0002
77 #define I2CMAL_BIT 0x0010
78 #define I2CBMFI_BIT 0x0001
79 #define I2CBMAL_BIT 0x0002
80 #define I2CBMNA_BIT 0x0004
81 #define I2CBMTO_BIT 0x0008
82 #define I2CBMIS_BIT 0x0010
83 #define I2CESRFI_BIT 0X0001
84 #define I2CESRTO_BIT 0x0002
85 #define I2CESRFIIE_BIT 0x1
86 #define I2CESRTOIE_BIT 0x2
87 #define I2CBMDZ_BIT 0x0040
88 #define I2CBMAG_BIT 0x0020
89 #define I2CMBB_BIT 0x0020
90 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
91 I2CBMTO_BIT | I2CBMIS_BIT)
92 #define I2C_ADDR_MSK 0xFF
93 #define I2C_MSB_2B_MSK 0x300
94 #define FAST_MODE_CLK 400
95 #define FAST_MODE_EN 0x0001
96 #define SUB_ADDR_LEN_MAX 4
97 #define BUF_LEN_MAX 32
98 #define PCH_BUFFER_MODE 0x1
99 #define EEPROM_SW_RST_MODE 0x0002
100 #define NORMAL_INTR_ENBL 0x0300
101 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
102 #define EEPROM_RST_INTR_DISBL 0x0
103 #define BUFFER_MODE_INTR_ENBL 0x001F
104 #define BUFFER_MODE_INTR_DISBL 0x0
105 #define NORMAL_MODE 0x0
106 #define BUFFER_MODE 0x1
107 #define EEPROM_SR_MODE 0x2
108 #define I2C_TX_MODE 0x0010
109 #define PCH_BUF_TX 0xFFF7
110 #define PCH_BUF_RD 0x0008
111 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
112 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
113 #define I2CMAL_EVENT 0x0001
114 #define I2CMCF_EVENT 0x0002
115 #define I2CBMFI_EVENT 0x0004
116 #define I2CBMAL_EVENT 0x0008
117 #define I2CBMNA_EVENT 0x0010
118 #define I2CBMTO_EVENT 0x0020
119 #define I2CBMIS_EVENT 0x0040
120 #define I2CESRFI_EVENT 0x0080
121 #define I2CESRTO_EVENT 0x0100
122 #define PCI_DEVICE_ID_PCH_I2C 0x8817
123
124 #define pch_dbg(adap, fmt, arg...) \
125 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
126
127 #define pch_err(adap, fmt, arg...) \
128 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
129
130 #define pch_pci_err(pdev, fmt, arg...) \
131 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
132
133 #define pch_pci_dbg(pdev, fmt, arg...) \
134 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
135
136 /*
137 Set the number of I2C instance max
138 Intel EG20T PCH : 1ch
139 OKI SEMICONDUCTOR ML7213 IOH : 2ch
140 */
141 #define PCH_I2C_MAX_DEV 2
142
143 /**
144 * struct i2c_algo_pch_data - for I2C driver functionalities
145 * @pch_adapter: stores the reference to i2c_adapter structure
146 * @p_adapter_info: stores the reference to adapter_info structure
147 * @pch_base_address: specifies the remapped base address
148 * @pch_buff_mode_en: specifies if buffer mode is enabled
149 * @pch_event_flag: specifies occurrence of interrupt events
150 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
151 */
152 struct i2c_algo_pch_data {
153 struct i2c_adapter pch_adapter;
154 struct adapter_info *p_adapter_info;
155 void __iomem *pch_base_address;
156 int pch_buff_mode_en;
157 u32 pch_event_flag;
158 bool pch_i2c_xfer_in_progress;
159 };
160
161 /**
162 * struct adapter_info - This structure holds the adapter information for the
163 PCH i2c controller
164 * @pch_data: stores a list of i2c_algo_pch_data
165 * @pch_i2c_suspended: specifies whether the system is suspended or not
166 * perhaps with more lines and words.
167 * @ch_num: specifies the number of i2c instance
168 *
169 * pch_data has as many elements as maximum I2C channels
170 */
171 struct adapter_info {
172 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
173 bool pch_i2c_suspended;
174 int ch_num;
175 };
176
177
178 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
179 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
180 static wait_queue_head_t pch_event;
181 static DEFINE_MUTEX(pch_mutex);
182
183 /* Definition for ML7213 by OKI SEMICONDUCTOR */
184 #define PCI_VENDOR_ID_ROHM 0x10DB
185 #define PCI_DEVICE_ID_ML7213_I2C 0x802D
186 #define PCI_DEVICE_ID_ML7223_I2C 0x8010
187
188 static struct pci_device_id __devinitdata pch_pcidev_id[] = {
189 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
190 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
191 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
192 {0,}
193 };
194
195 static irqreturn_t pch_i2c_handler(int irq, void *pData);
196
197 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
198 {
199 u32 val;
200 val = ioread32(addr + offset);
201 val |= bitmask;
202 iowrite32(val, addr + offset);
203 }
204
205 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
206 {
207 u32 val;
208 val = ioread32(addr + offset);
209 val &= (~bitmask);
210 iowrite32(val, addr + offset);
211 }
212
213 /**
214 * pch_i2c_init() - hardware initialization of I2C module
215 * @adap: Pointer to struct i2c_algo_pch_data.
216 */
217 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
218 {
219 void __iomem *p = adap->pch_base_address;
220 u32 pch_i2cbc;
221 u32 pch_i2ctmr;
222 u32 reg_value;
223
224 /* reset I2C controller */
225 iowrite32(0x01, p + PCH_I2CSRST);
226 msleep(20);
227 iowrite32(0x0, p + PCH_I2CSRST);
228
229 /* Initialize I2C registers */
230 iowrite32(0x21, p + PCH_I2CNF);
231
232 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
233
234 if (pch_i2c_speed != 400)
235 pch_i2c_speed = 100;
236
237 reg_value = PCH_I2CCTL_I2CMEN;
238 if (pch_i2c_speed == FAST_MODE_CLK) {
239 reg_value |= FAST_MODE_EN;
240 pch_dbg(adap, "Fast mode enabled\n");
241 }
242
243 if (pch_clk > PCH_MAX_CLK)
244 pch_clk = 62500;
245
246 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
247 /* Set transfer speed in I2CBC */
248 iowrite32(pch_i2cbc, p + PCH_I2CBC);
249
250 pch_i2ctmr = (pch_clk) / 8;
251 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
252
253 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
254 iowrite32(reg_value, p + PCH_I2CCTL);
255
256 pch_dbg(adap,
257 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
258 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
259
260 init_waitqueue_head(&pch_event);
261 }
262
263 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
264 {
265 return cmp1.tv64 < cmp2.tv64;
266 }
267
268 /**
269 * pch_i2c_wait_for_bus_idle() - check the status of bus.
270 * @adap: Pointer to struct i2c_algo_pch_data.
271 * @timeout: waiting time counter (us).
272 */
273 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
274 s32 timeout)
275 {
276 void __iomem *p = adap->pch_base_address;
277 ktime_t ns_val;
278
279 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
280 return 0;
281
282 /* MAX timeout value is timeout*1000*1000nsec */
283 ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
284 do {
285 msleep(20);
286 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
287 return 0;
288 } while (ktime_lt(ktime_get(), ns_val));
289
290 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
291 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
292 pch_i2c_init(adap);
293
294 return -ETIME;
295 }
296
297 /**
298 * pch_i2c_start() - Generate I2C start condition in normal mode.
299 * @adap: Pointer to struct i2c_algo_pch_data.
300 *
301 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
302 */
303 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
304 {
305 void __iomem *p = adap->pch_base_address;
306 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
307 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
308 }
309
310 /**
311 * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
312 * @adap: Pointer to struct i2c_algo_pch_data.
313 */
314 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
315 {
316 long ret;
317 ret = wait_event_timeout(pch_event,
318 (adap->pch_event_flag != 0), msecs_to_jiffies(50));
319
320 if (ret == 0) {
321 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
322 adap->pch_event_flag = 0;
323 return -ETIMEDOUT;
324 }
325
326 if (adap->pch_event_flag & I2C_ERROR_MASK) {
327 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
328 adap->pch_event_flag = 0;
329 return -EIO;
330 }
331
332 adap->pch_event_flag = 0;
333
334 return 0;
335 }
336
337 /**
338 * pch_i2c_getack() - to confirm ACK/NACK
339 * @adap: Pointer to struct i2c_algo_pch_data.
340 */
341 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
342 {
343 u32 reg_val;
344 void __iomem *p = adap->pch_base_address;
345 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
346
347 if (reg_val != 0) {
348 pch_err(adap, "return%d\n", -EPROTO);
349 return -EPROTO;
350 }
351
352 return 0;
353 }
354
355 /**
356 * pch_i2c_stop() - generate stop condition in normal mode.
357 * @adap: Pointer to struct i2c_algo_pch_data.
358 */
359 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
360 {
361 void __iomem *p = adap->pch_base_address;
362 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
363 /* clear the start bit */
364 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
365 }
366
367 /**
368 * pch_i2c_repstart() - generate repeated start condition in normal mode
369 * @adap: Pointer to struct i2c_algo_pch_data.
370 */
371 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
372 {
373 void __iomem *p = adap->pch_base_address;
374 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
375 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
376 }
377
378 /**
379 * pch_i2c_writebytes() - write data to I2C bus in normal mode
380 * @i2c_adap: Pointer to the struct i2c_adapter.
381 * @last: specifies whether last message or not.
382 * In the case of compound mode it will be 1 for last message,
383 * otherwise 0.
384 * @first: specifies whether first message or not.
385 * 1 for first message otherwise 0.
386 */
387 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
388 struct i2c_msg *msgs, u32 last, u32 first)
389 {
390 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
391 u8 *buf;
392 u32 length;
393 u32 addr;
394 u32 addr_2_msb;
395 u32 addr_8_lsb;
396 s32 wrcount;
397 s32 rtn;
398 void __iomem *p = adap->pch_base_address;
399
400 length = msgs->len;
401 buf = msgs->buf;
402 addr = msgs->addr;
403
404 /* enable master tx */
405 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
406
407 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
408 length);
409
410 if (first) {
411 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
412 return -ETIME;
413 }
414
415 if (msgs->flags & I2C_M_TEN) {
416 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
417 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
418 if (first)
419 pch_i2c_start(adap);
420
421 rtn = pch_i2c_wait_for_xfer_complete(adap);
422 if (rtn == 0) {
423 if (pch_i2c_getack(adap)) {
424 pch_dbg(adap, "Receive NACK for slave address"
425 "setting\n");
426 return -EIO;
427 }
428 addr_8_lsb = (addr & I2C_ADDR_MSK);
429 iowrite32(addr_8_lsb, p + PCH_I2CDR);
430 } else if (rtn == -EIO) { /* Arbitration Lost */
431 pch_err(adap, "Lost Arbitration\n");
432 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
433 I2CMAL_BIT);
434 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
435 I2CMIF_BIT);
436 pch_i2c_init(adap);
437 return -EAGAIN;
438 } else { /* wait-event timeout */
439 pch_i2c_stop(adap);
440 return -ETIME;
441 }
442 } else {
443 /* set 7 bit slave address and R/W bit as 0 */
444 iowrite32(addr << 1, p + PCH_I2CDR);
445 if (first)
446 pch_i2c_start(adap);
447 }
448
449 rtn = pch_i2c_wait_for_xfer_complete(adap);
450 if (rtn == 0) {
451 if (pch_i2c_getack(adap)) {
452 pch_dbg(adap, "Receive NACK for slave address"
453 "setting\n");
454 return -EIO;
455 }
456 } else if (rtn == -EIO) { /* Arbitration Lost */
457 pch_err(adap, "Lost Arbitration\n");
458 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
459 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
460 pch_i2c_init(adap);
461 return -EAGAIN;
462 } else { /* wait-event timeout */
463 pch_i2c_stop(adap);
464 return -ETIME;
465 }
466
467 for (wrcount = 0; wrcount < length; ++wrcount) {
468 /* write buffer value to I2C data register */
469 iowrite32(buf[wrcount], p + PCH_I2CDR);
470 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
471
472 rtn = pch_i2c_wait_for_xfer_complete(adap);
473 if (rtn == 0) {
474 if (pch_i2c_getack(adap)) {
475 pch_dbg(adap, "Receive NACK for slave address"
476 "setting\n");
477 return -EIO;
478 }
479 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
480 I2CMCF_BIT);
481 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
482 I2CMIF_BIT);
483 } else { /* wait-event timeout */
484 pch_i2c_stop(adap);
485 return -ETIME;
486 }
487 }
488
489 /* check if this is the last message */
490 if (last)
491 pch_i2c_stop(adap);
492 else
493 pch_i2c_repstart(adap);
494
495 pch_dbg(adap, "return=%d\n", wrcount);
496
497 return wrcount;
498 }
499
500 /**
501 * pch_i2c_sendack() - send ACK
502 * @adap: Pointer to struct i2c_algo_pch_data.
503 */
504 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
505 {
506 void __iomem *p = adap->pch_base_address;
507 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
508 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
509 }
510
511 /**
512 * pch_i2c_sendnack() - send NACK
513 * @adap: Pointer to struct i2c_algo_pch_data.
514 */
515 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
516 {
517 void __iomem *p = adap->pch_base_address;
518 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
519 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
520 }
521
522 /**
523 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
524 * @adap: Pointer to struct i2c_algo_pch_data.
525 *
526 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
527 */
528 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
529 {
530 void __iomem *p = adap->pch_base_address;
531 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
532 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
533 }
534
535 /**
536 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
537 * @i2c_adap: Pointer to the struct i2c_adapter.
538 * @msgs: Pointer to i2c_msg structure.
539 * @last: specifies whether last message or not.
540 * @first: specifies whether first message or not.
541 */
542 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
543 u32 last, u32 first)
544 {
545 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
546
547 u8 *buf;
548 u32 count;
549 u32 length;
550 u32 addr;
551 u32 addr_2_msb;
552 u32 addr_8_lsb;
553 void __iomem *p = adap->pch_base_address;
554 s32 rtn;
555
556 length = msgs->len;
557 buf = msgs->buf;
558 addr = msgs->addr;
559
560 /* enable master reception */
561 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
562
563 if (first) {
564 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
565 return -ETIME;
566 }
567
568 if (msgs->flags & I2C_M_TEN) {
569 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
570 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
571 if (first)
572 pch_i2c_start(adap);
573
574 rtn = pch_i2c_wait_for_xfer_complete(adap);
575 if (rtn == 0) {
576 if (pch_i2c_getack(adap)) {
577 pch_dbg(adap, "Receive NACK for slave address"
578 "setting\n");
579 return -EIO;
580 }
581 addr_8_lsb = (addr & I2C_ADDR_MSK);
582 iowrite32(addr_8_lsb, p + PCH_I2CDR);
583 } else if (rtn == -EIO) { /* Arbitration Lost */
584 pch_err(adap, "Lost Arbitration\n");
585 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
586 I2CMAL_BIT);
587 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
588 I2CMIF_BIT);
589 pch_i2c_init(adap);
590 return -EAGAIN;
591 } else { /* wait-event timeout */
592 pch_i2c_stop(adap);
593 return -ETIME;
594 }
595 pch_i2c_restart(adap);
596 rtn = pch_i2c_wait_for_xfer_complete(adap);
597 if (rtn == 0) {
598 if (pch_i2c_getack(adap)) {
599 pch_dbg(adap, "Receive NACK for slave address"
600 "setting\n");
601 return -EIO;
602 }
603 addr_2_msb |= I2C_RD;
604 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
605 p + PCH_I2CDR);
606 } else if (rtn == -EIO) { /* Arbitration Lost */
607 pch_err(adap, "Lost Arbitration\n");
608 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
609 I2CMAL_BIT);
610 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
611 I2CMIF_BIT);
612 pch_i2c_init(adap);
613 return -EAGAIN;
614 } else { /* wait-event timeout */
615 pch_i2c_stop(adap);
616 return -ETIME;
617 }
618 } else {
619 /* 7 address bits + R/W bit */
620 addr = (((addr) << 1) | (I2C_RD));
621 iowrite32(addr, p + PCH_I2CDR);
622 }
623
624 /* check if it is the first message */
625 if (first)
626 pch_i2c_start(adap);
627
628 rtn = pch_i2c_wait_for_xfer_complete(adap);
629 if (rtn == 0) {
630 if (pch_i2c_getack(adap)) {
631 pch_dbg(adap, "Receive NACK for slave address"
632 "setting\n");
633 return -EIO;
634 }
635 } else if (rtn == -EIO) { /* Arbitration Lost */
636 pch_err(adap, "Lost Arbitration\n");
637 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
638 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
639 pch_i2c_init(adap);
640 return -EAGAIN;
641 } else { /* wait-event timeout */
642 pch_i2c_stop(adap);
643 return -ETIME;
644 }
645
646 if (length == 0) {
647 pch_i2c_stop(adap);
648 ioread32(p + PCH_I2CDR); /* Dummy read needs */
649
650 count = length;
651 } else {
652 int read_index;
653 int loop;
654 pch_i2c_sendack(adap);
655
656 /* Dummy read */
657 for (loop = 1, read_index = 0; loop < length; loop++) {
658 buf[read_index] = ioread32(p + PCH_I2CDR);
659
660 if (loop != 1)
661 read_index++;
662
663 rtn = pch_i2c_wait_for_xfer_complete(adap);
664 if (rtn == 0) {
665 if (pch_i2c_getack(adap)) {
666 pch_dbg(adap, "Receive NACK for slave"
667 "address setting\n");
668 return -EIO;
669 }
670 } else { /* wait-event timeout */
671 pch_i2c_stop(adap);
672 return -ETIME;
673 }
674
675 } /* end for */
676
677 pch_i2c_sendnack(adap);
678
679 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
680
681 if (length != 1)
682 read_index++;
683
684 rtn = pch_i2c_wait_for_xfer_complete(adap);
685 if (rtn == 0) {
686 if (pch_i2c_getack(adap)) {
687 pch_dbg(adap, "Receive NACK for slave"
688 "address setting\n");
689 return -EIO;
690 }
691 } else { /* wait-event timeout */
692 pch_i2c_stop(adap);
693 return -ETIME;
694 }
695
696 if (last)
697 pch_i2c_stop(adap);
698 else
699 pch_i2c_repstart(adap);
700
701 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
702 count = read_index;
703 }
704
705 return count;
706 }
707
708 /**
709 * pch_i2c_cb() - Interrupt handler Call back function
710 * @adap: Pointer to struct i2c_algo_pch_data.
711 */
712 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
713 {
714 u32 sts;
715 void __iomem *p = adap->pch_base_address;
716
717 sts = ioread32(p + PCH_I2CSR);
718 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
719 if (sts & I2CMAL_BIT)
720 adap->pch_event_flag |= I2CMAL_EVENT;
721
722 if (sts & I2CMCF_BIT)
723 adap->pch_event_flag |= I2CMCF_EVENT;
724
725 /* clear the applicable bits */
726 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
727
728 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
729
730 wake_up(&pch_event);
731 }
732
733 /**
734 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
735 * @irq: irq number.
736 * @pData: cookie passed back to the handler function.
737 */
738 static irqreturn_t pch_i2c_handler(int irq, void *pData)
739 {
740 u32 reg_val;
741 int flag;
742 int i;
743 struct adapter_info *adap_info = pData;
744 void __iomem *p;
745 u32 mode;
746
747 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
748 p = adap_info->pch_data[i].pch_base_address;
749 mode = ioread32(p + PCH_I2CMOD);
750 mode &= BUFFER_MODE | EEPROM_SR_MODE;
751 if (mode != NORMAL_MODE) {
752 pch_err(adap_info->pch_data,
753 "I2C-%d mode(%d) is not supported\n", mode, i);
754 continue;
755 }
756 reg_val = ioread32(p + PCH_I2CSR);
757 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
758 pch_i2c_cb(&adap_info->pch_data[i]);
759 flag = 1;
760 }
761 }
762
763 return flag ? IRQ_HANDLED : IRQ_NONE;
764 }
765
766 /**
767 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
768 * @i2c_adap: Pointer to the struct i2c_adapter.
769 * @msgs: Pointer to i2c_msg structure.
770 * @num: number of messages.
771 */
772 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
773 struct i2c_msg *msgs, s32 num)
774 {
775 struct i2c_msg *pmsg;
776 u32 i = 0;
777 u32 status;
778 u32 msglen;
779 u32 subaddrlen;
780 s32 ret;
781
782 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
783
784 ret = mutex_lock_interruptible(&pch_mutex);
785 if (ret)
786 return -ERESTARTSYS;
787
788 if (adap->p_adapter_info->pch_i2c_suspended) {
789 mutex_unlock(&pch_mutex);
790 return -EBUSY;
791 }
792
793 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
794 adap->p_adapter_info->pch_i2c_suspended);
795 /* transfer not completed */
796 adap->pch_i2c_xfer_in_progress = true;
797
798 for (i = 0; i < num && ret >= 0; i++) {
799 pmsg = &msgs[i];
800 pmsg->flags |= adap->pch_buff_mode_en;
801 status = pmsg->flags;
802 pch_dbg(adap,
803 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
804 /* calculate sub address length and message length */
805 /* these are applicable only for buffer mode */
806 subaddrlen = pmsg->buf[0];
807 /* calculate actual message length excluding
808 * the sub address fields */
809 msglen = (pmsg->len) - (subaddrlen + 1);
810
811 if ((status & (I2C_M_RD)) != false) {
812 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
813 (i == 0));
814 } else {
815 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
816 (i == 0));
817 }
818 }
819
820 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
821
822 mutex_unlock(&pch_mutex);
823
824 return (ret < 0) ? ret : num;
825 }
826
827 /**
828 * pch_i2c_func() - return the functionality of the I2C driver
829 * @adap: Pointer to struct i2c_algo_pch_data.
830 */
831 static u32 pch_i2c_func(struct i2c_adapter *adap)
832 {
833 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
834 }
835
836 static struct i2c_algorithm pch_algorithm = {
837 .master_xfer = pch_i2c_xfer,
838 .functionality = pch_i2c_func
839 };
840
841 /**
842 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
843 * @adap: Pointer to struct i2c_algo_pch_data.
844 */
845 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
846 {
847 void __iomem *p = adap->pch_base_address;
848
849 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
850
851 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
852
853 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
854 }
855
856 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
857 const struct pci_device_id *id)
858 {
859 void __iomem *base_addr;
860 int ret;
861 int i, j;
862 struct adapter_info *adap_info;
863 struct i2c_adapter *pch_adap;
864
865 pch_pci_dbg(pdev, "Entered.\n");
866
867 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
868 if (adap_info == NULL) {
869 pch_pci_err(pdev, "Memory allocation FAILED\n");
870 return -ENOMEM;
871 }
872
873 ret = pci_enable_device(pdev);
874 if (ret) {
875 pch_pci_err(pdev, "pci_enable_device FAILED\n");
876 goto err_pci_enable;
877 }
878
879 ret = pci_request_regions(pdev, KBUILD_MODNAME);
880 if (ret) {
881 pch_pci_err(pdev, "pci_request_regions FAILED\n");
882 goto err_pci_req;
883 }
884
885 base_addr = pci_iomap(pdev, 1, 0);
886
887 if (base_addr == NULL) {
888 pch_pci_err(pdev, "pci_iomap FAILED\n");
889 ret = -ENOMEM;
890 goto err_pci_iomap;
891 }
892
893 /* Set the number of I2C channel instance */
894 adap_info->ch_num = id->driver_data;
895
896 for (i = 0; i < adap_info->ch_num; i++) {
897 pch_adap = &adap_info->pch_data[i].pch_adapter;
898 adap_info->pch_i2c_suspended = false;
899
900 adap_info->pch_data[i].p_adapter_info = adap_info;
901
902 pch_adap->owner = THIS_MODULE;
903 pch_adap->class = I2C_CLASS_HWMON;
904 strcpy(pch_adap->name, KBUILD_MODNAME);
905 pch_adap->algo = &pch_algorithm;
906 pch_adap->algo_data = &adap_info->pch_data[i];
907
908 /* base_addr + offset; */
909 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
910
911 pch_adap->dev.parent = &pdev->dev;
912
913 ret = i2c_add_adapter(pch_adap);
914 if (ret) {
915 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
916 goto err_i2c_add_adapter;
917 }
918
919 pch_i2c_init(&adap_info->pch_data[i]);
920 }
921 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
922 KBUILD_MODNAME, adap_info);
923 if (ret) {
924 pch_pci_err(pdev, "request_irq FAILED\n");
925 goto err_i2c_add_adapter;
926 }
927
928 pci_set_drvdata(pdev, adap_info);
929 pch_pci_dbg(pdev, "returns %d.\n", ret);
930 return 0;
931
932 err_i2c_add_adapter:
933 for (j = 0; j < i; j++)
934 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
935 pci_iounmap(pdev, base_addr);
936 err_pci_iomap:
937 pci_release_regions(pdev);
938 err_pci_req:
939 pci_disable_device(pdev);
940 err_pci_enable:
941 kfree(adap_info);
942 return ret;
943 }
944
945 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
946 {
947 int i;
948 struct adapter_info *adap_info = pci_get_drvdata(pdev);
949
950 free_irq(pdev->irq, adap_info);
951
952 for (i = 0; i < adap_info->ch_num; i++) {
953 pch_i2c_disbl_int(&adap_info->pch_data[i]);
954 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
955 }
956
957 if (adap_info->pch_data[0].pch_base_address)
958 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
959
960 for (i = 0; i < adap_info->ch_num; i++)
961 adap_info->pch_data[i].pch_base_address = 0;
962
963 pci_set_drvdata(pdev, NULL);
964
965 pci_release_regions(pdev);
966
967 pci_disable_device(pdev);
968 kfree(adap_info);
969 }
970
971 #ifdef CONFIG_PM
972 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
973 {
974 int ret;
975 int i;
976 struct adapter_info *adap_info = pci_get_drvdata(pdev);
977 void __iomem *p = adap_info->pch_data[0].pch_base_address;
978
979 adap_info->pch_i2c_suspended = true;
980
981 for (i = 0; i < adap_info->ch_num; i++) {
982 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
983 /* Wait until all channel transfers are completed */
984 msleep(20);
985 }
986 }
987
988 /* Disable the i2c interrupts */
989 for (i = 0; i < adap_info->ch_num; i++)
990 pch_i2c_disbl_int(&adap_info->pch_data[i]);
991
992 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
993 "invoked function pch_i2c_disbl_int successfully\n",
994 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
995 ioread32(p + PCH_I2CESRSTA));
996
997 ret = pci_save_state(pdev);
998
999 if (ret) {
1000 pch_pci_err(pdev, "pci_save_state\n");
1001 return ret;
1002 }
1003
1004 pci_enable_wake(pdev, PCI_D3hot, 0);
1005 pci_disable_device(pdev);
1006 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1007
1008 return 0;
1009 }
1010
1011 static int pch_i2c_resume(struct pci_dev *pdev)
1012 {
1013 int i;
1014 struct adapter_info *adap_info = pci_get_drvdata(pdev);
1015
1016 pci_set_power_state(pdev, PCI_D0);
1017 pci_restore_state(pdev);
1018
1019 if (pci_enable_device(pdev) < 0) {
1020 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
1021 return -EIO;
1022 }
1023
1024 pci_enable_wake(pdev, PCI_D3hot, 0);
1025
1026 for (i = 0; i < adap_info->ch_num; i++)
1027 pch_i2c_init(&adap_info->pch_data[i]);
1028
1029 adap_info->pch_i2c_suspended = false;
1030
1031 return 0;
1032 }
1033 #else
1034 #define pch_i2c_suspend NULL
1035 #define pch_i2c_resume NULL
1036 #endif
1037
1038 static struct pci_driver pch_pcidriver = {
1039 .name = KBUILD_MODNAME,
1040 .id_table = pch_pcidev_id,
1041 .probe = pch_i2c_probe,
1042 .remove = __devexit_p(pch_i2c_remove),
1043 .suspend = pch_i2c_suspend,
1044 .resume = pch_i2c_resume
1045 };
1046
1047 static int __init pch_pci_init(void)
1048 {
1049 return pci_register_driver(&pch_pcidriver);
1050 }
1051 module_init(pch_pci_init);
1052
1053 static void __exit pch_pci_exit(void)
1054 {
1055 pci_unregister_driver(&pch_pcidriver);
1056 }
1057 module_exit(pch_pci_exit);
1058
1059 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver");
1060 MODULE_LICENSE("GPL");
1061 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
1062 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
1063 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
Mirror of the linux-mips.org kernel tree