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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / i2c / busses / i2c-i801.c
blobab26840d0c7087073dbbba598953ebfca699b7b9
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54
55 Features supported by this driver:
56 Software PEC no
57 Hardware PEC yes
58 Block buffer yes
59 Block process call transaction no
60 I2C block read transaction yes (doesn't use the block buffer)
61 Slave mode no
62
63 See the file Documentation/i2c/busses/i2c-i801 for details.
64 */
65
66 #include <linux/module.h>
67 #include <linux/pci.h>
68 #include <linux/kernel.h>
69 #include <linux/stddef.h>
70 #include <linux/delay.h>
71 #include <linux/ioport.h>
72 #include <linux/init.h>
73 #include <linux/i2c.h>
74 #include <linux/acpi.h>
75 #include <linux/io.h>
76 #include <linux/dmi.h>
77 #include <linux/slab.h>
78
79 /* I801 SMBus address offsets */
80 #define SMBHSTSTS(p) (0 + (p)->smba)
81 #define SMBHSTCNT(p) (2 + (p)->smba)
82 #define SMBHSTCMD(p) (3 + (p)->smba)
83 #define SMBHSTADD(p) (4 + (p)->smba)
84 #define SMBHSTDAT0(p) (5 + (p)->smba)
85 #define SMBHSTDAT1(p) (6 + (p)->smba)
86 #define SMBBLKDAT(p) (7 + (p)->smba)
87 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
88 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
89 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
90
91 /* PCI Address Constants */
92 #define SMBBAR 4
93 #define SMBHSTCFG 0x040
94
95 /* Host configuration bits for SMBHSTCFG */
96 #define SMBHSTCFG_HST_EN 1
97 #define SMBHSTCFG_SMB_SMI_EN 2
98 #define SMBHSTCFG_I2C_EN 4
99
100 /* Auxiliary control register bits, ICH4+ only */
101 #define SMBAUXCTL_CRC 1
102 #define SMBAUXCTL_E32B 2
103
104 /* kill bit for SMBHSTCNT */
105 #define SMBHSTCNT_KILL 2
106
107 /* Other settings */
108 #define MAX_TIMEOUT 100
109 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
110
111 /* I801 command constants */
112 #define I801_QUICK 0x00
113 #define I801_BYTE 0x04
114 #define I801_BYTE_DATA 0x08
115 #define I801_WORD_DATA 0x0C
116 #define I801_PROC_CALL 0x10 /* unimplemented */
117 #define I801_BLOCK_DATA 0x14
118 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
119 #define I801_BLOCK_LAST 0x34
120 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
121 #define I801_START 0x40
122 #define I801_PEC_EN 0x80 /* ICH3 and later */
123
124 /* I801 Hosts Status register bits */
125 #define SMBHSTSTS_BYTE_DONE 0x80
126 #define SMBHSTSTS_INUSE_STS 0x40
127 #define SMBHSTSTS_SMBALERT_STS 0x20
128 #define SMBHSTSTS_FAILED 0x10
129 #define SMBHSTSTS_BUS_ERR 0x08
130 #define SMBHSTSTS_DEV_ERR 0x04
131 #define SMBHSTSTS_INTR 0x02
132 #define SMBHSTSTS_HOST_BUSY 0x01
133
134 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
135 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
136 SMBHSTSTS_INTR)
137
138 /* Older devices have their ID defined in <linux/pci_ids.h> */
139 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
140 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
141 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
145 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
146 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
147 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
148
149 struct i801_priv {
150 struct i2c_adapter adapter;
151 unsigned long smba;
152 unsigned char original_hstcfg;
153 struct pci_dev *pci_dev;
154 unsigned int features;
155 };
156
157 static struct pci_driver i801_driver;
158
159 #define FEATURE_SMBUS_PEC (1 << 0)
160 #define FEATURE_BLOCK_BUFFER (1 << 1)
161 #define FEATURE_BLOCK_PROC (1 << 2)
162 #define FEATURE_I2C_BLOCK_READ (1 << 3)
163 /* Not really a feature, but it's convenient to handle it as such */
164 #define FEATURE_IDF (1 << 15)
165
166 static const char *i801_feature_names[] = {
167 "SMBus PEC",
168 "Block buffer",
169 "Block process call",
170 "I2C block read",
171 };
172
173 static unsigned int disable_features;
174 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
175 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
176
177 /* Make sure the SMBus host is ready to start transmitting.
178 Return 0 if it is, -EBUSY if it is not. */
179 static int i801_check_pre(struct i801_priv *priv)
180 {
181 int status;
182
183 status = inb_p(SMBHSTSTS(priv));
184 if (status & SMBHSTSTS_HOST_BUSY) {
185 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
186 return -EBUSY;
187 }
188
189 status &= STATUS_FLAGS;
190 if (status) {
191 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
192 status);
193 outb_p(status, SMBHSTSTS(priv));
194 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
195 if (status) {
196 dev_err(&priv->pci_dev->dev,
197 "Failed clearing status flags (%02x)\n",
198 status);
199 return -EBUSY;
200 }
201 }
202
203 return 0;
204 }
205
206 /* Convert the status register to an error code, and clear it. */
207 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
208 {
209 int result = 0;
210
211 /* If the SMBus is still busy, we give up */
212 if (timeout) {
213 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
214 /* try to stop the current command */
215 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
216 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
217 SMBHSTCNT(priv));
218 msleep(1);
219 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
220 SMBHSTCNT(priv));
221
222 /* Check if it worked */
223 status = inb_p(SMBHSTSTS(priv));
224 if ((status & SMBHSTSTS_HOST_BUSY) ||
225 !(status & SMBHSTSTS_FAILED))
226 dev_err(&priv->pci_dev->dev,
227 "Failed terminating the transaction\n");
228 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
229 return -ETIMEDOUT;
230 }
231
232 if (status & SMBHSTSTS_FAILED) {
233 result = -EIO;
234 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
235 }
236 if (status & SMBHSTSTS_DEV_ERR) {
237 result = -ENXIO;
238 dev_dbg(&priv->pci_dev->dev, "No response\n");
239 }
240 if (status & SMBHSTSTS_BUS_ERR) {
241 result = -EAGAIN;
242 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
243 }
244
245 if (result) {
246 /* Clear error flags */
247 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
248 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
249 if (status) {
250 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
251 "flags at end of transaction (%02x)\n",
252 status);
253 }
254 }
255
256 return result;
257 }
258
259 static int i801_transaction(struct i801_priv *priv, int xact)
260 {
261 int status;
262 int result;
263 int timeout = 0;
264
265 result = i801_check_pre(priv);
266 if (result < 0)
267 return result;
268
269 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
270 * INTREN, SMBSCMD are passed in xact */
271 outb_p(xact | I801_START, SMBHSTCNT(priv));
272
273 /* We will always wait for a fraction of a second! */
274 do {
275 msleep(1);
276 status = inb_p(SMBHSTSTS(priv));
277 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
278
279 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
280 if (result < 0)
281 return result;
282
283 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
284 return 0;
285 }
286
287 /* wait for INTR bit as advised by Intel */
288 static void i801_wait_hwpec(struct i801_priv *priv)
289 {
290 int timeout = 0;
291 int status;
292
293 do {
294 msleep(1);
295 status = inb_p(SMBHSTSTS(priv));
296 } while ((!(status & SMBHSTSTS_INTR))
297 && (timeout++ < MAX_TIMEOUT));
298
299 if (timeout > MAX_TIMEOUT)
300 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
301
302 outb_p(status, SMBHSTSTS(priv));
303 }
304
305 static int i801_block_transaction_by_block(struct i801_priv *priv,
306 union i2c_smbus_data *data,
307 char read_write, int hwpec)
308 {
309 int i, len;
310 int status;
311
312 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
313
314 /* Use 32-byte buffer to process this transaction */
315 if (read_write == I2C_SMBUS_WRITE) {
316 len = data->block[0];
317 outb_p(len, SMBHSTDAT0(priv));
318 for (i = 0; i < len; i++)
319 outb_p(data->block[i+1], SMBBLKDAT(priv));
320 }
321
322 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
323 I801_PEC_EN * hwpec);
324 if (status)
325 return status;
326
327 if (read_write == I2C_SMBUS_READ) {
328 len = inb_p(SMBHSTDAT0(priv));
329 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
330 return -EPROTO;
331
332 data->block[0] = len;
333 for (i = 0; i < len; i++)
334 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
335 }
336 return 0;
337 }
338
339 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
340 union i2c_smbus_data *data,
341 char read_write, int command,
342 int hwpec)
343 {
344 int i, len;
345 int smbcmd;
346 int status;
347 int result;
348 int timeout;
349
350 result = i801_check_pre(priv);
351 if (result < 0)
352 return result;
353
354 len = data->block[0];
355
356 if (read_write == I2C_SMBUS_WRITE) {
357 outb_p(len, SMBHSTDAT0(priv));
358 outb_p(data->block[1], SMBBLKDAT(priv));
359 }
360
361 for (i = 1; i <= len; i++) {
362 if (i == len && read_write == I2C_SMBUS_READ) {
363 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
364 smbcmd = I801_I2C_BLOCK_LAST;
365 else
366 smbcmd = I801_BLOCK_LAST;
367 } else {
368 if (command == I2C_SMBUS_I2C_BLOCK_DATA
369 && read_write == I2C_SMBUS_READ)
370 smbcmd = I801_I2C_BLOCK_DATA;
371 else
372 smbcmd = I801_BLOCK_DATA;
373 }
374 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
375
376 if (i == 1)
377 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
378 SMBHSTCNT(priv));
379
380 /* We will always wait for a fraction of a second! */
381 timeout = 0;
382 do {
383 msleep(1);
384 status = inb_p(SMBHSTSTS(priv));
385 } while ((!(status & SMBHSTSTS_BYTE_DONE))
386 && (timeout++ < MAX_TIMEOUT));
387
388 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
389 if (result < 0)
390 return result;
391
392 if (i == 1 && read_write == I2C_SMBUS_READ
393 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
394 len = inb_p(SMBHSTDAT0(priv));
395 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
396 dev_err(&priv->pci_dev->dev,
397 "Illegal SMBus block read size %d\n",
398 len);
399 /* Recover */
400 while (inb_p(SMBHSTSTS(priv)) &
401 SMBHSTSTS_HOST_BUSY)
402 outb_p(SMBHSTSTS_BYTE_DONE,
403 SMBHSTSTS(priv));
404 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
405 return -EPROTO;
406 }
407 data->block[0] = len;
408 }
409
410 /* Retrieve/store value in SMBBLKDAT */
411 if (read_write == I2C_SMBUS_READ)
412 data->block[i] = inb_p(SMBBLKDAT(priv));
413 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
414 outb_p(data->block[i+1], SMBBLKDAT(priv));
415
416 /* signals SMBBLKDAT ready */
417 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
418 }
419
420 return 0;
421 }
422
423 static int i801_set_block_buffer_mode(struct i801_priv *priv)
424 {
425 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
426 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
427 return -EIO;
428 return 0;
429 }
430
431 /* Block transaction function */
432 static int i801_block_transaction(struct i801_priv *priv,
433 union i2c_smbus_data *data, char read_write,
434 int command, int hwpec)
435 {
436 int result = 0;
437 unsigned char hostc;
438
439 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
440 if (read_write == I2C_SMBUS_WRITE) {
441 /* set I2C_EN bit in configuration register */
442 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
443 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
444 hostc | SMBHSTCFG_I2C_EN);
445 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
446 dev_err(&priv->pci_dev->dev,
447 "I2C block read is unsupported!\n");
448 return -EOPNOTSUPP;
449 }
450 }
451
452 if (read_write == I2C_SMBUS_WRITE
453 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
454 if (data->block[0] < 1)
455 data->block[0] = 1;
456 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
457 data->block[0] = I2C_SMBUS_BLOCK_MAX;
458 } else {
459 data->block[0] = 32; /* max for SMBus block reads */
460 }
461
462 /* Experience has shown that the block buffer can only be used for
463 SMBus (not I2C) block transactions, even though the datasheet
464 doesn't mention this limitation. */
465 if ((priv->features & FEATURE_BLOCK_BUFFER)
466 && command != I2C_SMBUS_I2C_BLOCK_DATA
467 && i801_set_block_buffer_mode(priv) == 0)
468 result = i801_block_transaction_by_block(priv, data,
469 read_write, hwpec);
470 else
471 result = i801_block_transaction_byte_by_byte(priv, data,
472 read_write,
473 command, hwpec);
474
475 if (result == 0 && hwpec)
476 i801_wait_hwpec(priv);
477
478 if (command == I2C_SMBUS_I2C_BLOCK_DATA
479 && read_write == I2C_SMBUS_WRITE) {
480 /* restore saved configuration register value */
481 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
482 }
483 return result;
484 }
485
486 /* Return negative errno on error. */
487 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
488 unsigned short flags, char read_write, u8 command,
489 int size, union i2c_smbus_data *data)
490 {
491 int hwpec;
492 int block = 0;
493 int ret, xact = 0;
494 struct i801_priv *priv = i2c_get_adapdata(adap);
495
496 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
497 && size != I2C_SMBUS_QUICK
498 && size != I2C_SMBUS_I2C_BLOCK_DATA;
499
500 switch (size) {
501 case I2C_SMBUS_QUICK:
502 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
503 SMBHSTADD(priv));
504 xact = I801_QUICK;
505 break;
506 case I2C_SMBUS_BYTE:
507 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
508 SMBHSTADD(priv));
509 if (read_write == I2C_SMBUS_WRITE)
510 outb_p(command, SMBHSTCMD(priv));
511 xact = I801_BYTE;
512 break;
513 case I2C_SMBUS_BYTE_DATA:
514 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
515 SMBHSTADD(priv));
516 outb_p(command, SMBHSTCMD(priv));
517 if (read_write == I2C_SMBUS_WRITE)
518 outb_p(data->byte, SMBHSTDAT0(priv));
519 xact = I801_BYTE_DATA;
520 break;
521 case I2C_SMBUS_WORD_DATA:
522 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
523 SMBHSTADD(priv));
524 outb_p(command, SMBHSTCMD(priv));
525 if (read_write == I2C_SMBUS_WRITE) {
526 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
527 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
528 }
529 xact = I801_WORD_DATA;
530 break;
531 case I2C_SMBUS_BLOCK_DATA:
532 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
533 SMBHSTADD(priv));
534 outb_p(command, SMBHSTCMD(priv));
535 block = 1;
536 break;
537 case I2C_SMBUS_I2C_BLOCK_DATA:
538 /* NB: page 240 of ICH5 datasheet shows that the R/#W
539 * bit should be cleared here, even when reading */
540 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
541 if (read_write == I2C_SMBUS_READ) {
542 /* NB: page 240 of ICH5 datasheet also shows
543 * that DATA1 is the cmd field when reading */
544 outb_p(command, SMBHSTDAT1(priv));
545 } else
546 outb_p(command, SMBHSTCMD(priv));
547 block = 1;
548 break;
549 default:
550 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
551 size);
552 return -EOPNOTSUPP;
553 }
554
555 if (hwpec) /* enable/disable hardware PEC */
556 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
557 else
558 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
559 SMBAUXCTL(priv));
560
561 if (block)
562 ret = i801_block_transaction(priv, data, read_write, size,
563 hwpec);
564 else
565 ret = i801_transaction(priv, xact | ENABLE_INT9);
566
567 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
568 time, so we forcibly disable it after every transaction. Turn off
569 E32B for the same reason. */
570 if (hwpec || block)
571 outb_p(inb_p(SMBAUXCTL(priv)) &
572 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
573
574 if (block)
575 return ret;
576 if (ret)
577 return ret;
578 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
579 return 0;
580
581 switch (xact & 0x7f) {
582 case I801_BYTE: /* Result put in SMBHSTDAT0 */
583 case I801_BYTE_DATA:
584 data->byte = inb_p(SMBHSTDAT0(priv));
585 break;
586 case I801_WORD_DATA:
587 data->word = inb_p(SMBHSTDAT0(priv)) +
588 (inb_p(SMBHSTDAT1(priv)) << 8);
589 break;
590 }
591 return 0;
592 }
593
594
595 static u32 i801_func(struct i2c_adapter *adapter)
596 {
597 struct i801_priv *priv = i2c_get_adapdata(adapter);
598
599 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
600 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
601 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
602 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
603 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
604 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
605 }
606
607 static const struct i2c_algorithm smbus_algorithm = {
608 .smbus_xfer = i801_access,
609 .functionality = i801_func,
610 };
611
612 static const struct pci_device_id i801_ids[] = {
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
636 { 0, }
637 };
638
639 MODULE_DEVICE_TABLE(pci, i801_ids);
640
641 #if defined CONFIG_X86 && defined CONFIG_DMI
642 static unsigned char apanel_addr;
643
644 /* Scan the system ROM for the signature "FJKEYINF" */
645 static __init const void __iomem *bios_signature(const void __iomem *bios)
646 {
647 ssize_t offset;
648 const unsigned char signature[] = "FJKEYINF";
649
650 for (offset = 0; offset < 0x10000; offset += 0x10) {
651 if (check_signature(bios + offset, signature,
652 sizeof(signature)-1))
653 return bios + offset;
654 }
655 return NULL;
656 }
657
658 static void __init input_apanel_init(void)
659 {
660 void __iomem *bios;
661 const void __iomem *p;
662
663 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
664 p = bios_signature(bios);
665 if (p) {
666 /* just use the first address */
667 apanel_addr = readb(p + 8 + 3) >> 1;
668 }
669 iounmap(bios);
670 }
671
672 struct dmi_onboard_device_info {
673 const char *name;
674 u8 type;
675 unsigned short i2c_addr;
676 const char *i2c_type;
677 };
678
679 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
680 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
681 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
682 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
683 };
684
685 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
686 struct i2c_adapter *adap)
687 {
688 int i;
689 struct i2c_board_info info;
690
691 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
692 /* & ~0x80, ignore enabled/disabled bit */
693 if ((type & ~0x80) != dmi_devices[i].type)
694 continue;
695 if (strcasecmp(name, dmi_devices[i].name))
696 continue;
697
698 memset(&info, 0, sizeof(struct i2c_board_info));
699 info.addr = dmi_devices[i].i2c_addr;
700 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
701 i2c_new_device(adap, &info);
702 break;
703 }
704 }
705
706 /* We use our own function to check for onboard devices instead of
707 dmi_find_device() as some buggy BIOS's have the devices we are interested
708 in marked as disabled */
709 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
710 void *adap)
711 {
712 int i, count;
713
714 if (dm->type != 10)
715 return;
716
717 count = (dm->length - sizeof(struct dmi_header)) / 2;
718 for (i = 0; i < count; i++) {
719 const u8 *d = (char *)(dm + 1) + (i * 2);
720 const char *name = ((char *) dm) + dm->length;
721 u8 type = d[0];
722 u8 s = d[1];
723
724 if (!s)
725 continue;
726 s--;
727 while (s > 0 && name[0]) {
728 name += strlen(name) + 1;
729 s--;
730 }
731 if (name[0] == 0) /* Bogus string reference */
732 continue;
733
734 dmi_check_onboard_device(type, name, adap);
735 }
736 }
737
738 /* Register optional slaves */
739 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
740 {
741 /* Only register slaves on main SMBus channel */
742 if (priv->features & FEATURE_IDF)
743 return;
744
745 if (apanel_addr) {
746 struct i2c_board_info info;
747
748 memset(&info, 0, sizeof(struct i2c_board_info));
749 info.addr = apanel_addr;
750 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
751 i2c_new_device(&priv->adapter, &info);
752 }
753
754 if (dmi_name_in_vendors("FUJITSU"))
755 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
756 }
757 #else
758 static void __init input_apanel_init(void) {}
759 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
760 #endif /* CONFIG_X86 && CONFIG_DMI */
761
762 static int __devinit i801_probe(struct pci_dev *dev,
763 const struct pci_device_id *id)
764 {
765 unsigned char temp;
766 int err, i;
767 struct i801_priv *priv;
768
769 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
770 if (!priv)
771 return -ENOMEM;
772
773 i2c_set_adapdata(&priv->adapter, priv);
774 priv->adapter.owner = THIS_MODULE;
775 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
776 priv->adapter.algo = &smbus_algorithm;
777
778 priv->pci_dev = dev;
779 switch (dev->device) {
780 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
781 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
782 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
783 priv->features |= FEATURE_IDF;
784 /* fall through */
785 default:
786 priv->features |= FEATURE_I2C_BLOCK_READ;
787 /* fall through */
788 case PCI_DEVICE_ID_INTEL_82801DB_3:
789 priv->features |= FEATURE_SMBUS_PEC;
790 priv->features |= FEATURE_BLOCK_BUFFER;
791 /* fall through */
792 case PCI_DEVICE_ID_INTEL_82801CA_3:
793 case PCI_DEVICE_ID_INTEL_82801BA_2:
794 case PCI_DEVICE_ID_INTEL_82801AB_3:
795 case PCI_DEVICE_ID_INTEL_82801AA_3:
796 break;
797 }
798
799 /* Disable features on user request */
800 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
801 if (priv->features & disable_features & (1 << i))
802 dev_notice(&dev->dev, "%s disabled by user\n",
803 i801_feature_names[i]);
804 }
805 priv->features &= ~disable_features;
806
807 err = pci_enable_device(dev);
808 if (err) {
809 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
810 err);
811 goto exit;
812 }
813
814 /* Determine the address of the SMBus area */
815 priv->smba = pci_resource_start(dev, SMBBAR);
816 if (!priv->smba) {
817 dev_err(&dev->dev, "SMBus base address uninitialized, "
818 "upgrade BIOS\n");
819 err = -ENODEV;
820 goto exit;
821 }
822
823 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
824 if (err) {
825 err = -ENODEV;
826 goto exit;
827 }
828
829 err = pci_request_region(dev, SMBBAR, i801_driver.name);
830 if (err) {
831 dev_err(&dev->dev, "Failed to request SMBus region "
832 "0x%lx-0x%Lx\n", priv->smba,
833 (unsigned long long)pci_resource_end(dev, SMBBAR));
834 goto exit;
835 }
836
837 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
838 priv->original_hstcfg = temp;
839 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
840 if (!(temp & SMBHSTCFG_HST_EN)) {
841 dev_info(&dev->dev, "Enabling SMBus device\n");
842 temp |= SMBHSTCFG_HST_EN;
843 }
844 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
845
846 if (temp & SMBHSTCFG_SMB_SMI_EN)
847 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
848 else
849 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
850
851 /* Clear special mode bits */
852 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
853 outb_p(inb_p(SMBAUXCTL(priv)) &
854 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
855
856 /* set up the sysfs linkage to our parent device */
857 priv->adapter.dev.parent = &dev->dev;
858
859 /* Retry up to 3 times on lost arbitration */
860 priv->adapter.retries = 3;
861
862 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
863 "SMBus I801 adapter at %04lx", priv->smba);
864 err = i2c_add_adapter(&priv->adapter);
865 if (err) {
866 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
867 goto exit_release;
868 }
869
870 i801_probe_optional_slaves(priv);
871
872 pci_set_drvdata(dev, priv);
873 return 0;
874
875 exit_release:
876 pci_release_region(dev, SMBBAR);
877 exit:
878 kfree(priv);
879 return err;
880 }
881
882 static void __devexit i801_remove(struct pci_dev *dev)
883 {
884 struct i801_priv *priv = pci_get_drvdata(dev);
885
886 i2c_del_adapter(&priv->adapter);
887 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
888 pci_release_region(dev, SMBBAR);
889 pci_set_drvdata(dev, NULL);
890 kfree(priv);
891 /*
892 * do not call pci_disable_device(dev) since it can cause hard hangs on
893 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
894 */
895 }
896
897 #ifdef CONFIG_PM
898 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
899 {
900 struct i801_priv *priv = pci_get_drvdata(dev);
901
902 pci_save_state(dev);
903 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
904 pci_set_power_state(dev, pci_choose_state(dev, mesg));
905 return 0;
906 }
907
908 static int i801_resume(struct pci_dev *dev)
909 {
910 pci_set_power_state(dev, PCI_D0);
911 pci_restore_state(dev);
912 return pci_enable_device(dev);
913 }
914 #else
915 #define i801_suspend NULL
916 #define i801_resume NULL
917 #endif
918
919 static struct pci_driver i801_driver = {
920 .name = "i801_smbus",
921 .id_table = i801_ids,
922 .probe = i801_probe,
923 .remove = __devexit_p(i801_remove),
924 .suspend = i801_suspend,
925 .resume = i801_resume,
926 };
927
928 static int __init i2c_i801_init(void)
929 {
930 if (dmi_name_in_vendors("FUJITSU"))
931 input_apanel_init();
932 return pci_register_driver(&i801_driver);
933 }
934
935 static void __exit i2c_i801_exit(void)
936 {
937 pci_unregister_driver(&i801_driver);
938 }
939
940 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
941 "Jean Delvare <khali@linux-fr.org>");
942 MODULE_DESCRIPTION("I801 SMBus driver");
943 MODULE_LICENSE("GPL");
944
945 module_init(i2c_i801_init);
946 module_exit(i2c_i801_exit);
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