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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / net / wireless / ath / ath5k / reset.c
blob2abac257b4b460ede4c6a46f44986d23bdf28084
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 /*****************************\
23 Reset functions and helpers
24 \*****************************/
25
26 #include <asm/unaligned.h>
27
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include <linux/platform_device.h>
31 #include "ath5k.h"
32 #include "reg.h"
33 #include "debug.h"
34
35
36 /******************\
37 * Helper functions *
38 \******************/
39
40 /*
41 * Check if a register write has been completed
42 */
43 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
44 bool is_set)
45 {
46 int i;
47 u32 data;
48
49 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
50 data = ath5k_hw_reg_read(ah, reg);
51 if (is_set && (data & flag))
52 break;
53 else if ((data & flag) == val)
54 break;
55 udelay(15);
56 }
57
58 return (i <= 0) ? -EAGAIN : 0;
59 }
60
61
62 /*************************\
63 * Clock related functions *
64 \*************************/
65
66 /**
67 * ath5k_hw_htoclock - Translate usec to hw clock units
68 *
69 * @ah: The &struct ath5k_hw
70 * @usec: value in microseconds
71 */
72 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
73 {
74 struct ath_common *common = ath5k_hw_common(ah);
75 return usec * common->clockrate;
76 }
77
78 /**
79 * ath5k_hw_clocktoh - Translate hw clock units to usec
80 * @clock: value in hw clock units
81 */
82 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
83 {
84 struct ath_common *common = ath5k_hw_common(ah);
85 return clock / common->clockrate;
86 }
87
88 /**
89 * ath5k_hw_init_core_clock - Initialize core clock
90 *
91 * @ah The &struct ath5k_hw
92 *
93 * Initialize core clock parameters (usec, usec32, latencies etc).
94 */
95 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
96 {
97 struct ieee80211_channel *channel = ah->ah_current_channel;
98 struct ath_common *common = ath5k_hw_common(ah);
99 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
100
101 /*
102 * Set core clock frequency
103 */
104 switch (channel->hw_value) {
105 case AR5K_MODE_11A:
106 clock = 40;
107 break;
108 case AR5K_MODE_11B:
109 clock = 22;
110 break;
111 case AR5K_MODE_11G:
112 default:
113 clock = 44;
114 break;
115 }
116
117 /* Use clock multiplier for non-default
118 * bwmode */
119 switch (ah->ah_bwmode) {
120 case AR5K_BWMODE_40MHZ:
121 clock *= 2;
122 break;
123 case AR5K_BWMODE_10MHZ:
124 clock /= 2;
125 break;
126 case AR5K_BWMODE_5MHZ:
127 clock /= 4;
128 break;
129 default:
130 break;
131 }
132
133 common->clockrate = clock;
134
135 /*
136 * Set USEC parameters
137 */
138 /* Set USEC counter on PCU*/
139 usec = clock - 1;
140 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
141
142 /* Set usec duration on DCU */
143 if (ah->ah_version != AR5K_AR5210)
144 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
145 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
146 clock);
147
148 /* Set 32MHz USEC counter */
149 if ((ah->ah_radio == AR5K_RF5112) ||
150 (ah->ah_radio == AR5K_RF2413) ||
151 (ah->ah_radio == AR5K_RF5413) ||
152 (ah->ah_radio == AR5K_RF2316) ||
153 (ah->ah_radio == AR5K_RF2317))
154 /* Remain on 40MHz clock ? */
155 sclock = 40 - 1;
156 else
157 sclock = 32 - 1;
158 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
159
160 /*
161 * Set tx/rx latencies
162 */
163 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
164 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
165 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
166
167 /*
168 * Set default Tx frame to Tx data start delay
169 */
170 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
171
172 /*
173 * 5210 initvals don't include usec settings
174 * so we need to use magic values here for
175 * tx/rx latencies
176 */
177 if (ah->ah_version == AR5K_AR5210) {
178 /* same for turbo */
179 txlat = AR5K_INIT_TX_LATENCY_5210;
180 rxlat = AR5K_INIT_RX_LATENCY_5210;
181 }
182
183 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
184 /* 5311 has different tx/rx latency masks
185 * from 5211, since we deal 5311 the same
186 * as 5211 when setting initvals, shift
187 * values here to their proper locations
188 *
189 * Note: Initvals indicate tx/rx/ latencies
190 * are the same for turbo mode */
191 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
192 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
193 } else
194 switch (ah->ah_bwmode) {
195 case AR5K_BWMODE_10MHZ:
196 txlat = AR5K_REG_SM(txlat * 2,
197 AR5K_USEC_TX_LATENCY_5211);
198 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
199 AR5K_USEC_RX_LATENCY_5211);
200 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
201 break;
202 case AR5K_BWMODE_5MHZ:
203 txlat = AR5K_REG_SM(txlat * 4,
204 AR5K_USEC_TX_LATENCY_5211);
205 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
206 AR5K_USEC_RX_LATENCY_5211);
207 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
208 break;
209 case AR5K_BWMODE_40MHZ:
210 txlat = AR5K_INIT_TX_LAT_MIN;
211 rxlat = AR5K_REG_SM(rxlat / 2,
212 AR5K_USEC_RX_LATENCY_5211);
213 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
214 break;
215 default:
216 break;
217 }
218
219 usec_reg = (usec | sclock | txlat | rxlat);
220 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
221
222 /* On 5112 set tx frame to tx data start delay */
223 if (ah->ah_radio == AR5K_RF5112) {
224 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
225 AR5K_PHY_RF_CTL2_TXF2TXD_START,
226 txf2txs);
227 }
228 }
229
230 /*
231 * If there is an external 32KHz crystal available, use it
232 * as ref. clock instead of 32/40MHz clock and baseband clocks
233 * to save power during sleep or restore normal 32/40MHz
234 * operation.
235 *
236 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
237 * 123 - 127) require delay on access.
238 */
239 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
240 {
241 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
242 u32 scal, spending, sclock;
243
244 /* Only set 32KHz settings if we have an external
245 * 32KHz crystal present */
246 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
247 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
248 enable) {
249
250 /* 1 usec/cycle */
251 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
252 /* Set up tsf increment on each cycle */
253 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
254
255 /* Set baseband sleep control registers
256 * and sleep control rate */
257 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
258
259 if ((ah->ah_radio == AR5K_RF5112) ||
260 (ah->ah_radio == AR5K_RF5413) ||
261 (ah->ah_radio == AR5K_RF2316) ||
262 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
263 spending = 0x14;
264 else
265 spending = 0x18;
266 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
267
268 if ((ah->ah_radio == AR5K_RF5112) ||
269 (ah->ah_radio == AR5K_RF5413) ||
270 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
271 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
272 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
273 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
274 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
275 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
276 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
277 } else {
278 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
279 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
280 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
281 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
282 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
283 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
284 }
285
286 /* Enable sleep clock operation */
287 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
288 AR5K_PCICFG_SLEEP_CLOCK_EN);
289
290 } else {
291
292 /* Disable sleep clock operation and
293 * restore default parameters */
294 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
295 AR5K_PCICFG_SLEEP_CLOCK_EN);
296
297 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
298 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
299
300 /* Set DAC/ADC delays */
301 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
302 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
303
304 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
305 scal = AR5K_PHY_SCAL_32MHZ_2417;
306 else if (ee->ee_is_hb63)
307 scal = AR5K_PHY_SCAL_32MHZ_HB63;
308 else
309 scal = AR5K_PHY_SCAL_32MHZ;
310 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
311
312 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
313 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
314
315 if ((ah->ah_radio == AR5K_RF5112) ||
316 (ah->ah_radio == AR5K_RF5413) ||
317 (ah->ah_radio == AR5K_RF2316) ||
318 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
319 spending = 0x14;
320 else
321 spending = 0x18;
322 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
323
324 /* Set up tsf increment on each cycle */
325 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
326
327 if ((ah->ah_radio == AR5K_RF5112) ||
328 (ah->ah_radio == AR5K_RF5413) ||
329 (ah->ah_radio == AR5K_RF2316) ||
330 (ah->ah_radio == AR5K_RF2317))
331 sclock = 40 - 1;
332 else
333 sclock = 32 - 1;
334 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
335 }
336 }
337
338
339 /*********************\
340 * Reset/Sleep control *
341 \*********************/
342
343 /*
344 * Reset chipset
345 */
346 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
347 {
348 int ret;
349 u32 mask = val ? val : ~0U;
350
351 /* Read-and-clear RX Descriptor Pointer*/
352 ath5k_hw_reg_read(ah, AR5K_RXDP);
353
354 /*
355 * Reset the device and wait until success
356 */
357 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
358
359 /* Wait at least 128 PCI clocks */
360 udelay(15);
361
362 if (ah->ah_version == AR5K_AR5210) {
363 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
364 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
365 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
366 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
367 } else {
368 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
369 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
370 }
371
372 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
373
374 /*
375 * Reset configuration register (for hw byte-swap). Note that this
376 * is only set for big endian. We do the necessary magic in
377 * AR5K_INIT_CFG.
378 */
379 if ((val & AR5K_RESET_CTL_PCU) == 0)
380 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
381
382 return ret;
383 }
384
385 /*
386 * Reset AHB chipset
387 * AR5K_RESET_CTL_PCU flag resets WMAC
388 * AR5K_RESET_CTL_BASEBAND flag resets WBB
389 */
390 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
391 {
392 u32 mask = flags ? flags : ~0U;
393 u32 __iomem *reg;
394 u32 regval;
395 u32 val = 0;
396
397 /* ah->ah_mac_srev is not available at this point yet */
398 if (ah->devid >= AR5K_SREV_AR2315_R6) {
399 reg = (u32 __iomem *) AR5K_AR2315_RESET;
400 if (mask & AR5K_RESET_CTL_PCU)
401 val |= AR5K_AR2315_RESET_WMAC;
402 if (mask & AR5K_RESET_CTL_BASEBAND)
403 val |= AR5K_AR2315_RESET_BB_WARM;
404 } else {
405 reg = (u32 __iomem *) AR5K_AR5312_RESET;
406 if (to_platform_device(ah->dev)->id == 0) {
407 if (mask & AR5K_RESET_CTL_PCU)
408 val |= AR5K_AR5312_RESET_WMAC0;
409 if (mask & AR5K_RESET_CTL_BASEBAND)
410 val |= AR5K_AR5312_RESET_BB0_COLD |
411 AR5K_AR5312_RESET_BB0_WARM;
412 } else {
413 if (mask & AR5K_RESET_CTL_PCU)
414 val |= AR5K_AR5312_RESET_WMAC1;
415 if (mask & AR5K_RESET_CTL_BASEBAND)
416 val |= AR5K_AR5312_RESET_BB1_COLD |
417 AR5K_AR5312_RESET_BB1_WARM;
418 }
419 }
420
421 /* Put BB/MAC into reset */
422 regval = __raw_readl(reg);
423 __raw_writel(regval | val, reg);
424 regval = __raw_readl(reg);
425 udelay(100);
426
427 /* Bring BB/MAC out of reset */
428 __raw_writel(regval & ~val, reg);
429 regval = __raw_readl(reg);
430
431 /*
432 * Reset configuration register (for hw byte-swap). Note that this
433 * is only set for big endian. We do the necessary magic in
434 * AR5K_INIT_CFG.
435 */
436 if ((flags & AR5K_RESET_CTL_PCU) == 0)
437 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
438
439 return 0;
440 }
441
442
443 /*
444 * Sleep control
445 */
446 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
447 bool set_chip, u16 sleep_duration)
448 {
449 unsigned int i;
450 u32 staid, data;
451
452 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
453
454 switch (mode) {
455 case AR5K_PM_AUTO:
456 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
457 /* fallthrough */
458 case AR5K_PM_NETWORK_SLEEP:
459 if (set_chip)
460 ath5k_hw_reg_write(ah,
461 AR5K_SLEEP_CTL_SLE_ALLOW |
462 sleep_duration,
463 AR5K_SLEEP_CTL);
464
465 staid |= AR5K_STA_ID1_PWR_SV;
466 break;
467
468 case AR5K_PM_FULL_SLEEP:
469 if (set_chip)
470 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
471 AR5K_SLEEP_CTL);
472
473 staid |= AR5K_STA_ID1_PWR_SV;
474 break;
475
476 case AR5K_PM_AWAKE:
477
478 staid &= ~AR5K_STA_ID1_PWR_SV;
479
480 if (!set_chip)
481 goto commit;
482
483 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
484
485 /* If card is down we 'll get 0xffff... so we
486 * need to clean this up before we write the register
487 */
488 if (data & 0xffc00000)
489 data = 0;
490 else
491 /* Preserve sleep duration etc */
492 data = data & ~AR5K_SLEEP_CTL_SLE;
493
494 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
495 AR5K_SLEEP_CTL);
496 udelay(15);
497
498 for (i = 200; i > 0; i--) {
499 /* Check if the chip did wake up */
500 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
501 AR5K_PCICFG_SPWR_DN) == 0)
502 break;
503
504 /* Wait a bit and retry */
505 udelay(50);
506 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
507 AR5K_SLEEP_CTL);
508 }
509
510 /* Fail if the chip didn't wake up */
511 if (i == 0)
512 return -EIO;
513
514 break;
515
516 default:
517 return -EINVAL;
518 }
519
520 commit:
521 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
522
523 return 0;
524 }
525
526 /*
527 * Put device on hold
528 *
529 * Put MAC and Baseband on warm reset and
530 * keep that state (don't clean sleep control
531 * register). After this MAC and Baseband are
532 * disabled and a full reset is needed to come
533 * back. This way we save as much power as possible
534 * without putting the card on full sleep.
535 */
536 int ath5k_hw_on_hold(struct ath5k_hw *ah)
537 {
538 struct pci_dev *pdev = ah->pdev;
539 u32 bus_flags;
540 int ret;
541
542 if (ath5k_get_bus_type(ah) == ATH_AHB)
543 return 0;
544
545 /* Make sure device is awake */
546 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
547 if (ret) {
548 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
549 return ret;
550 }
551
552 /*
553 * Put chipset on warm reset...
554 *
555 * Note: putting PCI core on warm reset on PCI-E cards
556 * results card to hang and always return 0xffff... so
557 * we ignore that flag for PCI-E cards. On PCI cards
558 * this flag gets cleared after 64 PCI clocks.
559 */
560 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
561
562 if (ah->ah_version == AR5K_AR5210) {
563 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
564 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
565 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
566 mdelay(2);
567 } else {
568 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
569 AR5K_RESET_CTL_BASEBAND | bus_flags);
570 }
571
572 if (ret) {
573 ATH5K_ERR(ah, "failed to put device on warm reset\n");
574 return -EIO;
575 }
576
577 /* ...wakeup again!*/
578 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
579 if (ret) {
580 ATH5K_ERR(ah, "failed to put device on hold\n");
581 return ret;
582 }
583
584 return ret;
585 }
586
587 /*
588 * Bring up MAC + PHY Chips and program PLL
589 * Channel is NULL for the initial wakeup.
590 */
591 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
592 {
593 struct pci_dev *pdev = ah->pdev;
594 u32 turbo, mode, clock, bus_flags;
595 int ret;
596
597 turbo = 0;
598 mode = 0;
599 clock = 0;
600
601 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
602 /* Wakeup the device */
603 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
604 if (ret) {
605 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
606 return ret;
607 }
608 }
609
610 /*
611 * Put chipset on warm reset...
612 *
613 * Note: putting PCI core on warm reset on PCI-E cards
614 * results card to hang and always return 0xffff... so
615 * we ignore that flag for PCI-E cards. On PCI cards
616 * this flag gets cleared after 64 PCI clocks.
617 */
618 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
619
620 if (ah->ah_version == AR5K_AR5210) {
621 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
622 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
623 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
624 mdelay(2);
625 } else {
626 if (ath5k_get_bus_type(ah) == ATH_AHB)
627 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
628 AR5K_RESET_CTL_BASEBAND);
629 else
630 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
631 AR5K_RESET_CTL_BASEBAND | bus_flags);
632 }
633
634 if (ret) {
635 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
636 return -EIO;
637 }
638
639 /* ...wakeup again!...*/
640 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
641 if (ret) {
642 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
643 return ret;
644 }
645
646 /* ...reset configuration register on Wisoc ...
647 * ...clear reset control register and pull device out of
648 * warm reset on others */
649 if (ath5k_get_bus_type(ah) == ATH_AHB)
650 ret = ath5k_hw_wisoc_reset(ah, 0);
651 else
652 ret = ath5k_hw_nic_reset(ah, 0);
653
654 if (ret) {
655 ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
656 return -EIO;
657 }
658
659 /* On initialization skip PLL programming since we don't have
660 * a channel / mode set yet */
661 if (!channel)
662 return 0;
663
664 if (ah->ah_version != AR5K_AR5210) {
665 /*
666 * Get channel mode flags
667 */
668
669 if (ah->ah_radio >= AR5K_RF5112) {
670 mode = AR5K_PHY_MODE_RAD_RF5112;
671 clock = AR5K_PHY_PLL_RF5112;
672 } else {
673 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
674 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
675 }
676
677 if (channel->band == IEEE80211_BAND_2GHZ) {
678 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
679 clock |= AR5K_PHY_PLL_44MHZ;
680
681 if (channel->hw_value == AR5K_MODE_11B) {
682 mode |= AR5K_PHY_MODE_MOD_CCK;
683 } else {
684 /* XXX Dynamic OFDM/CCK is not supported by the
685 * AR5211 so we set MOD_OFDM for plain g (no
686 * CCK headers) operation. We need to test
687 * this, 5211 might support ofdm-only g after
688 * all, there are also initial register values
689 * in the code for g mode (see initvals.c).
690 */
691 if (ah->ah_version == AR5K_AR5211)
692 mode |= AR5K_PHY_MODE_MOD_OFDM;
693 else
694 mode |= AR5K_PHY_MODE_MOD_DYN;
695 }
696 } else if (channel->band == IEEE80211_BAND_5GHZ) {
697 mode |= (AR5K_PHY_MODE_FREQ_5GHZ |
698 AR5K_PHY_MODE_MOD_OFDM);
699
700 /* Different PLL setting for 5413 */
701 if (ah->ah_radio == AR5K_RF5413)
702 clock = AR5K_PHY_PLL_40MHZ_5413;
703 else
704 clock |= AR5K_PHY_PLL_40MHZ;
705 } else {
706 ATH5K_ERR(ah, "invalid radio frequency mode\n");
707 return -EINVAL;
708 }
709
710 /*XXX: Can bwmode be used with dynamic mode ?
711 * (I don't think it supports 44MHz) */
712 /* On 2425 initvals TURBO_SHORT is not present */
713 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
714 turbo = AR5K_PHY_TURBO_MODE |
715 (ah->ah_radio == AR5K_RF2425) ? 0 :
716 AR5K_PHY_TURBO_SHORT;
717 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
718 if (ah->ah_radio == AR5K_RF5413) {
719 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
720 AR5K_PHY_MODE_HALF_RATE :
721 AR5K_PHY_MODE_QUARTER_RATE;
722 } else if (ah->ah_version == AR5K_AR5212) {
723 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
724 AR5K_PHY_PLL_HALF_RATE :
725 AR5K_PHY_PLL_QUARTER_RATE;
726 }
727 }
728
729 } else { /* Reset the device */
730
731 /* ...enable Atheros turbo mode if requested */
732 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
733 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
734 AR5K_PHY_TURBO);
735 }
736
737 if (ah->ah_version != AR5K_AR5210) {
738
739 /* ...update PLL if needed */
740 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
741 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
742 udelay(300);
743 }
744
745 /* ...set the PHY operating mode */
746 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
747 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
748 }
749
750 return 0;
751 }
752
753
754 /**************************************\
755 * Post-initvals register modifications *
756 \**************************************/
757
758 /* TODO: Half/Quarter rate */
759 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
760 struct ieee80211_channel *channel)
761 {
762 if (ah->ah_version == AR5K_AR5212 &&
763 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
764
765 /* Setup ADC control */
766 ath5k_hw_reg_write(ah,
767 (AR5K_REG_SM(2,
768 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
769 AR5K_REG_SM(2,
770 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
771 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
772 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
773 AR5K_PHY_ADC_CTL);
774
775
776
777 /* Disable barker RSSI threshold */
778 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
779 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
780
781 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
782 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
783
784 /* Set the mute mask */
785 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
786 }
787
788 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
789 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
790 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
791
792 /* Enable DCU double buffering */
793 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
794 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
795 AR5K_TXCFG_DCU_DBL_BUF_DIS);
796
797 /* Set fast ADC */
798 if ((ah->ah_radio == AR5K_RF5413) ||
799 (ah->ah_radio == AR5K_RF2317) ||
800 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
801 u32 fast_adc = true;
802
803 if (channel->center_freq == 2462 ||
804 channel->center_freq == 2467)
805 fast_adc = 0;
806
807 /* Only update if needed */
808 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
809 ath5k_hw_reg_write(ah, fast_adc,
810 AR5K_PHY_FAST_ADC);
811 }
812
813 /* Fix for first revision of the RF5112 RF chipset */
814 if (ah->ah_radio == AR5K_RF5112 &&
815 ah->ah_radio_5ghz_revision <
816 AR5K_SREV_RAD_5112A) {
817 u32 data;
818 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
819 AR5K_PHY_CCKTXCTL);
820 if (channel->band == IEEE80211_BAND_5GHZ)
821 data = 0xffb81020;
822 else
823 data = 0xffb80d20;
824 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
825 }
826
827 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
828 /* Clear QCU/DCU clock gating register */
829 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
830 /* Set DAC/ADC delays */
831 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
832 AR5K_PHY_SCAL);
833 /* Enable PCU FIFO corruption ECO */
834 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
835 AR5K_DIAG_SW_ECO_ENABLE);
836 }
837
838 if (ah->ah_bwmode) {
839 /* Increase PHY switch and AGC settling time
840 * on turbo mode (ath5k_hw_commit_eeprom_settings
841 * will override settling time if available) */
842 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
843
844 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
845 AR5K_PHY_SETTLING_AGC,
846 AR5K_AGC_SETTLING_TURBO);
847
848 /* XXX: Initvals indicate we only increase
849 * switch time on AR5212, 5211 and 5210
850 * only change agc time (bug?) */
851 if (ah->ah_version == AR5K_AR5212)
852 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
853 AR5K_PHY_SETTLING_SWITCH,
854 AR5K_SWITCH_SETTLING_TURBO);
855
856 if (ah->ah_version == AR5K_AR5210) {
857 /* Set Frame Control Register */
858 ath5k_hw_reg_write(ah,
859 (AR5K_PHY_FRAME_CTL_INI |
860 AR5K_PHY_TURBO_MODE |
861 AR5K_PHY_TURBO_SHORT | 0x2020),
862 AR5K_PHY_FRAME_CTL_5210);
863 }
864 /* On 5413 PHY force window length for half/quarter rate*/
865 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
866 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
867 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
868 AR5K_PHY_FRAME_CTL_WIN_LEN,
869 3);
870 }
871 } else if (ah->ah_version == AR5K_AR5210) {
872 /* Set Frame Control Register for normal operation */
873 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
874 AR5K_PHY_FRAME_CTL_5210);
875 }
876 }
877
878 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
879 struct ieee80211_channel *channel)
880 {
881 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
882 s16 cck_ofdm_pwr_delta;
883 u8 ee_mode;
884
885 /* TODO: Add support for AR5210 EEPROM */
886 if (ah->ah_version == AR5K_AR5210)
887 return;
888
889 ee_mode = ath5k_eeprom_mode_from_channel(channel);
890
891 /* Adjust power delta for channel 14 */
892 if (channel->center_freq == 2484)
893 cck_ofdm_pwr_delta =
894 ((ee->ee_cck_ofdm_power_delta -
895 ee->ee_scaled_cck_delta) * 2) / 10;
896 else
897 cck_ofdm_pwr_delta =
898 (ee->ee_cck_ofdm_power_delta * 2) / 10;
899
900 /* Set CCK to OFDM power delta on tx power
901 * adjustment register */
902 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
903 if (channel->hw_value == AR5K_MODE_11G)
904 ath5k_hw_reg_write(ah,
905 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
906 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
907 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
908 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
909 AR5K_PHY_TX_PWR_ADJ);
910 else
911 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
912 } else {
913 /* For older revs we scale power on sw during tx power
914 * setup */
915 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
916 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
917 ee->ee_cck_ofdm_gain_delta;
918 }
919
920 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
921 * too */
922 ath5k_hw_set_antenna_switch(ah, ee_mode);
923
924 /* Noise floor threshold */
925 ath5k_hw_reg_write(ah,
926 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
927 AR5K_PHY_NFTHRES);
928
929 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
930 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
931 /* Switch settling time (Turbo) */
932 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
933 AR5K_PHY_SETTLING_SWITCH,
934 ee->ee_switch_settling_turbo[ee_mode]);
935
936 /* Tx/Rx attenuation (Turbo) */
937 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
938 AR5K_PHY_GAIN_TXRX_ATTEN,
939 ee->ee_atn_tx_rx_turbo[ee_mode]);
940
941 /* ADC/PGA desired size (Turbo) */
942 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
943 AR5K_PHY_DESIRED_SIZE_ADC,
944 ee->ee_adc_desired_size_turbo[ee_mode]);
945
946 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
947 AR5K_PHY_DESIRED_SIZE_PGA,
948 ee->ee_pga_desired_size_turbo[ee_mode]);
949
950 /* Tx/Rx margin (Turbo) */
951 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
952 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
953 ee->ee_margin_tx_rx_turbo[ee_mode]);
954
955 } else {
956 /* Switch settling time */
957 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
958 AR5K_PHY_SETTLING_SWITCH,
959 ee->ee_switch_settling[ee_mode]);
960
961 /* Tx/Rx attenuation */
962 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
963 AR5K_PHY_GAIN_TXRX_ATTEN,
964 ee->ee_atn_tx_rx[ee_mode]);
965
966 /* ADC/PGA desired size */
967 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
968 AR5K_PHY_DESIRED_SIZE_ADC,
969 ee->ee_adc_desired_size[ee_mode]);
970
971 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
972 AR5K_PHY_DESIRED_SIZE_PGA,
973 ee->ee_pga_desired_size[ee_mode]);
974
975 /* Tx/Rx margin */
976 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
977 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
978 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
979 ee->ee_margin_tx_rx[ee_mode]);
980 }
981
982 /* XPA delays */
983 ath5k_hw_reg_write(ah,
984 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
985 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
986 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
987 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
988
989 /* XLNA delay */
990 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
991 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
992 ee->ee_tx_end2xlna_enable[ee_mode]);
993
994 /* Thresh64 (ANI) */
995 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
996 AR5K_PHY_NF_THRESH62,
997 ee->ee_thr_62[ee_mode]);
998
999 /* False detect backoff for channels
1000 * that have spur noise. Write the new
1001 * cyclic power RSSI threshold. */
1002 if (ath5k_hw_chan_has_spur_noise(ah, channel))
1003 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1004 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1005 AR5K_INIT_CYCRSSI_THR1 +
1006 ee->ee_false_detect[ee_mode]);
1007 else
1008 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1009 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1010 AR5K_INIT_CYCRSSI_THR1);
1011
1012 /* I/Q correction (set enable bit last to match HAL sources) */
1013 /* TODO: Per channel i/q infos ? */
1014 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1015 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1016 ee->ee_i_cal[ee_mode]);
1017 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1018 ee->ee_q_cal[ee_mode]);
1019 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1020 }
1021
1022 /* Heavy clipping -disable for now */
1023 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1024 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1025 }
1026
1027
1028 /*********************\
1029 * Main reset function *
1030 \*********************/
1031
1032 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1033 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1034 {
1035 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1036 u8 mode;
1037 int i, ret;
1038
1039 tsf_up = 0;
1040 tsf_lo = 0;
1041 mode = 0;
1042
1043 /*
1044 * Sanity check for fast flag
1045 * Fast channel change only available
1046 * on AR2413/AR5413.
1047 */
1048 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1049 (ah->ah_radio != AR5K_RF5413))
1050 fast = 0;
1051
1052 /* Disable sleep clock operation
1053 * to avoid register access delay on certain
1054 * PHY registers */
1055 if (ah->ah_version == AR5K_AR5212)
1056 ath5k_hw_set_sleep_clock(ah, false);
1057
1058 /*
1059 * Stop PCU
1060 */
1061 ath5k_hw_stop_rx_pcu(ah);
1062
1063 /*
1064 * Stop DMA
1065 *
1066 * Note: If DMA didn't stop continue
1067 * since only a reset will fix it.
1068 */
1069 ret = ath5k_hw_dma_stop(ah);
1070
1071 /* RF Bus grant won't work if we have pending
1072 * frames */
1073 if (ret && fast) {
1074 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1075 "DMA didn't stop, falling back to normal reset\n");
1076 fast = 0;
1077 /* Non fatal, just continue with
1078 * normal reset */
1079 ret = 0;
1080 }
1081
1082 mode = channel->hw_value;
1083 switch (mode) {
1084 case AR5K_MODE_11A:
1085 break;
1086 case AR5K_MODE_11G:
1087 if (ah->ah_version <= AR5K_AR5211) {
1088 ATH5K_ERR(ah,
1089 "G mode not available on 5210/5211");
1090 return -EINVAL;
1091 }
1092 break;
1093 case AR5K_MODE_11B:
1094 if (ah->ah_version < AR5K_AR5211) {
1095 ATH5K_ERR(ah,
1096 "B mode not available on 5210");
1097 return -EINVAL;
1098 }
1099 break;
1100 default:
1101 ATH5K_ERR(ah,
1102 "invalid channel: %d\n", channel->center_freq);
1103 return -EINVAL;
1104 }
1105
1106 /*
1107 * If driver requested fast channel change and DMA has stopped
1108 * go on. If it fails continue with a normal reset.
1109 */
1110 if (fast) {
1111 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1112 if (ret) {
1113 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1114 "fast chan change failed, falling back to normal reset\n");
1115 /* Non fatal, can happen eg.
1116 * on mode change */
1117 ret = 0;
1118 } else {
1119 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1120 "fast chan change successful\n");
1121 return 0;
1122 }
1123 }
1124
1125 /*
1126 * Save some registers before a reset
1127 */
1128 if (ah->ah_version != AR5K_AR5210) {
1129 /*
1130 * Save frame sequence count
1131 * For revs. after Oahu, only save
1132 * seq num for DCU 0 (Global seq num)
1133 */
1134 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1135
1136 for (i = 0; i < 10; i++)
1137 s_seq[i] = ath5k_hw_reg_read(ah,
1138 AR5K_QUEUE_DCU_SEQNUM(i));
1139
1140 } else {
1141 s_seq[0] = ath5k_hw_reg_read(ah,
1142 AR5K_QUEUE_DCU_SEQNUM(0));
1143 }
1144
1145 /* TSF accelerates on AR5211 during reset
1146 * As a workaround save it here and restore
1147 * it later so that it's back in time after
1148 * reset. This way it'll get re-synced on the
1149 * next beacon without breaking ad-hoc.
1150 *
1151 * On AR5212 TSF is almost preserved across a
1152 * reset so it stays back in time anyway and
1153 * we don't have to save/restore it.
1154 *
1155 * XXX: Since this breaks power saving we have
1156 * to disable power saving until we receive the
1157 * next beacon, so we can resync beacon timers */
1158 if (ah->ah_version == AR5K_AR5211) {
1159 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1160 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1161 }
1162 }
1163
1164
1165 /*GPIOs*/
1166 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1167 AR5K_PCICFG_LEDSTATE;
1168 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1169 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1170
1171
1172 /*
1173 * Since we are going to write rf buffer
1174 * check if we have any pending gain_F
1175 * optimization settings
1176 */
1177 if (ah->ah_version == AR5K_AR5212 &&
1178 (ah->ah_radio <= AR5K_RF5112)) {
1179 if (!fast && ah->ah_rf_banks != NULL)
1180 ath5k_hw_gainf_calibrate(ah);
1181 }
1182
1183 /* Wakeup the device */
1184 ret = ath5k_hw_nic_wakeup(ah, channel);
1185 if (ret)
1186 return ret;
1187
1188 /* PHY access enable */
1189 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1190 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1191 else
1192 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1193 AR5K_PHY(0));
1194
1195 /* Write initial settings */
1196 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1197 if (ret)
1198 return ret;
1199
1200 /* Initialize core clock settings */
1201 ath5k_hw_init_core_clock(ah);
1202
1203 /*
1204 * Tweak initval settings for revised
1205 * chipsets and add some more config
1206 * bits
1207 */
1208 ath5k_hw_tweak_initval_settings(ah, channel);
1209
1210 /* Commit values from EEPROM */
1211 ath5k_hw_commit_eeprom_settings(ah, channel);
1212
1213
1214 /*
1215 * Restore saved values
1216 */
1217
1218 /* Seqnum, TSF */
1219 if (ah->ah_version != AR5K_AR5210) {
1220 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1221 for (i = 0; i < 10; i++)
1222 ath5k_hw_reg_write(ah, s_seq[i],
1223 AR5K_QUEUE_DCU_SEQNUM(i));
1224 } else {
1225 ath5k_hw_reg_write(ah, s_seq[0],
1226 AR5K_QUEUE_DCU_SEQNUM(0));
1227 }
1228
1229 if (ah->ah_version == AR5K_AR5211) {
1230 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1231 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1232 }
1233 }
1234
1235 /* Ledstate */
1236 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1237
1238 /* Gpio settings */
1239 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1240 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1241
1242 /*
1243 * Initialize PCU
1244 */
1245 ath5k_hw_pcu_init(ah, op_mode, mode);
1246
1247 /*
1248 * Initialize PHY
1249 */
1250 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1251 if (ret) {
1252 ATH5K_ERR(ah,
1253 "failed to initialize PHY (%i) !\n", ret);
1254 return ret;
1255 }
1256
1257 /*
1258 * Configure QCUs/DCUs
1259 */
1260 ret = ath5k_hw_init_queues(ah);
1261 if (ret)
1262 return ret;
1263
1264
1265 /*
1266 * Initialize DMA/Interrupts
1267 */
1268 ath5k_hw_dma_init(ah);
1269
1270
1271 /*
1272 * Enable 32KHz clock function for AR5212+ chips
1273 * Set clocks to 32KHz operation and use an
1274 * external 32KHz crystal when sleeping if one
1275 * exists.
1276 * Disabled by default because it is also disabled in
1277 * other drivers and it is known to cause stability
1278 * issues on some devices
1279 */
1280 if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1281 op_mode != NL80211_IFTYPE_AP)
1282 ath5k_hw_set_sleep_clock(ah, true);
1283
1284 /*
1285 * Disable beacons and reset the TSF
1286 */
1287 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1288 ath5k_hw_reset_tsf(ah);
1289 return 0;
1290 }
Mirror of the linux-mips.org kernel tree