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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / scsi / qla4xxx / ql4_mbx.c
blob4c2b84870392e16f1ed03428aa7ed9c004c9cbd9
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #include "ql4_def.h"
9 #include "ql4_glbl.h"
10 #include "ql4_dbg.h"
11 #include "ql4_inline.h"
12
13
14 /**
15 * qla4xxx_mailbox_command - issues mailbox commands
16 * @ha: Pointer to host adapter structure.
17 * @inCount: number of mailbox registers to load.
18 * @outCount: number of mailbox registers to return.
19 * @mbx_cmd: data pointer for mailbox in registers.
20 * @mbx_sts: data pointer for mailbox out registers.
21 *
22 * This routine issue mailbox commands and waits for completion.
23 * If outCount is 0, this routine completes successfully WITHOUT waiting
24 * for the mailbox command to complete.
25 **/
26 int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
27 uint8_t outCount, uint32_t *mbx_cmd,
28 uint32_t *mbx_sts)
29 {
30 int status = QLA_ERROR;
31 uint8_t i;
32 u_long wait_count;
33 uint32_t intr_status;
34 unsigned long flags = 0;
35 uint32_t dev_state;
36
37 /* Make sure that pointers are valid */
38 if (!mbx_cmd || !mbx_sts) {
39 DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
40 "pointer\n", ha->host_no, __func__));
41 return status;
42 }
43
44 if (is_qla8022(ha)) {
45 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
46 DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
47 "prematurely completing mbx cmd as firmware "
48 "recovery detected\n", ha->host_no, __func__));
49 return status;
50 }
51 /* Do not send any mbx cmd if h/w is in failed state*/
52 qla4_8xxx_idc_lock(ha);
53 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
54 qla4_8xxx_idc_unlock(ha);
55 if (dev_state == QLA82XX_DEV_FAILED) {
56 ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
57 "failed state, do not send any mailbox commands\n",
58 ha->host_no, __func__);
59 return status;
60 }
61 }
62
63 if ((is_aer_supported(ha)) &&
64 (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
65 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
66 "timeout MBX Exiting.\n", ha->host_no, __func__));
67 return status;
68 }
69
70 /* Mailbox code active */
71 wait_count = MBOX_TOV * 100;
72
73 while (wait_count--) {
74 mutex_lock(&ha->mbox_sem);
75 if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
76 set_bit(AF_MBOX_COMMAND, &ha->flags);
77 mutex_unlock(&ha->mbox_sem);
78 break;
79 }
80 mutex_unlock(&ha->mbox_sem);
81 if (!wait_count) {
82 DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
83 ha->host_no, __func__));
84 return status;
85 }
86 msleep(10);
87 }
88
89 spin_lock_irqsave(&ha->hardware_lock, flags);
90
91 ha->mbox_status_count = outCount;
92 for (i = 0; i < outCount; i++)
93 ha->mbox_status[i] = 0;
94
95 if (is_qla8022(ha)) {
96 /* Load all mailbox registers, except mailbox 0. */
97 DEBUG5(
98 printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
99 for (i = 0; i < inCount; i++)
100 printk("mb%d=%04x ", i, mbx_cmd[i]);
101 printk("\n"));
102
103 for (i = 1; i < inCount; i++)
104 writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
105 writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
106 readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
107 writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
108 } else {
109 /* Load all mailbox registers, except mailbox 0. */
110 for (i = 1; i < inCount; i++)
111 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
112
113 /* Wakeup firmware */
114 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
115 readl(&ha->reg->mailbox[0]);
116 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
117 readl(&ha->reg->ctrl_status);
118 }
119
120 spin_unlock_irqrestore(&ha->hardware_lock, flags);
121
122 /* Wait for completion */
123
124 /*
125 * If we don't want status, don't wait for the mailbox command to
126 * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
127 * you must poll the inbound Interrupt Mask for completion.
128 */
129 if (outCount == 0) {
130 status = QLA_SUCCESS;
131 goto mbox_exit;
132 }
133
134 /*
135 * Wait for completion: Poll or completion queue
136 */
137 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
138 test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
139 test_bit(AF_ONLINE, &ha->flags) &&
140 !test_bit(AF_HA_REMOVAL, &ha->flags)) {
141 /* Do not poll for completion. Use completion queue */
142 set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
143 wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
144 clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
145 } else {
146 /* Poll for command to complete */
147 wait_count = jiffies + MBOX_TOV * HZ;
148 while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
149 if (time_after_eq(jiffies, wait_count))
150 break;
151
152 /*
153 * Service the interrupt.
154 * The ISR will save the mailbox status registers
155 * to a temporary storage location in the adapter
156 * structure.
157 */
158
159 spin_lock_irqsave(&ha->hardware_lock, flags);
160 if (is_qla8022(ha)) {
161 intr_status =
162 readl(&ha->qla4_8xxx_reg->host_int);
163 if (intr_status & ISRX_82XX_RISC_INT) {
164 ha->mbox_status_count = outCount;
165 intr_status =
166 readl(&ha->qla4_8xxx_reg->host_status);
167 ha->isp_ops->interrupt_service_routine(
168 ha, intr_status);
169 if (test_bit(AF_INTERRUPTS_ON,
170 &ha->flags) &&
171 test_bit(AF_INTx_ENABLED,
172 &ha->flags))
173 qla4_8xxx_wr_32(ha,
174 ha->nx_legacy_intr.tgt_mask_reg,
175 0xfbff);
176 }
177 } else {
178 intr_status = readl(&ha->reg->ctrl_status);
179 if (intr_status & INTR_PENDING) {
180 /*
181 * Service the interrupt.
182 * The ISR will save the mailbox status
183 * registers to a temporary storage
184 * location in the adapter structure.
185 */
186 ha->mbox_status_count = outCount;
187 ha->isp_ops->interrupt_service_routine(
188 ha, intr_status);
189 }
190 }
191 spin_unlock_irqrestore(&ha->hardware_lock, flags);
192 msleep(10);
193 }
194 }
195
196 /* Check for mailbox timeout. */
197 if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
198 if (is_qla8022(ha) &&
199 test_bit(AF_FW_RECOVERY, &ha->flags)) {
200 DEBUG2(ql4_printk(KERN_INFO, ha,
201 "scsi%ld: %s: prematurely completing mbx cmd as "
202 "firmware recovery detected\n",
203 ha->host_no, __func__));
204 goto mbox_exit;
205 }
206 DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
207 " Scheduling Adapter Reset\n", ha->host_no,
208 mbx_cmd[0]));
209 ha->mailbox_timeout_count++;
210 mbx_sts[0] = (-1);
211 set_bit(DPC_RESET_HA, &ha->dpc_flags);
212 goto mbox_exit;
213 }
214
215 /*
216 * Copy the mailbox out registers to the caller's mailbox in/out
217 * structure.
218 */
219 spin_lock_irqsave(&ha->hardware_lock, flags);
220 for (i = 0; i < outCount; i++)
221 mbx_sts[i] = ha->mbox_status[i];
222
223 /* Set return status and error flags (if applicable). */
224 switch (ha->mbox_status[0]) {
225 case MBOX_STS_COMMAND_COMPLETE:
226 status = QLA_SUCCESS;
227 break;
228
229 case MBOX_STS_INTERMEDIATE_COMPLETION:
230 status = QLA_SUCCESS;
231 break;
232
233 case MBOX_STS_BUSY:
234 DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
235 ha->host_no, __func__, mbx_cmd[0]));
236 ha->mailbox_timeout_count++;
237 break;
238
239 default:
240 DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
241 "sts = %08X ****\n", ha->host_no, __func__,
242 mbx_cmd[0], mbx_sts[0]));
243 break;
244 }
245 spin_unlock_irqrestore(&ha->hardware_lock, flags);
246
247 mbox_exit:
248 mutex_lock(&ha->mbox_sem);
249 clear_bit(AF_MBOX_COMMAND, &ha->flags);
250 mutex_unlock(&ha->mbox_sem);
251 clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
252
253 return status;
254 }
255
256 void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
257 {
258 set_bit(AF_FW_RECOVERY, &ha->flags);
259 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
260 ha->host_no, __func__);
261
262 if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
263 if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
264 complete(&ha->mbx_intr_comp);
265 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
266 "recovery, doing premature completion of "
267 "mbx cmd\n", ha->host_no, __func__);
268
269 } else {
270 set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
271 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
272 "recovery, doing premature completion of "
273 "polling mbx cmd\n", ha->host_no, __func__);
274 }
275 }
276 }
277
278 static uint8_t
279 qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
280 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
281 {
282 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
283 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
284
285 if (is_qla8022(ha))
286 qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
287
288 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
289 mbox_cmd[1] = 0;
290 mbox_cmd[2] = LSDW(init_fw_cb_dma);
291 mbox_cmd[3] = MSDW(init_fw_cb_dma);
292 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
293 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
294
295 if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
296 QLA_SUCCESS) {
297 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
298 "MBOX_CMD_INITIALIZE_FIRMWARE"
299 " failed w/ status %04X\n",
300 ha->host_no, __func__, mbox_sts[0]));
301 return QLA_ERROR;
302 }
303 return QLA_SUCCESS;
304 }
305
306 uint8_t
307 qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
308 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
309 {
310 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
311 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
312 mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
313 mbox_cmd[2] = LSDW(init_fw_cb_dma);
314 mbox_cmd[3] = MSDW(init_fw_cb_dma);
315 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
316
317 if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
318 QLA_SUCCESS) {
319 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
320 "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
321 " failed w/ status %04X\n",
322 ha->host_no, __func__, mbox_sts[0]));
323 return QLA_ERROR;
324 }
325 return QLA_SUCCESS;
326 }
327
328 static void
329 qla4xxx_update_local_ip(struct scsi_qla_host *ha,
330 struct addr_ctrl_blk *init_fw_cb)
331 {
332 ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
333 ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
334 ha->ip_config.ipv4_addr_state =
335 le16_to_cpu(init_fw_cb->ipv4_addr_state);
336 ha->ip_config.eth_mtu_size =
337 le16_to_cpu(init_fw_cb->eth_mtu_size);
338 ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
339
340 if (ha->acb_version == ACB_SUPPORTED) {
341 ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
342 ha->ip_config.ipv6_addl_options =
343 le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
344 }
345
346 /* Save IPv4 Address Info */
347 memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
348 min(sizeof(ha->ip_config.ip_address),
349 sizeof(init_fw_cb->ipv4_addr)));
350 memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
351 min(sizeof(ha->ip_config.subnet_mask),
352 sizeof(init_fw_cb->ipv4_subnet)));
353 memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
354 min(sizeof(ha->ip_config.gateway),
355 sizeof(init_fw_cb->ipv4_gw_addr)));
356
357 ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
358
359 if (is_ipv6_enabled(ha)) {
360 /* Save IPv6 Address */
361 ha->ip_config.ipv6_link_local_state =
362 le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
363 ha->ip_config.ipv6_addr0_state =
364 le16_to_cpu(init_fw_cb->ipv6_addr0_state);
365 ha->ip_config.ipv6_addr1_state =
366 le16_to_cpu(init_fw_cb->ipv6_addr1_state);
367 ha->ip_config.ipv6_default_router_state =
368 le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
369 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
370 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
371
372 memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
373 init_fw_cb->ipv6_if_id,
374 min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
375 sizeof(init_fw_cb->ipv6_if_id)));
376 memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
377 min(sizeof(ha->ip_config.ipv6_addr0),
378 sizeof(init_fw_cb->ipv6_addr0)));
379 memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
380 min(sizeof(ha->ip_config.ipv6_addr1),
381 sizeof(init_fw_cb->ipv6_addr1)));
382 memcpy(&ha->ip_config.ipv6_default_router_addr,
383 init_fw_cb->ipv6_dflt_rtr_addr,
384 min(sizeof(ha->ip_config.ipv6_default_router_addr),
385 sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
386 ha->ip_config.ipv6_vlan_tag =
387 be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
388 ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
389 }
390 }
391
392 uint8_t
393 qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
394 uint32_t *mbox_cmd,
395 uint32_t *mbox_sts,
396 struct addr_ctrl_blk *init_fw_cb,
397 dma_addr_t init_fw_cb_dma)
398 {
399 if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
400 != QLA_SUCCESS) {
401 DEBUG2(printk(KERN_WARNING
402 "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
403 ha->host_no, __func__));
404 return QLA_ERROR;
405 }
406
407 DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
408
409 /* Save some info in adapter structure. */
410 ha->acb_version = init_fw_cb->acb_version;
411 ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
412 ha->heartbeat_interval = init_fw_cb->hb_interval;
413 memcpy(ha->name_string, init_fw_cb->iscsi_name,
414 min(sizeof(ha->name_string),
415 sizeof(init_fw_cb->iscsi_name)));
416 /*memcpy(ha->alias, init_fw_cb->Alias,
417 min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
418
419 qla4xxx_update_local_ip(ha, init_fw_cb);
420
421 return QLA_SUCCESS;
422 }
423
424 /**
425 * qla4xxx_initialize_fw_cb - initializes firmware control block.
426 * @ha: Pointer to host adapter structure.
427 **/
428 int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
429 {
430 struct addr_ctrl_blk *init_fw_cb;
431 dma_addr_t init_fw_cb_dma;
432 uint32_t mbox_cmd[MBOX_REG_COUNT];
433 uint32_t mbox_sts[MBOX_REG_COUNT];
434 int status = QLA_ERROR;
435
436 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
437 sizeof(struct addr_ctrl_blk),
438 &init_fw_cb_dma, GFP_KERNEL);
439 if (init_fw_cb == NULL) {
440 DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
441 ha->host_no, __func__));
442 goto exit_init_fw_cb_no_free;
443 }
444 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
445
446 /* Get Initialize Firmware Control Block. */
447 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
448 memset(&mbox_sts, 0, sizeof(mbox_sts));
449
450 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
451 QLA_SUCCESS) {
452 dma_free_coherent(&ha->pdev->dev,
453 sizeof(struct addr_ctrl_blk),
454 init_fw_cb, init_fw_cb_dma);
455 goto exit_init_fw_cb;
456 }
457
458 /* Initialize request and response queues. */
459 qla4xxx_init_rings(ha);
460
461 /* Fill in the request and response queue information. */
462 init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
463 init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
464 init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
465 init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
466 init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
467 init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
468 init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
469 init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
470 init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
471 init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
472
473 /* Set up required options. */
474 init_fw_cb->fw_options |=
475 __constant_cpu_to_le16(FWOPT_SESSION_MODE |
476 FWOPT_INITIATOR_MODE);
477
478 if (is_qla8022(ha))
479 init_fw_cb->fw_options |=
480 __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
481
482 init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
483
484 init_fw_cb->add_fw_options = 0;
485 init_fw_cb->add_fw_options |=
486 __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
487 init_fw_cb->add_fw_options |=
488 __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
489
490 if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
491 != QLA_SUCCESS) {
492 DEBUG2(printk(KERN_WARNING
493 "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
494 ha->host_no, __func__));
495 goto exit_init_fw_cb;
496 }
497
498 if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
499 init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
500 DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
501 ha->host_no, __func__));
502 goto exit_init_fw_cb;
503 }
504 status = QLA_SUCCESS;
505
506 exit_init_fw_cb:
507 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
508 init_fw_cb, init_fw_cb_dma);
509 exit_init_fw_cb_no_free:
510 return status;
511 }
512
513 /**
514 * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
515 * @ha: Pointer to host adapter structure.
516 **/
517 int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
518 {
519 struct addr_ctrl_blk *init_fw_cb;
520 dma_addr_t init_fw_cb_dma;
521 uint32_t mbox_cmd[MBOX_REG_COUNT];
522 uint32_t mbox_sts[MBOX_REG_COUNT];
523
524 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
525 sizeof(struct addr_ctrl_blk),
526 &init_fw_cb_dma, GFP_KERNEL);
527 if (init_fw_cb == NULL) {
528 printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
529 __func__);
530 return QLA_ERROR;
531 }
532
533 /* Get Initialize Firmware Control Block. */
534 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
535 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
536 QLA_SUCCESS) {
537 DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
538 ha->host_no, __func__));
539 dma_free_coherent(&ha->pdev->dev,
540 sizeof(struct addr_ctrl_blk),
541 init_fw_cb, init_fw_cb_dma);
542 return QLA_ERROR;
543 }
544
545 /* Save IP Address. */
546 qla4xxx_update_local_ip(ha, init_fw_cb);
547 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
548 init_fw_cb, init_fw_cb_dma);
549
550 return QLA_SUCCESS;
551 }
552
553 /**
554 * qla4xxx_get_firmware_state - gets firmware state of HBA
555 * @ha: Pointer to host adapter structure.
556 **/
557 int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
558 {
559 uint32_t mbox_cmd[MBOX_REG_COUNT];
560 uint32_t mbox_sts[MBOX_REG_COUNT];
561
562 /* Get firmware version */
563 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
564 memset(&mbox_sts, 0, sizeof(mbox_sts));
565
566 mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
567
568 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
569 QLA_SUCCESS) {
570 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
571 "status %04X\n", ha->host_no, __func__,
572 mbox_sts[0]));
573 return QLA_ERROR;
574 }
575 ha->firmware_state = mbox_sts[1];
576 ha->board_id = mbox_sts[2];
577 ha->addl_fw_state = mbox_sts[3];
578 DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
579 ha->host_no, __func__, ha->firmware_state);)
580
581 return QLA_SUCCESS;
582 }
583
584 /**
585 * qla4xxx_get_firmware_status - retrieves firmware status
586 * @ha: Pointer to host adapter structure.
587 **/
588 int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
589 {
590 uint32_t mbox_cmd[MBOX_REG_COUNT];
591 uint32_t mbox_sts[MBOX_REG_COUNT];
592
593 /* Get firmware version */
594 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
595 memset(&mbox_sts, 0, sizeof(mbox_sts));
596
597 mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
598
599 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
600 QLA_SUCCESS) {
601 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
602 "status %04X\n", ha->host_no, __func__,
603 mbox_sts[0]));
604 return QLA_ERROR;
605 }
606
607 ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
608 ha->host_no, mbox_sts[2]);
609
610 return QLA_SUCCESS;
611 }
612
613 /**
614 * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
615 * @ha: Pointer to host adapter structure.
616 * @fw_ddb_index: Firmware's device database index
617 * @fw_ddb_entry: Pointer to firmware's device database entry structure
618 * @num_valid_ddb_entries: Pointer to number of valid ddb entries
619 * @next_ddb_index: Pointer to next valid device database index
620 * @fw_ddb_device_state: Pointer to device state
621 **/
622 int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
623 uint16_t fw_ddb_index,
624 struct dev_db_entry *fw_ddb_entry,
625 dma_addr_t fw_ddb_entry_dma,
626 uint32_t *num_valid_ddb_entries,
627 uint32_t *next_ddb_index,
628 uint32_t *fw_ddb_device_state,
629 uint32_t *conn_err_detail,
630 uint16_t *tcp_source_port_num,
631 uint16_t *connection_id)
632 {
633 int status = QLA_ERROR;
634 uint16_t options;
635 uint32_t mbox_cmd[MBOX_REG_COUNT];
636 uint32_t mbox_sts[MBOX_REG_COUNT];
637
638 /* Make sure the device index is valid */
639 if (fw_ddb_index >= MAX_DDB_ENTRIES) {
640 DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
641 ha->host_no, __func__, fw_ddb_index));
642 goto exit_get_fwddb;
643 }
644 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
645 memset(&mbox_sts, 0, sizeof(mbox_sts));
646
647 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
648 mbox_cmd[1] = (uint32_t) fw_ddb_index;
649 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
650 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
651 mbox_cmd[4] = sizeof(struct dev_db_entry);
652
653 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
654 QLA_ERROR) {
655 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
656 " with status 0x%04X\n", ha->host_no, __func__,
657 mbox_sts[0]));
658 goto exit_get_fwddb;
659 }
660 if (fw_ddb_index != mbox_sts[1]) {
661 DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
662 ha->host_no, __func__, fw_ddb_index,
663 mbox_sts[1]));
664 goto exit_get_fwddb;
665 }
666 if (fw_ddb_entry) {
667 options = le16_to_cpu(fw_ddb_entry->options);
668 if (options & DDB_OPT_IPV6_DEVICE) {
669 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
670 "Next %d State %04x ConnErr %08x %pI6 "
671 ":%04d \"%s\"\n", __func__, fw_ddb_index,
672 mbox_sts[0], mbox_sts[2], mbox_sts[3],
673 mbox_sts[4], mbox_sts[5],
674 fw_ddb_entry->ip_addr,
675 le16_to_cpu(fw_ddb_entry->port),
676 fw_ddb_entry->iscsi_name);
677 } else {
678 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
679 "Next %d State %04x ConnErr %08x %pI4 "
680 ":%04d \"%s\"\n", __func__, fw_ddb_index,
681 mbox_sts[0], mbox_sts[2], mbox_sts[3],
682 mbox_sts[4], mbox_sts[5],
683 fw_ddb_entry->ip_addr,
684 le16_to_cpu(fw_ddb_entry->port),
685 fw_ddb_entry->iscsi_name);
686 }
687 }
688 if (num_valid_ddb_entries)
689 *num_valid_ddb_entries = mbox_sts[2];
690 if (next_ddb_index)
691 *next_ddb_index = mbox_sts[3];
692 if (fw_ddb_device_state)
693 *fw_ddb_device_state = mbox_sts[4];
694
695 /*
696 * RA: This mailbox has been changed to pass connection error and
697 * details. Its true for ISP4010 as per Version E - Not sure when it
698 * was changed. Get the time2wait from the fw_dd_entry field :
699 * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
700 * struct.
701 */
702 if (conn_err_detail)
703 *conn_err_detail = mbox_sts[5];
704 if (tcp_source_port_num)
705 *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
706 if (connection_id)
707 *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
708 status = QLA_SUCCESS;
709
710 exit_get_fwddb:
711 return status;
712 }
713
714 int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
715 {
716 uint32_t mbox_cmd[MBOX_REG_COUNT];
717 uint32_t mbox_sts[MBOX_REG_COUNT];
718 int status;
719
720 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
721 memset(&mbox_sts, 0, sizeof(mbox_sts));
722
723 mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
724 mbox_cmd[1] = fw_ddb_index;
725
726 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
727 &mbox_sts[0]);
728 DEBUG2(ql4_printk(KERN_INFO, ha,
729 "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
730 __func__, status, mbox_sts[0], mbox_sts[1]));
731 return status;
732 }
733
734 /**
735 * qla4xxx_set_fwddb_entry - sets a ddb entry.
736 * @ha: Pointer to host adapter structure.
737 * @fw_ddb_index: Firmware's device database index
738 * @fw_ddb_entry_dma: dma address of ddb entry
739 * @mbx_sts: mailbox 0 to be returned or NULL
740 *
741 * This routine initializes or updates the adapter's device database
742 * entry for the specified device.
743 **/
744 int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
745 dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
746 {
747 uint32_t mbox_cmd[MBOX_REG_COUNT];
748 uint32_t mbox_sts[MBOX_REG_COUNT];
749 int status;
750
751 /* Do not wait for completion. The firmware will send us an
752 * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
753 */
754 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
755 memset(&mbox_sts, 0, sizeof(mbox_sts));
756
757 mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
758 mbox_cmd[1] = (uint32_t) fw_ddb_index;
759 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
760 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
761 mbox_cmd[4] = sizeof(struct dev_db_entry);
762
763 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
764 &mbox_sts[0]);
765 if (mbx_sts)
766 *mbx_sts = mbox_sts[0];
767 DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
768 ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
769
770 return status;
771 }
772
773 int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
774 struct ddb_entry *ddb_entry, int options)
775 {
776 int status;
777 uint32_t mbox_cmd[MBOX_REG_COUNT];
778 uint32_t mbox_sts[MBOX_REG_COUNT];
779
780 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
781 memset(&mbox_sts, 0, sizeof(mbox_sts));
782
783 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
784 mbox_cmd[1] = ddb_entry->fw_ddb_index;
785 mbox_cmd[3] = options;
786
787 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
788 &mbox_sts[0]);
789 if (status != QLA_SUCCESS) {
790 DEBUG2(ql4_printk(KERN_INFO, ha,
791 "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
792 "failed sts %04X %04X", __func__,
793 mbox_sts[0], mbox_sts[1]));
794 }
795
796 return status;
797 }
798
799 /**
800 * qla4xxx_get_crash_record - retrieves crash record.
801 * @ha: Pointer to host adapter structure.
802 *
803 * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
804 **/
805 void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
806 {
807 uint32_t mbox_cmd[MBOX_REG_COUNT];
808 uint32_t mbox_sts[MBOX_REG_COUNT];
809 struct crash_record *crash_record = NULL;
810 dma_addr_t crash_record_dma = 0;
811 uint32_t crash_record_size = 0;
812
813 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
814 memset(&mbox_sts, 0, sizeof(mbox_cmd));
815
816 /* Get size of crash record. */
817 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
818
819 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
820 QLA_SUCCESS) {
821 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
822 ha->host_no, __func__));
823 goto exit_get_crash_record;
824 }
825 crash_record_size = mbox_sts[4];
826 if (crash_record_size == 0) {
827 DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
828 ha->host_no, __func__));
829 goto exit_get_crash_record;
830 }
831
832 /* Alloc Memory for Crash Record. */
833 crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
834 &crash_record_dma, GFP_KERNEL);
835 if (crash_record == NULL)
836 goto exit_get_crash_record;
837
838 /* Get Crash Record. */
839 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
840 memset(&mbox_sts, 0, sizeof(mbox_cmd));
841
842 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
843 mbox_cmd[2] = LSDW(crash_record_dma);
844 mbox_cmd[3] = MSDW(crash_record_dma);
845 mbox_cmd[4] = crash_record_size;
846
847 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
848 QLA_SUCCESS)
849 goto exit_get_crash_record;
850
851 /* Dump Crash Record. */
852
853 exit_get_crash_record:
854 if (crash_record)
855 dma_free_coherent(&ha->pdev->dev, crash_record_size,
856 crash_record, crash_record_dma);
857 }
858
859 /**
860 * qla4xxx_get_conn_event_log - retrieves connection event log
861 * @ha: Pointer to host adapter structure.
862 **/
863 void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
864 {
865 uint32_t mbox_cmd[MBOX_REG_COUNT];
866 uint32_t mbox_sts[MBOX_REG_COUNT];
867 struct conn_event_log_entry *event_log = NULL;
868 dma_addr_t event_log_dma = 0;
869 uint32_t event_log_size = 0;
870 uint32_t num_valid_entries;
871 uint32_t oldest_entry = 0;
872 uint32_t max_event_log_entries;
873 uint8_t i;
874
875 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
876 memset(&mbox_sts, 0, sizeof(mbox_cmd));
877
878 /* Get size of crash record. */
879 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
880
881 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
882 QLA_SUCCESS)
883 goto exit_get_event_log;
884
885 event_log_size = mbox_sts[4];
886 if (event_log_size == 0)
887 goto exit_get_event_log;
888
889 /* Alloc Memory for Crash Record. */
890 event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
891 &event_log_dma, GFP_KERNEL);
892 if (event_log == NULL)
893 goto exit_get_event_log;
894
895 /* Get Crash Record. */
896 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
897 memset(&mbox_sts, 0, sizeof(mbox_cmd));
898
899 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
900 mbox_cmd[2] = LSDW(event_log_dma);
901 mbox_cmd[3] = MSDW(event_log_dma);
902
903 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
904 QLA_SUCCESS) {
905 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
906 "log!\n", ha->host_no, __func__));
907 goto exit_get_event_log;
908 }
909
910 /* Dump Event Log. */
911 num_valid_entries = mbox_sts[1];
912
913 max_event_log_entries = event_log_size /
914 sizeof(struct conn_event_log_entry);
915
916 if (num_valid_entries > max_event_log_entries)
917 oldest_entry = num_valid_entries % max_event_log_entries;
918
919 DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
920 ha->host_no, num_valid_entries));
921
922 if (ql4xextended_error_logging == 3) {
923 if (oldest_entry == 0) {
924 /* Circular Buffer has not wrapped around */
925 for (i=0; i < num_valid_entries; i++) {
926 qla4xxx_dump_buffer((uint8_t *)event_log+
927 (i*sizeof(*event_log)),
928 sizeof(*event_log));
929 }
930 }
931 else {
932 /* Circular Buffer has wrapped around -
933 * display accordingly*/
934 for (i=oldest_entry; i < max_event_log_entries; i++) {
935 qla4xxx_dump_buffer((uint8_t *)event_log+
936 (i*sizeof(*event_log)),
937 sizeof(*event_log));
938 }
939 for (i=0; i < oldest_entry; i++) {
940 qla4xxx_dump_buffer((uint8_t *)event_log+
941 (i*sizeof(*event_log)),
942 sizeof(*event_log));
943 }
944 }
945 }
946
947 exit_get_event_log:
948 if (event_log)
949 dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
950 event_log_dma);
951 }
952
953 /**
954 * qla4xxx_abort_task - issues Abort Task
955 * @ha: Pointer to host adapter structure.
956 * @srb: Pointer to srb entry
957 *
958 * This routine performs a LUN RESET on the specified target/lun.
959 * The caller must ensure that the ddb_entry and lun_entry pointers
960 * are valid before calling this routine.
961 **/
962 int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
963 {
964 uint32_t mbox_cmd[MBOX_REG_COUNT];
965 uint32_t mbox_sts[MBOX_REG_COUNT];
966 struct scsi_cmnd *cmd = srb->cmd;
967 int status = QLA_SUCCESS;
968 unsigned long flags = 0;
969 uint32_t index;
970
971 /*
972 * Send abort task command to ISP, so that the ISP will return
973 * request with ABORT status
974 */
975 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
976 memset(&mbox_sts, 0, sizeof(mbox_sts));
977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979 index = (unsigned long)(unsigned char *)cmd->host_scribble;
980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
981
982 /* Firmware already posted completion on response queue */
983 if (index == MAX_SRBS)
984 return status;
985
986 mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
987 mbox_cmd[1] = srb->ddb->fw_ddb_index;
988 mbox_cmd[2] = index;
989 /* Immediate Command Enable */
990 mbox_cmd[5] = 0x01;
991
992 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
993 &mbox_sts[0]);
994 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
995 status = QLA_ERROR;
996
997 DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
998 "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
999 ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1000 mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1001 }
1002
1003 return status;
1004 }
1005
1006 /**
1007 * qla4xxx_reset_lun - issues LUN Reset
1008 * @ha: Pointer to host adapter structure.
1009 * @ddb_entry: Pointer to device database entry
1010 * @lun: lun number
1011 *
1012 * This routine performs a LUN RESET on the specified target/lun.
1013 * The caller must ensure that the ddb_entry and lun_entry pointers
1014 * are valid before calling this routine.
1015 **/
1016 int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1017 int lun)
1018 {
1019 uint32_t mbox_cmd[MBOX_REG_COUNT];
1020 uint32_t mbox_sts[MBOX_REG_COUNT];
1021 int status = QLA_SUCCESS;
1022
1023 DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
1024 ddb_entry->fw_ddb_index, lun));
1025
1026 /*
1027 * Send lun reset command to ISP, so that the ISP will return all
1028 * outstanding requests with RESET status
1029 */
1030 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1031 memset(&mbox_sts, 0, sizeof(mbox_sts));
1032
1033 mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1034 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1035 mbox_cmd[2] = lun << 8;
1036 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1037
1038 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
1039 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1040 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1041 status = QLA_ERROR;
1042
1043 return status;
1044 }
1045
1046 /**
1047 * qla4xxx_reset_target - issues target Reset
1048 * @ha: Pointer to host adapter structure.
1049 * @db_entry: Pointer to device database entry
1050 * @un_entry: Pointer to lun entry structure
1051 *
1052 * This routine performs a TARGET RESET on the specified target.
1053 * The caller must ensure that the ddb_entry pointers
1054 * are valid before calling this routine.
1055 **/
1056 int qla4xxx_reset_target(struct scsi_qla_host *ha,
1057 struct ddb_entry *ddb_entry)
1058 {
1059 uint32_t mbox_cmd[MBOX_REG_COUNT];
1060 uint32_t mbox_sts[MBOX_REG_COUNT];
1061 int status = QLA_SUCCESS;
1062
1063 DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
1064 ddb_entry->fw_ddb_index));
1065
1066 /*
1067 * Send target reset command to ISP, so that the ISP will return all
1068 * outstanding requests with RESET status
1069 */
1070 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1071 memset(&mbox_sts, 0, sizeof(mbox_sts));
1072
1073 mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1074 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1075 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1076
1077 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1078 &mbox_sts[0]);
1079 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1080 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1081 status = QLA_ERROR;
1082
1083 return status;
1084 }
1085
1086 int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1087 uint32_t offset, uint32_t len)
1088 {
1089 uint32_t mbox_cmd[MBOX_REG_COUNT];
1090 uint32_t mbox_sts[MBOX_REG_COUNT];
1091
1092 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1093 memset(&mbox_sts, 0, sizeof(mbox_sts));
1094
1095 mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1096 mbox_cmd[1] = LSDW(dma_addr);
1097 mbox_cmd[2] = MSDW(dma_addr);
1098 mbox_cmd[3] = offset;
1099 mbox_cmd[4] = len;
1100
1101 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
1102 QLA_SUCCESS) {
1103 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1104 "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1105 __func__, mbox_sts[0], mbox_sts[1], offset, len));
1106 return QLA_ERROR;
1107 }
1108 return QLA_SUCCESS;
1109 }
1110
1111 /**
1112 * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
1113 * @ha: Pointer to host adapter structure.
1114 *
1115 * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1116 * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1117 * those mailboxes, if unused.
1118 **/
1119 int qla4xxx_about_firmware(struct scsi_qla_host *ha)
1120 {
1121 struct about_fw_info *about_fw = NULL;
1122 dma_addr_t about_fw_dma;
1123 uint32_t mbox_cmd[MBOX_REG_COUNT];
1124 uint32_t mbox_sts[MBOX_REG_COUNT];
1125 int status = QLA_ERROR;
1126
1127 about_fw = dma_alloc_coherent(&ha->pdev->dev,
1128 sizeof(struct about_fw_info),
1129 &about_fw_dma, GFP_KERNEL);
1130 if (!about_fw) {
1131 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1132 "for about_fw\n", __func__));
1133 return status;
1134 }
1135
1136 memset(about_fw, 0, sizeof(struct about_fw_info));
1137 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1138 memset(&mbox_sts, 0, sizeof(mbox_sts));
1139
1140 mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
1141 mbox_cmd[2] = LSDW(about_fw_dma);
1142 mbox_cmd[3] = MSDW(about_fw_dma);
1143 mbox_cmd[4] = sizeof(struct about_fw_info);
1144
1145 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1146 &mbox_cmd[0], &mbox_sts[0]);
1147 if (status != QLA_SUCCESS) {
1148 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1149 "failed w/ status %04X\n", __func__,
1150 mbox_sts[0]));
1151 goto exit_about_fw;
1152 }
1153
1154 /* Save version information. */
1155 ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
1156 ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
1157 ha->patch_number = le16_to_cpu(about_fw->fw_patch);
1158 ha->build_number = le16_to_cpu(about_fw->fw_build);
1159 ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1160 ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1161 ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
1162 ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1163 ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1164 ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
1165 status = QLA_SUCCESS;
1166
1167 exit_about_fw:
1168 dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
1169 about_fw, about_fw_dma);
1170 return status;
1171 }
1172
1173 static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
1174 dma_addr_t dma_addr)
1175 {
1176 uint32_t mbox_cmd[MBOX_REG_COUNT];
1177 uint32_t mbox_sts[MBOX_REG_COUNT];
1178
1179 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1180 memset(&mbox_sts, 0, sizeof(mbox_sts));
1181
1182 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
1183 mbox_cmd[1] = options;
1184 mbox_cmd[2] = LSDW(dma_addr);
1185 mbox_cmd[3] = MSDW(dma_addr);
1186
1187 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
1188 QLA_SUCCESS) {
1189 DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1190 ha->host_no, __func__, mbox_sts[0]));
1191 return QLA_ERROR;
1192 }
1193 return QLA_SUCCESS;
1194 }
1195
1196 int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1197 uint32_t *mbx_sts)
1198 {
1199 int status;
1200 uint32_t mbox_cmd[MBOX_REG_COUNT];
1201 uint32_t mbox_sts[MBOX_REG_COUNT];
1202
1203 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1204 memset(&mbox_sts, 0, sizeof(mbox_sts));
1205
1206 mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
1207 mbox_cmd[1] = ddb_index;
1208
1209 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1210 &mbox_sts[0]);
1211 if (status != QLA_SUCCESS) {
1212 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1213 __func__, mbox_sts[0]));
1214 }
1215
1216 *mbx_sts = mbox_sts[0];
1217 return status;
1218 }
1219
1220 int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1221 {
1222 int status;
1223 uint32_t mbox_cmd[MBOX_REG_COUNT];
1224 uint32_t mbox_sts[MBOX_REG_COUNT];
1225
1226 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1227 memset(&mbox_sts, 0, sizeof(mbox_sts));
1228
1229 mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1230 mbox_cmd[1] = ddb_index;
1231
1232 status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
1233 &mbox_sts[0]);
1234 if (status != QLA_SUCCESS) {
1235 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1236 __func__, mbox_sts[0]));
1237 }
1238
1239 return status;
1240 }
1241
1242 int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1243 uint32_t offset, uint32_t length, uint32_t options)
1244 {
1245 uint32_t mbox_cmd[MBOX_REG_COUNT];
1246 uint32_t mbox_sts[MBOX_REG_COUNT];
1247 int status = QLA_SUCCESS;
1248
1249 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1250 memset(&mbox_sts, 0, sizeof(mbox_sts));
1251
1252 mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1253 mbox_cmd[1] = LSDW(dma_addr);
1254 mbox_cmd[2] = MSDW(dma_addr);
1255 mbox_cmd[3] = offset;
1256 mbox_cmd[4] = length;
1257 mbox_cmd[5] = options;
1258
1259 status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
1260 if (status != QLA_SUCCESS) {
1261 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1262 "failed w/ status %04X, mbx1 %04X\n",
1263 __func__, mbox_sts[0], mbox_sts[1]));
1264 }
1265 return status;
1266 }
1267
1268 int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1269 struct dev_db_entry *fw_ddb_entry,
1270 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1271 {
1272 uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1273 uint32_t dev_db_end_offset;
1274 int status = QLA_ERROR;
1275
1276 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1277
1278 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1279 dev_db_end_offset = FLASH_OFFSET_DB_END;
1280
1281 if (dev_db_start_offset > dev_db_end_offset) {
1282 DEBUG2(ql4_printk(KERN_ERR, ha,
1283 "%s:Invalid DDB index %d", __func__,
1284 ddb_index));
1285 goto exit_bootdb_failed;
1286 }
1287
1288 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1289 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1290 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1291 "failed\n", ha->host_no, __func__);
1292 goto exit_bootdb_failed;
1293 }
1294
1295 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1296 status = QLA_SUCCESS;
1297
1298 exit_bootdb_failed:
1299 return status;
1300 }
1301
1302 int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1303 uint16_t idx)
1304 {
1305 int ret = 0;
1306 int rval = QLA_ERROR;
1307 uint32_t offset = 0, chap_size;
1308 struct ql4_chap_table *chap_table;
1309 dma_addr_t chap_dma;
1310
1311 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1312 if (chap_table == NULL) {
1313 ret = -ENOMEM;
1314 goto exit_get_chap;
1315 }
1316
1317 chap_size = sizeof(struct ql4_chap_table);
1318 memset(chap_table, 0, chap_size);
1319
1320 if (is_qla40XX(ha))
1321 offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1322 else {
1323 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1324 /* flt_chap_size is CHAP table size for both ports
1325 * so divide it by 2 to calculate the offset for second port
1326 */
1327 if (ha->port_num == 1)
1328 offset += (ha->hw.flt_chap_size / 2);
1329 offset += (idx * chap_size);
1330 }
1331
1332 rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
1333 if (rval != QLA_SUCCESS) {
1334 ret = -EINVAL;
1335 goto exit_get_chap;
1336 }
1337
1338 DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1339 __le16_to_cpu(chap_table->cookie)));
1340
1341 if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1342 ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1343 goto exit_get_chap;
1344 }
1345
1346 strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1347 strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1348 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1349
1350 exit_get_chap:
1351 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1352 return ret;
1353 }
1354
1355 static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
1356 char *password, uint16_t idx, int bidi)
1357 {
1358 int ret = 0;
1359 int rval = QLA_ERROR;
1360 uint32_t offset = 0;
1361 struct ql4_chap_table *chap_table;
1362 dma_addr_t chap_dma;
1363
1364 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1365 if (chap_table == NULL) {
1366 ret = -ENOMEM;
1367 goto exit_set_chap;
1368 }
1369
1370 memset(chap_table, 0, sizeof(struct ql4_chap_table));
1371 if (bidi)
1372 chap_table->flags |= BIT_6; /* peer */
1373 else
1374 chap_table->flags |= BIT_7; /* local */
1375 chap_table->secret_len = strlen(password);
1376 strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
1377 strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
1378 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1379 offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
1380 rval = qla4xxx_set_flash(ha, chap_dma, offset,
1381 sizeof(struct ql4_chap_table),
1382 FLASH_OPT_RMW_COMMIT);
1383
1384 if (rval == QLA_SUCCESS && ha->chap_list) {
1385 /* Update ha chap_list cache */
1386 memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1387 chap_table, sizeof(struct ql4_chap_table));
1388 }
1389 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1390 if (rval != QLA_SUCCESS)
1391 ret = -EINVAL;
1392
1393 exit_set_chap:
1394 return ret;
1395 }
1396
1397 /**
1398 * qla4xxx_get_chap_index - Get chap index given username and secret
1399 * @ha: pointer to adapter structure
1400 * @username: CHAP username to be searched
1401 * @password: CHAP password to be searched
1402 * @bidi: Is this a BIDI CHAP
1403 * @chap_index: CHAP index to be returned
1404 *
1405 * Match the username and password in the chap_list, return the index if a
1406 * match is found. If a match is not found then add the entry in FLASH and
1407 * return the index at which entry is written in the FLASH.
1408 **/
1409 static int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1410 char *password, int bidi, uint16_t *chap_index)
1411 {
1412 int i, rval;
1413 int free_index = -1;
1414 int found_index = 0;
1415 int max_chap_entries = 0;
1416 struct ql4_chap_table *chap_table;
1417
1418 if (is_qla8022(ha))
1419 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1420 sizeof(struct ql4_chap_table);
1421 else
1422 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1423
1424 if (!ha->chap_list) {
1425 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1426 return QLA_ERROR;
1427 }
1428
1429 mutex_lock(&ha->chap_sem);
1430 for (i = 0; i < max_chap_entries; i++) {
1431 chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1432 if (chap_table->cookie !=
1433 __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1434 if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1435 free_index = i;
1436 continue;
1437 }
1438 if (bidi) {
1439 if (chap_table->flags & BIT_7)
1440 continue;
1441 } else {
1442 if (chap_table->flags & BIT_6)
1443 continue;
1444 }
1445 if (!strncmp(chap_table->secret, password,
1446 MAX_CHAP_SECRET_LEN) &&
1447 !strncmp(chap_table->name, username,
1448 MAX_CHAP_NAME_LEN)) {
1449 *chap_index = i;
1450 found_index = 1;
1451 break;
1452 }
1453 }
1454
1455 /* If chap entry is not present and a free index is available then
1456 * write the entry in flash
1457 */
1458 if (!found_index && free_index != -1) {
1459 rval = qla4xxx_set_chap(ha, username, password,
1460 free_index, bidi);
1461 if (!rval) {
1462 *chap_index = free_index;
1463 found_index = 1;
1464 }
1465 }
1466
1467 mutex_unlock(&ha->chap_sem);
1468
1469 if (found_index)
1470 return QLA_SUCCESS;
1471 return QLA_ERROR;
1472 }
1473
1474 int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1475 uint16_t fw_ddb_index,
1476 uint16_t connection_id,
1477 uint16_t option)
1478 {
1479 uint32_t mbox_cmd[MBOX_REG_COUNT];
1480 uint32_t mbox_sts[MBOX_REG_COUNT];
1481 int status = QLA_SUCCESS;
1482
1483 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1484 memset(&mbox_sts, 0, sizeof(mbox_sts));
1485
1486 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1487 mbox_cmd[1] = fw_ddb_index;
1488 mbox_cmd[2] = connection_id;
1489 mbox_cmd[3] = option;
1490
1491 status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
1492 if (status != QLA_SUCCESS) {
1493 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1494 "option %04x failed w/ status %04X %04X\n",
1495 __func__, option, mbox_sts[0], mbox_sts[1]));
1496 }
1497 return status;
1498 }
1499
1500 int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1501 {
1502 uint32_t mbox_cmd[MBOX_REG_COUNT];
1503 uint32_t mbox_sts[MBOX_REG_COUNT];
1504 int status = QLA_SUCCESS;
1505
1506 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1507 memset(&mbox_sts, 0, sizeof(mbox_sts));
1508
1509 mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1510
1511 status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
1512 if (status != QLA_SUCCESS) {
1513 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1514 "failed w/ status %04X %04X %04X", __func__,
1515 mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1516 }
1517 return status;
1518 }
1519
1520 int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1521 uint32_t acb_type, uint32_t len)
1522 {
1523 uint32_t mbox_cmd[MBOX_REG_COUNT];
1524 uint32_t mbox_sts[MBOX_REG_COUNT];
1525 int status = QLA_SUCCESS;
1526
1527 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1528 memset(&mbox_sts, 0, sizeof(mbox_sts));
1529
1530 mbox_cmd[0] = MBOX_CMD_GET_ACB;
1531 mbox_cmd[1] = acb_type;
1532 mbox_cmd[2] = LSDW(acb_dma);
1533 mbox_cmd[3] = MSDW(acb_dma);
1534 mbox_cmd[4] = len;
1535
1536 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1537 if (status != QLA_SUCCESS) {
1538 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1539 "failed w/ status %04X\n", __func__,
1540 mbox_sts[0]));
1541 }
1542 return status;
1543 }
1544
1545 int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1546 uint32_t *mbox_sts, dma_addr_t acb_dma)
1547 {
1548 int status = QLA_SUCCESS;
1549
1550 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1551 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1552 mbox_cmd[0] = MBOX_CMD_SET_ACB;
1553 mbox_cmd[1] = 0; /* Primary ACB */
1554 mbox_cmd[2] = LSDW(acb_dma);
1555 mbox_cmd[3] = MSDW(acb_dma);
1556 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1557
1558 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1559 if (status != QLA_SUCCESS) {
1560 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1561 "failed w/ status %04X\n", __func__,
1562 mbox_sts[0]));
1563 }
1564 return status;
1565 }
1566
1567 int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1568 struct ddb_entry *ddb_entry,
1569 struct iscsi_cls_conn *cls_conn,
1570 uint32_t *mbx_sts)
1571 {
1572 struct dev_db_entry *fw_ddb_entry;
1573 struct iscsi_conn *conn;
1574 struct iscsi_session *sess;
1575 struct qla_conn *qla_conn;
1576 struct sockaddr *dst_addr;
1577 dma_addr_t fw_ddb_entry_dma;
1578 int status = QLA_SUCCESS;
1579 int rval = 0;
1580 struct sockaddr_in *addr;
1581 struct sockaddr_in6 *addr6;
1582 char *ip;
1583 uint16_t iscsi_opts = 0;
1584 uint32_t options = 0;
1585 uint16_t idx;
1586
1587 fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1588 &fw_ddb_entry_dma, GFP_KERNEL);
1589 if (!fw_ddb_entry) {
1590 DEBUG2(ql4_printk(KERN_ERR, ha,
1591 "%s: Unable to allocate dma buffer.\n",
1592 __func__));
1593 rval = -ENOMEM;
1594 goto exit_set_param_no_free;
1595 }
1596
1597 conn = cls_conn->dd_data;
1598 qla_conn = conn->dd_data;
1599 sess = conn->session;
1600 dst_addr = &qla_conn->qla_ep->dst_addr;
1601
1602 if (dst_addr->sa_family == AF_INET6)
1603 options |= IPV6_DEFAULT_DDB_ENTRY;
1604
1605 status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
1606 if (status == QLA_ERROR) {
1607 rval = -EINVAL;
1608 goto exit_set_param;
1609 }
1610
1611 iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
1612 memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
1613
1614 memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
1615
1616 if (sess->targetname != NULL) {
1617 memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
1618 min(strlen(sess->targetname),
1619 sizeof(fw_ddb_entry->iscsi_name)));
1620 }
1621
1622 memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
1623 memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
1624
1625 fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
1626
1627 if (dst_addr->sa_family == AF_INET) {
1628 addr = (struct sockaddr_in *)dst_addr;
1629 ip = (char *)&addr->sin_addr;
1630 memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
1631 fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
1632 DEBUG2(ql4_printk(KERN_INFO, ha,
1633 "%s: Destination Address [%pI4]: index [%d]\n",
1634 __func__, fw_ddb_entry->ip_addr,
1635 ddb_entry->fw_ddb_index));
1636 } else if (dst_addr->sa_family == AF_INET6) {
1637 addr6 = (struct sockaddr_in6 *)dst_addr;
1638 ip = (char *)&addr6->sin6_addr;
1639 memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
1640 fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
1641 fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
1642 DEBUG2(ql4_printk(KERN_INFO, ha,
1643 "%s: Destination Address [%pI6]: index [%d]\n",
1644 __func__, fw_ddb_entry->ip_addr,
1645 ddb_entry->fw_ddb_index));
1646 } else {
1647 ql4_printk(KERN_ERR, ha,
1648 "%s: Failed to get IP Address\n",
1649 __func__);
1650 rval = -EINVAL;
1651 goto exit_set_param;
1652 }
1653
1654 /* CHAP */
1655 if (sess->username != NULL && sess->password != NULL) {
1656 if (strlen(sess->username) && strlen(sess->password)) {
1657 iscsi_opts |= BIT_7;
1658
1659 rval = qla4xxx_get_chap_index(ha, sess->username,
1660 sess->password,
1661 LOCAL_CHAP, &idx);
1662 if (rval)
1663 goto exit_set_param;
1664
1665 fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
1666 }
1667 }
1668
1669 if (sess->username_in != NULL && sess->password_in != NULL) {
1670 /* Check if BIDI CHAP */
1671 if (strlen(sess->username_in) && strlen(sess->password_in)) {
1672 iscsi_opts |= BIT_4;
1673
1674 rval = qla4xxx_get_chap_index(ha, sess->username_in,
1675 sess->password_in,
1676 BIDI_CHAP, &idx);
1677 if (rval)
1678 goto exit_set_param;
1679 }
1680 }
1681
1682 if (sess->initial_r2t_en)
1683 iscsi_opts |= BIT_10;
1684
1685 if (sess->imm_data_en)
1686 iscsi_opts |= BIT_11;
1687
1688 fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
1689
1690 if (conn->max_recv_dlength)
1691 fw_ddb_entry->iscsi_max_rcv_data_seg_len =
1692 __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
1693
1694 if (sess->max_r2t)
1695 fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
1696
1697 if (sess->first_burst)
1698 fw_ddb_entry->iscsi_first_burst_len =
1699 __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
1700
1701 if (sess->max_burst)
1702 fw_ddb_entry->iscsi_max_burst_len =
1703 __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
1704
1705 if (sess->time2wait)
1706 fw_ddb_entry->iscsi_def_time2wait =
1707 cpu_to_le16(sess->time2wait);
1708
1709 if (sess->time2retain)
1710 fw_ddb_entry->iscsi_def_time2retain =
1711 cpu_to_le16(sess->time2retain);
1712
1713 status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
1714 fw_ddb_entry_dma, mbx_sts);
1715
1716 if (status != QLA_SUCCESS)
1717 rval = -EINVAL;
1718 exit_set_param:
1719 dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1720 fw_ddb_entry, fw_ddb_entry_dma);
1721 exit_set_param_no_free:
1722 return rval;
1723 }
1724
1725 int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
1726 uint16_t stats_size, dma_addr_t stats_dma)
1727 {
1728 int status = QLA_SUCCESS;
1729 uint32_t mbox_cmd[MBOX_REG_COUNT];
1730 uint32_t mbox_sts[MBOX_REG_COUNT];
1731
1732 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1733 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1734 mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
1735 mbox_cmd[1] = fw_ddb_index;
1736 mbox_cmd[2] = LSDW(stats_dma);
1737 mbox_cmd[3] = MSDW(stats_dma);
1738 mbox_cmd[4] = stats_size;
1739
1740 status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
1741 if (status != QLA_SUCCESS) {
1742 DEBUG2(ql4_printk(KERN_WARNING, ha,
1743 "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
1744 "failed w/ status %04X\n", __func__,
1745 mbox_sts[0]));
1746 }
1747 return status;
1748 }
1749
1750 int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
1751 uint32_t ip_idx, uint32_t *sts)
1752 {
1753 uint32_t mbox_cmd[MBOX_REG_COUNT];
1754 uint32_t mbox_sts[MBOX_REG_COUNT];
1755 int status = QLA_SUCCESS;
1756
1757 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1758 memset(&mbox_sts, 0, sizeof(mbox_sts));
1759 mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
1760 mbox_cmd[1] = acb_idx;
1761 mbox_cmd[2] = ip_idx;
1762
1763 status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
1764 if (status != QLA_SUCCESS) {
1765 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
1766 "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
1767 "status %04X\n", __func__, mbox_sts[0]));
1768 }
1769 memcpy(sts, mbox_sts, sizeof(mbox_sts));
1770 return status;
1771 }
1772
1773 int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1774 uint32_t offset, uint32_t size)
1775 {
1776 int status = QLA_SUCCESS;
1777 uint32_t mbox_cmd[MBOX_REG_COUNT];
1778 uint32_t mbox_sts[MBOX_REG_COUNT];
1779
1780 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1781 memset(&mbox_sts, 0, sizeof(mbox_sts));
1782
1783 mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
1784 mbox_cmd[1] = LSDW(nvram_dma);
1785 mbox_cmd[2] = MSDW(nvram_dma);
1786 mbox_cmd[3] = offset;
1787 mbox_cmd[4] = size;
1788
1789 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1790 &mbox_sts[0]);
1791 if (status != QLA_SUCCESS) {
1792 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1793 "status %04X\n", ha->host_no, __func__,
1794 mbox_sts[0]));
1795 }
1796 return status;
1797 }
1798
1799 int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1800 uint32_t offset, uint32_t size)
1801 {
1802 int status = QLA_SUCCESS;
1803 uint32_t mbox_cmd[MBOX_REG_COUNT];
1804 uint32_t mbox_sts[MBOX_REG_COUNT];
1805
1806 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1807 memset(&mbox_sts, 0, sizeof(mbox_sts));
1808
1809 mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
1810 mbox_cmd[1] = LSDW(nvram_dma);
1811 mbox_cmd[2] = MSDW(nvram_dma);
1812 mbox_cmd[3] = offset;
1813 mbox_cmd[4] = size;
1814
1815 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1816 &mbox_sts[0]);
1817 if (status != QLA_SUCCESS) {
1818 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1819 "status %04X\n", ha->host_no, __func__,
1820 mbox_sts[0]));
1821 }
1822 return status;
1823 }
1824
1825 int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
1826 uint32_t region, uint32_t field0,
1827 uint32_t field1)
1828 {
1829 int status = QLA_SUCCESS;
1830 uint32_t mbox_cmd[MBOX_REG_COUNT];
1831 uint32_t mbox_sts[MBOX_REG_COUNT];
1832
1833 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1834 memset(&mbox_sts, 0, sizeof(mbox_sts));
1835
1836 mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
1837 mbox_cmd[3] = region;
1838 mbox_cmd[4] = field0;
1839 mbox_cmd[5] = field1;
1840
1841 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
1842 &mbox_sts[0]);
1843 if (status != QLA_SUCCESS) {
1844 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1845 "status %04X\n", ha->host_no, __func__,
1846 mbox_sts[0]));
1847 }
1848 return status;
1849 }
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