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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / tty / serial / 8250.c
bloba87a56cb5417b0f0804e532c5a260ab81b2329ea
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69 /*
70 * Debugging.
71 */
72 #if 0
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #else
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 #endif
77
78 #if 0
79 #define DEBUG_INTR(fmt...) printk(fmt)
80 #else
81 #define DEBUG_INTR(fmt...) do { } while (0)
82 #endif
83
84 #define PASS_LIMIT 512
85
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89 /*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94 #define is_real_interrupt(irq) ((irq) != 0)
95
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
98 #endif
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102
103 /*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107 #define CONFIG_HUB6 1
108
109 #include <asm/serial.h>
110 /*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125 #ifdef CONFIG_SERIAL_8250_RSA
126
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
131
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
312 [PORT_XR17D15X] = {
313 .name = "XR17D15X",
314 .fifo_size = 64,
315 .tx_loadsz = 64,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
318 },
319 };
320
321 #if defined(CONFIG_MIPS_ALCHEMY)
322
323 /* Au1x00 UART hardware has a weird register layout */
324 static const u8 au_io_in_map[] = {
325 [UART_RX] = 0,
326 [UART_IER] = 2,
327 [UART_IIR] = 3,
328 [UART_LCR] = 5,
329 [UART_MCR] = 6,
330 [UART_LSR] = 7,
331 [UART_MSR] = 8,
332 };
333
334 static const u8 au_io_out_map[] = {
335 [UART_TX] = 1,
336 [UART_IER] = 2,
337 [UART_FCR] = 4,
338 [UART_LCR] = 5,
339 [UART_MCR] = 6,
340 };
341
342 /* sane hardware needs no mapping */
343 static inline int map_8250_in_reg(struct uart_port *p, int offset)
344 {
345 if (p->iotype != UPIO_AU)
346 return offset;
347 return au_io_in_map[offset];
348 }
349
350 static inline int map_8250_out_reg(struct uart_port *p, int offset)
351 {
352 if (p->iotype != UPIO_AU)
353 return offset;
354 return au_io_out_map[offset];
355 }
356
357 #elif defined(CONFIG_SERIAL_8250_RM9K)
358
359 static const u8
360 regmap_in[8] = {
361 [UART_RX] = 0x00,
362 [UART_IER] = 0x0c,
363 [UART_IIR] = 0x14,
364 [UART_LCR] = 0x1c,
365 [UART_MCR] = 0x20,
366 [UART_LSR] = 0x24,
367 [UART_MSR] = 0x28,
368 [UART_SCR] = 0x2c
369 },
370 regmap_out[8] = {
371 [UART_TX] = 0x04,
372 [UART_IER] = 0x0c,
373 [UART_FCR] = 0x18,
374 [UART_LCR] = 0x1c,
375 [UART_MCR] = 0x20,
376 [UART_LSR] = 0x24,
377 [UART_MSR] = 0x28,
378 [UART_SCR] = 0x2c
379 };
380
381 static inline int map_8250_in_reg(struct uart_port *p, int offset)
382 {
383 if (p->iotype != UPIO_RM9000)
384 return offset;
385 return regmap_in[offset];
386 }
387
388 static inline int map_8250_out_reg(struct uart_port *p, int offset)
389 {
390 if (p->iotype != UPIO_RM9000)
391 return offset;
392 return regmap_out[offset];
393 }
394
395 #else
396
397 /* sane hardware needs no mapping */
398 #define map_8250_in_reg(up, offset) (offset)
399 #define map_8250_out_reg(up, offset) (offset)
400
401 #endif
402
403 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
404 {
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 return inb(p->iobase + 1);
408 }
409
410 static void hub6_serial_out(struct uart_port *p, int offset, int value)
411 {
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 outb(value, p->iobase + 1);
415 }
416
417 static unsigned int mem_serial_in(struct uart_port *p, int offset)
418 {
419 offset = map_8250_in_reg(p, offset) << p->regshift;
420 return readb(p->membase + offset);
421 }
422
423 static void mem_serial_out(struct uart_port *p, int offset, int value)
424 {
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 writeb(value, p->membase + offset);
427 }
428
429 static void mem32_serial_out(struct uart_port *p, int offset, int value)
430 {
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 writel(value, p->membase + offset);
433 }
434
435 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
436 {
437 offset = map_8250_in_reg(p, offset) << p->regshift;
438 return readl(p->membase + offset);
439 }
440
441 static unsigned int au_serial_in(struct uart_port *p, int offset)
442 {
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 return __raw_readl(p->membase + offset);
445 }
446
447 static void au_serial_out(struct uart_port *p, int offset, int value)
448 {
449 offset = map_8250_out_reg(p, offset) << p->regshift;
450 __raw_writel(value, p->membase + offset);
451 }
452
453 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
454 {
455 unsigned int tmp;
456 offset = map_8250_in_reg(p, offset) << p->regshift;
457 if (offset == UART_IIR) {
458 tmp = readl(p->membase + (UART_IIR & ~3));
459 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
460 } else
461 return readb(p->membase + offset);
462 }
463
464 static void tsi_serial_out(struct uart_port *p, int offset, int value)
465 {
466 offset = map_8250_out_reg(p, offset) << p->regshift;
467 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
468 writeb(value, p->membase + offset);
469 }
470
471 static unsigned int io_serial_in(struct uart_port *p, int offset)
472 {
473 offset = map_8250_in_reg(p, offset) << p->regshift;
474 return inb(p->iobase + offset);
475 }
476
477 static void io_serial_out(struct uart_port *p, int offset, int value)
478 {
479 offset = map_8250_out_reg(p, offset) << p->regshift;
480 outb(value, p->iobase + offset);
481 }
482
483 static int serial8250_default_handle_irq(struct uart_port *port);
484
485 static void set_io_from_upio(struct uart_port *p)
486 {
487 struct uart_8250_port *up =
488 container_of(p, struct uart_8250_port, port);
489 switch (p->iotype) {
490 case UPIO_HUB6:
491 p->serial_in = hub6_serial_in;
492 p->serial_out = hub6_serial_out;
493 break;
494
495 case UPIO_MEM:
496 p->serial_in = mem_serial_in;
497 p->serial_out = mem_serial_out;
498 break;
499
500 case UPIO_RM9000:
501 case UPIO_MEM32:
502 p->serial_in = mem32_serial_in;
503 p->serial_out = mem32_serial_out;
504 break;
505
506 case UPIO_AU:
507 p->serial_in = au_serial_in;
508 p->serial_out = au_serial_out;
509 break;
510
511 case UPIO_TSI:
512 p->serial_in = tsi_serial_in;
513 p->serial_out = tsi_serial_out;
514 break;
515
516 default:
517 p->serial_in = io_serial_in;
518 p->serial_out = io_serial_out;
519 break;
520 }
521 /* Remember loaded iotype */
522 up->cur_iotype = p->iotype;
523 p->handle_irq = serial8250_default_handle_irq;
524 }
525
526 static void
527 serial_out_sync(struct uart_8250_port *up, int offset, int value)
528 {
529 struct uart_port *p = &up->port;
530 switch (p->iotype) {
531 case UPIO_MEM:
532 case UPIO_MEM32:
533 case UPIO_AU:
534 p->serial_out(p, offset, value);
535 p->serial_in(p, UART_LCR); /* safe, no side-effects */
536 break;
537 default:
538 p->serial_out(p, offset, value);
539 }
540 }
541
542 #define serial_in(up, offset) \
543 (up->port.serial_in(&(up)->port, (offset)))
544 #define serial_out(up, offset, value) \
545 (up->port.serial_out(&(up)->port, (offset), (value)))
546 /*
547 * We used to support using pause I/O for certain machines. We
548 * haven't supported this for a while, but just in case it's badly
549 * needed for certain old 386 machines, I've left these #define's
550 * in....
551 */
552 #define serial_inp(up, offset) serial_in(up, offset)
553 #define serial_outp(up, offset, value) serial_out(up, offset, value)
554
555 /* Uart divisor latch read */
556 static inline int _serial_dl_read(struct uart_8250_port *up)
557 {
558 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
559 }
560
561 /* Uart divisor latch write */
562 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
563 {
564 serial_outp(up, UART_DLL, value & 0xff);
565 serial_outp(up, UART_DLM, value >> 8 & 0xff);
566 }
567
568 #if defined(CONFIG_MIPS_ALCHEMY)
569 /* Au1x00 haven't got a standard divisor latch */
570 static int serial_dl_read(struct uart_8250_port *up)
571 {
572 if (up->port.iotype == UPIO_AU)
573 return __raw_readl(up->port.membase + 0x28);
574 else
575 return _serial_dl_read(up);
576 }
577
578 static void serial_dl_write(struct uart_8250_port *up, int value)
579 {
580 if (up->port.iotype == UPIO_AU)
581 __raw_writel(value, up->port.membase + 0x28);
582 else
583 _serial_dl_write(up, value);
584 }
585 #elif defined(CONFIG_SERIAL_8250_RM9K)
586 static int serial_dl_read(struct uart_8250_port *up)
587 {
588 return (up->port.iotype == UPIO_RM9000) ?
589 (((__raw_readl(up->port.membase + 0x10) << 8) |
590 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
591 _serial_dl_read(up);
592 }
593
594 static void serial_dl_write(struct uart_8250_port *up, int value)
595 {
596 if (up->port.iotype == UPIO_RM9000) {
597 __raw_writel(value, up->port.membase + 0x08);
598 __raw_writel(value >> 8, up->port.membase + 0x10);
599 } else {
600 _serial_dl_write(up, value);
601 }
602 }
603 #else
604 #define serial_dl_read(up) _serial_dl_read(up)
605 #define serial_dl_write(up, value) _serial_dl_write(up, value)
606 #endif
607
608 /*
609 * For the 16C950
610 */
611 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
612 {
613 serial_out(up, UART_SCR, offset);
614 serial_out(up, UART_ICR, value);
615 }
616
617 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
618 {
619 unsigned int value;
620
621 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
622 serial_out(up, UART_SCR, offset);
623 value = serial_in(up, UART_ICR);
624 serial_icr_write(up, UART_ACR, up->acr);
625
626 return value;
627 }
628
629 /*
630 * FIFO support.
631 */
632 static void serial8250_clear_fifos(struct uart_8250_port *p)
633 {
634 if (p->capabilities & UART_CAP_FIFO) {
635 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
636 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
637 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
638 serial_outp(p, UART_FCR, 0);
639 }
640 }
641
642 /*
643 * IER sleep support. UARTs which have EFRs need the "extended
644 * capability" bit enabled. Note that on XR16C850s, we need to
645 * reset LCR to write to IER.
646 */
647 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
648 {
649 if (p->capabilities & UART_CAP_SLEEP) {
650 if (p->capabilities & UART_CAP_EFR) {
651 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
652 serial_outp(p, UART_EFR, UART_EFR_ECB);
653 serial_outp(p, UART_LCR, 0);
654 }
655 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
656 if (p->capabilities & UART_CAP_EFR) {
657 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
658 serial_outp(p, UART_EFR, 0);
659 serial_outp(p, UART_LCR, 0);
660 }
661 }
662 }
663
664 #ifdef CONFIG_SERIAL_8250_RSA
665 /*
666 * Attempts to turn on the RSA FIFO. Returns zero on failure.
667 * We set the port uart clock rate if we succeed.
668 */
669 static int __enable_rsa(struct uart_8250_port *up)
670 {
671 unsigned char mode;
672 int result;
673
674 mode = serial_inp(up, UART_RSA_MSR);
675 result = mode & UART_RSA_MSR_FIFO;
676
677 if (!result) {
678 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
679 mode = serial_inp(up, UART_RSA_MSR);
680 result = mode & UART_RSA_MSR_FIFO;
681 }
682
683 if (result)
684 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
685
686 return result;
687 }
688
689 static void enable_rsa(struct uart_8250_port *up)
690 {
691 if (up->port.type == PORT_RSA) {
692 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
693 spin_lock_irq(&up->port.lock);
694 __enable_rsa(up);
695 spin_unlock_irq(&up->port.lock);
696 }
697 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
698 serial_outp(up, UART_RSA_FRR, 0);
699 }
700 }
701
702 /*
703 * Attempts to turn off the RSA FIFO. Returns zero on failure.
704 * It is unknown why interrupts were disabled in here. However,
705 * the caller is expected to preserve this behaviour by grabbing
706 * the spinlock before calling this function.
707 */
708 static void disable_rsa(struct uart_8250_port *up)
709 {
710 unsigned char mode;
711 int result;
712
713 if (up->port.type == PORT_RSA &&
714 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
715 spin_lock_irq(&up->port.lock);
716
717 mode = serial_inp(up, UART_RSA_MSR);
718 result = !(mode & UART_RSA_MSR_FIFO);
719
720 if (!result) {
721 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
722 mode = serial_inp(up, UART_RSA_MSR);
723 result = !(mode & UART_RSA_MSR_FIFO);
724 }
725
726 if (result)
727 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
728 spin_unlock_irq(&up->port.lock);
729 }
730 }
731 #endif /* CONFIG_SERIAL_8250_RSA */
732
733 /*
734 * This is a quickie test to see how big the FIFO is.
735 * It doesn't work at all the time, more's the pity.
736 */
737 static int size_fifo(struct uart_8250_port *up)
738 {
739 unsigned char old_fcr, old_mcr, old_lcr;
740 unsigned short old_dl;
741 int count;
742
743 old_lcr = serial_inp(up, UART_LCR);
744 serial_outp(up, UART_LCR, 0);
745 old_fcr = serial_inp(up, UART_FCR);
746 old_mcr = serial_inp(up, UART_MCR);
747 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
748 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
749 serial_outp(up, UART_MCR, UART_MCR_LOOP);
750 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
751 old_dl = serial_dl_read(up);
752 serial_dl_write(up, 0x0001);
753 serial_outp(up, UART_LCR, 0x03);
754 for (count = 0; count < 256; count++)
755 serial_outp(up, UART_TX, count);
756 mdelay(20);/* FIXME - schedule_timeout */
757 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
758 (count < 256); count++)
759 serial_inp(up, UART_RX);
760 serial_outp(up, UART_FCR, old_fcr);
761 serial_outp(up, UART_MCR, old_mcr);
762 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
763 serial_dl_write(up, old_dl);
764 serial_outp(up, UART_LCR, old_lcr);
765
766 return count;
767 }
768
769 /*
770 * Read UART ID using the divisor method - set DLL and DLM to zero
771 * and the revision will be in DLL and device type in DLM. We
772 * preserve the device state across this.
773 */
774 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
775 {
776 unsigned char old_dll, old_dlm, old_lcr;
777 unsigned int id;
778
779 old_lcr = serial_inp(p, UART_LCR);
780 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
781
782 old_dll = serial_inp(p, UART_DLL);
783 old_dlm = serial_inp(p, UART_DLM);
784
785 serial_outp(p, UART_DLL, 0);
786 serial_outp(p, UART_DLM, 0);
787
788 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
789
790 serial_outp(p, UART_DLL, old_dll);
791 serial_outp(p, UART_DLM, old_dlm);
792 serial_outp(p, UART_LCR, old_lcr);
793
794 return id;
795 }
796
797 /*
798 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
799 * When this function is called we know it is at least a StarTech
800 * 16650 V2, but it might be one of several StarTech UARTs, or one of
801 * its clones. (We treat the broken original StarTech 16650 V1 as a
802 * 16550, and why not? Startech doesn't seem to even acknowledge its
803 * existence.)
804 *
805 * What evil have men's minds wrought...
806 */
807 static void autoconfig_has_efr(struct uart_8250_port *up)
808 {
809 unsigned int id1, id2, id3, rev;
810
811 /*
812 * Everything with an EFR has SLEEP
813 */
814 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
815
816 /*
817 * First we check to see if it's an Oxford Semiconductor UART.
818 *
819 * If we have to do this here because some non-National
820 * Semiconductor clone chips lock up if you try writing to the
821 * LSR register (which serial_icr_read does)
822 */
823
824 /*
825 * Check for Oxford Semiconductor 16C950.
826 *
827 * EFR [4] must be set else this test fails.
828 *
829 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
830 * claims that it's needed for 952 dual UART's (which are not
831 * recommended for new designs).
832 */
833 up->acr = 0;
834 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
835 serial_out(up, UART_EFR, UART_EFR_ECB);
836 serial_out(up, UART_LCR, 0x00);
837 id1 = serial_icr_read(up, UART_ID1);
838 id2 = serial_icr_read(up, UART_ID2);
839 id3 = serial_icr_read(up, UART_ID3);
840 rev = serial_icr_read(up, UART_REV);
841
842 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
843
844 if (id1 == 0x16 && id2 == 0xC9 &&
845 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
846 up->port.type = PORT_16C950;
847
848 /*
849 * Enable work around for the Oxford Semiconductor 952 rev B
850 * chip which causes it to seriously miscalculate baud rates
851 * when DLL is 0.
852 */
853 if (id3 == 0x52 && rev == 0x01)
854 up->bugs |= UART_BUG_QUOT;
855 return;
856 }
857
858 /*
859 * We check for a XR16C850 by setting DLL and DLM to 0, and then
860 * reading back DLL and DLM. The chip type depends on the DLM
861 * value read back:
862 * 0x10 - XR16C850 and the DLL contains the chip revision.
863 * 0x12 - XR16C2850.
864 * 0x14 - XR16C854.
865 */
866 id1 = autoconfig_read_divisor_id(up);
867 DEBUG_AUTOCONF("850id=%04x ", id1);
868
869 id2 = id1 >> 8;
870 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
871 up->port.type = PORT_16850;
872 return;
873 }
874
875 /*
876 * It wasn't an XR16C850.
877 *
878 * We distinguish between the '654 and the '650 by counting
879 * how many bytes are in the FIFO. I'm using this for now,
880 * since that's the technique that was sent to me in the
881 * serial driver update, but I'm not convinced this works.
882 * I've had problems doing this in the past. -TYT
883 */
884 if (size_fifo(up) == 64)
885 up->port.type = PORT_16654;
886 else
887 up->port.type = PORT_16650V2;
888 }
889
890 /*
891 * We detected a chip without a FIFO. Only two fall into
892 * this category - the original 8250 and the 16450. The
893 * 16450 has a scratch register (accessible with LCR=0)
894 */
895 static void autoconfig_8250(struct uart_8250_port *up)
896 {
897 unsigned char scratch, status1, status2;
898
899 up->port.type = PORT_8250;
900
901 scratch = serial_in(up, UART_SCR);
902 serial_outp(up, UART_SCR, 0xa5);
903 status1 = serial_in(up, UART_SCR);
904 serial_outp(up, UART_SCR, 0x5a);
905 status2 = serial_in(up, UART_SCR);
906 serial_outp(up, UART_SCR, scratch);
907
908 if (status1 == 0xa5 && status2 == 0x5a)
909 up->port.type = PORT_16450;
910 }
911
912 static int broken_efr(struct uart_8250_port *up)
913 {
914 /*
915 * Exar ST16C2550 "A2" devices incorrectly detect as
916 * having an EFR, and report an ID of 0x0201. See
917 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
918 */
919 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
920 return 1;
921
922 return 0;
923 }
924
925 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
926 {
927 unsigned char status;
928
929 status = serial_in(up, 0x04); /* EXCR2 */
930 #define PRESL(x) ((x) & 0x30)
931 if (PRESL(status) == 0x10) {
932 /* already in high speed mode */
933 return 0;
934 } else {
935 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
936 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
937 serial_outp(up, 0x04, status);
938 }
939 return 1;
940 }
941
942 /*
943 * We know that the chip has FIFOs. Does it have an EFR? The
944 * EFR is located in the same register position as the IIR and
945 * we know the top two bits of the IIR are currently set. The
946 * EFR should contain zero. Try to read the EFR.
947 */
948 static void autoconfig_16550a(struct uart_8250_port *up)
949 {
950 unsigned char status1, status2;
951 unsigned int iersave;
952
953 up->port.type = PORT_16550A;
954 up->capabilities |= UART_CAP_FIFO;
955
956 /*
957 * Check for presence of the EFR when DLAB is set.
958 * Only ST16C650V1 UARTs pass this test.
959 */
960 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
961 if (serial_in(up, UART_EFR) == 0) {
962 serial_outp(up, UART_EFR, 0xA8);
963 if (serial_in(up, UART_EFR) != 0) {
964 DEBUG_AUTOCONF("EFRv1 ");
965 up->port.type = PORT_16650;
966 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
967 } else {
968 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
969 }
970 serial_outp(up, UART_EFR, 0);
971 return;
972 }
973
974 /*
975 * Maybe it requires 0xbf to be written to the LCR.
976 * (other ST16C650V2 UARTs, TI16C752A, etc)
977 */
978 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
979 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
980 DEBUG_AUTOCONF("EFRv2 ");
981 autoconfig_has_efr(up);
982 return;
983 }
984
985 /*
986 * Check for a National Semiconductor SuperIO chip.
987 * Attempt to switch to bank 2, read the value of the LOOP bit
988 * from EXCR1. Switch back to bank 0, change it in MCR. Then
989 * switch back to bank 2, read it from EXCR1 again and check
990 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
991 */
992 serial_outp(up, UART_LCR, 0);
993 status1 = serial_in(up, UART_MCR);
994 serial_outp(up, UART_LCR, 0xE0);
995 status2 = serial_in(up, 0x02); /* EXCR1 */
996
997 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
998 serial_outp(up, UART_LCR, 0);
999 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1000 serial_outp(up, UART_LCR, 0xE0);
1001 status2 = serial_in(up, 0x02); /* EXCR1 */
1002 serial_outp(up, UART_LCR, 0);
1003 serial_outp(up, UART_MCR, status1);
1004
1005 if ((status2 ^ status1) & UART_MCR_LOOP) {
1006 unsigned short quot;
1007
1008 serial_outp(up, UART_LCR, 0xE0);
1009
1010 quot = serial_dl_read(up);
1011 quot <<= 3;
1012
1013 if (ns16550a_goto_highspeed(up))
1014 serial_dl_write(up, quot);
1015
1016 serial_outp(up, UART_LCR, 0);
1017
1018 up->port.uartclk = 921600*16;
1019 up->port.type = PORT_NS16550A;
1020 up->capabilities |= UART_NATSEMI;
1021 return;
1022 }
1023 }
1024
1025 /*
1026 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1027 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1028 * Try setting it with and without DLAB set. Cheap clones
1029 * set bit 5 without DLAB set.
1030 */
1031 serial_outp(up, UART_LCR, 0);
1032 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1033 status1 = serial_in(up, UART_IIR) >> 5;
1034 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1035 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1036 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1037 status2 = serial_in(up, UART_IIR) >> 5;
1038 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1039 serial_outp(up, UART_LCR, 0);
1040
1041 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1042
1043 if (status1 == 6 && status2 == 7) {
1044 up->port.type = PORT_16750;
1045 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1046 return;
1047 }
1048
1049 /*
1050 * Try writing and reading the UART_IER_UUE bit (b6).
1051 * If it works, this is probably one of the Xscale platform's
1052 * internal UARTs.
1053 * We're going to explicitly set the UUE bit to 0 before
1054 * trying to write and read a 1 just to make sure it's not
1055 * already a 1 and maybe locked there before we even start start.
1056 */
1057 iersave = serial_in(up, UART_IER);
1058 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1059 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1060 /*
1061 * OK it's in a known zero state, try writing and reading
1062 * without disturbing the current state of the other bits.
1063 */
1064 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1065 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1066 /*
1067 * It's an Xscale.
1068 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1069 */
1070 DEBUG_AUTOCONF("Xscale ");
1071 up->port.type = PORT_XSCALE;
1072 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1073 return;
1074 }
1075 } else {
1076 /*
1077 * If we got here we couldn't force the IER_UUE bit to 0.
1078 * Log it and continue.
1079 */
1080 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1081 }
1082 serial_outp(up, UART_IER, iersave);
1083
1084 /*
1085 * Exar uarts have EFR in a weird location
1086 */
1087 if (up->port.flags & UPF_EXAR_EFR) {
1088 up->port.type = PORT_XR17D15X;
1089 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1090 }
1091
1092 /*
1093 * We distinguish between 16550A and U6 16550A by counting
1094 * how many bytes are in the FIFO.
1095 */
1096 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1097 up->port.type = PORT_U6_16550A;
1098 up->capabilities |= UART_CAP_AFE;
1099 }
1100 }
1101
1102 /*
1103 * This routine is called by rs_init() to initialize a specific serial
1104 * port. It determines what type of UART chip this serial port is
1105 * using: 8250, 16450, 16550, 16550A. The important question is
1106 * whether or not this UART is a 16550A or not, since this will
1107 * determine whether or not we can use its FIFO features or not.
1108 */
1109 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1110 {
1111 unsigned char status1, scratch, scratch2, scratch3;
1112 unsigned char save_lcr, save_mcr;
1113 unsigned long flags;
1114
1115 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1116 return;
1117
1118 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1119 serial_index(&up->port), up->port.iobase, up->port.membase);
1120
1121 /*
1122 * We really do need global IRQs disabled here - we're going to
1123 * be frobbing the chips IRQ enable register to see if it exists.
1124 */
1125 spin_lock_irqsave(&up->port.lock, flags);
1126
1127 up->capabilities = 0;
1128 up->bugs = 0;
1129
1130 if (!(up->port.flags & UPF_BUGGY_UART)) {
1131 /*
1132 * Do a simple existence test first; if we fail this,
1133 * there's no point trying anything else.
1134 *
1135 * 0x80 is used as a nonsense port to prevent against
1136 * false positives due to ISA bus float. The
1137 * assumption is that 0x80 is a non-existent port;
1138 * which should be safe since include/asm/io.h also
1139 * makes this assumption.
1140 *
1141 * Note: this is safe as long as MCR bit 4 is clear
1142 * and the device is in "PC" mode.
1143 */
1144 scratch = serial_inp(up, UART_IER);
1145 serial_outp(up, UART_IER, 0);
1146 #ifdef __i386__
1147 outb(0xff, 0x080);
1148 #endif
1149 /*
1150 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1151 * 16C754B) allow only to modify them if an EFR bit is set.
1152 */
1153 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1154 serial_outp(up, UART_IER, 0x0F);
1155 #ifdef __i386__
1156 outb(0, 0x080);
1157 #endif
1158 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1159 serial_outp(up, UART_IER, scratch);
1160 if (scratch2 != 0 || scratch3 != 0x0F) {
1161 /*
1162 * We failed; there's nothing here
1163 */
1164 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1165 scratch2, scratch3);
1166 goto out;
1167 }
1168 }
1169
1170 save_mcr = serial_in(up, UART_MCR);
1171 save_lcr = serial_in(up, UART_LCR);
1172
1173 /*
1174 * Check to see if a UART is really there. Certain broken
1175 * internal modems based on the Rockwell chipset fail this
1176 * test, because they apparently don't implement the loopback
1177 * test mode. So this test is skipped on the COM 1 through
1178 * COM 4 ports. This *should* be safe, since no board
1179 * manufacturer would be stupid enough to design a board
1180 * that conflicts with COM 1-4 --- we hope!
1181 */
1182 if (!(up->port.flags & UPF_SKIP_TEST)) {
1183 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1184 status1 = serial_inp(up, UART_MSR) & 0xF0;
1185 serial_outp(up, UART_MCR, save_mcr);
1186 if (status1 != 0x90) {
1187 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1188 status1);
1189 goto out;
1190 }
1191 }
1192
1193 /*
1194 * We're pretty sure there's a port here. Lets find out what
1195 * type of port it is. The IIR top two bits allows us to find
1196 * out if it's 8250 or 16450, 16550, 16550A or later. This
1197 * determines what we test for next.
1198 *
1199 * We also initialise the EFR (if any) to zero for later. The
1200 * EFR occupies the same register location as the FCR and IIR.
1201 */
1202 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1203 serial_outp(up, UART_EFR, 0);
1204 serial_outp(up, UART_LCR, 0);
1205
1206 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1207 scratch = serial_in(up, UART_IIR) >> 6;
1208
1209 DEBUG_AUTOCONF("iir=%d ", scratch);
1210
1211 switch (scratch) {
1212 case 0:
1213 autoconfig_8250(up);
1214 break;
1215 case 1:
1216 up->port.type = PORT_UNKNOWN;
1217 break;
1218 case 2:
1219 up->port.type = PORT_16550;
1220 break;
1221 case 3:
1222 autoconfig_16550a(up);
1223 break;
1224 }
1225
1226 #ifdef CONFIG_SERIAL_8250_RSA
1227 /*
1228 * Only probe for RSA ports if we got the region.
1229 */
1230 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1231 int i;
1232
1233 for (i = 0 ; i < probe_rsa_count; ++i) {
1234 if (probe_rsa[i] == up->port.iobase &&
1235 __enable_rsa(up)) {
1236 up->port.type = PORT_RSA;
1237 break;
1238 }
1239 }
1240 }
1241 #endif
1242
1243 serial_outp(up, UART_LCR, save_lcr);
1244
1245 if (up->capabilities != uart_config[up->port.type].flags) {
1246 printk(KERN_WARNING
1247 "ttyS%d: detected caps %08x should be %08x\n",
1248 serial_index(&up->port), up->capabilities,
1249 uart_config[up->port.type].flags);
1250 }
1251
1252 up->port.fifosize = uart_config[up->port.type].fifo_size;
1253 up->capabilities = uart_config[up->port.type].flags;
1254 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1255
1256 if (up->port.type == PORT_UNKNOWN)
1257 goto out;
1258
1259 /*
1260 * Reset the UART.
1261 */
1262 #ifdef CONFIG_SERIAL_8250_RSA
1263 if (up->port.type == PORT_RSA)
1264 serial_outp(up, UART_RSA_FRR, 0);
1265 #endif
1266 serial_outp(up, UART_MCR, save_mcr);
1267 serial8250_clear_fifos(up);
1268 serial_in(up, UART_RX);
1269 if (up->capabilities & UART_CAP_UUE)
1270 serial_outp(up, UART_IER, UART_IER_UUE);
1271 else
1272 serial_outp(up, UART_IER, 0);
1273
1274 out:
1275 spin_unlock_irqrestore(&up->port.lock, flags);
1276 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1277 }
1278
1279 static void autoconfig_irq(struct uart_8250_port *up)
1280 {
1281 unsigned char save_mcr, save_ier;
1282 unsigned char save_ICP = 0;
1283 unsigned int ICP = 0;
1284 unsigned long irqs;
1285 int irq;
1286
1287 if (up->port.flags & UPF_FOURPORT) {
1288 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1289 save_ICP = inb_p(ICP);
1290 outb_p(0x80, ICP);
1291 (void) inb_p(ICP);
1292 }
1293
1294 /* forget possible initially masked and pending IRQ */
1295 probe_irq_off(probe_irq_on());
1296 save_mcr = serial_inp(up, UART_MCR);
1297 save_ier = serial_inp(up, UART_IER);
1298 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1299
1300 irqs = probe_irq_on();
1301 serial_outp(up, UART_MCR, 0);
1302 udelay(10);
1303 if (up->port.flags & UPF_FOURPORT) {
1304 serial_outp(up, UART_MCR,
1305 UART_MCR_DTR | UART_MCR_RTS);
1306 } else {
1307 serial_outp(up, UART_MCR,
1308 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1309 }
1310 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1311 (void)serial_inp(up, UART_LSR);
1312 (void)serial_inp(up, UART_RX);
1313 (void)serial_inp(up, UART_IIR);
1314 (void)serial_inp(up, UART_MSR);
1315 serial_outp(up, UART_TX, 0xFF);
1316 udelay(20);
1317 irq = probe_irq_off(irqs);
1318
1319 serial_outp(up, UART_MCR, save_mcr);
1320 serial_outp(up, UART_IER, save_ier);
1321
1322 if (up->port.flags & UPF_FOURPORT)
1323 outb_p(save_ICP, ICP);
1324
1325 up->port.irq = (irq > 0) ? irq : 0;
1326 }
1327
1328 static inline void __stop_tx(struct uart_8250_port *p)
1329 {
1330 if (p->ier & UART_IER_THRI) {
1331 p->ier &= ~UART_IER_THRI;
1332 serial_out(p, UART_IER, p->ier);
1333 }
1334 }
1335
1336 static void serial8250_stop_tx(struct uart_port *port)
1337 {
1338 struct uart_8250_port *up =
1339 container_of(port, struct uart_8250_port, port);
1340
1341 __stop_tx(up);
1342
1343 /*
1344 * We really want to stop the transmitter from sending.
1345 */
1346 if (up->port.type == PORT_16C950) {
1347 up->acr |= UART_ACR_TXDIS;
1348 serial_icr_write(up, UART_ACR, up->acr);
1349 }
1350 }
1351
1352 static void transmit_chars(struct uart_8250_port *up);
1353
1354 static void serial8250_start_tx(struct uart_port *port)
1355 {
1356 struct uart_8250_port *up =
1357 container_of(port, struct uart_8250_port, port);
1358
1359 if (!(up->ier & UART_IER_THRI)) {
1360 up->ier |= UART_IER_THRI;
1361 serial_out(up, UART_IER, up->ier);
1362
1363 if (up->bugs & UART_BUG_TXEN) {
1364 unsigned char lsr;
1365 lsr = serial_in(up, UART_LSR);
1366 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1367 if ((up->port.type == PORT_RM9000) ?
1368 (lsr & UART_LSR_THRE) :
1369 (lsr & UART_LSR_TEMT))
1370 transmit_chars(up);
1371 }
1372 }
1373
1374 /*
1375 * Re-enable the transmitter if we disabled it.
1376 */
1377 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1378 up->acr &= ~UART_ACR_TXDIS;
1379 serial_icr_write(up, UART_ACR, up->acr);
1380 }
1381 }
1382
1383 static void serial8250_stop_rx(struct uart_port *port)
1384 {
1385 struct uart_8250_port *up =
1386 container_of(port, struct uart_8250_port, port);
1387
1388 up->ier &= ~UART_IER_RLSI;
1389 up->port.read_status_mask &= ~UART_LSR_DR;
1390 serial_out(up, UART_IER, up->ier);
1391 }
1392
1393 static void serial8250_enable_ms(struct uart_port *port)
1394 {
1395 struct uart_8250_port *up =
1396 container_of(port, struct uart_8250_port, port);
1397
1398 /* no MSR capabilities */
1399 if (up->bugs & UART_BUG_NOMSR)
1400 return;
1401
1402 up->ier |= UART_IER_MSI;
1403 serial_out(up, UART_IER, up->ier);
1404 }
1405
1406 /*
1407 * Clear the Tegra rx fifo after a break
1408 *
1409 * FIXME: This needs to become a port specific callback once we have a
1410 * framework for this
1411 */
1412 static void clear_rx_fifo(struct uart_8250_port *up)
1413 {
1414 unsigned int status, tmout = 10000;
1415 do {
1416 status = serial_in(up, UART_LSR);
1417 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1418 status = serial_in(up, UART_RX);
1419 else
1420 break;
1421 if (--tmout == 0)
1422 break;
1423 udelay(1);
1424 } while (1);
1425 }
1426
1427 static void
1428 receive_chars(struct uart_8250_port *up, unsigned int *status)
1429 {
1430 struct tty_struct *tty = up->port.state->port.tty;
1431 unsigned char ch, lsr = *status;
1432 int max_count = 256;
1433 char flag;
1434
1435 do {
1436 if (likely(lsr & UART_LSR_DR))
1437 ch = serial_inp(up, UART_RX);
1438 else
1439 /*
1440 * Intel 82571 has a Serial Over Lan device that will
1441 * set UART_LSR_BI without setting UART_LSR_DR when
1442 * it receives a break. To avoid reading from the
1443 * receive buffer without UART_LSR_DR bit set, we
1444 * just force the read character to be 0
1445 */
1446 ch = 0;
1447
1448 flag = TTY_NORMAL;
1449 up->port.icount.rx++;
1450
1451 lsr |= up->lsr_saved_flags;
1452 up->lsr_saved_flags = 0;
1453
1454 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1455 /*
1456 * For statistics only
1457 */
1458 if (lsr & UART_LSR_BI) {
1459 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1460 up->port.icount.brk++;
1461 /*
1462 * If tegra port then clear the rx fifo to
1463 * accept another break/character.
1464 */
1465 if (up->port.type == PORT_TEGRA)
1466 clear_rx_fifo(up);
1467
1468 /*
1469 * We do the SysRQ and SAK checking
1470 * here because otherwise the break
1471 * may get masked by ignore_status_mask
1472 * or read_status_mask.
1473 */
1474 if (uart_handle_break(&up->port))
1475 goto ignore_char;
1476 } else if (lsr & UART_LSR_PE)
1477 up->port.icount.parity++;
1478 else if (lsr & UART_LSR_FE)
1479 up->port.icount.frame++;
1480 if (lsr & UART_LSR_OE)
1481 up->port.icount.overrun++;
1482
1483 /*
1484 * Mask off conditions which should be ignored.
1485 */
1486 lsr &= up->port.read_status_mask;
1487
1488 if (lsr & UART_LSR_BI) {
1489 DEBUG_INTR("handling break....");
1490 flag = TTY_BREAK;
1491 } else if (lsr & UART_LSR_PE)
1492 flag = TTY_PARITY;
1493 else if (lsr & UART_LSR_FE)
1494 flag = TTY_FRAME;
1495 }
1496 if (uart_handle_sysrq_char(&up->port, ch))
1497 goto ignore_char;
1498
1499 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1500
1501 ignore_char:
1502 lsr = serial_inp(up, UART_LSR);
1503 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1504 spin_unlock(&up->port.lock);
1505 tty_flip_buffer_push(tty);
1506 spin_lock(&up->port.lock);
1507 *status = lsr;
1508 }
1509
1510 static void transmit_chars(struct uart_8250_port *up)
1511 {
1512 struct circ_buf *xmit = &up->port.state->xmit;
1513 int count;
1514
1515 if (up->port.x_char) {
1516 serial_outp(up, UART_TX, up->port.x_char);
1517 up->port.icount.tx++;
1518 up->port.x_char = 0;
1519 return;
1520 }
1521 if (uart_tx_stopped(&up->port)) {
1522 serial8250_stop_tx(&up->port);
1523 return;
1524 }
1525 if (uart_circ_empty(xmit)) {
1526 __stop_tx(up);
1527 return;
1528 }
1529
1530 count = up->tx_loadsz;
1531 do {
1532 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1533 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1534 up->port.icount.tx++;
1535 if (uart_circ_empty(xmit))
1536 break;
1537 } while (--count > 0);
1538
1539 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1540 uart_write_wakeup(&up->port);
1541
1542 DEBUG_INTR("THRE...");
1543
1544 if (uart_circ_empty(xmit))
1545 __stop_tx(up);
1546 }
1547
1548 static unsigned int check_modem_status(struct uart_8250_port *up)
1549 {
1550 unsigned int status = serial_in(up, UART_MSR);
1551
1552 status |= up->msr_saved_flags;
1553 up->msr_saved_flags = 0;
1554 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1555 up->port.state != NULL) {
1556 if (status & UART_MSR_TERI)
1557 up->port.icount.rng++;
1558 if (status & UART_MSR_DDSR)
1559 up->port.icount.dsr++;
1560 if (status & UART_MSR_DDCD)
1561 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1562 if (status & UART_MSR_DCTS)
1563 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1564
1565 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1566 }
1567
1568 return status;
1569 }
1570
1571 /*
1572 * This handles the interrupt from one port.
1573 */
1574 static void serial8250_handle_port(struct uart_8250_port *up)
1575 {
1576 unsigned int status;
1577 unsigned long flags;
1578
1579 spin_lock_irqsave(&up->port.lock, flags);
1580
1581 status = serial_inp(up, UART_LSR);
1582
1583 DEBUG_INTR("status = %x...", status);
1584
1585 if (status & (UART_LSR_DR | UART_LSR_BI))
1586 receive_chars(up, &status);
1587 check_modem_status(up);
1588 if (status & UART_LSR_THRE)
1589 transmit_chars(up);
1590
1591 spin_unlock_irqrestore(&up->port.lock, flags);
1592 }
1593
1594 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1595 {
1596 struct uart_8250_port *up =
1597 container_of(port, struct uart_8250_port, port);
1598
1599 if (!(iir & UART_IIR_NO_INT)) {
1600 serial8250_handle_port(up);
1601 return 1;
1602 }
1603
1604 return 0;
1605 }
1606 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1607
1608 static int serial8250_default_handle_irq(struct uart_port *port)
1609 {
1610 struct uart_8250_port *up =
1611 container_of(port, struct uart_8250_port, port);
1612 unsigned int iir = serial_in(up, UART_IIR);
1613
1614 return serial8250_handle_irq(port, iir);
1615 }
1616
1617 /*
1618 * This is the serial driver's interrupt routine.
1619 *
1620 * Arjan thinks the old way was overly complex, so it got simplified.
1621 * Alan disagrees, saying that need the complexity to handle the weird
1622 * nature of ISA shared interrupts. (This is a special exception.)
1623 *
1624 * In order to handle ISA shared interrupts properly, we need to check
1625 * that all ports have been serviced, and therefore the ISA interrupt
1626 * line has been de-asserted.
1627 *
1628 * This means we need to loop through all ports. checking that they
1629 * don't have an interrupt pending.
1630 */
1631 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1632 {
1633 struct irq_info *i = dev_id;
1634 struct list_head *l, *end = NULL;
1635 int pass_counter = 0, handled = 0;
1636
1637 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1638
1639 spin_lock(&i->lock);
1640
1641 l = i->head;
1642 do {
1643 struct uart_8250_port *up;
1644 struct uart_port *port;
1645
1646 up = list_entry(l, struct uart_8250_port, list);
1647 port = &up->port;
1648
1649 if (port->handle_irq(port)) {
1650 handled = 1;
1651 end = NULL;
1652 } else if (end == NULL)
1653 end = l;
1654
1655 l = l->next;
1656
1657 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1658 /* If we hit this, we're dead. */
1659 printk_ratelimited(KERN_ERR
1660 "serial8250: too much work for irq%d\n", irq);
1661 break;
1662 }
1663 } while (l != end);
1664
1665 spin_unlock(&i->lock);
1666
1667 DEBUG_INTR("end.\n");
1668
1669 return IRQ_RETVAL(handled);
1670 }
1671
1672 /*
1673 * To support ISA shared interrupts, we need to have one interrupt
1674 * handler that ensures that the IRQ line has been deasserted
1675 * before returning. Failing to do this will result in the IRQ
1676 * line being stuck active, and, since ISA irqs are edge triggered,
1677 * no more IRQs will be seen.
1678 */
1679 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1680 {
1681 spin_lock_irq(&i->lock);
1682
1683 if (!list_empty(i->head)) {
1684 if (i->head == &up->list)
1685 i->head = i->head->next;
1686 list_del(&up->list);
1687 } else {
1688 BUG_ON(i->head != &up->list);
1689 i->head = NULL;
1690 }
1691 spin_unlock_irq(&i->lock);
1692 /* List empty so throw away the hash node */
1693 if (i->head == NULL) {
1694 hlist_del(&i->node);
1695 kfree(i);
1696 }
1697 }
1698
1699 static int serial_link_irq_chain(struct uart_8250_port *up)
1700 {
1701 struct hlist_head *h;
1702 struct hlist_node *n;
1703 struct irq_info *i;
1704 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1705
1706 mutex_lock(&hash_mutex);
1707
1708 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1709
1710 hlist_for_each(n, h) {
1711 i = hlist_entry(n, struct irq_info, node);
1712 if (i->irq == up->port.irq)
1713 break;
1714 }
1715
1716 if (n == NULL) {
1717 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1718 if (i == NULL) {
1719 mutex_unlock(&hash_mutex);
1720 return -ENOMEM;
1721 }
1722 spin_lock_init(&i->lock);
1723 i->irq = up->port.irq;
1724 hlist_add_head(&i->node, h);
1725 }
1726 mutex_unlock(&hash_mutex);
1727
1728 spin_lock_irq(&i->lock);
1729
1730 if (i->head) {
1731 list_add(&up->list, i->head);
1732 spin_unlock_irq(&i->lock);
1733
1734 ret = 0;
1735 } else {
1736 INIT_LIST_HEAD(&up->list);
1737 i->head = &up->list;
1738 spin_unlock_irq(&i->lock);
1739 irq_flags |= up->port.irqflags;
1740 ret = request_irq(up->port.irq, serial8250_interrupt,
1741 irq_flags, "serial", i);
1742 if (ret < 0)
1743 serial_do_unlink(i, up);
1744 }
1745
1746 return ret;
1747 }
1748
1749 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1750 {
1751 struct irq_info *i;
1752 struct hlist_node *n;
1753 struct hlist_head *h;
1754
1755 mutex_lock(&hash_mutex);
1756
1757 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1758
1759 hlist_for_each(n, h) {
1760 i = hlist_entry(n, struct irq_info, node);
1761 if (i->irq == up->port.irq)
1762 break;
1763 }
1764
1765 BUG_ON(n == NULL);
1766 BUG_ON(i->head == NULL);
1767
1768 if (list_empty(i->head))
1769 free_irq(up->port.irq, i);
1770
1771 serial_do_unlink(i, up);
1772 mutex_unlock(&hash_mutex);
1773 }
1774
1775 /*
1776 * This function is used to handle ports that do not have an
1777 * interrupt. This doesn't work very well for 16450's, but gives
1778 * barely passable results for a 16550A. (Although at the expense
1779 * of much CPU overhead).
1780 */
1781 static void serial8250_timeout(unsigned long data)
1782 {
1783 struct uart_8250_port *up = (struct uart_8250_port *)data;
1784 unsigned int iir;
1785
1786 iir = serial_in(up, UART_IIR);
1787 if (!(iir & UART_IIR_NO_INT))
1788 serial8250_handle_port(up);
1789 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1790 }
1791
1792 static void serial8250_backup_timeout(unsigned long data)
1793 {
1794 struct uart_8250_port *up = (struct uart_8250_port *)data;
1795 unsigned int iir, ier = 0, lsr;
1796 unsigned long flags;
1797
1798 spin_lock_irqsave(&up->port.lock, flags);
1799
1800 /*
1801 * Must disable interrupts or else we risk racing with the interrupt
1802 * based handler.
1803 */
1804 if (is_real_interrupt(up->port.irq)) {
1805 ier = serial_in(up, UART_IER);
1806 serial_out(up, UART_IER, 0);
1807 }
1808
1809 iir = serial_in(up, UART_IIR);
1810
1811 /*
1812 * This should be a safe test for anyone who doesn't trust the
1813 * IIR bits on their UART, but it's specifically designed for
1814 * the "Diva" UART used on the management processor on many HP
1815 * ia64 and parisc boxes.
1816 */
1817 lsr = serial_in(up, UART_LSR);
1818 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1819 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1820 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1821 (lsr & UART_LSR_THRE)) {
1822 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1823 iir |= UART_IIR_THRI;
1824 }
1825
1826 if (!(iir & UART_IIR_NO_INT))
1827 transmit_chars(up);
1828
1829 if (is_real_interrupt(up->port.irq))
1830 serial_out(up, UART_IER, ier);
1831
1832 spin_unlock_irqrestore(&up->port.lock, flags);
1833
1834 /* Standard timer interval plus 0.2s to keep the port running */
1835 mod_timer(&up->timer,
1836 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1837 }
1838
1839 static unsigned int serial8250_tx_empty(struct uart_port *port)
1840 {
1841 struct uart_8250_port *up =
1842 container_of(port, struct uart_8250_port, port);
1843 unsigned long flags;
1844 unsigned int lsr;
1845
1846 spin_lock_irqsave(&up->port.lock, flags);
1847 lsr = serial_in(up, UART_LSR);
1848 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1849 spin_unlock_irqrestore(&up->port.lock, flags);
1850
1851 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1852 }
1853
1854 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1855 {
1856 struct uart_8250_port *up =
1857 container_of(port, struct uart_8250_port, port);
1858 unsigned int status;
1859 unsigned int ret;
1860
1861 status = check_modem_status(up);
1862
1863 ret = 0;
1864 if (status & UART_MSR_DCD)
1865 ret |= TIOCM_CAR;
1866 if (status & UART_MSR_RI)
1867 ret |= TIOCM_RNG;
1868 if (status & UART_MSR_DSR)
1869 ret |= TIOCM_DSR;
1870 if (status & UART_MSR_CTS)
1871 ret |= TIOCM_CTS;
1872 return ret;
1873 }
1874
1875 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1876 {
1877 struct uart_8250_port *up =
1878 container_of(port, struct uart_8250_port, port);
1879 unsigned char mcr = 0;
1880
1881 if (mctrl & TIOCM_RTS)
1882 mcr |= UART_MCR_RTS;
1883 if (mctrl & TIOCM_DTR)
1884 mcr |= UART_MCR_DTR;
1885 if (mctrl & TIOCM_OUT1)
1886 mcr |= UART_MCR_OUT1;
1887 if (mctrl & TIOCM_OUT2)
1888 mcr |= UART_MCR_OUT2;
1889 if (mctrl & TIOCM_LOOP)
1890 mcr |= UART_MCR_LOOP;
1891
1892 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1893
1894 serial_out(up, UART_MCR, mcr);
1895 }
1896
1897 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1898 {
1899 struct uart_8250_port *up =
1900 container_of(port, struct uart_8250_port, port);
1901 unsigned long flags;
1902
1903 spin_lock_irqsave(&up->port.lock, flags);
1904 if (break_state == -1)
1905 up->lcr |= UART_LCR_SBC;
1906 else
1907 up->lcr &= ~UART_LCR_SBC;
1908 serial_out(up, UART_LCR, up->lcr);
1909 spin_unlock_irqrestore(&up->port.lock, flags);
1910 }
1911
1912 /*
1913 * Wait for transmitter & holding register to empty
1914 */
1915 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1916 {
1917 unsigned int status, tmout = 10000;
1918
1919 /* Wait up to 10ms for the character(s) to be sent. */
1920 for (;;) {
1921 status = serial_in(up, UART_LSR);
1922
1923 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1924
1925 if ((status & bits) == bits)
1926 break;
1927 if (--tmout == 0)
1928 break;
1929 udelay(1);
1930 }
1931
1932 /* Wait up to 1s for flow control if necessary */
1933 if (up->port.flags & UPF_CONS_FLOW) {
1934 unsigned int tmout;
1935 for (tmout = 1000000; tmout; tmout--) {
1936 unsigned int msr = serial_in(up, UART_MSR);
1937 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1938 if (msr & UART_MSR_CTS)
1939 break;
1940 udelay(1);
1941 touch_nmi_watchdog();
1942 }
1943 }
1944 }
1945
1946 #ifdef CONFIG_CONSOLE_POLL
1947 /*
1948 * Console polling routines for writing and reading from the uart while
1949 * in an interrupt or debug context.
1950 */
1951
1952 static int serial8250_get_poll_char(struct uart_port *port)
1953 {
1954 struct uart_8250_port *up =
1955 container_of(port, struct uart_8250_port, port);
1956 unsigned char lsr = serial_inp(up, UART_LSR);
1957
1958 if (!(lsr & UART_LSR_DR))
1959 return NO_POLL_CHAR;
1960
1961 return serial_inp(up, UART_RX);
1962 }
1963
1964
1965 static void serial8250_put_poll_char(struct uart_port *port,
1966 unsigned char c)
1967 {
1968 unsigned int ier;
1969 struct uart_8250_port *up =
1970 container_of(port, struct uart_8250_port, port);
1971
1972 /*
1973 * First save the IER then disable the interrupts
1974 */
1975 ier = serial_in(up, UART_IER);
1976 if (up->capabilities & UART_CAP_UUE)
1977 serial_out(up, UART_IER, UART_IER_UUE);
1978 else
1979 serial_out(up, UART_IER, 0);
1980
1981 wait_for_xmitr(up, BOTH_EMPTY);
1982 /*
1983 * Send the character out.
1984 * If a LF, also do CR...
1985 */
1986 serial_out(up, UART_TX, c);
1987 if (c == 10) {
1988 wait_for_xmitr(up, BOTH_EMPTY);
1989 serial_out(up, UART_TX, 13);
1990 }
1991
1992 /*
1993 * Finally, wait for transmitter to become empty
1994 * and restore the IER
1995 */
1996 wait_for_xmitr(up, BOTH_EMPTY);
1997 serial_out(up, UART_IER, ier);
1998 }
1999
2000 #endif /* CONFIG_CONSOLE_POLL */
2001
2002 static int serial8250_startup(struct uart_port *port)
2003 {
2004 struct uart_8250_port *up =
2005 container_of(port, struct uart_8250_port, port);
2006 unsigned long flags;
2007 unsigned char lsr, iir;
2008 int retval;
2009
2010 up->port.fifosize = uart_config[up->port.type].fifo_size;
2011 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2012 up->capabilities = uart_config[up->port.type].flags;
2013 up->mcr = 0;
2014
2015 if (up->port.iotype != up->cur_iotype)
2016 set_io_from_upio(port);
2017
2018 if (up->port.type == PORT_16C950) {
2019 /* Wake up and initialize UART */
2020 up->acr = 0;
2021 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2022 serial_outp(up, UART_EFR, UART_EFR_ECB);
2023 serial_outp(up, UART_IER, 0);
2024 serial_outp(up, UART_LCR, 0);
2025 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2026 serial_outp(up, UART_LCR, 0xBF);
2027 serial_outp(up, UART_EFR, UART_EFR_ECB);
2028 serial_outp(up, UART_LCR, 0);
2029 }
2030
2031 #ifdef CONFIG_SERIAL_8250_RSA
2032 /*
2033 * If this is an RSA port, see if we can kick it up to the
2034 * higher speed clock.
2035 */
2036 enable_rsa(up);
2037 #endif
2038
2039 /*
2040 * Clear the FIFO buffers and disable them.
2041 * (they will be reenabled in set_termios())
2042 */
2043 serial8250_clear_fifos(up);
2044
2045 /*
2046 * Clear the interrupt registers.
2047 */
2048 (void) serial_inp(up, UART_LSR);
2049 (void) serial_inp(up, UART_RX);
2050 (void) serial_inp(up, UART_IIR);
2051 (void) serial_inp(up, UART_MSR);
2052
2053 /*
2054 * At this point, there's no way the LSR could still be 0xff;
2055 * if it is, then bail out, because there's likely no UART
2056 * here.
2057 */
2058 if (!(up->port.flags & UPF_BUGGY_UART) &&
2059 (serial_inp(up, UART_LSR) == 0xff)) {
2060 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2061 serial_index(&up->port));
2062 return -ENODEV;
2063 }
2064
2065 /*
2066 * For a XR16C850, we need to set the trigger levels
2067 */
2068 if (up->port.type == PORT_16850) {
2069 unsigned char fctr;
2070
2071 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2072
2073 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2074 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2075 serial_outp(up, UART_TRG, UART_TRG_96);
2076 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2077 serial_outp(up, UART_TRG, UART_TRG_96);
2078
2079 serial_outp(up, UART_LCR, 0);
2080 }
2081
2082 if (is_real_interrupt(up->port.irq)) {
2083 unsigned char iir1;
2084 /*
2085 * Test for UARTs that do not reassert THRE when the
2086 * transmitter is idle and the interrupt has already
2087 * been cleared. Real 16550s should always reassert
2088 * this interrupt whenever the transmitter is idle and
2089 * the interrupt is enabled. Delays are necessary to
2090 * allow register changes to become visible.
2091 */
2092 spin_lock_irqsave(&up->port.lock, flags);
2093 if (up->port.irqflags & IRQF_SHARED)
2094 disable_irq_nosync(up->port.irq);
2095
2096 wait_for_xmitr(up, UART_LSR_THRE);
2097 serial_out_sync(up, UART_IER, UART_IER_THRI);
2098 udelay(1); /* allow THRE to set */
2099 iir1 = serial_in(up, UART_IIR);
2100 serial_out(up, UART_IER, 0);
2101 serial_out_sync(up, UART_IER, UART_IER_THRI);
2102 udelay(1); /* allow a working UART time to re-assert THRE */
2103 iir = serial_in(up, UART_IIR);
2104 serial_out(up, UART_IER, 0);
2105
2106 if (up->port.irqflags & IRQF_SHARED)
2107 enable_irq(up->port.irq);
2108 spin_unlock_irqrestore(&up->port.lock, flags);
2109
2110 /*
2111 * If the interrupt is not reasserted, setup a timer to
2112 * kick the UART on a regular basis.
2113 */
2114 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2115 up->bugs |= UART_BUG_THRE;
2116 pr_debug("ttyS%d - using backup timer\n",
2117 serial_index(port));
2118 }
2119 }
2120
2121 /*
2122 * The above check will only give an accurate result the first time
2123 * the port is opened so this value needs to be preserved.
2124 */
2125 if (up->bugs & UART_BUG_THRE) {
2126 up->timer.function = serial8250_backup_timeout;
2127 up->timer.data = (unsigned long)up;
2128 mod_timer(&up->timer, jiffies +
2129 uart_poll_timeout(port) + HZ / 5);
2130 }
2131
2132 /*
2133 * If the "interrupt" for this port doesn't correspond with any
2134 * hardware interrupt, we use a timer-based system. The original
2135 * driver used to do this with IRQ0.
2136 */
2137 if (!is_real_interrupt(up->port.irq)) {
2138 up->timer.data = (unsigned long)up;
2139 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2140 } else {
2141 retval = serial_link_irq_chain(up);
2142 if (retval)
2143 return retval;
2144 }
2145
2146 /*
2147 * Now, initialize the UART
2148 */
2149 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2150
2151 spin_lock_irqsave(&up->port.lock, flags);
2152 if (up->port.flags & UPF_FOURPORT) {
2153 if (!is_real_interrupt(up->port.irq))
2154 up->port.mctrl |= TIOCM_OUT1;
2155 } else
2156 /*
2157 * Most PC uarts need OUT2 raised to enable interrupts.
2158 */
2159 if (is_real_interrupt(up->port.irq))
2160 up->port.mctrl |= TIOCM_OUT2;
2161
2162 serial8250_set_mctrl(&up->port, up->port.mctrl);
2163
2164 /* Serial over Lan (SoL) hack:
2165 Intel 8257x Gigabit ethernet chips have a
2166 16550 emulation, to be used for Serial Over Lan.
2167 Those chips take a longer time than a normal
2168 serial device to signalize that a transmission
2169 data was queued. Due to that, the above test generally
2170 fails. One solution would be to delay the reading of
2171 iir. However, this is not reliable, since the timeout
2172 is variable. So, let's just don't test if we receive
2173 TX irq. This way, we'll never enable UART_BUG_TXEN.
2174 */
2175 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2176 goto dont_test_tx_en;
2177
2178 /*
2179 * Do a quick test to see if we receive an
2180 * interrupt when we enable the TX irq.
2181 */
2182 serial_outp(up, UART_IER, UART_IER_THRI);
2183 lsr = serial_in(up, UART_LSR);
2184 iir = serial_in(up, UART_IIR);
2185 serial_outp(up, UART_IER, 0);
2186
2187 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2188 if (!(up->bugs & UART_BUG_TXEN)) {
2189 up->bugs |= UART_BUG_TXEN;
2190 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2191 serial_index(port));
2192 }
2193 } else {
2194 up->bugs &= ~UART_BUG_TXEN;
2195 }
2196
2197 dont_test_tx_en:
2198 spin_unlock_irqrestore(&up->port.lock, flags);
2199
2200 /*
2201 * Clear the interrupt registers again for luck, and clear the
2202 * saved flags to avoid getting false values from polling
2203 * routines or the previous session.
2204 */
2205 serial_inp(up, UART_LSR);
2206 serial_inp(up, UART_RX);
2207 serial_inp(up, UART_IIR);
2208 serial_inp(up, UART_MSR);
2209 up->lsr_saved_flags = 0;
2210 up->msr_saved_flags = 0;
2211
2212 /*
2213 * Finally, enable interrupts. Note: Modem status interrupts
2214 * are set via set_termios(), which will be occurring imminently
2215 * anyway, so we don't enable them here.
2216 */
2217 up->ier = UART_IER_RLSI | UART_IER_RDI;
2218 serial_outp(up, UART_IER, up->ier);
2219
2220 if (up->port.flags & UPF_FOURPORT) {
2221 unsigned int icp;
2222 /*
2223 * Enable interrupts on the AST Fourport board
2224 */
2225 icp = (up->port.iobase & 0xfe0) | 0x01f;
2226 outb_p(0x80, icp);
2227 (void) inb_p(icp);
2228 }
2229
2230 return 0;
2231 }
2232
2233 static void serial8250_shutdown(struct uart_port *port)
2234 {
2235 struct uart_8250_port *up =
2236 container_of(port, struct uart_8250_port, port);
2237 unsigned long flags;
2238
2239 /*
2240 * Disable interrupts from this port
2241 */
2242 up->ier = 0;
2243 serial_outp(up, UART_IER, 0);
2244
2245 spin_lock_irqsave(&up->port.lock, flags);
2246 if (up->port.flags & UPF_FOURPORT) {
2247 /* reset interrupts on the AST Fourport board */
2248 inb((up->port.iobase & 0xfe0) | 0x1f);
2249 up->port.mctrl |= TIOCM_OUT1;
2250 } else
2251 up->port.mctrl &= ~TIOCM_OUT2;
2252
2253 serial8250_set_mctrl(&up->port, up->port.mctrl);
2254 spin_unlock_irqrestore(&up->port.lock, flags);
2255
2256 /*
2257 * Disable break condition and FIFOs
2258 */
2259 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2260 serial8250_clear_fifos(up);
2261
2262 #ifdef CONFIG_SERIAL_8250_RSA
2263 /*
2264 * Reset the RSA board back to 115kbps compat mode.
2265 */
2266 disable_rsa(up);
2267 #endif
2268
2269 /*
2270 * Read data port to reset things, and then unlink from
2271 * the IRQ chain.
2272 */
2273 (void) serial_in(up, UART_RX);
2274
2275 del_timer_sync(&up->timer);
2276 up->timer.function = serial8250_timeout;
2277 if (is_real_interrupt(up->port.irq))
2278 serial_unlink_irq_chain(up);
2279 }
2280
2281 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2282 {
2283 unsigned int quot;
2284
2285 /*
2286 * Handle magic divisors for baud rates above baud_base on
2287 * SMSC SuperIO chips.
2288 */
2289 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2290 baud == (port->uartclk/4))
2291 quot = 0x8001;
2292 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2293 baud == (port->uartclk/8))
2294 quot = 0x8002;
2295 else
2296 quot = uart_get_divisor(port, baud);
2297
2298 return quot;
2299 }
2300
2301 void
2302 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2303 struct ktermios *old)
2304 {
2305 struct uart_8250_port *up =
2306 container_of(port, struct uart_8250_port, port);
2307 unsigned char cval, fcr = 0;
2308 unsigned long flags;
2309 unsigned int baud, quot;
2310
2311 switch (termios->c_cflag & CSIZE) {
2312 case CS5:
2313 cval = UART_LCR_WLEN5;
2314 break;
2315 case CS6:
2316 cval = UART_LCR_WLEN6;
2317 break;
2318 case CS7:
2319 cval = UART_LCR_WLEN7;
2320 break;
2321 default:
2322 case CS8:
2323 cval = UART_LCR_WLEN8;
2324 break;
2325 }
2326
2327 if (termios->c_cflag & CSTOPB)
2328 cval |= UART_LCR_STOP;
2329 if (termios->c_cflag & PARENB)
2330 cval |= UART_LCR_PARITY;
2331 if (!(termios->c_cflag & PARODD))
2332 cval |= UART_LCR_EPAR;
2333 #ifdef CMSPAR
2334 if (termios->c_cflag & CMSPAR)
2335 cval |= UART_LCR_SPAR;
2336 #endif
2337
2338 /*
2339 * Ask the core to calculate the divisor for us.
2340 */
2341 baud = uart_get_baud_rate(port, termios, old,
2342 port->uartclk / 16 / 0xffff,
2343 port->uartclk / 16);
2344 quot = serial8250_get_divisor(port, baud);
2345
2346 /*
2347 * Oxford Semi 952 rev B workaround
2348 */
2349 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2350 quot++;
2351
2352 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2353 if (baud < 2400)
2354 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2355 else
2356 fcr = uart_config[up->port.type].fcr;
2357 }
2358
2359 /*
2360 * MCR-based auto flow control. When AFE is enabled, RTS will be
2361 * deasserted when the receive FIFO contains more characters than
2362 * the trigger, or the MCR RTS bit is cleared. In the case where
2363 * the remote UART is not using CTS auto flow control, we must
2364 * have sufficient FIFO entries for the latency of the remote
2365 * UART to respond. IOW, at least 32 bytes of FIFO.
2366 */
2367 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2368 up->mcr &= ~UART_MCR_AFE;
2369 if (termios->c_cflag & CRTSCTS)
2370 up->mcr |= UART_MCR_AFE;
2371 }
2372
2373 /*
2374 * Ok, we're now changing the port state. Do it with
2375 * interrupts disabled.
2376 */
2377 spin_lock_irqsave(&up->port.lock, flags);
2378
2379 /*
2380 * Update the per-port timeout.
2381 */
2382 uart_update_timeout(port, termios->c_cflag, baud);
2383
2384 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2385 if (termios->c_iflag & INPCK)
2386 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2387 if (termios->c_iflag & (BRKINT | PARMRK))
2388 up->port.read_status_mask |= UART_LSR_BI;
2389
2390 /*
2391 * Characteres to ignore
2392 */
2393 up->port.ignore_status_mask = 0;
2394 if (termios->c_iflag & IGNPAR)
2395 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2396 if (termios->c_iflag & IGNBRK) {
2397 up->port.ignore_status_mask |= UART_LSR_BI;
2398 /*
2399 * If we're ignoring parity and break indicators,
2400 * ignore overruns too (for real raw support).
2401 */
2402 if (termios->c_iflag & IGNPAR)
2403 up->port.ignore_status_mask |= UART_LSR_OE;
2404 }
2405
2406 /*
2407 * ignore all characters if CREAD is not set
2408 */
2409 if ((termios->c_cflag & CREAD) == 0)
2410 up->port.ignore_status_mask |= UART_LSR_DR;
2411
2412 /*
2413 * CTS flow control flag and modem status interrupts
2414 */
2415 up->ier &= ~UART_IER_MSI;
2416 if (!(up->bugs & UART_BUG_NOMSR) &&
2417 UART_ENABLE_MS(&up->port, termios->c_cflag))
2418 up->ier |= UART_IER_MSI;
2419 if (up->capabilities & UART_CAP_UUE)
2420 up->ier |= UART_IER_UUE;
2421 if (up->capabilities & UART_CAP_RTOIE)
2422 up->ier |= UART_IER_RTOIE;
2423
2424 serial_out(up, UART_IER, up->ier);
2425
2426 if (up->capabilities & UART_CAP_EFR) {
2427 unsigned char efr = 0;
2428 /*
2429 * TI16C752/Startech hardware flow control. FIXME:
2430 * - TI16C752 requires control thresholds to be set.
2431 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2432 */
2433 if (termios->c_cflag & CRTSCTS)
2434 efr |= UART_EFR_CTS;
2435
2436 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2437 if (up->port.flags & UPF_EXAR_EFR)
2438 serial_outp(up, UART_XR_EFR, efr);
2439 else
2440 serial_outp(up, UART_EFR, efr);
2441 }
2442
2443 #ifdef CONFIG_ARCH_OMAP
2444 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2445 if (cpu_is_omap1510() && is_omap_port(up)) {
2446 if (baud == 115200) {
2447 quot = 1;
2448 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2449 } else
2450 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2451 }
2452 #endif
2453
2454 if (up->capabilities & UART_NATSEMI) {
2455 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2456 serial_outp(up, UART_LCR, 0xe0);
2457 } else {
2458 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2459 }
2460
2461 serial_dl_write(up, quot);
2462
2463 /*
2464 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2465 * is written without DLAB set, this mode will be disabled.
2466 */
2467 if (up->port.type == PORT_16750)
2468 serial_outp(up, UART_FCR, fcr);
2469
2470 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2471 up->lcr = cval; /* Save LCR */
2472 if (up->port.type != PORT_16750) {
2473 if (fcr & UART_FCR_ENABLE_FIFO) {
2474 /* emulated UARTs (Lucent Venus 167x) need two steps */
2475 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2476 }
2477 serial_outp(up, UART_FCR, fcr); /* set fcr */
2478 }
2479 serial8250_set_mctrl(&up->port, up->port.mctrl);
2480 spin_unlock_irqrestore(&up->port.lock, flags);
2481 /* Don't rewrite B0 */
2482 if (tty_termios_baud_rate(termios))
2483 tty_termios_encode_baud_rate(termios, baud, baud);
2484 }
2485 EXPORT_SYMBOL(serial8250_do_set_termios);
2486
2487 static void
2488 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2489 struct ktermios *old)
2490 {
2491 if (port->set_termios)
2492 port->set_termios(port, termios, old);
2493 else
2494 serial8250_do_set_termios(port, termios, old);
2495 }
2496
2497 static void
2498 serial8250_set_ldisc(struct uart_port *port, int new)
2499 {
2500 if (new == N_PPS) {
2501 port->flags |= UPF_HARDPPS_CD;
2502 serial8250_enable_ms(port);
2503 } else
2504 port->flags &= ~UPF_HARDPPS_CD;
2505 }
2506
2507
2508 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2509 unsigned int oldstate)
2510 {
2511 struct uart_8250_port *p =
2512 container_of(port, struct uart_8250_port, port);
2513
2514 serial8250_set_sleep(p, state != 0);
2515 }
2516 EXPORT_SYMBOL(serial8250_do_pm);
2517
2518 static void
2519 serial8250_pm(struct uart_port *port, unsigned int state,
2520 unsigned int oldstate)
2521 {
2522 if (port->pm)
2523 port->pm(port, state, oldstate);
2524 else
2525 serial8250_do_pm(port, state, oldstate);
2526 }
2527
2528 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2529 {
2530 if (pt->port.iotype == UPIO_AU)
2531 return 0x1000;
2532 #ifdef CONFIG_ARCH_OMAP
2533 if (is_omap_port(pt))
2534 return 0x16 << pt->port.regshift;
2535 #endif
2536 return 8 << pt->port.regshift;
2537 }
2538
2539 /*
2540 * Resource handling.
2541 */
2542 static int serial8250_request_std_resource(struct uart_8250_port *up)
2543 {
2544 unsigned int size = serial8250_port_size(up);
2545 int ret = 0;
2546
2547 switch (up->port.iotype) {
2548 case UPIO_AU:
2549 case UPIO_TSI:
2550 case UPIO_MEM32:
2551 case UPIO_MEM:
2552 if (!up->port.mapbase)
2553 break;
2554
2555 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2556 ret = -EBUSY;
2557 break;
2558 }
2559
2560 if (up->port.flags & UPF_IOREMAP) {
2561 up->port.membase = ioremap_nocache(up->port.mapbase,
2562 size);
2563 if (!up->port.membase) {
2564 release_mem_region(up->port.mapbase, size);
2565 ret = -ENOMEM;
2566 }
2567 }
2568 break;
2569
2570 case UPIO_HUB6:
2571 case UPIO_PORT:
2572 if (!request_region(up->port.iobase, size, "serial"))
2573 ret = -EBUSY;
2574 break;
2575 }
2576 return ret;
2577 }
2578
2579 static void serial8250_release_std_resource(struct uart_8250_port *up)
2580 {
2581 unsigned int size = serial8250_port_size(up);
2582
2583 switch (up->port.iotype) {
2584 case UPIO_AU:
2585 case UPIO_TSI:
2586 case UPIO_MEM32:
2587 case UPIO_MEM:
2588 if (!up->port.mapbase)
2589 break;
2590
2591 if (up->port.flags & UPF_IOREMAP) {
2592 iounmap(up->port.membase);
2593 up->port.membase = NULL;
2594 }
2595
2596 release_mem_region(up->port.mapbase, size);
2597 break;
2598
2599 case UPIO_HUB6:
2600 case UPIO_PORT:
2601 release_region(up->port.iobase, size);
2602 break;
2603 }
2604 }
2605
2606 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2607 {
2608 unsigned long start = UART_RSA_BASE << up->port.regshift;
2609 unsigned int size = 8 << up->port.regshift;
2610 int ret = -EINVAL;
2611
2612 switch (up->port.iotype) {
2613 case UPIO_HUB6:
2614 case UPIO_PORT:
2615 start += up->port.iobase;
2616 if (request_region(start, size, "serial-rsa"))
2617 ret = 0;
2618 else
2619 ret = -EBUSY;
2620 break;
2621 }
2622
2623 return ret;
2624 }
2625
2626 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2627 {
2628 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2629 unsigned int size = 8 << up->port.regshift;
2630
2631 switch (up->port.iotype) {
2632 case UPIO_HUB6:
2633 case UPIO_PORT:
2634 release_region(up->port.iobase + offset, size);
2635 break;
2636 }
2637 }
2638
2639 static void serial8250_release_port(struct uart_port *port)
2640 {
2641 struct uart_8250_port *up =
2642 container_of(port, struct uart_8250_port, port);
2643
2644 serial8250_release_std_resource(up);
2645 if (up->port.type == PORT_RSA)
2646 serial8250_release_rsa_resource(up);
2647 }
2648
2649 static int serial8250_request_port(struct uart_port *port)
2650 {
2651 struct uart_8250_port *up =
2652 container_of(port, struct uart_8250_port, port);
2653 int ret = 0;
2654
2655 ret = serial8250_request_std_resource(up);
2656 if (ret == 0 && up->port.type == PORT_RSA) {
2657 ret = serial8250_request_rsa_resource(up);
2658 if (ret < 0)
2659 serial8250_release_std_resource(up);
2660 }
2661
2662 return ret;
2663 }
2664
2665 static void serial8250_config_port(struct uart_port *port, int flags)
2666 {
2667 struct uart_8250_port *up =
2668 container_of(port, struct uart_8250_port, port);
2669 int probeflags = PROBE_ANY;
2670 int ret;
2671
2672 /*
2673 * Find the region that we can probe for. This in turn
2674 * tells us whether we can probe for the type of port.
2675 */
2676 ret = serial8250_request_std_resource(up);
2677 if (ret < 0)
2678 return;
2679
2680 ret = serial8250_request_rsa_resource(up);
2681 if (ret < 0)
2682 probeflags &= ~PROBE_RSA;
2683
2684 if (up->port.iotype != up->cur_iotype)
2685 set_io_from_upio(port);
2686
2687 if (flags & UART_CONFIG_TYPE)
2688 autoconfig(up, probeflags);
2689
2690 /* if access method is AU, it is a 16550 with a quirk */
2691 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2692 up->bugs |= UART_BUG_NOMSR;
2693
2694 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2695 autoconfig_irq(up);
2696
2697 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2698 serial8250_release_rsa_resource(up);
2699 if (up->port.type == PORT_UNKNOWN)
2700 serial8250_release_std_resource(up);
2701 }
2702
2703 static int
2704 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2705 {
2706 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2707 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2708 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2709 ser->type == PORT_STARTECH)
2710 return -EINVAL;
2711 return 0;
2712 }
2713
2714 static const char *
2715 serial8250_type(struct uart_port *port)
2716 {
2717 int type = port->type;
2718
2719 if (type >= ARRAY_SIZE(uart_config))
2720 type = 0;
2721 return uart_config[type].name;
2722 }
2723
2724 static struct uart_ops serial8250_pops = {
2725 .tx_empty = serial8250_tx_empty,
2726 .set_mctrl = serial8250_set_mctrl,
2727 .get_mctrl = serial8250_get_mctrl,
2728 .stop_tx = serial8250_stop_tx,
2729 .start_tx = serial8250_start_tx,
2730 .stop_rx = serial8250_stop_rx,
2731 .enable_ms = serial8250_enable_ms,
2732 .break_ctl = serial8250_break_ctl,
2733 .startup = serial8250_startup,
2734 .shutdown = serial8250_shutdown,
2735 .set_termios = serial8250_set_termios,
2736 .set_ldisc = serial8250_set_ldisc,
2737 .pm = serial8250_pm,
2738 .type = serial8250_type,
2739 .release_port = serial8250_release_port,
2740 .request_port = serial8250_request_port,
2741 .config_port = serial8250_config_port,
2742 .verify_port = serial8250_verify_port,
2743 #ifdef CONFIG_CONSOLE_POLL
2744 .poll_get_char = serial8250_get_poll_char,
2745 .poll_put_char = serial8250_put_poll_char,
2746 #endif
2747 };
2748
2749 static struct uart_8250_port serial8250_ports[UART_NR];
2750
2751 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2752 unsigned short *capabilities);
2753
2754 void serial8250_set_isa_configurator(
2755 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2756 {
2757 serial8250_isa_config = v;
2758 }
2759 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2760
2761 static void __init serial8250_isa_init_ports(void)
2762 {
2763 struct uart_8250_port *up;
2764 static int first = 1;
2765 int i, irqflag = 0;
2766
2767 if (!first)
2768 return;
2769 first = 0;
2770
2771 for (i = 0; i < nr_uarts; i++) {
2772 struct uart_8250_port *up = &serial8250_ports[i];
2773
2774 up->port.line = i;
2775 spin_lock_init(&up->port.lock);
2776
2777 init_timer(&up->timer);
2778 up->timer.function = serial8250_timeout;
2779
2780 /*
2781 * ALPHA_KLUDGE_MCR needs to be killed.
2782 */
2783 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2784 up->mcr_force = ALPHA_KLUDGE_MCR;
2785
2786 up->port.ops = &serial8250_pops;
2787 }
2788
2789 if (share_irqs)
2790 irqflag = IRQF_SHARED;
2791
2792 for (i = 0, up = serial8250_ports;
2793 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2794 i++, up++) {
2795 up->port.iobase = old_serial_port[i].port;
2796 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2797 up->port.irqflags = old_serial_port[i].irqflags;
2798 up->port.uartclk = old_serial_port[i].baud_base * 16;
2799 up->port.flags = old_serial_port[i].flags;
2800 up->port.hub6 = old_serial_port[i].hub6;
2801 up->port.membase = old_serial_port[i].iomem_base;
2802 up->port.iotype = old_serial_port[i].io_type;
2803 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2804 set_io_from_upio(&up->port);
2805 up->port.irqflags |= irqflag;
2806 if (serial8250_isa_config != NULL)
2807 serial8250_isa_config(i, &up->port, &up->capabilities);
2808
2809 }
2810 }
2811
2812 static void
2813 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2814 {
2815 up->port.type = type;
2816 up->port.fifosize = uart_config[type].fifo_size;
2817 up->capabilities = uart_config[type].flags;
2818 up->tx_loadsz = uart_config[type].tx_loadsz;
2819 }
2820
2821 static void __init
2822 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2823 {
2824 int i;
2825
2826 for (i = 0; i < nr_uarts; i++) {
2827 struct uart_8250_port *up = &serial8250_ports[i];
2828 up->cur_iotype = 0xFF;
2829 }
2830
2831 serial8250_isa_init_ports();
2832
2833 for (i = 0; i < nr_uarts; i++) {
2834 struct uart_8250_port *up = &serial8250_ports[i];
2835
2836 up->port.dev = dev;
2837
2838 if (up->port.flags & UPF_FIXED_TYPE)
2839 serial8250_init_fixed_type_port(up, up->port.type);
2840
2841 uart_add_one_port(drv, &up->port);
2842 }
2843 }
2844
2845 #ifdef CONFIG_SERIAL_8250_CONSOLE
2846
2847 static void serial8250_console_putchar(struct uart_port *port, int ch)
2848 {
2849 struct uart_8250_port *up =
2850 container_of(port, struct uart_8250_port, port);
2851
2852 wait_for_xmitr(up, UART_LSR_THRE);
2853 serial_out(up, UART_TX, ch);
2854 }
2855
2856 /*
2857 * Print a string to the serial port trying not to disturb
2858 * any possible real use of the port...
2859 *
2860 * The console_lock must be held when we get here.
2861 */
2862 static void
2863 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2864 {
2865 struct uart_8250_port *up = &serial8250_ports[co->index];
2866 unsigned long flags;
2867 unsigned int ier;
2868 int locked = 1;
2869
2870 touch_nmi_watchdog();
2871
2872 local_irq_save(flags);
2873 if (up->port.sysrq) {
2874 /* serial8250_handle_port() already took the lock */
2875 locked = 0;
2876 } else if (oops_in_progress) {
2877 locked = spin_trylock(&up->port.lock);
2878 } else
2879 spin_lock(&up->port.lock);
2880
2881 /*
2882 * First save the IER then disable the interrupts
2883 */
2884 ier = serial_in(up, UART_IER);
2885
2886 if (up->capabilities & UART_CAP_UUE)
2887 serial_out(up, UART_IER, UART_IER_UUE);
2888 else
2889 serial_out(up, UART_IER, 0);
2890
2891 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2892
2893 /*
2894 * Finally, wait for transmitter to become empty
2895 * and restore the IER
2896 */
2897 wait_for_xmitr(up, BOTH_EMPTY);
2898 serial_out(up, UART_IER, ier);
2899
2900 /*
2901 * The receive handling will happen properly because the
2902 * receive ready bit will still be set; it is not cleared
2903 * on read. However, modem control will not, we must
2904 * call it if we have saved something in the saved flags
2905 * while processing with interrupts off.
2906 */
2907 if (up->msr_saved_flags)
2908 check_modem_status(up);
2909
2910 if (locked)
2911 spin_unlock(&up->port.lock);
2912 local_irq_restore(flags);
2913 }
2914
2915 static int __init serial8250_console_setup(struct console *co, char *options)
2916 {
2917 struct uart_port *port;
2918 int baud = 9600;
2919 int bits = 8;
2920 int parity = 'n';
2921 int flow = 'n';
2922
2923 /*
2924 * Check whether an invalid uart number has been specified, and
2925 * if so, search for the first available port that does have
2926 * console support.
2927 */
2928 if (co->index >= nr_uarts)
2929 co->index = 0;
2930 port = &serial8250_ports[co->index].port;
2931 if (!port->iobase && !port->membase)
2932 return -ENODEV;
2933
2934 if (options)
2935 uart_parse_options(options, &baud, &parity, &bits, &flow);
2936
2937 return uart_set_options(port, co, baud, parity, bits, flow);
2938 }
2939
2940 static int serial8250_console_early_setup(void)
2941 {
2942 return serial8250_find_port_for_earlycon();
2943 }
2944
2945 static struct console serial8250_console = {
2946 .name = "ttyS",
2947 .write = serial8250_console_write,
2948 .device = uart_console_device,
2949 .setup = serial8250_console_setup,
2950 .early_setup = serial8250_console_early_setup,
2951 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2952 .index = -1,
2953 .data = &serial8250_reg,
2954 };
2955
2956 static int __init serial8250_console_init(void)
2957 {
2958 if (nr_uarts > UART_NR)
2959 nr_uarts = UART_NR;
2960
2961 serial8250_isa_init_ports();
2962 register_console(&serial8250_console);
2963 return 0;
2964 }
2965 console_initcall(serial8250_console_init);
2966
2967 int serial8250_find_port(struct uart_port *p)
2968 {
2969 int line;
2970 struct uart_port *port;
2971
2972 for (line = 0; line < nr_uarts; line++) {
2973 port = &serial8250_ports[line].port;
2974 if (uart_match_port(p, port))
2975 return line;
2976 }
2977 return -ENODEV;
2978 }
2979
2980 #define SERIAL8250_CONSOLE &serial8250_console
2981 #else
2982 #define SERIAL8250_CONSOLE NULL
2983 #endif
2984
2985 static struct uart_driver serial8250_reg = {
2986 .owner = THIS_MODULE,
2987 .driver_name = "serial",
2988 .dev_name = "ttyS",
2989 .major = TTY_MAJOR,
2990 .minor = 64,
2991 .cons = SERIAL8250_CONSOLE,
2992 };
2993
2994 /*
2995 * early_serial_setup - early registration for 8250 ports
2996 *
2997 * Setup an 8250 port structure prior to console initialisation. Use
2998 * after console initialisation will cause undefined behaviour.
2999 */
3000 int __init early_serial_setup(struct uart_port *port)
3001 {
3002 struct uart_port *p;
3003
3004 if (port->line >= ARRAY_SIZE(serial8250_ports))
3005 return -ENODEV;
3006
3007 serial8250_isa_init_ports();
3008 p = &serial8250_ports[port->line].port;
3009 p->iobase = port->iobase;
3010 p->membase = port->membase;
3011 p->irq = port->irq;
3012 p->irqflags = port->irqflags;
3013 p->uartclk = port->uartclk;
3014 p->fifosize = port->fifosize;
3015 p->regshift = port->regshift;
3016 p->iotype = port->iotype;
3017 p->flags = port->flags;
3018 p->mapbase = port->mapbase;
3019 p->private_data = port->private_data;
3020 p->type = port->type;
3021 p->line = port->line;
3022
3023 set_io_from_upio(p);
3024 if (port->serial_in)
3025 p->serial_in = port->serial_in;
3026 if (port->serial_out)
3027 p->serial_out = port->serial_out;
3028 if (port->handle_irq)
3029 p->handle_irq = port->handle_irq;
3030 else
3031 p->handle_irq = serial8250_default_handle_irq;
3032
3033 return 0;
3034 }
3035
3036 /**
3037 * serial8250_suspend_port - suspend one serial port
3038 * @line: serial line number
3039 *
3040 * Suspend one serial port.
3041 */
3042 void serial8250_suspend_port(int line)
3043 {
3044 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3045 }
3046
3047 /**
3048 * serial8250_resume_port - resume one serial port
3049 * @line: serial line number
3050 *
3051 * Resume one serial port.
3052 */
3053 void serial8250_resume_port(int line)
3054 {
3055 struct uart_8250_port *up = &serial8250_ports[line];
3056
3057 if (up->capabilities & UART_NATSEMI) {
3058 /* Ensure it's still in high speed mode */
3059 serial_outp(up, UART_LCR, 0xE0);
3060
3061 ns16550a_goto_highspeed(up);
3062
3063 serial_outp(up, UART_LCR, 0);
3064 up->port.uartclk = 921600*16;
3065 }
3066 uart_resume_port(&serial8250_reg, &up->port);
3067 }
3068
3069 /*
3070 * Register a set of serial devices attached to a platform device. The
3071 * list is terminated with a zero flags entry, which means we expect
3072 * all entries to have at least UPF_BOOT_AUTOCONF set.
3073 */
3074 static int __devinit serial8250_probe(struct platform_device *dev)
3075 {
3076 struct plat_serial8250_port *p = dev->dev.platform_data;
3077 struct uart_port port;
3078 int ret, i, irqflag = 0;
3079
3080 memset(&port, 0, sizeof(struct uart_port));
3081
3082 if (share_irqs)
3083 irqflag = IRQF_SHARED;
3084
3085 for (i = 0; p && p->flags != 0; p++, i++) {
3086 port.iobase = p->iobase;
3087 port.membase = p->membase;
3088 port.irq = p->irq;
3089 port.irqflags = p->irqflags;
3090 port.uartclk = p->uartclk;
3091 port.regshift = p->regshift;
3092 port.iotype = p->iotype;
3093 port.flags = p->flags;
3094 port.mapbase = p->mapbase;
3095 port.hub6 = p->hub6;
3096 port.private_data = p->private_data;
3097 port.type = p->type;
3098 port.serial_in = p->serial_in;
3099 port.serial_out = p->serial_out;
3100 port.handle_irq = p->handle_irq;
3101 port.set_termios = p->set_termios;
3102 port.pm = p->pm;
3103 port.dev = &dev->dev;
3104 port.irqflags |= irqflag;
3105 ret = serial8250_register_port(&port);
3106 if (ret < 0) {
3107 dev_err(&dev->dev, "unable to register port at index %d "
3108 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3109 p->iobase, (unsigned long long)p->mapbase,
3110 p->irq, ret);
3111 }
3112 }
3113 return 0;
3114 }
3115
3116 /*
3117 * Remove serial ports registered against a platform device.
3118 */
3119 static int __devexit serial8250_remove(struct platform_device *dev)
3120 {
3121 int i;
3122
3123 for (i = 0; i < nr_uarts; i++) {
3124 struct uart_8250_port *up = &serial8250_ports[i];
3125
3126 if (up->port.dev == &dev->dev)
3127 serial8250_unregister_port(i);
3128 }
3129 return 0;
3130 }
3131
3132 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3133 {
3134 int i;
3135
3136 for (i = 0; i < UART_NR; i++) {
3137 struct uart_8250_port *up = &serial8250_ports[i];
3138
3139 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3140 uart_suspend_port(&serial8250_reg, &up->port);
3141 }
3142
3143 return 0;
3144 }
3145
3146 static int serial8250_resume(struct platform_device *dev)
3147 {
3148 int i;
3149
3150 for (i = 0; i < UART_NR; i++) {
3151 struct uart_8250_port *up = &serial8250_ports[i];
3152
3153 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3154 serial8250_resume_port(i);
3155 }
3156
3157 return 0;
3158 }
3159
3160 static struct platform_driver serial8250_isa_driver = {
3161 .probe = serial8250_probe,
3162 .remove = __devexit_p(serial8250_remove),
3163 .suspend = serial8250_suspend,
3164 .resume = serial8250_resume,
3165 .driver = {
3166 .name = "serial8250",
3167 .owner = THIS_MODULE,
3168 },
3169 };
3170
3171 /*
3172 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3173 * in the table in include/asm/serial.h
3174 */
3175 static struct platform_device *serial8250_isa_devs;
3176
3177 /*
3178 * serial8250_register_port and serial8250_unregister_port allows for
3179 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3180 * modems and PCI multiport cards.
3181 */
3182 static DEFINE_MUTEX(serial_mutex);
3183
3184 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3185 {
3186 int i;
3187
3188 /*
3189 * First, find a port entry which matches.
3190 */
3191 for (i = 0; i < nr_uarts; i++)
3192 if (uart_match_port(&serial8250_ports[i].port, port))
3193 return &serial8250_ports[i];
3194
3195 /*
3196 * We didn't find a matching entry, so look for the first
3197 * free entry. We look for one which hasn't been previously
3198 * used (indicated by zero iobase).
3199 */
3200 for (i = 0; i < nr_uarts; i++)
3201 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3202 serial8250_ports[i].port.iobase == 0)
3203 return &serial8250_ports[i];
3204
3205 /*
3206 * That also failed. Last resort is to find any entry which
3207 * doesn't have a real port associated with it.
3208 */
3209 for (i = 0; i < nr_uarts; i++)
3210 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3211 return &serial8250_ports[i];
3212
3213 return NULL;
3214 }
3215
3216 /**
3217 * serial8250_register_port - register a serial port
3218 * @port: serial port template
3219 *
3220 * Configure the serial port specified by the request. If the
3221 * port exists and is in use, it is hung up and unregistered
3222 * first.
3223 *
3224 * The port is then probed and if necessary the IRQ is autodetected
3225 * If this fails an error is returned.
3226 *
3227 * On success the port is ready to use and the line number is returned.
3228 */
3229 int serial8250_register_port(struct uart_port *port)
3230 {
3231 struct uart_8250_port *uart;
3232 int ret = -ENOSPC;
3233
3234 if (port->uartclk == 0)
3235 return -EINVAL;
3236
3237 mutex_lock(&serial_mutex);
3238
3239 uart = serial8250_find_match_or_unused(port);
3240 if (uart) {
3241 uart_remove_one_port(&serial8250_reg, &uart->port);
3242
3243 uart->port.iobase = port->iobase;
3244 uart->port.membase = port->membase;
3245 uart->port.irq = port->irq;
3246 uart->port.irqflags = port->irqflags;
3247 uart->port.uartclk = port->uartclk;
3248 uart->port.fifosize = port->fifosize;
3249 uart->port.regshift = port->regshift;
3250 uart->port.iotype = port->iotype;
3251 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3252 uart->port.mapbase = port->mapbase;
3253 uart->port.private_data = port->private_data;
3254 if (port->dev)
3255 uart->port.dev = port->dev;
3256
3257 if (port->flags & UPF_FIXED_TYPE)
3258 serial8250_init_fixed_type_port(uart, port->type);
3259
3260 set_io_from_upio(&uart->port);
3261 /* Possibly override default I/O functions. */
3262 if (port->serial_in)
3263 uart->port.serial_in = port->serial_in;
3264 if (port->serial_out)
3265 uart->port.serial_out = port->serial_out;
3266 if (port->handle_irq)
3267 uart->port.handle_irq = port->handle_irq;
3268 /* Possibly override set_termios call */
3269 if (port->set_termios)
3270 uart->port.set_termios = port->set_termios;
3271 if (port->pm)
3272 uart->port.pm = port->pm;
3273
3274 if (serial8250_isa_config != NULL)
3275 serial8250_isa_config(0, &uart->port,
3276 &uart->capabilities);
3277
3278 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3279 if (ret == 0)
3280 ret = uart->port.line;
3281 }
3282 mutex_unlock(&serial_mutex);
3283
3284 return ret;
3285 }
3286 EXPORT_SYMBOL(serial8250_register_port);
3287
3288 /**
3289 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3290 * @line: serial line number
3291 *
3292 * Remove one serial port. This may not be called from interrupt
3293 * context. We hand the port back to the our control.
3294 */
3295 void serial8250_unregister_port(int line)
3296 {
3297 struct uart_8250_port *uart = &serial8250_ports[line];
3298
3299 mutex_lock(&serial_mutex);
3300 uart_remove_one_port(&serial8250_reg, &uart->port);
3301 if (serial8250_isa_devs) {
3302 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3303 uart->port.type = PORT_UNKNOWN;
3304 uart->port.dev = &serial8250_isa_devs->dev;
3305 uart->capabilities = uart_config[uart->port.type].flags;
3306 uart_add_one_port(&serial8250_reg, &uart->port);
3307 } else {
3308 uart->port.dev = NULL;
3309 }
3310 mutex_unlock(&serial_mutex);
3311 }
3312 EXPORT_SYMBOL(serial8250_unregister_port);
3313
3314 static int __init serial8250_init(void)
3315 {
3316 int ret;
3317
3318 if (nr_uarts > UART_NR)
3319 nr_uarts = UART_NR;
3320
3321 printk(KERN_INFO "Serial: 8250/16550 driver, "
3322 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3323 share_irqs ? "en" : "dis");
3324
3325 #ifdef CONFIG_SPARC
3326 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3327 #else
3328 serial8250_reg.nr = UART_NR;
3329 ret = uart_register_driver(&serial8250_reg);
3330 #endif
3331 if (ret)
3332 goto out;
3333
3334 serial8250_isa_devs = platform_device_alloc("serial8250",
3335 PLAT8250_DEV_LEGACY);
3336 if (!serial8250_isa_devs) {
3337 ret = -ENOMEM;
3338 goto unreg_uart_drv;
3339 }
3340
3341 ret = platform_device_add(serial8250_isa_devs);
3342 if (ret)
3343 goto put_dev;
3344
3345 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3346
3347 ret = platform_driver_register(&serial8250_isa_driver);
3348 if (ret == 0)
3349 goto out;
3350
3351 platform_device_del(serial8250_isa_devs);
3352 put_dev:
3353 platform_device_put(serial8250_isa_devs);
3354 unreg_uart_drv:
3355 #ifdef CONFIG_SPARC
3356 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3357 #else
3358 uart_unregister_driver(&serial8250_reg);
3359 #endif
3360 out:
3361 return ret;
3362 }
3363
3364 static void __exit serial8250_exit(void)
3365 {
3366 struct platform_device *isa_dev = serial8250_isa_devs;
3367
3368 /*
3369 * This tells serial8250_unregister_port() not to re-register
3370 * the ports (thereby making serial8250_isa_driver permanently
3371 * in use.)
3372 */
3373 serial8250_isa_devs = NULL;
3374
3375 platform_driver_unregister(&serial8250_isa_driver);
3376 platform_device_unregister(isa_dev);
3377
3378 #ifdef CONFIG_SPARC
3379 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3380 #else
3381 uart_unregister_driver(&serial8250_reg);
3382 #endif
3383 }
3384
3385 module_init(serial8250_init);
3386 module_exit(serial8250_exit);
3387
3388 EXPORT_SYMBOL(serial8250_suspend_port);
3389 EXPORT_SYMBOL(serial8250_resume_port);
3390
3391 MODULE_LICENSE("GPL");
3392 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3393
3394 module_param(share_irqs, uint, 0644);
3395 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3396 " (unsafe)");
3397
3398 module_param(nr_uarts, uint, 0644);
3399 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3400
3401 module_param(skip_txen_test, uint, 0644);
3402 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3403
3404 #ifdef CONFIG_SERIAL_8250_RSA
3405 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3406 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3407 #endif
3408 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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