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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / tty / serial / max3107.c
blobdb00b595cab08eba2edc1d6295b6b66946becaf7
1 /*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/gpio.h>
37 #include <linux/spi/spi.h>
38 #include <linux/freezer.h>
39 #include "max3107.h"
40
41 static const struct baud_table brg26_ext[] = {
42 { 300, MAX3107_BRG26_B300 },
43 { 600, MAX3107_BRG26_B600 },
44 { 1200, MAX3107_BRG26_B1200 },
45 { 2400, MAX3107_BRG26_B2400 },
46 { 4800, MAX3107_BRG26_B4800 },
47 { 9600, MAX3107_BRG26_B9600 },
48 { 19200, MAX3107_BRG26_B19200 },
49 { 57600, MAX3107_BRG26_B57600 },
50 { 115200, MAX3107_BRG26_B115200 },
51 { 230400, MAX3107_BRG26_B230400 },
52 { 460800, MAX3107_BRG26_B460800 },
53 { 921600, MAX3107_BRG26_B921600 },
54 { 0, 0 }
55 };
56
57 static const struct baud_table brg13_int[] = {
58 { 300, MAX3107_BRG13_IB300 },
59 { 600, MAX3107_BRG13_IB600 },
60 { 1200, MAX3107_BRG13_IB1200 },
61 { 2400, MAX3107_BRG13_IB2400 },
62 { 4800, MAX3107_BRG13_IB4800 },
63 { 9600, MAX3107_BRG13_IB9600 },
64 { 19200, MAX3107_BRG13_IB19200 },
65 { 57600, MAX3107_BRG13_IB57600 },
66 { 115200, MAX3107_BRG13_IB115200 },
67 { 230400, MAX3107_BRG13_IB230400 },
68 { 460800, MAX3107_BRG13_IB460800 },
69 { 921600, MAX3107_BRG13_IB921600 },
70 { 0, 0 }
71 };
72
73 static u32 get_new_brg(int baud, struct max3107_port *s)
74 {
75 int i;
76 const struct baud_table *baud_tbl = s->baud_tbl;
77
78 for (i = 0; i < 13; i++) {
79 if (baud == baud_tbl[i].baud)
80 return baud_tbl[i].new_brg;
81 }
82
83 return 0;
84 }
85
86 /* Perform SPI transfer for write/read of device register(s) */
87 int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
88 {
89 struct spi_message spi_msg;
90 struct spi_transfer spi_xfer;
91
92 /* Initialize SPI ,message */
93 spi_message_init(&spi_msg);
94
95 /* Initialize SPI transfer */
96 memset(&spi_xfer, 0, sizeof spi_xfer);
97 spi_xfer.len = len;
98 spi_xfer.tx_buf = tx;
99 spi_xfer.rx_buf = rx;
100 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
101
102 /* Add SPI transfer to SPI message */
103 spi_message_add_tail(&spi_xfer, &spi_msg);
104
105 #ifdef DBG_TRACE_SPI_DATA
106 {
107 int i;
108 pr_info("tx len %d:\n", spi_xfer.len);
109 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
110 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
111 pr_info("\n");
112 }
113 #endif
114
115 /* Perform synchronous SPI transfer */
116 if (spi_sync(s->spi, &spi_msg)) {
117 dev_err(&s->spi->dev, "spi_sync failure\n");
118 return -EIO;
119 }
120
121 #ifdef DBG_TRACE_SPI_DATA
122 if (spi_xfer.rx_buf) {
123 int i;
124 pr_info("rx len %d:\n", spi_xfer.len);
125 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
126 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
127 pr_info("\n");
128 }
129 #endif
130 return 0;
131 }
132 EXPORT_SYMBOL_GPL(max3107_rw);
133
134 /* Puts received data to circular buffer */
135 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
136 int len)
137 {
138 struct uart_port *port = &s->port;
139 struct tty_struct *tty;
140
141 if (!port->state)
142 return;
143
144 tty = port->state->port.tty;
145 if (!tty)
146 return;
147
148 /* Insert received data */
149 tty_insert_flip_string(tty, data, len);
150 /* Update RX counter */
151 port->icount.rx += len;
152 }
153
154 /* Handle data receiving */
155 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
156 {
157 int i;
158 int j;
159 int len; /* SPI transfer buffer length */
160 u16 *buf;
161 u8 *valid_str;
162
163 if (!s->rx_enabled)
164 /* RX is disabled */
165 return;
166
167 if (rxlvl == 0) {
168 /* RX fifo is empty */
169 return;
170 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
171 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
172 /* Ensure sanity of RX level */
173 rxlvl = MAX3107_RX_FIFO_SIZE;
174 }
175 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
176 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
177 return;
178 }
179 buf = s->rxbuf;
180 valid_str = s->rxstr;
181 while (rxlvl) {
182 pr_debug("rxlvl %d\n", rxlvl);
183 /* Clear buffer */
184 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
185 len = 0;
186 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
187 /* First disable RX FIFO interrupt */
188 pr_debug("Disabling RX INT\n");
189 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
190 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
191 buf[0] |= s->irqen_reg;
192 len++;
193 }
194 /* Just increase the length by amount of words in FIFO since
195 * buffer was zeroed and SPI transfer of 0x0000 means reading
196 * from RX FIFO
197 */
198 len += rxlvl;
199 /* Append RX level query */
200 buf[len] = MAX3107_RXFIFOLVL_REG;
201 len++;
202
203 /* Perform the SPI transfer */
204 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
205 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
206 return;
207 }
208
209 /* Skip RX FIFO interrupt disabling word if it was added */
210 j = ((len - 1) - rxlvl);
211 /* Read received words */
212 for (i = 0; i < rxlvl; i++, j++)
213 valid_str[i] = (u8)buf[j];
214 put_data_to_circ_buf(s, valid_str, rxlvl);
215 /* Get new RX level */
216 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
217 }
218
219 if (s->rx_enabled) {
220 /* RX still enabled, re-enable RX FIFO interrupt */
221 pr_debug("Enabling RX INT\n");
222 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
223 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
224 buf[0] |= s->irqen_reg;
225 if (max3107_rw(s, (u8 *)buf, NULL, 2))
226 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
227 }
228
229 /* Push the received data to receivers */
230 if (s->port.state->port.tty)
231 tty_flip_buffer_push(s->port.state->port.tty);
232 }
233
234
235 /* Handle data sending */
236 static void max3107_handletx(struct max3107_port *s)
237 {
238 struct circ_buf *xmit = &s->port.state->xmit;
239 int i;
240 unsigned long flags;
241 int len; /* SPI transfer buffer length */
242 u16 *buf;
243
244 if (!s->tx_fifo_empty)
245 /* Don't send more data before previous data is sent */
246 return;
247
248 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
249 /* No data to send or TX is stopped */
250 return;
251
252 if (!s->txbuf) {
253 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
254 return;
255 }
256 buf = s->txbuf;
257 /* Get length of data pending in circular buffer */
258 len = uart_circ_chars_pending(xmit);
259 if (len) {
260 /* Limit to size of TX FIFO */
261 if (len > MAX3107_TX_FIFO_SIZE)
262 len = MAX3107_TX_FIFO_SIZE;
263
264 pr_debug("txlen %d\n", len);
265
266 /* Update TX counter */
267 s->port.icount.tx += len;
268
269 /* TX FIFO will no longer be empty */
270 s->tx_fifo_empty = 0;
271
272 i = 0;
273 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
274 /* First disable TX empty interrupt */
275 pr_debug("Disabling TE INT\n");
276 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
277 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
278 buf[i] |= s->irqen_reg;
279 i++;
280 len++;
281 }
282 /* Add data to send */
283 spin_lock_irqsave(&s->port.lock, flags);
284 for ( ; i < len ; i++) {
285 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
286 buf[i] |= ((u16)xmit->buf[xmit->tail] &
287 MAX3107_SPI_TX_DATA_MASK);
288 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
289 }
290 spin_unlock_irqrestore(&s->port.lock, flags);
291 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
292 /* Enable TX empty interrupt */
293 pr_debug("Enabling TE INT\n");
294 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
295 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
296 buf[i] |= s->irqen_reg;
297 i++;
298 len++;
299 }
300 if (!s->tx_enabled) {
301 /* Enable TX */
302 pr_debug("Enable TX\n");
303 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
304 spin_lock_irqsave(&s->data_lock, flags);
305 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
306 buf[i] |= s->mode1_reg;
307 spin_unlock_irqrestore(&s->data_lock, flags);
308 s->tx_enabled = 1;
309 i++;
310 len++;
311 }
312
313 /* Perform the SPI transfer */
314 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
315 dev_err(&s->spi->dev,
316 "SPI transfer TX handling failed\n");
317 return;
318 }
319 }
320
321 /* Indicate wake up if circular buffer is getting low on data */
322 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
323 uart_write_wakeup(&s->port);
324
325 }
326
327 /* Handle interrupts
328 * Also reads and returns current RX FIFO level
329 */
330 static u16 handle_interrupt(struct max3107_port *s)
331 {
332 u16 buf[4]; /* Buffer for SPI transfers */
333 u8 irq_status;
334 u16 rx_level;
335 unsigned long flags;
336
337 /* Read IRQ status register */
338 buf[0] = MAX3107_IRQSTS_REG;
339 /* Read status IRQ status register */
340 buf[1] = MAX3107_STS_IRQSTS_REG;
341 /* Read LSR IRQ status register */
342 buf[2] = MAX3107_LSR_IRQSTS_REG;
343 /* Query RX level */
344 buf[3] = MAX3107_RXFIFOLVL_REG;
345
346 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
347 dev_err(&s->spi->dev,
348 "SPI transfer for INTR handling failed\n");
349 return 0;
350 }
351
352 irq_status = (u8)buf[0];
353 pr_debug("IRQSTS %x\n", irq_status);
354 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
355
356 if (irq_status & MAX3107_IRQ_LSR_BIT) {
357 /* LSR interrupt */
358 if (buf[2] & MAX3107_LSR_RXTO_BIT)
359 /* RX timeout interrupt,
360 * handled by normal RX handling
361 */
362 pr_debug("RX TO INT\n");
363 }
364
365 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
366 /* Tx empty interrupt,
367 * disable TX and set tx_fifo_empty flag
368 */
369 pr_debug("TE INT, disabling TX\n");
370 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
371 spin_lock_irqsave(&s->data_lock, flags);
372 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
373 buf[0] |= s->mode1_reg;
374 spin_unlock_irqrestore(&s->data_lock, flags);
375 if (max3107_rw(s, (u8 *)buf, NULL, 2))
376 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
377 s->tx_enabled = 0;
378 s->tx_fifo_empty = 1;
379 }
380
381 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
382 /* RX FIFO interrupt,
383 * handled by normal RX handling
384 */
385 pr_debug("RFIFO INT\n");
386
387 /* Return RX level */
388 return rx_level;
389 }
390
391 /* Trigger work thread*/
392 static void max3107_dowork(struct max3107_port *s)
393 {
394 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
395 queue_work(s->workqueue, &s->work);
396 else
397 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
398 }
399
400 /* Work thread */
401 static void max3107_work(struct work_struct *w)
402 {
403 struct max3107_port *s = container_of(w, struct max3107_port, work);
404 u16 rxlvl = 0;
405 int len; /* SPI transfer buffer length */
406 u16 buf[5]; /* Buffer for SPI transfers */
407 unsigned long flags;
408
409 /* Start by reading current RX FIFO level */
410 buf[0] = MAX3107_RXFIFOLVL_REG;
411 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
412 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
413 rxlvl = 0;
414 } else {
415 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
416 }
417
418 do {
419 pr_debug("rxlvl %d\n", rxlvl);
420
421 /* Handle RX */
422 max3107_handlerx(s, rxlvl);
423 rxlvl = 0;
424
425 if (s->handle_irq) {
426 /* Handle pending interrupts
427 * We also get new RX FIFO level since new data may
428 * have been received while pushing received data to
429 * receivers
430 */
431 s->handle_irq = 0;
432 rxlvl = handle_interrupt(s);
433 }
434
435 /* Handle TX */
436 max3107_handletx(s);
437
438 /* Handle configuration changes */
439 len = 0;
440 spin_lock_irqsave(&s->data_lock, flags);
441 if (s->mode1_commit) {
442 pr_debug("mode1_commit\n");
443 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
444 buf[len++] |= s->mode1_reg;
445 s->mode1_commit = 0;
446 }
447 if (s->lcr_commit) {
448 pr_debug("lcr_commit\n");
449 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
450 buf[len++] |= s->lcr_reg;
451 s->lcr_commit = 0;
452 }
453 if (s->brg_commit) {
454 pr_debug("brg_commit\n");
455 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
456 buf[len++] |= ((s->brg_cfg >> 16) &
457 MAX3107_SPI_TX_DATA_MASK);
458 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
459 buf[len++] |= ((s->brg_cfg >> 8) &
460 MAX3107_SPI_TX_DATA_MASK);
461 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
462 buf[len++] |= ((s->brg_cfg) & 0xff);
463 s->brg_commit = 0;
464 }
465 spin_unlock_irqrestore(&s->data_lock, flags);
466
467 if (len > 0) {
468 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
469 dev_err(&s->spi->dev,
470 "SPI transfer config failed\n");
471 }
472
473 /* Reloop if interrupt handling indicated data in RX FIFO */
474 } while (rxlvl);
475
476 }
477
478 /* Set sleep mode */
479 static void max3107_set_sleep(struct max3107_port *s, int mode)
480 {
481 u16 buf[1]; /* Buffer for SPI transfer */
482 unsigned long flags;
483 pr_debug("enter, mode %d\n", mode);
484
485 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
486 spin_lock_irqsave(&s->data_lock, flags);
487 switch (mode) {
488 case MAX3107_DISABLE_FORCED_SLEEP:
489 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
490 break;
491 case MAX3107_ENABLE_FORCED_SLEEP:
492 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
493 break;
494 case MAX3107_DISABLE_AUTOSLEEP:
495 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
496 break;
497 case MAX3107_ENABLE_AUTOSLEEP:
498 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
499 break;
500 default:
501 spin_unlock_irqrestore(&s->data_lock, flags);
502 dev_warn(&s->spi->dev, "invalid sleep mode\n");
503 return;
504 }
505 buf[0] |= s->mode1_reg;
506 spin_unlock_irqrestore(&s->data_lock, flags);
507
508 if (max3107_rw(s, (u8 *)buf, NULL, 2))
509 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
510
511 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
512 mode == MAX3107_DISABLE_FORCED_SLEEP)
513 msleep(MAX3107_WAKEUP_DELAY);
514 }
515
516 /* Perform full register initialization */
517 static void max3107_register_init(struct max3107_port *s)
518 {
519 u16 buf[11]; /* Buffer for SPI transfers */
520
521 /* 1. Configure baud rate, 9600 as default */
522 s->baud = 9600;
523 /* the below is default*/
524 if (s->ext_clk) {
525 s->brg_cfg = MAX3107_BRG26_B9600;
526 s->baud_tbl = (struct baud_table *)brg26_ext;
527 } else {
528 s->brg_cfg = MAX3107_BRG13_IB9600;
529 s->baud_tbl = (struct baud_table *)brg13_int;
530 }
531
532 if (s->pdata->init)
533 s->pdata->init(s);
534
535 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
536 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
537 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
538 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
539 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
540 | ((s->brg_cfg) & 0xff);
541
542 /* 2. Configure LCR register, 8N1 mode by default */
543 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
544 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
545 | s->lcr_reg;
546
547 /* 3. Configure MODE 1 register */
548 s->mode1_reg = 0;
549 /* Enable IRQ pin */
550 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
551 /* Disable TX */
552 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
553 s->tx_enabled = 0;
554 /* RX is enabled */
555 s->rx_enabled = 1;
556 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
557 | s->mode1_reg;
558
559 /* 4. Configure MODE 2 register */
560 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
561 if (s->loopback) {
562 /* Enable loopback */
563 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
564 }
565 /* Reset FIFOs */
566 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
567 s->tx_fifo_empty = 1;
568
569 /* 5. Configure FIFO trigger level register */
570 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
571 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
572 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
573
574 /* 6. Configure flow control levels */
575 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
576 /* Flow control halt level 96, resume level 48 */
577 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
578
579 /* 7. Configure flow control */
580 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
581 /* Enable auto CTS and auto RTS flow control */
582 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
583
584 /* 8. Configure RX timeout register */
585 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
586 /* Timeout after 48 character intervals */
587 buf[9] |= 0x0030;
588
589 /* 9. Configure LSR interrupt enable register */
590 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
591 /* Enable RX timeout interrupt */
592 buf[10] |= MAX3107_LSR_RXTO_BIT;
593
594 /* Perform SPI transfer */
595 if (max3107_rw(s, (u8 *)buf, NULL, 22))
596 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
597
598 /* 10. Clear IRQ status register by reading it */
599 buf[0] = MAX3107_IRQSTS_REG;
600
601 /* 11. Configure interrupt enable register */
602 /* Enable LSR interrupt */
603 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
604 /* Enable RX FIFO interrupt */
605 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
606 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
607 | s->irqen_reg;
608
609 /* 12. Clear FIFO reset that was set in step 6 */
610 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
611 if (s->loopback) {
612 /* Keep loopback enabled */
613 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
614 }
615
616 /* Perform SPI transfer */
617 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
618 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
619
620 }
621
622 /* IRQ handler */
623 static irqreturn_t max3107_irq(int irqno, void *dev_id)
624 {
625 struct max3107_port *s = dev_id;
626
627 if (irqno != s->spi->irq) {
628 /* Unexpected IRQ */
629 return IRQ_NONE;
630 }
631
632 /* Indicate irq */
633 s->handle_irq = 1;
634
635 /* Trigger work thread */
636 max3107_dowork(s);
637
638 return IRQ_HANDLED;
639 }
640
641 /* HW suspension function
642 *
643 * Currently autosleep is used to decrease current consumption, alternative
644 * approach would be to set the chip to reset mode if UART is not being
645 * used but that would mess the GPIOs
646 *
647 */
648 void max3107_hw_susp(struct max3107_port *s, int suspend)
649 {
650 pr_debug("enter, suspend %d\n", suspend);
651
652 if (suspend) {
653 /* Suspend requested,
654 * enable autosleep to decrease current consumption
655 */
656 s->suspended = 1;
657 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
658 } else {
659 /* Resume requested,
660 * disable autosleep
661 */
662 s->suspended = 0;
663 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
664 }
665 }
666 EXPORT_SYMBOL_GPL(max3107_hw_susp);
667
668 /* Modem status IRQ enabling */
669 static void max3107_enable_ms(struct uart_port *port)
670 {
671 /* Modem status not supported */
672 }
673
674 /* Data send function */
675 static void max3107_start_tx(struct uart_port *port)
676 {
677 struct max3107_port *s = container_of(port, struct max3107_port, port);
678
679 /* Trigger work thread for sending data */
680 max3107_dowork(s);
681 }
682
683 /* Function for checking that there is no pending transfers */
684 static unsigned int max3107_tx_empty(struct uart_port *port)
685 {
686 struct max3107_port *s = container_of(port, struct max3107_port, port);
687
688 pr_debug("returning %d\n",
689 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
690 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
691 }
692
693 /* Function for stopping RX */
694 static void max3107_stop_rx(struct uart_port *port)
695 {
696 struct max3107_port *s = container_of(port, struct max3107_port, port);
697 unsigned long flags;
698
699 /* Set RX disabled in MODE 1 register */
700 spin_lock_irqsave(&s->data_lock, flags);
701 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
702 s->mode1_commit = 1;
703 spin_unlock_irqrestore(&s->data_lock, flags);
704 /* Set RX disabled */
705 s->rx_enabled = 0;
706 /* Trigger work thread for doing the actual configuration change */
707 max3107_dowork(s);
708 }
709
710 /* Function for returning control pin states */
711 static unsigned int max3107_get_mctrl(struct uart_port *port)
712 {
713 /* DCD and DSR are not wired and CTS/RTS is handled automatically
714 * so just indicate DSR and CAR asserted
715 */
716 return TIOCM_DSR | TIOCM_CAR;
717 }
718
719 /* Function for setting control pin states */
720 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
721 {
722 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
723 * so do nothing
724 */
725 }
726
727 /* Function for configuring UART parameters */
728 static void max3107_set_termios(struct uart_port *port,
729 struct ktermios *termios,
730 struct ktermios *old)
731 {
732 struct max3107_port *s = container_of(port, struct max3107_port, port);
733 struct tty_struct *tty;
734 int baud;
735 u16 new_lcr = 0;
736 u32 new_brg = 0;
737 unsigned long flags;
738
739 if (!port->state)
740 return;
741
742 tty = port->state->port.tty;
743 if (!tty)
744 return;
745
746 /* Get new LCR register values */
747 /* Word size */
748 if ((termios->c_cflag & CSIZE) == CS7)
749 new_lcr |= MAX3107_LCR_WORD_LEN_7;
750 else
751 new_lcr |= MAX3107_LCR_WORD_LEN_8;
752
753 /* Parity */
754 if (termios->c_cflag & PARENB) {
755 new_lcr |= MAX3107_LCR_PARITY_BIT;
756 if (!(termios->c_cflag & PARODD))
757 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
758 }
759
760 /* Stop bits */
761 if (termios->c_cflag & CSTOPB) {
762 /* 2 stop bits */
763 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
764 }
765
766 /* Mask termios capabilities we don't support */
767 termios->c_cflag &= ~CMSPAR;
768
769 /* Set status ignore mask */
770 s->port.ignore_status_mask = 0;
771 if (termios->c_iflag & IGNPAR)
772 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
773
774 /* Set low latency to immediately handle pushed data */
775 s->port.state->port.tty->low_latency = 1;
776
777 /* Get new baud rate generator configuration */
778 baud = tty_get_baud_rate(tty);
779
780 spin_lock_irqsave(&s->data_lock, flags);
781 new_brg = get_new_brg(baud, s);
782 /* if can't find the corrent config, use previous */
783 if (!new_brg) {
784 baud = s->baud;
785 new_brg = s->brg_cfg;
786 }
787 spin_unlock_irqrestore(&s->data_lock, flags);
788 tty_termios_encode_baud_rate(termios, baud, baud);
789 s->baud = baud;
790
791 /* Update timeout according to new baud rate */
792 uart_update_timeout(port, termios->c_cflag, baud);
793
794 spin_lock_irqsave(&s->data_lock, flags);
795 if (s->lcr_reg != new_lcr) {
796 s->lcr_reg = new_lcr;
797 s->lcr_commit = 1;
798 }
799 if (s->brg_cfg != new_brg) {
800 s->brg_cfg = new_brg;
801 s->brg_commit = 1;
802 }
803 spin_unlock_irqrestore(&s->data_lock, flags);
804
805 /* Trigger work thread for doing the actual configuration change */
806 max3107_dowork(s);
807 }
808
809 /* Port shutdown function */
810 static void max3107_shutdown(struct uart_port *port)
811 {
812 struct max3107_port *s = container_of(port, struct max3107_port, port);
813
814 if (s->suspended && s->pdata->hw_suspend)
815 s->pdata->hw_suspend(s, 0);
816
817 /* Free the interrupt */
818 free_irq(s->spi->irq, s);
819
820 if (s->workqueue) {
821 /* Flush and destroy work queue */
822 flush_workqueue(s->workqueue);
823 destroy_workqueue(s->workqueue);
824 s->workqueue = NULL;
825 }
826
827 /* Suspend HW */
828 if (s->pdata->hw_suspend)
829 s->pdata->hw_suspend(s, 1);
830 }
831
832 /* Port startup function */
833 static int max3107_startup(struct uart_port *port)
834 {
835 struct max3107_port *s = container_of(port, struct max3107_port, port);
836
837 /* Initialize work queue */
838 s->workqueue = create_freezable_workqueue("max3107");
839 if (!s->workqueue) {
840 dev_err(&s->spi->dev, "Workqueue creation failed\n");
841 return -EBUSY;
842 }
843 INIT_WORK(&s->work, max3107_work);
844
845 /* Setup IRQ */
846 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
847 "max3107", s)) {
848 dev_err(&s->spi->dev, "IRQ reguest failed\n");
849 destroy_workqueue(s->workqueue);
850 s->workqueue = NULL;
851 return -EBUSY;
852 }
853
854 /* Resume HW */
855 if (s->pdata->hw_suspend)
856 s->pdata->hw_suspend(s, 0);
857
858 /* Init registers */
859 max3107_register_init(s);
860
861 return 0;
862 }
863
864 /* Port type function */
865 static const char *max3107_type(struct uart_port *port)
866 {
867 struct max3107_port *s = container_of(port, struct max3107_port, port);
868 return s->spi->modalias;
869 }
870
871 /* Port release function */
872 static void max3107_release_port(struct uart_port *port)
873 {
874 /* Do nothing */
875 }
876
877 /* Port request function */
878 static int max3107_request_port(struct uart_port *port)
879 {
880 /* Do nothing */
881 return 0;
882 }
883
884 /* Port config function */
885 static void max3107_config_port(struct uart_port *port, int flags)
886 {
887 struct max3107_port *s = container_of(port, struct max3107_port, port);
888 s->port.type = PORT_MAX3107;
889 }
890
891 /* Port verify function */
892 static int max3107_verify_port(struct uart_port *port,
893 struct serial_struct *ser)
894 {
895 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
896 return 0;
897
898 return -EINVAL;
899 }
900
901 /* Port stop TX function */
902 static void max3107_stop_tx(struct uart_port *port)
903 {
904 /* Do nothing */
905 }
906
907 /* Port break control function */
908 static void max3107_break_ctl(struct uart_port *port, int break_state)
909 {
910 /* We don't support break control, do nothing */
911 }
912
913
914 /* Port functions */
915 static struct uart_ops max3107_ops = {
916 .tx_empty = max3107_tx_empty,
917 .set_mctrl = max3107_set_mctrl,
918 .get_mctrl = max3107_get_mctrl,
919 .stop_tx = max3107_stop_tx,
920 .start_tx = max3107_start_tx,
921 .stop_rx = max3107_stop_rx,
922 .enable_ms = max3107_enable_ms,
923 .break_ctl = max3107_break_ctl,
924 .startup = max3107_startup,
925 .shutdown = max3107_shutdown,
926 .set_termios = max3107_set_termios,
927 .type = max3107_type,
928 .release_port = max3107_release_port,
929 .request_port = max3107_request_port,
930 .config_port = max3107_config_port,
931 .verify_port = max3107_verify_port,
932 };
933
934 /* UART driver data */
935 static struct uart_driver max3107_uart_driver = {
936 .owner = THIS_MODULE,
937 .driver_name = "ttyMAX",
938 .dev_name = "ttyMAX",
939 .nr = 1,
940 };
941
942 static int driver_registered = 0;
943
944
945
946 /* 'Generic' platform data */
947 static struct max3107_plat generic_plat_data = {
948 .loopback = 0,
949 .ext_clk = 1,
950 .hw_suspend = max3107_hw_susp,
951 .polled_mode = 0,
952 .poll_time = 0,
953 };
954
955
956 /*******************************************************************/
957
958 /**
959 * max3107_probe - SPI bus probe entry point
960 * @spi: the spi device
961 *
962 * SPI wants us to probe this device and if appropriate claim it.
963 * Perform any platform specific requirements and then initialise
964 * the device.
965 */
966
967 int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
968 {
969 struct max3107_port *s;
970 u16 buf[2]; /* Buffer for SPI transfers */
971 int retval;
972
973 pr_info("enter max3107 probe\n");
974
975 /* Allocate port structure */
976 s = kzalloc(sizeof(*s), GFP_KERNEL);
977 if (!s) {
978 pr_err("Allocating port structure failed\n");
979 return -ENOMEM;
980 }
981
982 s->pdata = pdata;
983
984 /* SPI Rx buffer
985 * +2 for RX FIFO interrupt
986 * disabling and RX level query
987 */
988 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
989 if (!s->rxbuf) {
990 pr_err("Allocating RX buffer failed\n");
991 retval = -ENOMEM;
992 goto err_free4;
993 }
994 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
995 if (!s->rxstr) {
996 pr_err("Allocating RX buffer failed\n");
997 retval = -ENOMEM;
998 goto err_free3;
999 }
1000 /* SPI Tx buffer
1001 * SPI transfer buffer
1002 * +3 for TX FIFO empty
1003 * interrupt disabling and
1004 * enabling and TX enabling
1005 */
1006 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1007 if (!s->txbuf) {
1008 pr_err("Allocating TX buffer failed\n");
1009 retval = -ENOMEM;
1010 goto err_free2;
1011 }
1012 /* Initialize shared data lock */
1013 spin_lock_init(&s->data_lock);
1014
1015 /* SPI intializations */
1016 dev_set_drvdata(&spi->dev, s);
1017 spi->mode = SPI_MODE_0;
1018 spi->dev.platform_data = pdata;
1019 spi->bits_per_word = 16;
1020 s->ext_clk = pdata->ext_clk;
1021 s->loopback = pdata->loopback;
1022 spi_setup(spi);
1023 s->spi = spi;
1024
1025 /* Check REV ID to ensure we are talking to what we expect */
1026 buf[0] = MAX3107_REVID_REG;
1027 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1028 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1029 retval = -EIO;
1030 goto err_free1;
1031 }
1032 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1033 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1034 dev_err(&s->spi->dev, "REVID %x does not match\n",
1035 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1036 retval = -ENODEV;
1037 goto err_free1;
1038 }
1039
1040 /* Disable all interrupts */
1041 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1042 buf[0] |= 0x0000;
1043
1044 /* Configure clock source */
1045 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1046 if (s->ext_clk) {
1047 /* External clock */
1048 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1049 }
1050
1051 /* PLL bypass ON */
1052 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1053
1054 /* Perform SPI transfer */
1055 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1056 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1057 retval = -EIO;
1058 goto err_free1;
1059 }
1060
1061 /* Register UART driver */
1062 if (!driver_registered) {
1063 retval = uart_register_driver(&max3107_uart_driver);
1064 if (retval) {
1065 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1066 goto err_free1;
1067 }
1068 driver_registered = 1;
1069 }
1070
1071 /* Initialize UART port data */
1072 s->port.fifosize = 128;
1073 s->port.ops = &max3107_ops;
1074 s->port.line = 0;
1075 s->port.dev = &spi->dev;
1076 s->port.uartclk = 9600;
1077 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1078 s->port.irq = s->spi->irq;
1079 s->port.type = PORT_MAX3107;
1080
1081 /* Add UART port */
1082 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1083 if (retval < 0) {
1084 dev_err(&s->spi->dev, "Adding UART port failed\n");
1085 goto err_free1;
1086 }
1087
1088 if (pdata->configure) {
1089 retval = pdata->configure(s);
1090 if (retval < 0)
1091 goto err_free1;
1092 }
1093
1094 /* Go to suspend mode */
1095 if (pdata->hw_suspend)
1096 pdata->hw_suspend(s, 1);
1097
1098 return 0;
1099
1100 err_free1:
1101 kfree(s->txbuf);
1102 err_free2:
1103 kfree(s->rxstr);
1104 err_free3:
1105 kfree(s->rxbuf);
1106 err_free4:
1107 kfree(s);
1108 return retval;
1109 }
1110 EXPORT_SYMBOL_GPL(max3107_probe);
1111
1112 /* Driver remove function */
1113 int max3107_remove(struct spi_device *spi)
1114 {
1115 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1116
1117 pr_info("enter max3107 remove\n");
1118
1119 /* Remove port */
1120 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1121 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1122
1123
1124 /* Free TxRx buffer */
1125 kfree(s->rxbuf);
1126 kfree(s->rxstr);
1127 kfree(s->txbuf);
1128
1129 /* Free port structure */
1130 kfree(s);
1131
1132 return 0;
1133 }
1134 EXPORT_SYMBOL_GPL(max3107_remove);
1135
1136 /* Driver suspend function */
1137 int max3107_suspend(struct spi_device *spi, pm_message_t state)
1138 {
1139 #ifdef CONFIG_PM
1140 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1141
1142 pr_debug("enter suspend\n");
1143
1144 /* Suspend UART port */
1145 uart_suspend_port(&max3107_uart_driver, &s->port);
1146
1147 /* Go to suspend mode */
1148 if (s->pdata->hw_suspend)
1149 s->pdata->hw_suspend(s, 1);
1150 #endif /* CONFIG_PM */
1151 return 0;
1152 }
1153 EXPORT_SYMBOL_GPL(max3107_suspend);
1154
1155 /* Driver resume function */
1156 int max3107_resume(struct spi_device *spi)
1157 {
1158 #ifdef CONFIG_PM
1159 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1160
1161 pr_debug("enter resume\n");
1162
1163 /* Resume from suspend */
1164 if (s->pdata->hw_suspend)
1165 s->pdata->hw_suspend(s, 0);
1166
1167 /* Resume UART port */
1168 uart_resume_port(&max3107_uart_driver, &s->port);
1169 #endif /* CONFIG_PM */
1170 return 0;
1171 }
1172 EXPORT_SYMBOL_GPL(max3107_resume);
1173
1174 static int max3107_probe_generic(struct spi_device *spi)
1175 {
1176 return max3107_probe(spi, &generic_plat_data);
1177 }
1178
1179 /* Spi driver data */
1180 static struct spi_driver max3107_driver = {
1181 .driver = {
1182 .name = "max3107",
1183 .bus = &spi_bus_type,
1184 .owner = THIS_MODULE,
1185 },
1186 .probe = max3107_probe_generic,
1187 .remove = __devexit_p(max3107_remove),
1188 .suspend = max3107_suspend,
1189 .resume = max3107_resume,
1190 };
1191
1192 /* Driver init function */
1193 static int __init max3107_init(void)
1194 {
1195 pr_info("enter max3107 init\n");
1196 return spi_register_driver(&max3107_driver);
1197 }
1198
1199 /* Driver exit function */
1200 static void __exit max3107_exit(void)
1201 {
1202 pr_info("enter max3107 exit\n");
1203 /* Unregister UART driver */
1204 if (driver_registered)
1205 uart_unregister_driver(&max3107_uart_driver);
1206 spi_unregister_driver(&max3107_driver);
1207 }
1208
1209 module_init(max3107_init);
1210 module_exit(max3107_exit);
1211
1212 MODULE_DESCRIPTION("MAX3107 driver");
1213 MODULE_AUTHOR("Aavamobile");
1214 MODULE_ALIAS("spi:max3107");
1215 MODULE_LICENSE("GPL v2");
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