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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / tty / serial / samsung.c
blobb31f1c3a2c4c607268b795641bf6b9f8b1d10c0b
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
45
46 #include <asm/irq.h>
47
48 #include <mach/hardware.h>
49 #include <mach/map.h>
50
51 #include <plat/regs-serial.h>
52
53 #include "samsung.h"
54
55 /* UART name and device definitions */
56
57 #define S3C24XX_SERIAL_NAME "ttySAC"
58 #define S3C24XX_SERIAL_MAJOR 204
59 #define S3C24XX_SERIAL_MINOR 64
60
61 /* macros to change one thing to another */
62
63 #define tx_enabled(port) ((port)->unused[0])
64 #define rx_enabled(port) ((port)->unused[1])
65
66 /* flag to ignore all characters coming in */
67 #define RXSTAT_DUMMY_READ (0x10000000)
68
69 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
70 {
71 return container_of(port, struct s3c24xx_uart_port, port);
72 }
73
74 /* translate a port to the device name */
75
76 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
77 {
78 return to_platform_device(port->dev)->name;
79 }
80
81 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
82 {
83 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
84 }
85
86 /*
87 * s3c64xx and later SoC's include the interrupt mask and status registers in
88 * the controller itself, unlike the s3c24xx SoC's which have these registers
89 * in the interrupt controller. Check if the port type is s3c64xx or higher.
90 */
91 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
92 {
93 return to_ourport(port)->info->type == PORT_S3C6400;
94 }
95
96 static void s3c24xx_serial_rx_enable(struct uart_port *port)
97 {
98 unsigned long flags;
99 unsigned int ucon, ufcon;
100 int count = 10000;
101
102 spin_lock_irqsave(&port->lock, flags);
103
104 while (--count && !s3c24xx_serial_txempty_nofifo(port))
105 udelay(100);
106
107 ufcon = rd_regl(port, S3C2410_UFCON);
108 ufcon |= S3C2410_UFCON_RESETRX;
109 wr_regl(port, S3C2410_UFCON, ufcon);
110
111 ucon = rd_regl(port, S3C2410_UCON);
112 ucon |= S3C2410_UCON_RXIRQMODE;
113 wr_regl(port, S3C2410_UCON, ucon);
114
115 rx_enabled(port) = 1;
116 spin_unlock_irqrestore(&port->lock, flags);
117 }
118
119 static void s3c24xx_serial_rx_disable(struct uart_port *port)
120 {
121 unsigned long flags;
122 unsigned int ucon;
123
124 spin_lock_irqsave(&port->lock, flags);
125
126 ucon = rd_regl(port, S3C2410_UCON);
127 ucon &= ~S3C2410_UCON_RXIRQMODE;
128 wr_regl(port, S3C2410_UCON, ucon);
129
130 rx_enabled(port) = 0;
131 spin_unlock_irqrestore(&port->lock, flags);
132 }
133
134 static void s3c24xx_serial_stop_tx(struct uart_port *port)
135 {
136 struct s3c24xx_uart_port *ourport = to_ourport(port);
137
138 if (tx_enabled(port)) {
139 if (s3c24xx_serial_has_interrupt_mask(port))
140 __set_bit(S3C64XX_UINTM_TXD,
141 portaddrl(port, S3C64XX_UINTM));
142 else
143 disable_irq_nosync(ourport->tx_irq);
144 tx_enabled(port) = 0;
145 if (port->flags & UPF_CONS_FLOW)
146 s3c24xx_serial_rx_enable(port);
147 }
148 }
149
150 static void s3c24xx_serial_start_tx(struct uart_port *port)
151 {
152 struct s3c24xx_uart_port *ourport = to_ourport(port);
153
154 if (!tx_enabled(port)) {
155 if (port->flags & UPF_CONS_FLOW)
156 s3c24xx_serial_rx_disable(port);
157
158 if (s3c24xx_serial_has_interrupt_mask(port))
159 __clear_bit(S3C64XX_UINTM_TXD,
160 portaddrl(port, S3C64XX_UINTM));
161 else
162 enable_irq(ourport->tx_irq);
163 tx_enabled(port) = 1;
164 }
165 }
166
167 static void s3c24xx_serial_stop_rx(struct uart_port *port)
168 {
169 struct s3c24xx_uart_port *ourport = to_ourport(port);
170
171 if (rx_enabled(port)) {
172 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
173 if (s3c24xx_serial_has_interrupt_mask(port))
174 __set_bit(S3C64XX_UINTM_RXD,
175 portaddrl(port, S3C64XX_UINTM));
176 else
177 disable_irq_nosync(ourport->rx_irq);
178 rx_enabled(port) = 0;
179 }
180 }
181
182 static void s3c24xx_serial_enable_ms(struct uart_port *port)
183 {
184 }
185
186 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
187 {
188 return to_ourport(port)->info;
189 }
190
191 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
192 {
193 if (port->dev == NULL)
194 return NULL;
195
196 return (struct s3c2410_uartcfg *)port->dev->platform_data;
197 }
198
199 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
200 unsigned long ufstat)
201 {
202 struct s3c24xx_uart_info *info = ourport->info;
203
204 if (ufstat & info->rx_fifofull)
205 return info->fifosize;
206
207 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
208 }
209
210
211 /* ? - where has parity gone?? */
212 #define S3C2410_UERSTAT_PARITY (0x1000)
213
214 static irqreturn_t
215 s3c24xx_serial_rx_chars(int irq, void *dev_id)
216 {
217 struct s3c24xx_uart_port *ourport = dev_id;
218 struct uart_port *port = &ourport->port;
219 struct tty_struct *tty = port->state->port.tty;
220 unsigned int ufcon, ch, flag, ufstat, uerstat;
221 int max_count = 64;
222
223 while (max_count-- > 0) {
224 ufcon = rd_regl(port, S3C2410_UFCON);
225 ufstat = rd_regl(port, S3C2410_UFSTAT);
226
227 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
228 break;
229
230 uerstat = rd_regl(port, S3C2410_UERSTAT);
231 ch = rd_regb(port, S3C2410_URXH);
232
233 if (port->flags & UPF_CONS_FLOW) {
234 int txe = s3c24xx_serial_txempty_nofifo(port);
235
236 if (rx_enabled(port)) {
237 if (!txe) {
238 rx_enabled(port) = 0;
239 continue;
240 }
241 } else {
242 if (txe) {
243 ufcon |= S3C2410_UFCON_RESETRX;
244 wr_regl(port, S3C2410_UFCON, ufcon);
245 rx_enabled(port) = 1;
246 goto out;
247 }
248 continue;
249 }
250 }
251
252 /* insert the character into the buffer */
253
254 flag = TTY_NORMAL;
255 port->icount.rx++;
256
257 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
258 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
259 ch, uerstat);
260
261 /* check for break */
262 if (uerstat & S3C2410_UERSTAT_BREAK) {
263 dbg("break!\n");
264 port->icount.brk++;
265 if (uart_handle_break(port))
266 goto ignore_char;
267 }
268
269 if (uerstat & S3C2410_UERSTAT_FRAME)
270 port->icount.frame++;
271 if (uerstat & S3C2410_UERSTAT_OVERRUN)
272 port->icount.overrun++;
273
274 uerstat &= port->read_status_mask;
275
276 if (uerstat & S3C2410_UERSTAT_BREAK)
277 flag = TTY_BREAK;
278 else if (uerstat & S3C2410_UERSTAT_PARITY)
279 flag = TTY_PARITY;
280 else if (uerstat & (S3C2410_UERSTAT_FRAME |
281 S3C2410_UERSTAT_OVERRUN))
282 flag = TTY_FRAME;
283 }
284
285 if (uart_handle_sysrq_char(port, ch))
286 goto ignore_char;
287
288 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
289 ch, flag);
290
291 ignore_char:
292 continue;
293 }
294 tty_flip_buffer_push(tty);
295
296 out:
297 return IRQ_HANDLED;
298 }
299
300 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
301 {
302 struct s3c24xx_uart_port *ourport = id;
303 struct uart_port *port = &ourport->port;
304 struct circ_buf *xmit = &port->state->xmit;
305 int count = 256;
306
307 if (port->x_char) {
308 wr_regb(port, S3C2410_UTXH, port->x_char);
309 port->icount.tx++;
310 port->x_char = 0;
311 goto out;
312 }
313
314 /* if there isn't anything more to transmit, or the uart is now
315 * stopped, disable the uart and exit
316 */
317
318 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
319 s3c24xx_serial_stop_tx(port);
320 goto out;
321 }
322
323 /* try and drain the buffer... */
324
325 while (!uart_circ_empty(xmit) && count-- > 0) {
326 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
327 break;
328
329 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
330 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
331 port->icount.tx++;
332 }
333
334 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
335 uart_write_wakeup(port);
336
337 if (uart_circ_empty(xmit))
338 s3c24xx_serial_stop_tx(port);
339
340 out:
341 return IRQ_HANDLED;
342 }
343
344 /* interrupt handler for s3c64xx and later SoC's.*/
345 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
346 {
347 struct s3c24xx_uart_port *ourport = id;
348 struct uart_port *port = &ourport->port;
349 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
350 unsigned long flags;
351 irqreturn_t ret = IRQ_HANDLED;
352
353 spin_lock_irqsave(&port->lock, flags);
354 if (pend & S3C64XX_UINTM_RXD_MSK) {
355 ret = s3c24xx_serial_rx_chars(irq, id);
356 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
357 }
358 if (pend & S3C64XX_UINTM_TXD_MSK) {
359 ret = s3c24xx_serial_tx_chars(irq, id);
360 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
361 }
362 spin_unlock_irqrestore(&port->lock, flags);
363 return ret;
364 }
365
366 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
367 {
368 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
369 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
370 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
371
372 if (ufcon & S3C2410_UFCON_FIFOMODE) {
373 if ((ufstat & info->tx_fifomask) != 0 ||
374 (ufstat & info->tx_fifofull))
375 return 0;
376
377 return 1;
378 }
379
380 return s3c24xx_serial_txempty_nofifo(port);
381 }
382
383 /* no modem control lines */
384 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
385 {
386 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
387
388 if (umstat & S3C2410_UMSTAT_CTS)
389 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
390 else
391 return TIOCM_CAR | TIOCM_DSR;
392 }
393
394 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
395 {
396 /* todo - possibly remove AFC and do manual CTS */
397 }
398
399 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
400 {
401 unsigned long flags;
402 unsigned int ucon;
403
404 spin_lock_irqsave(&port->lock, flags);
405
406 ucon = rd_regl(port, S3C2410_UCON);
407
408 if (break_state)
409 ucon |= S3C2410_UCON_SBREAK;
410 else
411 ucon &= ~S3C2410_UCON_SBREAK;
412
413 wr_regl(port, S3C2410_UCON, ucon);
414
415 spin_unlock_irqrestore(&port->lock, flags);
416 }
417
418 static void s3c24xx_serial_shutdown(struct uart_port *port)
419 {
420 struct s3c24xx_uart_port *ourport = to_ourport(port);
421
422 if (ourport->tx_claimed) {
423 if (!s3c24xx_serial_has_interrupt_mask(port))
424 free_irq(ourport->tx_irq, ourport);
425 tx_enabled(port) = 0;
426 ourport->tx_claimed = 0;
427 }
428
429 if (ourport->rx_claimed) {
430 if (!s3c24xx_serial_has_interrupt_mask(port))
431 free_irq(ourport->rx_irq, ourport);
432 ourport->rx_claimed = 0;
433 rx_enabled(port) = 0;
434 }
435
436 /* Clear pending interrupts and mask all interrupts */
437 if (s3c24xx_serial_has_interrupt_mask(port)) {
438 wr_regl(port, S3C64XX_UINTP, 0xf);
439 wr_regl(port, S3C64XX_UINTM, 0xf);
440 }
441 }
442
443 static int s3c24xx_serial_startup(struct uart_port *port)
444 {
445 struct s3c24xx_uart_port *ourport = to_ourport(port);
446 int ret;
447
448 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
449 port->mapbase, port->membase);
450
451 rx_enabled(port) = 1;
452
453 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
454 s3c24xx_serial_portname(port), ourport);
455
456 if (ret != 0) {
457 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
458 return ret;
459 }
460
461 ourport->rx_claimed = 1;
462
463 dbg("requesting tx irq...\n");
464
465 tx_enabled(port) = 1;
466
467 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
468 s3c24xx_serial_portname(port), ourport);
469
470 if (ret) {
471 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
472 goto err;
473 }
474
475 ourport->tx_claimed = 1;
476
477 dbg("s3c24xx_serial_startup ok\n");
478
479 /* the port reset code should have done the correct
480 * register setup for the port controls */
481
482 return ret;
483
484 err:
485 s3c24xx_serial_shutdown(port);
486 return ret;
487 }
488
489 static int s3c64xx_serial_startup(struct uart_port *port)
490 {
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
492 int ret;
493
494 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
495 port->mapbase, port->membase);
496
497 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
498 s3c24xx_serial_portname(port), ourport);
499 if (ret) {
500 printk(KERN_ERR "cannot get irq %d\n", port->irq);
501 return ret;
502 }
503
504 /* For compatibility with s3c24xx Soc's */
505 rx_enabled(port) = 1;
506 ourport->rx_claimed = 1;
507 tx_enabled(port) = 0;
508 ourport->tx_claimed = 1;
509
510 /* Enable Rx Interrupt */
511 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
512 dbg("s3c64xx_serial_startup ok\n");
513 return ret;
514 }
515
516 /* power power management control */
517
518 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
519 unsigned int old)
520 {
521 struct s3c24xx_uart_port *ourport = to_ourport(port);
522
523 ourport->pm_level = level;
524
525 switch (level) {
526 case 3:
527 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
528 clk_disable(ourport->baudclk);
529
530 clk_disable(ourport->clk);
531 break;
532
533 case 0:
534 clk_enable(ourport->clk);
535
536 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
537 clk_enable(ourport->baudclk);
538
539 break;
540 default:
541 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
542 }
543 }
544
545 /* baud rate calculation
546 *
547 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
548 * of different sources, including the peripheral clock ("pclk") and an
549 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
550 * with a programmable extra divisor.
551 *
552 * The following code goes through the clock sources, and calculates the
553 * baud clocks (and the resultant actual baud rates) and then tries to
554 * pick the closest one and select that.
555 *
556 */
557
558
559 #define MAX_CLKS (8)
560
561 static struct s3c24xx_uart_clksrc tmp_clksrc = {
562 .name = "pclk",
563 .min_baud = 0,
564 .max_baud = 0,
565 .divisor = 1,
566 };
567
568 static inline int
569 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
570 {
571 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
572
573 return (info->get_clksrc)(port, c);
574 }
575
576 static inline int
577 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
578 {
579 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
580
581 return (info->set_clksrc)(port, c);
582 }
583
584 struct baud_calc {
585 struct s3c24xx_uart_clksrc *clksrc;
586 unsigned int calc;
587 unsigned int divslot;
588 unsigned int quot;
589 struct clk *src;
590 };
591
592 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
593 struct uart_port *port,
594 struct s3c24xx_uart_clksrc *clksrc,
595 unsigned int baud)
596 {
597 struct s3c24xx_uart_port *ourport = to_ourport(port);
598 unsigned long rate;
599
600 calc->src = clk_get(port->dev, clksrc->name);
601 if (calc->src == NULL || IS_ERR(calc->src))
602 return 0;
603
604 rate = clk_get_rate(calc->src);
605 rate /= clksrc->divisor;
606
607 calc->clksrc = clksrc;
608
609 if (ourport->info->has_divslot) {
610 unsigned long div = rate / baud;
611
612 /* The UDIVSLOT register on the newer UARTs allows us to
613 * get a divisor adjustment of 1/16th on the baud clock.
614 *
615 * We don't keep the UDIVSLOT value (the 16ths we calculated
616 * by not multiplying the baud by 16) as it is easy enough
617 * to recalculate.
618 */
619
620 calc->quot = div / 16;
621 calc->calc = rate / div;
622 } else {
623 calc->quot = (rate + (8 * baud)) / (16 * baud);
624 calc->calc = (rate / (calc->quot * 16));
625 }
626
627 calc->quot--;
628 return 1;
629 }
630
631 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
632 struct s3c24xx_uart_clksrc **clksrc,
633 struct clk **clk,
634 unsigned int baud)
635 {
636 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
637 struct s3c24xx_uart_clksrc *clkp;
638 struct baud_calc res[MAX_CLKS];
639 struct baud_calc *resptr, *best, *sptr;
640 int i;
641
642 clkp = cfg->clocks;
643 best = NULL;
644
645 if (cfg->clocks_size < 2) {
646 if (cfg->clocks_size == 0)
647 clkp = &tmp_clksrc;
648
649 /* check to see if we're sourcing fclk, and if so we're
650 * going to have to update the clock source
651 */
652
653 if (strcmp(clkp->name, "fclk") == 0) {
654 struct s3c24xx_uart_clksrc src;
655
656 s3c24xx_serial_getsource(port, &src);
657
658 /* check that the port already using fclk, and if
659 * not, then re-select fclk
660 */
661
662 if (strcmp(src.name, clkp->name) == 0) {
663 s3c24xx_serial_setsource(port, clkp);
664 s3c24xx_serial_getsource(port, &src);
665 }
666
667 clkp->divisor = src.divisor;
668 }
669
670 s3c24xx_serial_calcbaud(res, port, clkp, baud);
671 best = res;
672 resptr = best + 1;
673 } else {
674 resptr = res;
675
676 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
677 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
678 resptr++;
679 }
680 }
681
682 /* ok, we now need to select the best clock we found */
683
684 if (!best) {
685 unsigned int deviation = (1<<30)|((1<<30)-1);
686 int calc_deviation;
687
688 for (sptr = res; sptr < resptr; sptr++) {
689 calc_deviation = baud - sptr->calc;
690 if (calc_deviation < 0)
691 calc_deviation = -calc_deviation;
692
693 if (calc_deviation < deviation) {
694 best = sptr;
695 deviation = calc_deviation;
696 }
697 }
698 }
699
700 /* store results to pass back */
701
702 *clksrc = best->clksrc;
703 *clk = best->src;
704
705 return best->quot;
706 }
707
708 /* udivslot_table[]
709 *
710 * This table takes the fractional value of the baud divisor and gives
711 * the recommended setting for the UDIVSLOT register.
712 */
713 static u16 udivslot_table[16] = {
714 [0] = 0x0000,
715 [1] = 0x0080,
716 [2] = 0x0808,
717 [3] = 0x0888,
718 [4] = 0x2222,
719 [5] = 0x4924,
720 [6] = 0x4A52,
721 [7] = 0x54AA,
722 [8] = 0x5555,
723 [9] = 0xD555,
724 [10] = 0xD5D5,
725 [11] = 0xDDD5,
726 [12] = 0xDDDD,
727 [13] = 0xDFDD,
728 [14] = 0xDFDF,
729 [15] = 0xFFDF,
730 };
731
732 static void s3c24xx_serial_set_termios(struct uart_port *port,
733 struct ktermios *termios,
734 struct ktermios *old)
735 {
736 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
737 struct s3c24xx_uart_port *ourport = to_ourport(port);
738 struct s3c24xx_uart_clksrc *clksrc = NULL;
739 struct clk *clk = NULL;
740 unsigned long flags;
741 unsigned int baud, quot;
742 unsigned int ulcon;
743 unsigned int umcon;
744 unsigned int udivslot = 0;
745
746 /*
747 * We don't support modem control lines.
748 */
749 termios->c_cflag &= ~(HUPCL | CMSPAR);
750 termios->c_cflag |= CLOCAL;
751
752 /*
753 * Ask the core to calculate the divisor for us.
754 */
755
756 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
757
758 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
759 quot = port->custom_divisor;
760 else
761 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
762
763 /* check to see if we need to change clock source */
764
765 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
766 dbg("selecting clock %p\n", clk);
767 s3c24xx_serial_setsource(port, clksrc);
768
769 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
770 clk_disable(ourport->baudclk);
771 ourport->baudclk = NULL;
772 }
773
774 clk_enable(clk);
775
776 ourport->clksrc = clksrc;
777 ourport->baudclk = clk;
778 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
779 }
780
781 if (ourport->info->has_divslot) {
782 unsigned int div = ourport->baudclk_rate / baud;
783
784 if (cfg->has_fracval) {
785 udivslot = (div & 15);
786 dbg("fracval = %04x\n", udivslot);
787 } else {
788 udivslot = udivslot_table[div & 15];
789 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
790 }
791 }
792
793 switch (termios->c_cflag & CSIZE) {
794 case CS5:
795 dbg("config: 5bits/char\n");
796 ulcon = S3C2410_LCON_CS5;
797 break;
798 case CS6:
799 dbg("config: 6bits/char\n");
800 ulcon = S3C2410_LCON_CS6;
801 break;
802 case CS7:
803 dbg("config: 7bits/char\n");
804 ulcon = S3C2410_LCON_CS7;
805 break;
806 case CS8:
807 default:
808 dbg("config: 8bits/char\n");
809 ulcon = S3C2410_LCON_CS8;
810 break;
811 }
812
813 /* preserve original lcon IR settings */
814 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
815
816 if (termios->c_cflag & CSTOPB)
817 ulcon |= S3C2410_LCON_STOPB;
818
819 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
820
821 if (termios->c_cflag & PARENB) {
822 if (termios->c_cflag & PARODD)
823 ulcon |= S3C2410_LCON_PODD;
824 else
825 ulcon |= S3C2410_LCON_PEVEN;
826 } else {
827 ulcon |= S3C2410_LCON_PNONE;
828 }
829
830 spin_lock_irqsave(&port->lock, flags);
831
832 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
833 ulcon, quot, udivslot);
834
835 wr_regl(port, S3C2410_ULCON, ulcon);
836 wr_regl(port, S3C2410_UBRDIV, quot);
837 wr_regl(port, S3C2410_UMCON, umcon);
838
839 if (ourport->info->has_divslot)
840 wr_regl(port, S3C2443_DIVSLOT, udivslot);
841
842 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
843 rd_regl(port, S3C2410_ULCON),
844 rd_regl(port, S3C2410_UCON),
845 rd_regl(port, S3C2410_UFCON));
846
847 /*
848 * Update the per-port timeout.
849 */
850 uart_update_timeout(port, termios->c_cflag, baud);
851
852 /*
853 * Which character status flags are we interested in?
854 */
855 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
856 if (termios->c_iflag & INPCK)
857 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
858
859 /*
860 * Which character status flags should we ignore?
861 */
862 port->ignore_status_mask = 0;
863 if (termios->c_iflag & IGNPAR)
864 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
865 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
866 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
867
868 /*
869 * Ignore all characters if CREAD is not set.
870 */
871 if ((termios->c_cflag & CREAD) == 0)
872 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
873
874 spin_unlock_irqrestore(&port->lock, flags);
875 }
876
877 static const char *s3c24xx_serial_type(struct uart_port *port)
878 {
879 switch (port->type) {
880 case PORT_S3C2410:
881 return "S3C2410";
882 case PORT_S3C2440:
883 return "S3C2440";
884 case PORT_S3C2412:
885 return "S3C2412";
886 case PORT_S3C6400:
887 return "S3C6400/10";
888 default:
889 return NULL;
890 }
891 }
892
893 #define MAP_SIZE (0x100)
894
895 static void s3c24xx_serial_release_port(struct uart_port *port)
896 {
897 release_mem_region(port->mapbase, MAP_SIZE);
898 }
899
900 static int s3c24xx_serial_request_port(struct uart_port *port)
901 {
902 const char *name = s3c24xx_serial_portname(port);
903 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
904 }
905
906 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
907 {
908 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
909
910 if (flags & UART_CONFIG_TYPE &&
911 s3c24xx_serial_request_port(port) == 0)
912 port->type = info->type;
913 }
914
915 /*
916 * verify the new serial_struct (for TIOCSSERIAL).
917 */
918 static int
919 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
920 {
921 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
922
923 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
924 return -EINVAL;
925
926 return 0;
927 }
928
929
930 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
931
932 static struct console s3c24xx_serial_console;
933
934 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
935 #else
936 #define S3C24XX_SERIAL_CONSOLE NULL
937 #endif
938
939 static struct uart_ops s3c24xx_serial_ops = {
940 .pm = s3c24xx_serial_pm,
941 .tx_empty = s3c24xx_serial_tx_empty,
942 .get_mctrl = s3c24xx_serial_get_mctrl,
943 .set_mctrl = s3c24xx_serial_set_mctrl,
944 .stop_tx = s3c24xx_serial_stop_tx,
945 .start_tx = s3c24xx_serial_start_tx,
946 .stop_rx = s3c24xx_serial_stop_rx,
947 .enable_ms = s3c24xx_serial_enable_ms,
948 .break_ctl = s3c24xx_serial_break_ctl,
949 .startup = s3c24xx_serial_startup,
950 .shutdown = s3c24xx_serial_shutdown,
951 .set_termios = s3c24xx_serial_set_termios,
952 .type = s3c24xx_serial_type,
953 .release_port = s3c24xx_serial_release_port,
954 .request_port = s3c24xx_serial_request_port,
955 .config_port = s3c24xx_serial_config_port,
956 .verify_port = s3c24xx_serial_verify_port,
957 };
958
959 static struct uart_driver s3c24xx_uart_drv = {
960 .owner = THIS_MODULE,
961 .driver_name = "s3c2410_serial",
962 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
963 .cons = S3C24XX_SERIAL_CONSOLE,
964 .dev_name = S3C24XX_SERIAL_NAME,
965 .major = S3C24XX_SERIAL_MAJOR,
966 .minor = S3C24XX_SERIAL_MINOR,
967 };
968
969 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
970 [0] = {
971 .port = {
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
973 .iotype = UPIO_MEM,
974 .uartclk = 0,
975 .fifosize = 16,
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
978 .line = 0,
979 }
980 },
981 [1] = {
982 .port = {
983 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
984 .iotype = UPIO_MEM,
985 .uartclk = 0,
986 .fifosize = 16,
987 .ops = &s3c24xx_serial_ops,
988 .flags = UPF_BOOT_AUTOCONF,
989 .line = 1,
990 }
991 },
992 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
993
994 [2] = {
995 .port = {
996 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
997 .iotype = UPIO_MEM,
998 .uartclk = 0,
999 .fifosize = 16,
1000 .ops = &s3c24xx_serial_ops,
1001 .flags = UPF_BOOT_AUTOCONF,
1002 .line = 2,
1003 }
1004 },
1005 #endif
1006 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1007 [3] = {
1008 .port = {
1009 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1010 .iotype = UPIO_MEM,
1011 .uartclk = 0,
1012 .fifosize = 16,
1013 .ops = &s3c24xx_serial_ops,
1014 .flags = UPF_BOOT_AUTOCONF,
1015 .line = 3,
1016 }
1017 }
1018 #endif
1019 };
1020
1021 /* s3c24xx_serial_resetport
1022 *
1023 * wrapper to call the specific reset for this port (reset the fifos
1024 * and the settings)
1025 */
1026
1027 static inline int s3c24xx_serial_resetport(struct uart_port *port,
1028 struct s3c2410_uartcfg *cfg)
1029 {
1030 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1031
1032 return (info->reset_port)(port, cfg);
1033 }
1034
1035
1036 #ifdef CONFIG_CPU_FREQ
1037
1038 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1039 unsigned long val, void *data)
1040 {
1041 struct s3c24xx_uart_port *port;
1042 struct uart_port *uport;
1043
1044 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1045 uport = &port->port;
1046
1047 /* check to see if port is enabled */
1048
1049 if (port->pm_level != 0)
1050 return 0;
1051
1052 /* try and work out if the baudrate is changing, we can detect
1053 * a change in rate, but we do not have support for detecting
1054 * a disturbance in the clock-rate over the change.
1055 */
1056
1057 if (IS_ERR(port->clk))
1058 goto exit;
1059
1060 if (port->baudclk_rate == clk_get_rate(port->clk))
1061 goto exit;
1062
1063 if (val == CPUFREQ_PRECHANGE) {
1064 /* we should really shut the port down whilst the
1065 * frequency change is in progress. */
1066
1067 } else if (val == CPUFREQ_POSTCHANGE) {
1068 struct ktermios *termios;
1069 struct tty_struct *tty;
1070
1071 if (uport->state == NULL)
1072 goto exit;
1073
1074 tty = uport->state->port.tty;
1075
1076 if (tty == NULL)
1077 goto exit;
1078
1079 termios = tty->termios;
1080
1081 if (termios == NULL) {
1082 printk(KERN_WARNING "%s: no termios?\n", __func__);
1083 goto exit;
1084 }
1085
1086 s3c24xx_serial_set_termios(uport, termios, NULL);
1087 }
1088
1089 exit:
1090 return 0;
1091 }
1092
1093 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1094 {
1095 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1096
1097 return cpufreq_register_notifier(&port->freq_transition,
1098 CPUFREQ_TRANSITION_NOTIFIER);
1099 }
1100
1101 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1102 {
1103 cpufreq_unregister_notifier(&port->freq_transition,
1104 CPUFREQ_TRANSITION_NOTIFIER);
1105 }
1106
1107 #else
1108 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1109 {
1110 return 0;
1111 }
1112
1113 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1114 {
1115 }
1116 #endif
1117
1118 /* s3c24xx_serial_init_port
1119 *
1120 * initialise a single serial port from the platform device given
1121 */
1122
1123 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1124 struct s3c24xx_uart_info *info,
1125 struct platform_device *platdev)
1126 {
1127 struct uart_port *port = &ourport->port;
1128 struct s3c2410_uartcfg *cfg;
1129 struct resource *res;
1130 int ret;
1131
1132 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1133
1134 if (platdev == NULL)
1135 return -ENODEV;
1136
1137 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1138
1139 if (port->mapbase != 0)
1140 return 0;
1141
1142 if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1143 printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1144 cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1145 return -ERANGE;
1146 }
1147
1148 /* setup info for port */
1149 port->dev = &platdev->dev;
1150 ourport->info = info;
1151
1152 /* Startup sequence is different for s3c64xx and higher SoC's */
1153 if (s3c24xx_serial_has_interrupt_mask(port))
1154 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1155
1156 /* copy the info in from provided structure */
1157 ourport->port.fifosize = info->fifosize;
1158
1159 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1160
1161 port->uartclk = 1;
1162
1163 if (cfg->uart_flags & UPF_CONS_FLOW) {
1164 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1165 port->flags |= UPF_CONS_FLOW;
1166 }
1167
1168 /* sort our the physical and virtual addresses for each UART */
1169
1170 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1171 if (res == NULL) {
1172 printk(KERN_ERR "failed to find memory resource for uart\n");
1173 return -EINVAL;
1174 }
1175
1176 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1177
1178 port->mapbase = res->start;
1179 port->membase = S3C_VA_UART + (res->start & 0xfffff);
1180 ret = platform_get_irq(platdev, 0);
1181 if (ret < 0)
1182 port->irq = 0;
1183 else {
1184 port->irq = ret;
1185 ourport->rx_irq = ret;
1186 ourport->tx_irq = ret + 1;
1187 }
1188
1189 ret = platform_get_irq(platdev, 1);
1190 if (ret > 0)
1191 ourport->tx_irq = ret;
1192
1193 ourport->clk = clk_get(&platdev->dev, "uart");
1194
1195 /* Keep all interrupts masked and cleared */
1196 if (s3c24xx_serial_has_interrupt_mask(port)) {
1197 wr_regl(port, S3C64XX_UINTM, 0xf);
1198 wr_regl(port, S3C64XX_UINTP, 0xf);
1199 wr_regl(port, S3C64XX_UINTSP, 0xf);
1200 }
1201
1202 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1203 port->mapbase, port->membase, port->irq,
1204 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1205
1206 /* reset the fifos (and setup the uart) */
1207 s3c24xx_serial_resetport(port, cfg);
1208 return 0;
1209 }
1210
1211 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1212 struct device_attribute *attr,
1213 char *buf)
1214 {
1215 struct uart_port *port = s3c24xx_dev_to_port(dev);
1216 struct s3c24xx_uart_port *ourport = to_ourport(port);
1217
1218 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1219 }
1220
1221 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1222
1223 /* Device driver serial port probe */
1224
1225 static int probe_index;
1226
1227 int s3c24xx_serial_probe(struct platform_device *dev,
1228 struct s3c24xx_uart_info *info)
1229 {
1230 struct s3c24xx_uart_port *ourport;
1231 int ret;
1232
1233 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1234
1235 ourport = &s3c24xx_serial_ports[probe_index];
1236 probe_index++;
1237
1238 dbg("%s: initialising port %p...\n", __func__, ourport);
1239
1240 ret = s3c24xx_serial_init_port(ourport, info, dev);
1241 if (ret < 0)
1242 goto probe_err;
1243
1244 dbg("%s: adding port\n", __func__);
1245 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1246 platform_set_drvdata(dev, &ourport->port);
1247
1248 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1249 if (ret < 0)
1250 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1251
1252 ret = s3c24xx_serial_cpufreq_register(ourport);
1253 if (ret < 0)
1254 dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1255
1256 return 0;
1257
1258 probe_err:
1259 return ret;
1260 }
1261
1262 EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1263
1264 int __devexit s3c24xx_serial_remove(struct platform_device *dev)
1265 {
1266 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1267
1268 if (port) {
1269 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1270 device_remove_file(&dev->dev, &dev_attr_clock_source);
1271 uart_remove_one_port(&s3c24xx_uart_drv, port);
1272 }
1273
1274 return 0;
1275 }
1276
1277 EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1278
1279 /* UART power management code */
1280 #ifdef CONFIG_PM_SLEEP
1281 static int s3c24xx_serial_suspend(struct device *dev)
1282 {
1283 struct uart_port *port = s3c24xx_dev_to_port(dev);
1284
1285 if (port)
1286 uart_suspend_port(&s3c24xx_uart_drv, port);
1287
1288 return 0;
1289 }
1290
1291 static int s3c24xx_serial_resume(struct device *dev)
1292 {
1293 struct uart_port *port = s3c24xx_dev_to_port(dev);
1294 struct s3c24xx_uart_port *ourport = to_ourport(port);
1295
1296 if (port) {
1297 clk_enable(ourport->clk);
1298 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1299 clk_disable(ourport->clk);
1300
1301 uart_resume_port(&s3c24xx_uart_drv, port);
1302 }
1303
1304 return 0;
1305 }
1306
1307 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1308 .suspend = s3c24xx_serial_suspend,
1309 .resume = s3c24xx_serial_resume,
1310 };
1311 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1312
1313 #else /* !CONFIG_PM_SLEEP */
1314
1315 #define SERIAL_SAMSUNG_PM_OPS NULL
1316 #endif /* CONFIG_PM_SLEEP */
1317
1318 int s3c24xx_serial_init(struct platform_driver *drv,
1319 struct s3c24xx_uart_info *info)
1320 {
1321 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1322
1323 drv->driver.pm = SERIAL_SAMSUNG_PM_OPS;
1324
1325 return platform_driver_register(drv);
1326 }
1327
1328 EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1329
1330 /* module initialisation code */
1331
1332 static int __init s3c24xx_serial_modinit(void)
1333 {
1334 int ret;
1335
1336 ret = uart_register_driver(&s3c24xx_uart_drv);
1337 if (ret < 0) {
1338 printk(KERN_ERR "failed to register UART driver\n");
1339 return -1;
1340 }
1341
1342 return 0;
1343 }
1344
1345 static void __exit s3c24xx_serial_modexit(void)
1346 {
1347 uart_unregister_driver(&s3c24xx_uart_drv);
1348 }
1349
1350 module_init(s3c24xx_serial_modinit);
1351 module_exit(s3c24xx_serial_modexit);
1352
1353 /* Console code */
1354
1355 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1356
1357 static struct uart_port *cons_uart;
1358
1359 static int
1360 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1361 {
1362 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1363 unsigned long ufstat, utrstat;
1364
1365 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1366 /* fifo mode - check amount of data in fifo registers... */
1367
1368 ufstat = rd_regl(port, S3C2410_UFSTAT);
1369 return (ufstat & info->tx_fifofull) ? 0 : 1;
1370 }
1371
1372 /* in non-fifo mode, we go and use the tx buffer empty */
1373
1374 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1375 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1376 }
1377
1378 static void
1379 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1380 {
1381 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1382 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1383 barrier();
1384 wr_regb(cons_uart, S3C2410_UTXH, ch);
1385 }
1386
1387 static void
1388 s3c24xx_serial_console_write(struct console *co, const char *s,
1389 unsigned int count)
1390 {
1391 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1392 }
1393
1394 static void __init
1395 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1396 int *parity, int *bits)
1397 {
1398 struct s3c24xx_uart_clksrc clksrc;
1399 struct clk *clk;
1400 unsigned int ulcon;
1401 unsigned int ucon;
1402 unsigned int ubrdiv;
1403 unsigned long rate;
1404
1405 ulcon = rd_regl(port, S3C2410_ULCON);
1406 ucon = rd_regl(port, S3C2410_UCON);
1407 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1408
1409 dbg("s3c24xx_serial_get_options: port=%p\n"
1410 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1411 port, ulcon, ucon, ubrdiv);
1412
1413 if ((ucon & 0xf) != 0) {
1414 /* consider the serial port configured if the tx/rx mode set */
1415
1416 switch (ulcon & S3C2410_LCON_CSMASK) {
1417 case S3C2410_LCON_CS5:
1418 *bits = 5;
1419 break;
1420 case S3C2410_LCON_CS6:
1421 *bits = 6;
1422 break;
1423 case S3C2410_LCON_CS7:
1424 *bits = 7;
1425 break;
1426 default:
1427 case S3C2410_LCON_CS8:
1428 *bits = 8;
1429 break;
1430 }
1431
1432 switch (ulcon & S3C2410_LCON_PMASK) {
1433 case S3C2410_LCON_PEVEN:
1434 *parity = 'e';
1435 break;
1436
1437 case S3C2410_LCON_PODD:
1438 *parity = 'o';
1439 break;
1440
1441 case S3C2410_LCON_PNONE:
1442 default:
1443 *parity = 'n';
1444 }
1445
1446 /* now calculate the baud rate */
1447
1448 s3c24xx_serial_getsource(port, &clksrc);
1449
1450 clk = clk_get(port->dev, clksrc.name);
1451 if (!IS_ERR(clk) && clk != NULL)
1452 rate = clk_get_rate(clk) / clksrc.divisor;
1453 else
1454 rate = 1;
1455
1456
1457 *baud = rate / (16 * (ubrdiv + 1));
1458 dbg("calculated baud %d\n", *baud);
1459 }
1460
1461 }
1462
1463 /* s3c24xx_serial_init_ports
1464 *
1465 * initialise the serial ports from the machine provided initialisation
1466 * data.
1467 */
1468
1469 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
1470 {
1471 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1472 struct platform_device **platdev_ptr;
1473 int i;
1474
1475 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1476
1477 platdev_ptr = s3c24xx_uart_devs;
1478
1479 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
1480 s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
1481 }
1482
1483 return 0;
1484 }
1485
1486 static int __init
1487 s3c24xx_serial_console_setup(struct console *co, char *options)
1488 {
1489 struct uart_port *port;
1490 int baud = 9600;
1491 int bits = 8;
1492 int parity = 'n';
1493 int flow = 'n';
1494
1495 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1496 co, co->index, options);
1497
1498 /* is this a valid port */
1499
1500 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1501 co->index = 0;
1502
1503 port = &s3c24xx_serial_ports[co->index].port;
1504
1505 /* is the port configured? */
1506
1507 if (port->mapbase == 0x0)
1508 return -ENODEV;
1509
1510 cons_uart = port;
1511
1512 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1513
1514 /*
1515 * Check whether an invalid uart number has been specified, and
1516 * if so, search for the first available port that does have
1517 * console support.
1518 */
1519 if (options)
1520 uart_parse_options(options, &baud, &parity, &bits, &flow);
1521 else
1522 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1523
1524 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1525
1526 return uart_set_options(port, co, baud, parity, bits, flow);
1527 }
1528
1529 /* s3c24xx_serial_initconsole
1530 *
1531 * initialise the console from one of the uart drivers
1532 */
1533
1534 static struct console s3c24xx_serial_console = {
1535 .name = S3C24XX_SERIAL_NAME,
1536 .device = uart_console_device,
1537 .flags = CON_PRINTBUFFER,
1538 .index = -1,
1539 .write = s3c24xx_serial_console_write,
1540 .setup = s3c24xx_serial_console_setup,
1541 .data = &s3c24xx_uart_drv,
1542 };
1543
1544 int s3c24xx_serial_initconsole(struct platform_driver *drv,
1545 struct s3c24xx_uart_info **info)
1546
1547 {
1548 struct platform_device *dev = s3c24xx_uart_devs[0];
1549
1550 dbg("s3c24xx_serial_initconsole\n");
1551
1552 /* select driver based on the cpu */
1553
1554 if (dev == NULL) {
1555 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1556 return 0;
1557 }
1558
1559 if (strcmp(dev->name, drv->driver.name) != 0)
1560 return 0;
1561
1562 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1563 s3c24xx_serial_init_ports(info);
1564
1565 register_console(&s3c24xx_serial_console);
1566 return 0;
1567 }
1568
1569 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1570
1571 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1572 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1573 MODULE_LICENSE("GPL v2");
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