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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / usb / host / isp1760-hcd.c
blob27dfab80ed8f3982c4454295481222e1698c6a6b
1 /*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/list.h>
18 #include <linux/usb.h>
19 #include <linux/usb/hcd.h>
20 #include <linux/debugfs.h>
21 #include <linux/uaccess.h>
22 #include <linux/io.h>
23 #include <linux/mm.h>
24 #include <linux/timer.h>
25 #include <asm/unaligned.h>
26 #include <asm/cacheflush.h>
27 #include <linux/gpio.h>
28
29 #include "isp1760-hcd.h"
30
31 static struct kmem_cache *qtd_cachep;
32 static struct kmem_cache *qh_cachep;
33 static struct kmem_cache *urb_listitem_cachep;
34
35 struct isp1760_hcd {
36 u32 hcs_params;
37 spinlock_t lock;
38 struct slotinfo atl_slots[32];
39 int atl_done_map;
40 struct slotinfo int_slots[32];
41 int int_done_map;
42 struct memory_chunk memory_pool[BLOCKS];
43 struct list_head controlqhs, bulkqhs, interruptqhs;
44
45 /* periodic schedule support */
46 #define DEFAULT_I_TDPS 1024
47 unsigned periodic_size;
48 unsigned i_thresh;
49 unsigned long reset_done;
50 unsigned long next_statechange;
51 unsigned int devflags;
52
53 int rst_gpio;
54 };
55
56 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
57 {
58 return (struct isp1760_hcd *) (hcd->hcd_priv);
59 }
60
61 /* Section 2.2 Host Controller Capability Registers */
62 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
63 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
64 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
65 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
66 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
67 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
68 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
69
70 /* Section 2.3 Host Controller Operational Registers */
71 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
72 #define CMD_RESET (1<<1) /* reset HC not bus */
73 #define CMD_RUN (1<<0) /* start/stop HC */
74 #define STS_PCD (1<<2) /* port change detect */
75 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
76
77 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
78 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
79 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
80 #define PORT_RESET (1<<8) /* reset port */
81 #define PORT_SUSPEND (1<<7) /* suspend port */
82 #define PORT_RESUME (1<<6) /* resume it */
83 #define PORT_PE (1<<2) /* port enable */
84 #define PORT_CSC (1<<1) /* connect status change */
85 #define PORT_CONNECT (1<<0) /* device connected */
86 #define PORT_RWC_BITS (PORT_CSC)
87
88 struct isp1760_qtd {
89 u8 packet_type;
90 void *data_buffer;
91 u32 payload_addr;
92
93 /* the rest is HCD-private */
94 struct list_head qtd_list;
95 struct urb *urb;
96 size_t length;
97 size_t actual_length;
98
99 /* QTD_ENQUEUED: waiting for transfer (inactive) */
100 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
101 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
102 interrupt handler may touch this qtd! */
103 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
104 /* QTD_RETIRE: transfer error/abort qtd */
105 #define QTD_ENQUEUED 0
106 #define QTD_PAYLOAD_ALLOC 1
107 #define QTD_XFER_STARTED 2
108 #define QTD_XFER_COMPLETE 3
109 #define QTD_RETIRE 4
110 u32 status;
111 };
112
113 /* Queue head, one for each active endpoint */
114 struct isp1760_qh {
115 struct list_head qh_list;
116 struct list_head qtd_list;
117 u32 toggle;
118 u32 ping;
119 int slot;
120 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
121 };
122
123 struct urb_listitem {
124 struct list_head urb_list;
125 struct urb *urb;
126 };
127
128 /*
129 * Access functions for isp176x registers (addresses 0..0x03FF).
130 */
131 static u32 reg_read32(void __iomem *base, u32 reg)
132 {
133 return readl(base + reg);
134 }
135
136 static void reg_write32(void __iomem *base, u32 reg, u32 val)
137 {
138 writel(val, base + reg);
139 }
140
141 /*
142 * Access functions for isp176x memory (offset >= 0x0400).
143 *
144 * bank_reads8() reads memory locations prefetched by an earlier write to
145 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
146 * bank optimizations, you should use the more generic mem_reads8() below.
147 *
148 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
149 * below.
150 *
151 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
152 * doesn't quite work because some people have to enforce 32-bit access
153 */
154 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
155 __u32 *dst, u32 bytes)
156 {
157 __u32 __iomem *src;
158 u32 val;
159 __u8 *src_byteptr;
160 __u8 *dst_byteptr;
161
162 src = src_base + (bank_addr | src_offset);
163
164 if (src_offset < PAYLOAD_OFFSET) {
165 while (bytes >= 4) {
166 *dst = le32_to_cpu(__raw_readl(src));
167 bytes -= 4;
168 src++;
169 dst++;
170 }
171 } else {
172 while (bytes >= 4) {
173 *dst = __raw_readl(src);
174 bytes -= 4;
175 src++;
176 dst++;
177 }
178 }
179
180 if (!bytes)
181 return;
182
183 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
184 * allocated.
185 */
186 if (src_offset < PAYLOAD_OFFSET)
187 val = le32_to_cpu(__raw_readl(src));
188 else
189 val = __raw_readl(src);
190
191 dst_byteptr = (void *) dst;
192 src_byteptr = (void *) &val;
193 while (bytes > 0) {
194 *dst_byteptr = *src_byteptr;
195 dst_byteptr++;
196 src_byteptr++;
197 bytes--;
198 }
199 }
200
201 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
202 u32 bytes)
203 {
204 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
205 ndelay(90);
206 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
207 }
208
209 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
210 __u32 const *src, u32 bytes)
211 {
212 __u32 __iomem *dst;
213
214 dst = dst_base + dst_offset;
215
216 if (dst_offset < PAYLOAD_OFFSET) {
217 while (bytes >= 4) {
218 __raw_writel(cpu_to_le32(*src), dst);
219 bytes -= 4;
220 src++;
221 dst++;
222 }
223 } else {
224 while (bytes >= 4) {
225 __raw_writel(*src, dst);
226 bytes -= 4;
227 src++;
228 dst++;
229 }
230 }
231
232 if (!bytes)
233 return;
234 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
235 * extra bytes should not be read by the HW.
236 */
237
238 if (dst_offset < PAYLOAD_OFFSET)
239 __raw_writel(cpu_to_le32(*src), dst);
240 else
241 __raw_writel(*src, dst);
242 }
243
244 /*
245 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
246 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
247 */
248 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
249 struct ptd *ptd)
250 {
251 reg_write32(base, HC_MEMORY_REG,
252 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
253 ndelay(90);
254 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
255 (void *) ptd, sizeof(*ptd));
256 }
257
258 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
259 struct ptd *ptd)
260 {
261 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
262 &ptd->dw1, 7*sizeof(ptd->dw1));
263 /* Make sure dw0 gets written last (after other dw's and after payload)
264 since it contains the enable bit */
265 wmb();
266 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
267 sizeof(ptd->dw0));
268 }
269
270
271 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
272 static void init_memory(struct isp1760_hcd *priv)
273 {
274 int i, curr;
275 u32 payload_addr;
276
277 payload_addr = PAYLOAD_OFFSET;
278 for (i = 0; i < BLOCK_1_NUM; i++) {
279 priv->memory_pool[i].start = payload_addr;
280 priv->memory_pool[i].size = BLOCK_1_SIZE;
281 priv->memory_pool[i].free = 1;
282 payload_addr += priv->memory_pool[i].size;
283 }
284
285 curr = i;
286 for (i = 0; i < BLOCK_2_NUM; i++) {
287 priv->memory_pool[curr + i].start = payload_addr;
288 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
289 priv->memory_pool[curr + i].free = 1;
290 payload_addr += priv->memory_pool[curr + i].size;
291 }
292
293 curr = i;
294 for (i = 0; i < BLOCK_3_NUM; i++) {
295 priv->memory_pool[curr + i].start = payload_addr;
296 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
297 priv->memory_pool[curr + i].free = 1;
298 payload_addr += priv->memory_pool[curr + i].size;
299 }
300
301 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
302 }
303
304 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
305 {
306 struct isp1760_hcd *priv = hcd_to_priv(hcd);
307 int i;
308
309 WARN_ON(qtd->payload_addr);
310
311 if (!qtd->length)
312 return;
313
314 for (i = 0; i < BLOCKS; i++) {
315 if (priv->memory_pool[i].size >= qtd->length &&
316 priv->memory_pool[i].free) {
317 priv->memory_pool[i].free = 0;
318 qtd->payload_addr = priv->memory_pool[i].start;
319 return;
320 }
321 }
322 }
323
324 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
325 {
326 struct isp1760_hcd *priv = hcd_to_priv(hcd);
327 int i;
328
329 if (!qtd->payload_addr)
330 return;
331
332 for (i = 0; i < BLOCKS; i++) {
333 if (priv->memory_pool[i].start == qtd->payload_addr) {
334 WARN_ON(priv->memory_pool[i].free);
335 priv->memory_pool[i].free = 1;
336 qtd->payload_addr = 0;
337 return;
338 }
339 }
340
341 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
342 __func__, qtd->payload_addr);
343 WARN_ON(1);
344 qtd->payload_addr = 0;
345 }
346
347 static int handshake(struct usb_hcd *hcd, u32 reg,
348 u32 mask, u32 done, int usec)
349 {
350 u32 result;
351
352 do {
353 result = reg_read32(hcd->regs, reg);
354 if (result == ~0)
355 return -ENODEV;
356 result &= mask;
357 if (result == done)
358 return 0;
359 udelay(1);
360 usec--;
361 } while (usec > 0);
362 return -ETIMEDOUT;
363 }
364
365 /* reset a non-running (STS_HALT == 1) controller */
366 static int ehci_reset(struct usb_hcd *hcd)
367 {
368 int retval;
369 struct isp1760_hcd *priv = hcd_to_priv(hcd);
370
371 u32 command = reg_read32(hcd->regs, HC_USBCMD);
372
373 command |= CMD_RESET;
374 reg_write32(hcd->regs, HC_USBCMD, command);
375 hcd->state = HC_STATE_HALT;
376 priv->next_statechange = jiffies;
377 retval = handshake(hcd, HC_USBCMD,
378 CMD_RESET, 0, 250 * 1000);
379 return retval;
380 }
381
382 static struct isp1760_qh *qh_alloc(gfp_t flags)
383 {
384 struct isp1760_qh *qh;
385
386 qh = kmem_cache_zalloc(qh_cachep, flags);
387 if (!qh)
388 return NULL;
389
390 INIT_LIST_HEAD(&qh->qh_list);
391 INIT_LIST_HEAD(&qh->qtd_list);
392 qh->slot = -1;
393
394 return qh;
395 }
396
397 static void qh_free(struct isp1760_qh *qh)
398 {
399 WARN_ON(!list_empty(&qh->qtd_list));
400 WARN_ON(qh->slot > -1);
401 kmem_cache_free(qh_cachep, qh);
402 }
403
404 /* one-time init, only for memory state */
405 static int priv_init(struct usb_hcd *hcd)
406 {
407 struct isp1760_hcd *priv = hcd_to_priv(hcd);
408 u32 hcc_params;
409
410 spin_lock_init(&priv->lock);
411
412 INIT_LIST_HEAD(&priv->interruptqhs);
413 INIT_LIST_HEAD(&priv->controlqhs);
414 INIT_LIST_HEAD(&priv->bulkqhs);
415
416 /*
417 * hw default: 1K periodic list heads, one per frame.
418 * periodic_size can shrink by USBCMD update if hcc_params allows.
419 */
420 priv->periodic_size = DEFAULT_I_TDPS;
421
422 /* controllers may cache some of the periodic schedule ... */
423 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
424 /* full frame cache */
425 if (HCC_ISOC_CACHE(hcc_params))
426 priv->i_thresh = 8;
427 else /* N microframes cached */
428 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
429
430 return 0;
431 }
432
433 static int isp1760_hc_setup(struct usb_hcd *hcd)
434 {
435 struct isp1760_hcd *priv = hcd_to_priv(hcd);
436 int result;
437 u32 scratch, hwmode;
438
439 /* low-level chip reset */
440 if (gpio_is_valid(priv->rst_gpio)) {
441 unsigned int rst_lvl;
442
443 rst_lvl = (priv->devflags &
444 ISP1760_FLAG_RESET_ACTIVE_HIGH) ? 1 : 0;
445
446 gpio_set_value(priv->rst_gpio, rst_lvl);
447 mdelay(50);
448 gpio_set_value(priv->rst_gpio, !rst_lvl);
449 }
450
451 /* Setup HW Mode Control: This assumes a level active-low interrupt */
452 hwmode = HW_DATA_BUS_32BIT;
453
454 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
455 hwmode &= ~HW_DATA_BUS_32BIT;
456 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
457 hwmode |= HW_ANA_DIGI_OC;
458 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
459 hwmode |= HW_DACK_POL_HIGH;
460 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
461 hwmode |= HW_DREQ_POL_HIGH;
462 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
463 hwmode |= HW_INTR_HIGH_ACT;
464 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
465 hwmode |= HW_INTR_EDGE_TRIG;
466
467 /*
468 * We have to set this first in case we're in 16-bit mode.
469 * Write it twice to ensure correct upper bits if switching
470 * to 16-bit mode.
471 */
472 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
473 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
474
475 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
476 /* Change bus pattern */
477 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
478 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
479 if (scratch != 0xdeadbabe) {
480 dev_err(hcd->self.controller, "Scratch test failed.\n");
481 return -ENODEV;
482 }
483
484 /* pre reset */
485 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
486 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
487 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
488 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
489
490 /* reset */
491 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
492 mdelay(100);
493
494 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
495 mdelay(100);
496
497 result = ehci_reset(hcd);
498 if (result)
499 return result;
500
501 /* Step 11 passed */
502
503 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
504 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
505 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
506 "analog" : "digital");
507
508 /* ATL reset */
509 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
510 mdelay(10);
511 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
512
513 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
514
515 /*
516 * PORT 1 Control register of the ISP1760 is the OTG control
517 * register on ISP1761. Since there is no OTG or device controller
518 * support in this driver, we use port 1 as a "normal" USB host port on
519 * both chips.
520 */
521 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
522 mdelay(10);
523
524 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
525
526 return priv_init(hcd);
527 }
528
529 static u32 base_to_chip(u32 base)
530 {
531 return ((base - 0x400) >> 3);
532 }
533
534 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
535 {
536 struct urb *urb;
537
538 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
539 return 1;
540
541 urb = qtd->urb;
542 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
543 return (qtd->urb != urb);
544 }
545
546 /* magic numbers that can affect system performance */
547 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
548 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
549 #define EHCI_TUNE_RL_TT 0
550 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
551 #define EHCI_TUNE_MULT_TT 1
552 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
553
554 static void create_ptd_atl(struct isp1760_qh *qh,
555 struct isp1760_qtd *qtd, struct ptd *ptd)
556 {
557 u32 maxpacket;
558 u32 multi;
559 u32 rl = RL_COUNTER;
560 u32 nak = NAK_COUNTER;
561
562 memset(ptd, 0, sizeof(*ptd));
563
564 /* according to 3.6.2, max packet len can not be > 0x400 */
565 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
566 usb_pipeout(qtd->urb->pipe));
567 multi = 1 + ((maxpacket >> 11) & 0x3);
568 maxpacket &= 0x7ff;
569
570 /* DW0 */
571 ptd->dw0 = DW0_VALID_BIT;
572 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
573 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
574 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
575
576 /* DW1 */
577 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
578 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
579 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
580
581 if (usb_pipebulk(qtd->urb->pipe))
582 ptd->dw1 |= DW1_TRANS_BULK;
583 else if (usb_pipeint(qtd->urb->pipe))
584 ptd->dw1 |= DW1_TRANS_INT;
585
586 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
587 /* split transaction */
588
589 ptd->dw1 |= DW1_TRANS_SPLIT;
590 if (qtd->urb->dev->speed == USB_SPEED_LOW)
591 ptd->dw1 |= DW1_SE_USB_LOSPEED;
592
593 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
594 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
595
596 /* SE bit for Split INT transfers */
597 if (usb_pipeint(qtd->urb->pipe) &&
598 (qtd->urb->dev->speed == USB_SPEED_LOW))
599 ptd->dw1 |= 2 << 16;
600
601 rl = 0;
602 nak = 0;
603 } else {
604 ptd->dw0 |= TO_DW0_MULTI(multi);
605 if (usb_pipecontrol(qtd->urb->pipe) ||
606 usb_pipebulk(qtd->urb->pipe))
607 ptd->dw3 |= TO_DW3_PING(qh->ping);
608 }
609 /* DW2 */
610 ptd->dw2 = 0;
611 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
612 ptd->dw2 |= TO_DW2_RL(rl);
613
614 /* DW3 */
615 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
616 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
617 if (usb_pipecontrol(qtd->urb->pipe)) {
618 if (qtd->data_buffer == qtd->urb->setup_packet)
619 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
620 else if (last_qtd_of_urb(qtd, qh))
621 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
622 }
623
624 ptd->dw3 |= DW3_ACTIVE_BIT;
625 /* Cerr */
626 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
627 }
628
629 static void transform_add_int(struct isp1760_qh *qh,
630 struct isp1760_qtd *qtd, struct ptd *ptd)
631 {
632 u32 usof;
633 u32 period;
634
635 /*
636 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
637 * the algorithm from the original Philips driver code, which was
638 * pretty much used in this driver before as well, is quite horrendous
639 * and, i believe, incorrect. The code below follows the datasheet and
640 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
641 * more reliable this way (fingers crossed...).
642 */
643
644 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
645 /* urb->interval is in units of microframes (1/8 ms) */
646 period = qtd->urb->interval >> 3;
647
648 if (qtd->urb->interval > 4)
649 usof = 0x01; /* One bit set =>
650 interval 1 ms * uFrame-match */
651 else if (qtd->urb->interval > 2)
652 usof = 0x22; /* Two bits set => interval 1/2 ms */
653 else if (qtd->urb->interval > 1)
654 usof = 0x55; /* Four bits set => interval 1/4 ms */
655 else
656 usof = 0xff; /* All bits set => interval 1/8 ms */
657 } else {
658 /* urb->interval is in units of frames (1 ms) */
659 period = qtd->urb->interval;
660 usof = 0x0f; /* Execute Start Split on any of the
661 four first uFrames */
662
663 /*
664 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
665 * complete split needs to be sent. Valid only for IN." Also,
666 * "All bits can be set to one for every transfer." (p 82,
667 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
668 * that number come from? 0xff seems to work fine...
669 */
670 /* ptd->dw5 = 0x1c; */
671 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
672 }
673
674 period = period >> 1;/* Ensure equal or shorter period than requested */
675 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
676
677 ptd->dw2 |= period;
678 ptd->dw4 = usof;
679 }
680
681 static void create_ptd_int(struct isp1760_qh *qh,
682 struct isp1760_qtd *qtd, struct ptd *ptd)
683 {
684 create_ptd_atl(qh, qtd, ptd);
685 transform_add_int(qh, qtd, ptd);
686 }
687
688 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
689 __releases(priv->lock)
690 __acquires(priv->lock)
691 {
692 struct isp1760_hcd *priv = hcd_to_priv(hcd);
693
694 if (!urb->unlinked) {
695 if (urb->status == -EINPROGRESS)
696 urb->status = 0;
697 }
698
699 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
700 void *ptr;
701 for (ptr = urb->transfer_buffer;
702 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
703 ptr += PAGE_SIZE)
704 flush_dcache_page(virt_to_page(ptr));
705 }
706
707 /* complete() can reenter this HCD */
708 usb_hcd_unlink_urb_from_ep(hcd, urb);
709 spin_unlock(&priv->lock);
710 usb_hcd_giveback_urb(hcd, urb, urb->status);
711 spin_lock(&priv->lock);
712 }
713
714 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
715 u8 packet_type)
716 {
717 struct isp1760_qtd *qtd;
718
719 qtd = kmem_cache_zalloc(qtd_cachep, flags);
720 if (!qtd)
721 return NULL;
722
723 INIT_LIST_HEAD(&qtd->qtd_list);
724 qtd->urb = urb;
725 qtd->packet_type = packet_type;
726 qtd->status = QTD_ENQUEUED;
727 qtd->actual_length = 0;
728
729 return qtd;
730 }
731
732 static void qtd_free(struct isp1760_qtd *qtd)
733 {
734 WARN_ON(qtd->payload_addr);
735 kmem_cache_free(qtd_cachep, qtd);
736 }
737
738 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
739 struct slotinfo *slots, struct isp1760_qtd *qtd,
740 struct isp1760_qh *qh, struct ptd *ptd)
741 {
742 struct isp1760_hcd *priv = hcd_to_priv(hcd);
743 int skip_map;
744
745 WARN_ON((slot < 0) || (slot > 31));
746 WARN_ON(qtd->length && !qtd->payload_addr);
747 WARN_ON(slots[slot].qtd);
748 WARN_ON(slots[slot].qh);
749 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
750
751 /* Make sure done map has not triggered from some unlinked transfer */
752 if (ptd_offset == ATL_PTD_OFFSET) {
753 priv->atl_done_map |= reg_read32(hcd->regs,
754 HC_ATL_PTD_DONEMAP_REG);
755 priv->atl_done_map &= ~(1 << slot);
756 } else {
757 priv->int_done_map |= reg_read32(hcd->regs,
758 HC_INT_PTD_DONEMAP_REG);
759 priv->int_done_map &= ~(1 << slot);
760 }
761
762 qh->slot = slot;
763 qtd->status = QTD_XFER_STARTED;
764 slots[slot].timestamp = jiffies;
765 slots[slot].qtd = qtd;
766 slots[slot].qh = qh;
767 ptd_write(hcd->regs, ptd_offset, slot, ptd);
768
769 if (ptd_offset == ATL_PTD_OFFSET) {
770 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
771 skip_map &= ~(1 << qh->slot);
772 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
773 } else {
774 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
775 skip_map &= ~(1 << qh->slot);
776 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
777 }
778 }
779
780 static int is_short_bulk(struct isp1760_qtd *qtd)
781 {
782 return (usb_pipebulk(qtd->urb->pipe) &&
783 (qtd->actual_length < qtd->length));
784 }
785
786 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
787 struct list_head *urb_list)
788 {
789 int last_qtd;
790 struct isp1760_qtd *qtd, *qtd_next;
791 struct urb_listitem *urb_listitem;
792
793 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
794 if (qtd->status < QTD_XFER_COMPLETE)
795 break;
796
797 last_qtd = last_qtd_of_urb(qtd, qh);
798
799 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
800 qtd_next->status = QTD_RETIRE;
801
802 if (qtd->status == QTD_XFER_COMPLETE) {
803 if (qtd->actual_length) {
804 switch (qtd->packet_type) {
805 case IN_PID:
806 mem_reads8(hcd->regs, qtd->payload_addr,
807 qtd->data_buffer,
808 qtd->actual_length);
809 /* Fall through (?) */
810 case OUT_PID:
811 qtd->urb->actual_length +=
812 qtd->actual_length;
813 /* Fall through ... */
814 case SETUP_PID:
815 break;
816 }
817 }
818
819 if (is_short_bulk(qtd)) {
820 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
821 qtd->urb->status = -EREMOTEIO;
822 if (!last_qtd)
823 qtd_next->status = QTD_RETIRE;
824 }
825 }
826
827 if (qtd->payload_addr)
828 free_mem(hcd, qtd);
829
830 if (last_qtd) {
831 if ((qtd->status == QTD_RETIRE) &&
832 (qtd->urb->status == -EINPROGRESS))
833 qtd->urb->status = -EPIPE;
834 /* Defer calling of urb_done() since it releases lock */
835 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
836 GFP_ATOMIC);
837 if (unlikely(!urb_listitem))
838 break; /* Try again on next call */
839 urb_listitem->urb = qtd->urb;
840 list_add_tail(&urb_listitem->urb_list, urb_list);
841 }
842
843 list_del(&qtd->qtd_list);
844 qtd_free(qtd);
845 }
846 }
847
848 #define ENQUEUE_DEPTH 2
849 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
850 {
851 struct isp1760_hcd *priv = hcd_to_priv(hcd);
852 int ptd_offset;
853 struct slotinfo *slots;
854 int curr_slot, free_slot;
855 int n;
856 struct ptd ptd;
857 struct isp1760_qtd *qtd;
858
859 if (unlikely(list_empty(&qh->qtd_list))) {
860 WARN_ON(1);
861 return;
862 }
863
864 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
865 if (qh->tt_buffer_dirty)
866 return;
867
868 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
869 qtd_list)->urb->pipe)) {
870 ptd_offset = INT_PTD_OFFSET;
871 slots = priv->int_slots;
872 } else {
873 ptd_offset = ATL_PTD_OFFSET;
874 slots = priv->atl_slots;
875 }
876
877 free_slot = -1;
878 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
879 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
880 free_slot = curr_slot;
881 if (slots[curr_slot].qh == qh)
882 break;
883 }
884
885 n = 0;
886 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
887 if (qtd->status == QTD_ENQUEUED) {
888 WARN_ON(qtd->payload_addr);
889 alloc_mem(hcd, qtd);
890 if ((qtd->length) && (!qtd->payload_addr))
891 break;
892
893 if ((qtd->length) &&
894 ((qtd->packet_type == SETUP_PID) ||
895 (qtd->packet_type == OUT_PID))) {
896 mem_writes8(hcd->regs, qtd->payload_addr,
897 qtd->data_buffer, qtd->length);
898 }
899
900 qtd->status = QTD_PAYLOAD_ALLOC;
901 }
902
903 if (qtd->status == QTD_PAYLOAD_ALLOC) {
904 /*
905 if ((curr_slot > 31) && (free_slot == -1))
906 dev_dbg(hcd->self.controller, "%s: No slot "
907 "available for transfer\n", __func__);
908 */
909 /* Start xfer for this endpoint if not already done */
910 if ((curr_slot > 31) && (free_slot > -1)) {
911 if (usb_pipeint(qtd->urb->pipe))
912 create_ptd_int(qh, qtd, &ptd);
913 else
914 create_ptd_atl(qh, qtd, &ptd);
915
916 start_bus_transfer(hcd, ptd_offset, free_slot,
917 slots, qtd, qh, &ptd);
918 curr_slot = free_slot;
919 }
920
921 n++;
922 if (n >= ENQUEUE_DEPTH)
923 break;
924 }
925 }
926 }
927
928 void schedule_ptds(struct usb_hcd *hcd)
929 {
930 struct isp1760_hcd *priv;
931 struct isp1760_qh *qh, *qh_next;
932 struct list_head *ep_queue;
933 struct usb_host_endpoint *ep;
934 LIST_HEAD(urb_list);
935 struct urb_listitem *urb_listitem, *urb_listitem_next;
936
937 if (!hcd) {
938 WARN_ON(1);
939 return;
940 }
941
942 priv = hcd_to_priv(hcd);
943
944 /*
945 * check finished/retired xfers, transfer payloads, call urb_done()
946 */
947 ep_queue = &priv->interruptqhs;
948 while (ep_queue) {
949 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
950 ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
951 qtd_list)->urb->ep;
952 collect_qtds(hcd, qh, &urb_list);
953 if (list_empty(&qh->qtd_list)) {
954 list_del(&qh->qh_list);
955 if (ep->hcpriv == NULL) {
956 /* Endpoint has been disabled, so we
957 can free the associated queue head. */
958 qh_free(qh);
959 }
960 }
961 }
962
963 if (ep_queue == &priv->interruptqhs)
964 ep_queue = &priv->controlqhs;
965 else if (ep_queue == &priv->controlqhs)
966 ep_queue = &priv->bulkqhs;
967 else
968 ep_queue = NULL;
969 }
970
971 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
972 urb_list) {
973 isp1760_urb_done(hcd, urb_listitem->urb);
974 kmem_cache_free(urb_listitem_cachep, urb_listitem);
975 }
976
977 /*
978 * Schedule packets for transfer.
979 *
980 * According to USB2.0 specification:
981 *
982 * 1st prio: interrupt xfers, up to 80 % of bandwidth
983 * 2nd prio: control xfers
984 * 3rd prio: bulk xfers
985 *
986 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
987 * is very unclear on how to prioritize traffic):
988 *
989 * 1) Enqueue any queued control transfers, as long as payload chip mem
990 * and PTD ATL slots are available.
991 * 2) Enqueue any queued INT transfers, as long as payload chip mem
992 * and PTD INT slots are available.
993 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
994 * and PTD ATL slots are available.
995 *
996 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
997 * conservation of chip mem and performance.
998 *
999 * I'm sure this scheme could be improved upon!
1000 */
1001 ep_queue = &priv->controlqhs;
1002 while (ep_queue) {
1003 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1004 enqueue_qtds(hcd, qh);
1005
1006 if (ep_queue == &priv->controlqhs)
1007 ep_queue = &priv->interruptqhs;
1008 else if (ep_queue == &priv->interruptqhs)
1009 ep_queue = &priv->bulkqhs;
1010 else
1011 ep_queue = NULL;
1012 }
1013 }
1014
1015 #define PTD_STATE_QTD_DONE 1
1016 #define PTD_STATE_QTD_RELOAD 2
1017 #define PTD_STATE_URB_RETIRE 3
1018
1019 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1020 struct urb *urb)
1021 {
1022 __dw dw4;
1023 int i;
1024
1025 dw4 = ptd->dw4;
1026 dw4 >>= 8;
1027
1028 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1029 need to handle these errors? Is it done in hardware? */
1030
1031 if (ptd->dw3 & DW3_HALT_BIT) {
1032
1033 urb->status = -EPROTO; /* Default unknown error */
1034
1035 for (i = 0; i < 8; i++) {
1036 switch (dw4 & 0x7) {
1037 case INT_UNDERRUN:
1038 dev_dbg(hcd->self.controller, "%s: underrun "
1039 "during uFrame %d\n",
1040 __func__, i);
1041 urb->status = -ECOMM; /* Could not write data */
1042 break;
1043 case INT_EXACT:
1044 dev_dbg(hcd->self.controller, "%s: transaction "
1045 "error during uFrame %d\n",
1046 __func__, i);
1047 urb->status = -EPROTO; /* timeout, bad CRC, PID
1048 error etc. */
1049 break;
1050 case INT_BABBLE:
1051 dev_dbg(hcd->self.controller, "%s: babble "
1052 "error during uFrame %d\n",
1053 __func__, i);
1054 urb->status = -EOVERFLOW;
1055 break;
1056 }
1057 dw4 >>= 3;
1058 }
1059
1060 return PTD_STATE_URB_RETIRE;
1061 }
1062
1063 return PTD_STATE_QTD_DONE;
1064 }
1065
1066 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1067 struct urb *urb)
1068 {
1069 WARN_ON(!ptd);
1070 if (ptd->dw3 & DW3_HALT_BIT) {
1071 if (ptd->dw3 & DW3_BABBLE_BIT)
1072 urb->status = -EOVERFLOW;
1073 else if (FROM_DW3_CERR(ptd->dw3))
1074 urb->status = -EPIPE; /* Stall */
1075 else if (ptd->dw3 & DW3_ERROR_BIT)
1076 urb->status = -EPROTO; /* XactErr */
1077 else
1078 urb->status = -EPROTO; /* Unknown */
1079 /*
1080 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1081 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1082 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1083 __func__,
1084 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1085 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1086 */
1087 return PTD_STATE_URB_RETIRE;
1088 }
1089
1090 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1091 /* Transfer Error, *but* active and no HALT -> reload */
1092 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1093 return PTD_STATE_QTD_RELOAD;
1094 }
1095
1096 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1097 /*
1098 * NAKs are handled in HW by the chip. Usually if the
1099 * device is not able to send data fast enough.
1100 * This happens mostly on slower hardware.
1101 */
1102 return PTD_STATE_QTD_RELOAD;
1103 }
1104
1105 return PTD_STATE_QTD_DONE;
1106 }
1107
1108 static void handle_done_ptds(struct usb_hcd *hcd)
1109 {
1110 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1111 struct ptd ptd;
1112 struct isp1760_qh *qh;
1113 int slot;
1114 int state;
1115 struct slotinfo *slots;
1116 u32 ptd_offset;
1117 struct isp1760_qtd *qtd;
1118 int modified;
1119 int skip_map;
1120
1121 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1122 priv->int_done_map &= ~skip_map;
1123 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1124 priv->atl_done_map &= ~skip_map;
1125
1126 modified = priv->int_done_map || priv->atl_done_map;
1127
1128 while (priv->int_done_map || priv->atl_done_map) {
1129 if (priv->int_done_map) {
1130 /* INT ptd */
1131 slot = __ffs(priv->int_done_map);
1132 priv->int_done_map &= ~(1 << slot);
1133 slots = priv->int_slots;
1134 /* This should not trigger, and could be removed if
1135 noone have any problems with it triggering: */
1136 if (!slots[slot].qh) {
1137 WARN_ON(1);
1138 continue;
1139 }
1140 ptd_offset = INT_PTD_OFFSET;
1141 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1142 state = check_int_transfer(hcd, &ptd,
1143 slots[slot].qtd->urb);
1144 } else {
1145 /* ATL ptd */
1146 slot = __ffs(priv->atl_done_map);
1147 priv->atl_done_map &= ~(1 << slot);
1148 slots = priv->atl_slots;
1149 /* This should not trigger, and could be removed if
1150 noone have any problems with it triggering: */
1151 if (!slots[slot].qh) {
1152 WARN_ON(1);
1153 continue;
1154 }
1155 ptd_offset = ATL_PTD_OFFSET;
1156 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1157 state = check_atl_transfer(hcd, &ptd,
1158 slots[slot].qtd->urb);
1159 }
1160
1161 qtd = slots[slot].qtd;
1162 slots[slot].qtd = NULL;
1163 qh = slots[slot].qh;
1164 slots[slot].qh = NULL;
1165 qh->slot = -1;
1166
1167 WARN_ON(qtd->status != QTD_XFER_STARTED);
1168
1169 switch (state) {
1170 case PTD_STATE_QTD_DONE:
1171 if ((usb_pipeint(qtd->urb->pipe)) &&
1172 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1173 qtd->actual_length =
1174 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1175 else
1176 qtd->actual_length =
1177 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1178
1179 qtd->status = QTD_XFER_COMPLETE;
1180 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1181 is_short_bulk(qtd))
1182 qtd = NULL;
1183 else
1184 qtd = list_entry(qtd->qtd_list.next,
1185 typeof(*qtd), qtd_list);
1186
1187 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1188 qh->ping = FROM_DW3_PING(ptd.dw3);
1189 break;
1190
1191 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1192 qtd->status = QTD_PAYLOAD_ALLOC;
1193 ptd.dw0 |= DW0_VALID_BIT;
1194 /* RL counter = ERR counter */
1195 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1196 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1197 ptd.dw3 &= ~TO_DW3_CERR(3);
1198 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1199 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1200 qh->ping = FROM_DW3_PING(ptd.dw3);
1201 break;
1202
1203 case PTD_STATE_URB_RETIRE:
1204 qtd->status = QTD_RETIRE;
1205 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1206 (qtd->urb->status != -EPIPE) &&
1207 (qtd->urb->status != -EREMOTEIO)) {
1208 qh->tt_buffer_dirty = 1;
1209 if (usb_hub_clear_tt_buffer(qtd->urb))
1210 /* Clear failed; let's hope things work
1211 anyway */
1212 qh->tt_buffer_dirty = 0;
1213 }
1214 qtd = NULL;
1215 qh->toggle = 0;
1216 qh->ping = 0;
1217 break;
1218
1219 default:
1220 WARN_ON(1);
1221 continue;
1222 }
1223
1224 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1225 if (slots == priv->int_slots) {
1226 if (state == PTD_STATE_QTD_RELOAD)
1227 dev_err(hcd->self.controller,
1228 "%s: PTD_STATE_QTD_RELOAD on "
1229 "interrupt packet\n", __func__);
1230 if (state != PTD_STATE_QTD_RELOAD)
1231 create_ptd_int(qh, qtd, &ptd);
1232 } else {
1233 if (state != PTD_STATE_QTD_RELOAD)
1234 create_ptd_atl(qh, qtd, &ptd);
1235 }
1236
1237 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1238 qh, &ptd);
1239 }
1240 }
1241
1242 if (modified)
1243 schedule_ptds(hcd);
1244 }
1245
1246 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1247 {
1248 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1249 u32 imask;
1250 irqreturn_t irqret = IRQ_NONE;
1251
1252 spin_lock(&priv->lock);
1253
1254 if (!(hcd->state & HC_STATE_RUNNING))
1255 goto leave;
1256
1257 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1258 if (unlikely(!imask))
1259 goto leave;
1260 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1261
1262 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1263 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1264
1265 handle_done_ptds(hcd);
1266
1267 irqret = IRQ_HANDLED;
1268 leave:
1269 spin_unlock(&priv->lock);
1270
1271 return irqret;
1272 }
1273
1274 /*
1275 * Workaround for problem described in chip errata 2:
1276 *
1277 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1278 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1279 * ATL done interrupts (the "instead of" might be important since it seems
1280 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1281 * to set the PTD's done bit in addition to not generating an interrupt!).
1282 *
1283 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1284 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1285 *
1286 * If we use SOF interrupts only, we get latency between ptd completion and the
1287 * actual handling. This is very noticeable in testusb runs which takes several
1288 * minutes longer without ATL interrupts.
1289 *
1290 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1291 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1292 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1293 * completed and its done map bit is set.
1294 *
1295 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1296 * not to cause too much lag when this HW bug occurs, while still hopefully
1297 * ensuring that the check does not falsely trigger.
1298 */
1299 #define SLOT_TIMEOUT 300
1300 #define SLOT_CHECK_PERIOD 200
1301 static struct timer_list errata2_timer;
1302
1303 void errata2_function(unsigned long data)
1304 {
1305 struct usb_hcd *hcd = (struct usb_hcd *) data;
1306 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1307 int slot;
1308 struct ptd ptd;
1309 unsigned long spinflags;
1310
1311 spin_lock_irqsave(&priv->lock, spinflags);
1312
1313 for (slot = 0; slot < 32; slot++)
1314 if (priv->atl_slots[slot].qh && time_after(jiffies,
1315 priv->atl_slots[slot].timestamp +
1316 SLOT_TIMEOUT * HZ / 1000)) {
1317 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1318 if (!FROM_DW0_VALID(ptd.dw0) &&
1319 !FROM_DW3_ACTIVE(ptd.dw3))
1320 priv->atl_done_map |= 1 << slot;
1321 }
1322
1323 if (priv->atl_done_map)
1324 handle_done_ptds(hcd);
1325
1326 spin_unlock_irqrestore(&priv->lock, spinflags);
1327
1328 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1329 add_timer(&errata2_timer);
1330 }
1331
1332 static int isp1760_run(struct usb_hcd *hcd)
1333 {
1334 int retval;
1335 u32 temp;
1336 u32 command;
1337 u32 chipid;
1338
1339 hcd->uses_new_polling = 1;
1340
1341 hcd->state = HC_STATE_RUNNING;
1342
1343 /* Set PTD interrupt AND & OR maps */
1344 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1345 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1346 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1347 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1348 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1349 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1350 /* step 23 passed */
1351
1352 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1353 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1354
1355 command = reg_read32(hcd->regs, HC_USBCMD);
1356 command &= ~(CMD_LRESET|CMD_RESET);
1357 command |= CMD_RUN;
1358 reg_write32(hcd->regs, HC_USBCMD, command);
1359
1360 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1361 if (retval)
1362 return retval;
1363
1364 /*
1365 * XXX
1366 * Spec says to write FLAG_CF as last config action, priv code grabs
1367 * the semaphore while doing so.
1368 */
1369 down_write(&ehci_cf_port_reset_rwsem);
1370 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1371
1372 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1373 up_write(&ehci_cf_port_reset_rwsem);
1374 if (retval)
1375 return retval;
1376
1377 init_timer(&errata2_timer);
1378 errata2_timer.function = errata2_function;
1379 errata2_timer.data = (unsigned long) hcd;
1380 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1381 add_timer(&errata2_timer);
1382
1383 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1384 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1385 chipid & 0xffff, chipid >> 16);
1386
1387 /* PTD Register Init Part 2, Step 28 */
1388
1389 /* Setup registers controlling PTD checking */
1390 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1391 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1392 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1393 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1394 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1395 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1396 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1397 ATL_BUF_FILL | INT_BUF_FILL);
1398
1399 /* GRR this is run-once init(), being done every time the HC starts.
1400 * So long as they're part of class devices, we can't do it init()
1401 * since the class device isn't created that early.
1402 */
1403 return 0;
1404 }
1405
1406 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1407 {
1408 qtd->data_buffer = databuffer;
1409
1410 if (len > MAX_PAYLOAD_SIZE)
1411 len = MAX_PAYLOAD_SIZE;
1412 qtd->length = len;
1413
1414 return qtd->length;
1415 }
1416
1417 static void qtd_list_free(struct list_head *qtd_list)
1418 {
1419 struct isp1760_qtd *qtd, *qtd_next;
1420
1421 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1422 list_del(&qtd->qtd_list);
1423 qtd_free(qtd);
1424 }
1425 }
1426
1427 /*
1428 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1429 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1430 */
1431 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1432 static void packetize_urb(struct usb_hcd *hcd,
1433 struct urb *urb, struct list_head *head, gfp_t flags)
1434 {
1435 struct isp1760_qtd *qtd;
1436 void *buf;
1437 int len, maxpacketsize;
1438 u8 packet_type;
1439
1440 /*
1441 * URBs map to sequences of QTDs: one logical transaction
1442 */
1443
1444 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1445 /* XXX This looks like usb storage / SCSI bug */
1446 dev_err(hcd->self.controller,
1447 "buf is null, dma is %08lx len is %d\n",
1448 (long unsigned)urb->transfer_dma,
1449 urb->transfer_buffer_length);
1450 WARN_ON(1);
1451 }
1452
1453 if (usb_pipein(urb->pipe))
1454 packet_type = IN_PID;
1455 else
1456 packet_type = OUT_PID;
1457
1458 if (usb_pipecontrol(urb->pipe)) {
1459 qtd = qtd_alloc(flags, urb, SETUP_PID);
1460 if (!qtd)
1461 goto cleanup;
1462 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1463 list_add_tail(&qtd->qtd_list, head);
1464
1465 /* for zero length DATA stages, STATUS is always IN */
1466 if (urb->transfer_buffer_length == 0)
1467 packet_type = IN_PID;
1468 }
1469
1470 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1471 usb_pipeout(urb->pipe)));
1472
1473 /*
1474 * buffer gets wrapped in one or more qtds;
1475 * last one may be "short" (including zero len)
1476 * and may serve as a control status ack
1477 */
1478 buf = urb->transfer_buffer;
1479 len = urb->transfer_buffer_length;
1480
1481 for (;;) {
1482 int this_qtd_len;
1483
1484 qtd = qtd_alloc(flags, urb, packet_type);
1485 if (!qtd)
1486 goto cleanup;
1487 this_qtd_len = qtd_fill(qtd, buf, len);
1488 list_add_tail(&qtd->qtd_list, head);
1489
1490 len -= this_qtd_len;
1491 buf += this_qtd_len;
1492
1493 if (len <= 0)
1494 break;
1495 }
1496
1497 /*
1498 * control requests may need a terminating data "status" ack;
1499 * bulk ones may need a terminating short packet (zero length).
1500 */
1501 if (urb->transfer_buffer_length != 0) {
1502 int one_more = 0;
1503
1504 if (usb_pipecontrol(urb->pipe)) {
1505 one_more = 1;
1506 if (packet_type == IN_PID)
1507 packet_type = OUT_PID;
1508 else
1509 packet_type = IN_PID;
1510 } else if (usb_pipebulk(urb->pipe)
1511 && (urb->transfer_flags & URB_ZERO_PACKET)
1512 && !(urb->transfer_buffer_length %
1513 maxpacketsize)) {
1514 one_more = 1;
1515 }
1516 if (one_more) {
1517 qtd = qtd_alloc(flags, urb, packet_type);
1518 if (!qtd)
1519 goto cleanup;
1520
1521 /* never any data in such packets */
1522 qtd_fill(qtd, NULL, 0);
1523 list_add_tail(&qtd->qtd_list, head);
1524 }
1525 }
1526
1527 return;
1528
1529 cleanup:
1530 qtd_list_free(head);
1531 }
1532
1533 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1534 gfp_t mem_flags)
1535 {
1536 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1537 struct list_head *ep_queue;
1538 struct isp1760_qh *qh, *qhit;
1539 unsigned long spinflags;
1540 LIST_HEAD(new_qtds);
1541 int retval;
1542 int qh_in_queue;
1543
1544 switch (usb_pipetype(urb->pipe)) {
1545 case PIPE_CONTROL:
1546 ep_queue = &priv->controlqhs;
1547 break;
1548 case PIPE_BULK:
1549 ep_queue = &priv->bulkqhs;
1550 break;
1551 case PIPE_INTERRUPT:
1552 if (urb->interval < 0)
1553 return -EINVAL;
1554 /* FIXME: Check bandwidth */
1555 ep_queue = &priv->interruptqhs;
1556 break;
1557 case PIPE_ISOCHRONOUS:
1558 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1559 "not yet supported\n",
1560 __func__);
1561 return -EPIPE;
1562 default:
1563 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1564 __func__);
1565 return -EPIPE;
1566 }
1567
1568 if (usb_pipein(urb->pipe))
1569 urb->actual_length = 0;
1570
1571 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1572 if (list_empty(&new_qtds))
1573 return -ENOMEM;
1574
1575 retval = 0;
1576 spin_lock_irqsave(&priv->lock, spinflags);
1577
1578 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1579 retval = -ESHUTDOWN;
1580 goto out;
1581 }
1582 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1583 if (retval)
1584 goto out;
1585
1586 qh = urb->ep->hcpriv;
1587 if (qh) {
1588 qh_in_queue = 0;
1589 list_for_each_entry(qhit, ep_queue, qh_list) {
1590 if (qhit == qh) {
1591 qh_in_queue = 1;
1592 break;
1593 }
1594 }
1595 if (!qh_in_queue)
1596 list_add_tail(&qh->qh_list, ep_queue);
1597 } else {
1598 qh = qh_alloc(GFP_ATOMIC);
1599 if (!qh) {
1600 retval = -ENOMEM;
1601 usb_hcd_unlink_urb_from_ep(hcd, urb);
1602 goto out;
1603 }
1604 list_add_tail(&qh->qh_list, ep_queue);
1605 urb->ep->hcpriv = qh;
1606 }
1607
1608 list_splice_tail(&new_qtds, &qh->qtd_list);
1609 schedule_ptds(hcd);
1610
1611 out:
1612 spin_unlock_irqrestore(&priv->lock, spinflags);
1613 return retval;
1614 }
1615
1616 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1617 struct isp1760_qh *qh)
1618 {
1619 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1620 int skip_map;
1621
1622 WARN_ON(qh->slot == -1);
1623
1624 /* We need to forcefully reclaim the slot since some transfers never
1625 return, e.g. interrupt transfers and NAKed bulk transfers. */
1626 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1627 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1628 skip_map |= (1 << qh->slot);
1629 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1630 priv->atl_slots[qh->slot].qh = NULL;
1631 priv->atl_slots[qh->slot].qtd = NULL;
1632 } else {
1633 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1634 skip_map |= (1 << qh->slot);
1635 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1636 priv->int_slots[qh->slot].qh = NULL;
1637 priv->int_slots[qh->slot].qtd = NULL;
1638 }
1639
1640 qh->slot = -1;
1641 }
1642
1643 /*
1644 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1645 * any active transfer belonging to the urb in the process.
1646 */
1647 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1648 struct isp1760_qtd *qtd)
1649 {
1650 struct urb *urb;
1651 int urb_was_running;
1652
1653 urb = qtd->urb;
1654 urb_was_running = 0;
1655 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1656 if (qtd->urb != urb)
1657 break;
1658
1659 if (qtd->status >= QTD_XFER_STARTED)
1660 urb_was_running = 1;
1661 if (last_qtd_of_urb(qtd, qh) &&
1662 (qtd->status >= QTD_XFER_COMPLETE))
1663 urb_was_running = 0;
1664
1665 if (qtd->status == QTD_XFER_STARTED)
1666 kill_transfer(hcd, urb, qh);
1667 qtd->status = QTD_RETIRE;
1668 }
1669
1670 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1671 qh->tt_buffer_dirty = 1;
1672 if (usb_hub_clear_tt_buffer(urb))
1673 /* Clear failed; let's hope things work anyway */
1674 qh->tt_buffer_dirty = 0;
1675 }
1676 }
1677
1678 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1679 int status)
1680 {
1681 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1682 unsigned long spinflags;
1683 struct isp1760_qh *qh;
1684 struct isp1760_qtd *qtd;
1685 int retval = 0;
1686
1687 spin_lock_irqsave(&priv->lock, spinflags);
1688 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1689 if (retval)
1690 goto out;
1691
1692 qh = urb->ep->hcpriv;
1693 if (!qh) {
1694 retval = -EINVAL;
1695 goto out;
1696 }
1697
1698 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1699 if (qtd->urb == urb) {
1700 dequeue_urb_from_qtd(hcd, qh, qtd);
1701 break;
1702 }
1703
1704 urb->status = status;
1705 schedule_ptds(hcd);
1706
1707 out:
1708 spin_unlock_irqrestore(&priv->lock, spinflags);
1709 return retval;
1710 }
1711
1712 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1713 struct usb_host_endpoint *ep)
1714 {
1715 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1716 unsigned long spinflags;
1717 struct isp1760_qh *qh;
1718 struct isp1760_qtd *qtd;
1719
1720 spin_lock_irqsave(&priv->lock, spinflags);
1721
1722 qh = ep->hcpriv;
1723 if (!qh)
1724 goto out;
1725
1726 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1727 if (qtd->status != QTD_RETIRE) {
1728 dequeue_urb_from_qtd(hcd, qh, qtd);
1729 qtd->urb->status = -ECONNRESET;
1730 }
1731
1732 ep->hcpriv = NULL;
1733 /* Cannot free qh here since it will be parsed by schedule_ptds() */
1734
1735 schedule_ptds(hcd);
1736
1737 out:
1738 spin_unlock_irqrestore(&priv->lock, spinflags);
1739 }
1740
1741 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1742 {
1743 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1744 u32 temp, status = 0;
1745 u32 mask;
1746 int retval = 1;
1747 unsigned long flags;
1748
1749 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1750 if (!HC_IS_RUNNING(hcd->state))
1751 return 0;
1752
1753 /* init status to no-changes */
1754 buf[0] = 0;
1755 mask = PORT_CSC;
1756
1757 spin_lock_irqsave(&priv->lock, flags);
1758 temp = reg_read32(hcd->regs, HC_PORTSC1);
1759
1760 if (temp & PORT_OWNER) {
1761 if (temp & PORT_CSC) {
1762 temp &= ~PORT_CSC;
1763 reg_write32(hcd->regs, HC_PORTSC1, temp);
1764 goto done;
1765 }
1766 }
1767
1768 /*
1769 * Return status information even for ports with OWNER set.
1770 * Otherwise khubd wouldn't see the disconnect event when a
1771 * high-speed device is switched over to the companion
1772 * controller by the user.
1773 */
1774
1775 if ((temp & mask) != 0
1776 || ((temp & PORT_RESUME) != 0
1777 && time_after_eq(jiffies,
1778 priv->reset_done))) {
1779 buf [0] |= 1 << (0 + 1);
1780 status = STS_PCD;
1781 }
1782 /* FIXME autosuspend idle root hubs */
1783 done:
1784 spin_unlock_irqrestore(&priv->lock, flags);
1785 return status ? retval : 0;
1786 }
1787
1788 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1789 struct usb_hub_descriptor *desc)
1790 {
1791 int ports = HCS_N_PORTS(priv->hcs_params);
1792 u16 temp;
1793
1794 desc->bDescriptorType = 0x29;
1795 /* priv 1.0, 2.3.9 says 20ms max */
1796 desc->bPwrOn2PwrGood = 10;
1797 desc->bHubContrCurrent = 0;
1798
1799 desc->bNbrPorts = ports;
1800 temp = 1 + (ports / 8);
1801 desc->bDescLength = 7 + 2 * temp;
1802
1803 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1804 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1805 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1806
1807 /* per-port overcurrent reporting */
1808 temp = 0x0008;
1809 if (HCS_PPC(priv->hcs_params))
1810 /* per-port power control */
1811 temp |= 0x0001;
1812 else
1813 /* no power switching */
1814 temp |= 0x0002;
1815 desc->wHubCharacteristics = cpu_to_le16(temp);
1816 }
1817
1818 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1819
1820 static int check_reset_complete(struct usb_hcd *hcd, int index,
1821 int port_status)
1822 {
1823 if (!(port_status & PORT_CONNECT))
1824 return port_status;
1825
1826 /* if reset finished and it's still not enabled -- handoff */
1827 if (!(port_status & PORT_PE)) {
1828
1829 dev_info(hcd->self.controller,
1830 "port %d full speed --> companion\n",
1831 index + 1);
1832
1833 port_status |= PORT_OWNER;
1834 port_status &= ~PORT_RWC_BITS;
1835 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1836
1837 } else
1838 dev_info(hcd->self.controller, "port %d high speed\n",
1839 index + 1);
1840
1841 return port_status;
1842 }
1843
1844 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1845 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1846 {
1847 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1848 int ports = HCS_N_PORTS(priv->hcs_params);
1849 u32 temp, status;
1850 unsigned long flags;
1851 int retval = 0;
1852 unsigned selector;
1853
1854 /*
1855 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1856 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1857 * (track current state ourselves) ... blink for diagnostics,
1858 * power, "this is the one", etc. EHCI spec supports this.
1859 */
1860
1861 spin_lock_irqsave(&priv->lock, flags);
1862 switch (typeReq) {
1863 case ClearHubFeature:
1864 switch (wValue) {
1865 case C_HUB_LOCAL_POWER:
1866 case C_HUB_OVER_CURRENT:
1867 /* no hub-wide feature/status flags */
1868 break;
1869 default:
1870 goto error;
1871 }
1872 break;
1873 case ClearPortFeature:
1874 if (!wIndex || wIndex > ports)
1875 goto error;
1876 wIndex--;
1877 temp = reg_read32(hcd->regs, HC_PORTSC1);
1878
1879 /*
1880 * Even if OWNER is set, so the port is owned by the
1881 * companion controller, khubd needs to be able to clear
1882 * the port-change status bits (especially
1883 * USB_PORT_STAT_C_CONNECTION).
1884 */
1885
1886 switch (wValue) {
1887 case USB_PORT_FEAT_ENABLE:
1888 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1889 break;
1890 case USB_PORT_FEAT_C_ENABLE:
1891 /* XXX error? */
1892 break;
1893 case USB_PORT_FEAT_SUSPEND:
1894 if (temp & PORT_RESET)
1895 goto error;
1896
1897 if (temp & PORT_SUSPEND) {
1898 if ((temp & PORT_PE) == 0)
1899 goto error;
1900 /* resume signaling for 20 msec */
1901 temp &= ~(PORT_RWC_BITS);
1902 reg_write32(hcd->regs, HC_PORTSC1,
1903 temp | PORT_RESUME);
1904 priv->reset_done = jiffies +
1905 msecs_to_jiffies(20);
1906 }
1907 break;
1908 case USB_PORT_FEAT_C_SUSPEND:
1909 /* we auto-clear this feature */
1910 break;
1911 case USB_PORT_FEAT_POWER:
1912 if (HCS_PPC(priv->hcs_params))
1913 reg_write32(hcd->regs, HC_PORTSC1,
1914 temp & ~PORT_POWER);
1915 break;
1916 case USB_PORT_FEAT_C_CONNECTION:
1917 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1918 break;
1919 case USB_PORT_FEAT_C_OVER_CURRENT:
1920 /* XXX error ?*/
1921 break;
1922 case USB_PORT_FEAT_C_RESET:
1923 /* GetPortStatus clears reset */
1924 break;
1925 default:
1926 goto error;
1927 }
1928 reg_read32(hcd->regs, HC_USBCMD);
1929 break;
1930 case GetHubDescriptor:
1931 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1932 buf);
1933 break;
1934 case GetHubStatus:
1935 /* no hub-wide feature/status flags */
1936 memset(buf, 0, 4);
1937 break;
1938 case GetPortStatus:
1939 if (!wIndex || wIndex > ports)
1940 goto error;
1941 wIndex--;
1942 status = 0;
1943 temp = reg_read32(hcd->regs, HC_PORTSC1);
1944
1945 /* wPortChange bits */
1946 if (temp & PORT_CSC)
1947 status |= USB_PORT_STAT_C_CONNECTION << 16;
1948
1949
1950 /* whoever resumes must GetPortStatus to complete it!! */
1951 if (temp & PORT_RESUME) {
1952 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1953
1954 /* Remote Wakeup received? */
1955 if (!priv->reset_done) {
1956 /* resume signaling for 20 msec */
1957 priv->reset_done = jiffies
1958 + msecs_to_jiffies(20);
1959 /* check the port again */
1960 mod_timer(&hcd->rh_timer, priv->reset_done);
1961 }
1962
1963 /* resume completed? */
1964 else if (time_after_eq(jiffies,
1965 priv->reset_done)) {
1966 status |= USB_PORT_STAT_C_SUSPEND << 16;
1967 priv->reset_done = 0;
1968
1969 /* stop resume signaling */
1970 temp = reg_read32(hcd->regs, HC_PORTSC1);
1971 reg_write32(hcd->regs, HC_PORTSC1,
1972 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1973 retval = handshake(hcd, HC_PORTSC1,
1974 PORT_RESUME, 0, 2000 /* 2msec */);
1975 if (retval != 0) {
1976 dev_err(hcd->self.controller,
1977 "port %d resume error %d\n",
1978 wIndex + 1, retval);
1979 goto error;
1980 }
1981 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1982 }
1983 }
1984
1985 /* whoever resets must GetPortStatus to complete it!! */
1986 if ((temp & PORT_RESET)
1987 && time_after_eq(jiffies,
1988 priv->reset_done)) {
1989 status |= USB_PORT_STAT_C_RESET << 16;
1990 priv->reset_done = 0;
1991
1992 /* force reset to complete */
1993 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1994 /* REVISIT: some hardware needs 550+ usec to clear
1995 * this bit; seems too long to spin routinely...
1996 */
1997 retval = handshake(hcd, HC_PORTSC1,
1998 PORT_RESET, 0, 750);
1999 if (retval != 0) {
2000 dev_err(hcd->self.controller, "port %d reset error %d\n",
2001 wIndex + 1, retval);
2002 goto error;
2003 }
2004
2005 /* see what we found out */
2006 temp = check_reset_complete(hcd, wIndex,
2007 reg_read32(hcd->regs, HC_PORTSC1));
2008 }
2009 /*
2010 * Even if OWNER is set, there's no harm letting khubd
2011 * see the wPortStatus values (they should all be 0 except
2012 * for PORT_POWER anyway).
2013 */
2014
2015 if (temp & PORT_OWNER)
2016 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2017
2018 if (temp & PORT_CONNECT) {
2019 status |= USB_PORT_STAT_CONNECTION;
2020 /* status may be from integrated TT */
2021 status |= USB_PORT_STAT_HIGH_SPEED;
2022 }
2023 if (temp & PORT_PE)
2024 status |= USB_PORT_STAT_ENABLE;
2025 if (temp & (PORT_SUSPEND|PORT_RESUME))
2026 status |= USB_PORT_STAT_SUSPEND;
2027 if (temp & PORT_RESET)
2028 status |= USB_PORT_STAT_RESET;
2029 if (temp & PORT_POWER)
2030 status |= USB_PORT_STAT_POWER;
2031
2032 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2033 break;
2034 case SetHubFeature:
2035 switch (wValue) {
2036 case C_HUB_LOCAL_POWER:
2037 case C_HUB_OVER_CURRENT:
2038 /* no hub-wide feature/status flags */
2039 break;
2040 default:
2041 goto error;
2042 }
2043 break;
2044 case SetPortFeature:
2045 selector = wIndex >> 8;
2046 wIndex &= 0xff;
2047 if (!wIndex || wIndex > ports)
2048 goto error;
2049 wIndex--;
2050 temp = reg_read32(hcd->regs, HC_PORTSC1);
2051 if (temp & PORT_OWNER)
2052 break;
2053
2054 /* temp &= ~PORT_RWC_BITS; */
2055 switch (wValue) {
2056 case USB_PORT_FEAT_ENABLE:
2057 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2058 break;
2059
2060 case USB_PORT_FEAT_SUSPEND:
2061 if ((temp & PORT_PE) == 0
2062 || (temp & PORT_RESET) != 0)
2063 goto error;
2064
2065 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2066 break;
2067 case USB_PORT_FEAT_POWER:
2068 if (HCS_PPC(priv->hcs_params))
2069 reg_write32(hcd->regs, HC_PORTSC1,
2070 temp | PORT_POWER);
2071 break;
2072 case USB_PORT_FEAT_RESET:
2073 if (temp & PORT_RESUME)
2074 goto error;
2075 /* line status bits may report this as low speed,
2076 * which can be fine if this root hub has a
2077 * transaction translator built in.
2078 */
2079 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2080 && PORT_USB11(temp)) {
2081 temp |= PORT_OWNER;
2082 } else {
2083 temp |= PORT_RESET;
2084 temp &= ~PORT_PE;
2085
2086 /*
2087 * caller must wait, then call GetPortStatus
2088 * usb 2.0 spec says 50 ms resets on root
2089 */
2090 priv->reset_done = jiffies +
2091 msecs_to_jiffies(50);
2092 }
2093 reg_write32(hcd->regs, HC_PORTSC1, temp);
2094 break;
2095 default:
2096 goto error;
2097 }
2098 reg_read32(hcd->regs, HC_USBCMD);
2099 break;
2100
2101 default:
2102 error:
2103 /* "stall" on error */
2104 retval = -EPIPE;
2105 }
2106 spin_unlock_irqrestore(&priv->lock, flags);
2107 return retval;
2108 }
2109
2110 static int isp1760_get_frame(struct usb_hcd *hcd)
2111 {
2112 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2113 u32 fr;
2114
2115 fr = reg_read32(hcd->regs, HC_FRINDEX);
2116 return (fr >> 3) % priv->periodic_size;
2117 }
2118
2119 static void isp1760_stop(struct usb_hcd *hcd)
2120 {
2121 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2122 u32 temp;
2123
2124 del_timer(&errata2_timer);
2125
2126 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2127 NULL, 0);
2128 mdelay(20);
2129
2130 spin_lock_irq(&priv->lock);
2131 ehci_reset(hcd);
2132 /* Disable IRQ */
2133 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2134 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2135 spin_unlock_irq(&priv->lock);
2136
2137 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2138 }
2139
2140 static void isp1760_shutdown(struct usb_hcd *hcd)
2141 {
2142 u32 command, temp;
2143
2144 isp1760_stop(hcd);
2145 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2146 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2147
2148 command = reg_read32(hcd->regs, HC_USBCMD);
2149 command &= ~CMD_RUN;
2150 reg_write32(hcd->regs, HC_USBCMD, command);
2151 }
2152
2153 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2154 struct usb_host_endpoint *ep)
2155 {
2156 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2157 struct isp1760_qh *qh = ep->hcpriv;
2158 unsigned long spinflags;
2159
2160 if (!qh)
2161 return;
2162
2163 spin_lock_irqsave(&priv->lock, spinflags);
2164 qh->tt_buffer_dirty = 0;
2165 schedule_ptds(hcd);
2166 spin_unlock_irqrestore(&priv->lock, spinflags);
2167 }
2168
2169
2170 static const struct hc_driver isp1760_hc_driver = {
2171 .description = "isp1760-hcd",
2172 .product_desc = "NXP ISP1760 USB Host Controller",
2173 .hcd_priv_size = sizeof(struct isp1760_hcd),
2174 .irq = isp1760_irq,
2175 .flags = HCD_MEMORY | HCD_USB2,
2176 .reset = isp1760_hc_setup,
2177 .start = isp1760_run,
2178 .stop = isp1760_stop,
2179 .shutdown = isp1760_shutdown,
2180 .urb_enqueue = isp1760_urb_enqueue,
2181 .urb_dequeue = isp1760_urb_dequeue,
2182 .endpoint_disable = isp1760_endpoint_disable,
2183 .get_frame_number = isp1760_get_frame,
2184 .hub_status_data = isp1760_hub_status_data,
2185 .hub_control = isp1760_hub_control,
2186 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2187 };
2188
2189 int __init init_kmem_once(void)
2190 {
2191 urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2192 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2193 SLAB_MEM_SPREAD, NULL);
2194
2195 if (!urb_listitem_cachep)
2196 return -ENOMEM;
2197
2198 qtd_cachep = kmem_cache_create("isp1760_qtd",
2199 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2200 SLAB_MEM_SPREAD, NULL);
2201
2202 if (!qtd_cachep)
2203 return -ENOMEM;
2204
2205 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2206 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2207
2208 if (!qh_cachep) {
2209 kmem_cache_destroy(qtd_cachep);
2210 return -ENOMEM;
2211 }
2212
2213 return 0;
2214 }
2215
2216 void deinit_kmem_cache(void)
2217 {
2218 kmem_cache_destroy(qtd_cachep);
2219 kmem_cache_destroy(qh_cachep);
2220 kmem_cache_destroy(urb_listitem_cachep);
2221 }
2222
2223 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2224 int irq, unsigned long irqflags,
2225 int rst_gpio,
2226 struct device *dev, const char *busname,
2227 unsigned int devflags)
2228 {
2229 struct usb_hcd *hcd;
2230 struct isp1760_hcd *priv;
2231 int ret;
2232
2233 if (usb_disabled())
2234 return ERR_PTR(-ENODEV);
2235
2236 /* prevent usb-core allocating DMA pages */
2237 dev->dma_mask = NULL;
2238
2239 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2240 if (!hcd)
2241 return ERR_PTR(-ENOMEM);
2242
2243 priv = hcd_to_priv(hcd);
2244 priv->devflags = devflags;
2245 priv->rst_gpio = rst_gpio;
2246 init_memory(priv);
2247 hcd->regs = ioremap(res_start, res_len);
2248 if (!hcd->regs) {
2249 ret = -EIO;
2250 goto err_put;
2251 }
2252
2253 hcd->irq = irq;
2254 hcd->rsrc_start = res_start;
2255 hcd->rsrc_len = res_len;
2256
2257 ret = usb_add_hcd(hcd, irq, irqflags);
2258 if (ret)
2259 goto err_unmap;
2260
2261 return hcd;
2262
2263 err_unmap:
2264 iounmap(hcd->regs);
2265
2266 err_put:
2267 usb_put_hcd(hcd);
2268
2269 return ERR_PTR(ret);
2270 }
2271
2272 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2273 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2274 MODULE_LICENSE("GPL v2");
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