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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / drivers / video / omap2 / dss / dsi.c
blob43c04a9889c46214819781126d841e38bf004e62
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/debugfs.h>
39 #include <linux/pm_runtime.h>
40
41 #include <video/omapdss.h>
42 #include <video/mipi_display.h>
43 #include <plat/clock.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47
48 /*#define VERBOSE_IRQ*/
49 #define DSI_CATCH_MISSING_TE
50
51 struct dsi_reg { u16 idx; };
52
53 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
54
55 #define DSI_SZ_REGS SZ_1K
56 /* DSI Protocol Engine */
57
58 #define DSI_REVISION DSI_REG(0x0000)
59 #define DSI_SYSCONFIG DSI_REG(0x0010)
60 #define DSI_SYSSTATUS DSI_REG(0x0014)
61 #define DSI_IRQSTATUS DSI_REG(0x0018)
62 #define DSI_IRQENABLE DSI_REG(0x001C)
63 #define DSI_CTRL DSI_REG(0x0040)
64 #define DSI_GNQ DSI_REG(0x0044)
65 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
66 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
67 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
68 #define DSI_CLK_CTRL DSI_REG(0x0054)
69 #define DSI_TIMING1 DSI_REG(0x0058)
70 #define DSI_TIMING2 DSI_REG(0x005C)
71 #define DSI_VM_TIMING1 DSI_REG(0x0060)
72 #define DSI_VM_TIMING2 DSI_REG(0x0064)
73 #define DSI_VM_TIMING3 DSI_REG(0x0068)
74 #define DSI_CLK_TIMING DSI_REG(0x006C)
75 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
76 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
77 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
78 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
79 #define DSI_VM_TIMING4 DSI_REG(0x0080)
80 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
81 #define DSI_VM_TIMING5 DSI_REG(0x0088)
82 #define DSI_VM_TIMING6 DSI_REG(0x008C)
83 #define DSI_VM_TIMING7 DSI_REG(0x0090)
84 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
85 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
86 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
89 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
90 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
91 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
92
93 /* DSIPHY_SCP */
94
95 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
96 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
97 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
98 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
99 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
100
101 /* DSI_PLL_CTRL_SCP */
102
103 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
104 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
105 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
106 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
107 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
108
109 #define REG_GET(dsidev, idx, start, end) \
110 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
111
112 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
113 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
114
115 /* Global interrupts */
116 #define DSI_IRQ_VC0 (1 << 0)
117 #define DSI_IRQ_VC1 (1 << 1)
118 #define DSI_IRQ_VC2 (1 << 2)
119 #define DSI_IRQ_VC3 (1 << 3)
120 #define DSI_IRQ_WAKEUP (1 << 4)
121 #define DSI_IRQ_RESYNC (1 << 5)
122 #define DSI_IRQ_PLL_LOCK (1 << 7)
123 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
124 #define DSI_IRQ_PLL_RECALL (1 << 9)
125 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
126 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
127 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
128 #define DSI_IRQ_TE_TRIGGER (1 << 16)
129 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
130 #define DSI_IRQ_SYNC_LOST (1 << 18)
131 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
132 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
133 #define DSI_IRQ_ERROR_MASK \
134 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
135 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
136 #define DSI_IRQ_CHANNEL_MASK 0xf
137
138 /* Virtual channel interrupts */
139 #define DSI_VC_IRQ_CS (1 << 0)
140 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
141 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
142 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
143 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
144 #define DSI_VC_IRQ_BTA (1 << 5)
145 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
146 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
147 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
148 #define DSI_VC_IRQ_ERROR_MASK \
149 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
150 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
151 DSI_VC_IRQ_FIFO_TX_UDF)
152
153 /* ComplexIO interrupts */
154 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
155 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
156 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
157 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
158 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
159 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
160 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
161 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
162 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
163 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
164 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
165 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
166 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
167 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
168 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
169 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
170 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
171 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
172 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
173 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
186 #define DSI_CIO_IRQ_ERROR_MASK \
187 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
188 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
189 DSI_CIO_IRQ_ERRSYNCESC5 | \
190 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
191 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
192 DSI_CIO_IRQ_ERRESC5 | \
193 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
194 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
195 DSI_CIO_IRQ_ERRCONTROL5 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
201
202 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
203
204 #define DSI_MAX_NR_ISRS 2
205
206 struct dsi_isr_data {
207 omap_dsi_isr_t isr;
208 void *arg;
209 u32 mask;
210 };
211
212 enum fifo_size {
213 DSI_FIFO_SIZE_0 = 0,
214 DSI_FIFO_SIZE_32 = 1,
215 DSI_FIFO_SIZE_64 = 2,
216 DSI_FIFO_SIZE_96 = 3,
217 DSI_FIFO_SIZE_128 = 4,
218 };
219
220 enum dsi_vc_source {
221 DSI_VC_SOURCE_L4 = 0,
222 DSI_VC_SOURCE_VP,
223 };
224
225 enum dsi_lane {
226 DSI_CLK_P = 1 << 0,
227 DSI_CLK_N = 1 << 1,
228 DSI_DATA1_P = 1 << 2,
229 DSI_DATA1_N = 1 << 3,
230 DSI_DATA2_P = 1 << 4,
231 DSI_DATA2_N = 1 << 5,
232 DSI_DATA3_P = 1 << 6,
233 DSI_DATA3_N = 1 << 7,
234 DSI_DATA4_P = 1 << 8,
235 DSI_DATA4_N = 1 << 9,
236 };
237
238 struct dsi_update_region {
239 u16 x, y, w, h;
240 struct omap_dss_device *device;
241 };
242
243 struct dsi_irq_stats {
244 unsigned long last_reset;
245 unsigned irq_count;
246 unsigned dsi_irqs[32];
247 unsigned vc_irqs[4][32];
248 unsigned cio_irqs[32];
249 };
250
251 struct dsi_isr_tables {
252 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
253 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
255 };
256
257 struct dsi_data {
258 struct platform_device *pdev;
259 void __iomem *base;
260
261 int irq;
262
263 struct clk *dss_clk;
264 struct clk *sys_clk;
265
266 int (*enable_pads)(int dsi_id, unsigned lane_mask);
267 void (*disable_pads)(int dsi_id, unsigned lane_mask);
268
269 struct dsi_clock_info current_cinfo;
270
271 bool vdds_dsi_enabled;
272 struct regulator *vdds_dsi_reg;
273
274 struct {
275 enum dsi_vc_source source;
276 struct omap_dss_device *dssdev;
277 enum fifo_size fifo_size;
278 int vc_id;
279 } vc[4];
280
281 struct mutex lock;
282 struct semaphore bus_lock;
283
284 unsigned pll_locked;
285
286 spinlock_t irq_lock;
287 struct dsi_isr_tables isr_tables;
288 /* space for a copy used by the interrupt handler */
289 struct dsi_isr_tables isr_tables_copy;
290
291 int update_channel;
292 struct dsi_update_region update_region;
293
294 bool te_enabled;
295 bool ulps_enabled;
296
297 void (*framedone_callback)(int, void *);
298 void *framedone_data;
299
300 struct delayed_work framedone_timeout_work;
301
302 #ifdef DSI_CATCH_MISSING_TE
303 struct timer_list te_timer;
304 #endif
305
306 unsigned long cache_req_pck;
307 unsigned long cache_clk_freq;
308 struct dsi_clock_info cache_cinfo;
309
310 u32 errors;
311 spinlock_t errors_lock;
312 #ifdef DEBUG
313 ktime_t perf_setup_time;
314 ktime_t perf_start_time;
315 #endif
316 int debug_read;
317 int debug_write;
318
319 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
320 spinlock_t irq_stats_lock;
321 struct dsi_irq_stats irq_stats;
322 #endif
323 /* DSI PLL Parameter Ranges */
324 unsigned long regm_max, regn_max;
325 unsigned long regm_dispc_max, regm_dsi_max;
326 unsigned long fint_min, fint_max;
327 unsigned long lpdiv_max;
328
329 int num_data_lanes;
330
331 unsigned scp_clk_refcount;
332 };
333
334 struct dsi_packet_sent_handler_data {
335 struct platform_device *dsidev;
336 struct completion *completion;
337 };
338
339 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
340
341 #ifdef DEBUG
342 static unsigned int dsi_perf;
343 module_param_named(dsi_perf, dsi_perf, bool, 0644);
344 #endif
345
346 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
347 {
348 return dev_get_drvdata(&dsidev->dev);
349 }
350
351 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
352 {
353 return dsi_pdev_map[dssdev->phy.dsi.module];
354 }
355
356 struct platform_device *dsi_get_dsidev_from_id(int module)
357 {
358 return dsi_pdev_map[module];
359 }
360
361 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
362 {
363 return dsidev->id;
364 }
365
366 static inline void dsi_write_reg(struct platform_device *dsidev,
367 const struct dsi_reg idx, u32 val)
368 {
369 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
370
371 __raw_writel(val, dsi->base + idx.idx);
372 }
373
374 static inline u32 dsi_read_reg(struct platform_device *dsidev,
375 const struct dsi_reg idx)
376 {
377 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
378
379 return __raw_readl(dsi->base + idx.idx);
380 }
381
382 void dsi_bus_lock(struct omap_dss_device *dssdev)
383 {
384 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
386
387 down(&dsi->bus_lock);
388 }
389 EXPORT_SYMBOL(dsi_bus_lock);
390
391 void dsi_bus_unlock(struct omap_dss_device *dssdev)
392 {
393 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
394 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
395
396 up(&dsi->bus_lock);
397 }
398 EXPORT_SYMBOL(dsi_bus_unlock);
399
400 static bool dsi_bus_is_locked(struct platform_device *dsidev)
401 {
402 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
403
404 return dsi->bus_lock.count == 0;
405 }
406
407 static void dsi_completion_handler(void *data, u32 mask)
408 {
409 complete((struct completion *)data);
410 }
411
412 static inline int wait_for_bit_change(struct platform_device *dsidev,
413 const struct dsi_reg idx, int bitnum, int value)
414 {
415 int t = 100000;
416
417 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
418 if (--t == 0)
419 return !value;
420 }
421
422 return value;
423 }
424
425 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
426 {
427 switch (fmt) {
428 case OMAP_DSS_DSI_FMT_RGB888:
429 case OMAP_DSS_DSI_FMT_RGB666:
430 return 24;
431 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
432 return 18;
433 case OMAP_DSS_DSI_FMT_RGB565:
434 return 16;
435 default:
436 BUG();
437 }
438 }
439
440 #ifdef DEBUG
441 static void dsi_perf_mark_setup(struct platform_device *dsidev)
442 {
443 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
444 dsi->perf_setup_time = ktime_get();
445 }
446
447 static void dsi_perf_mark_start(struct platform_device *dsidev)
448 {
449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
450 dsi->perf_start_time = ktime_get();
451 }
452
453 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
454 {
455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
456 struct omap_dss_device *dssdev = dsi->update_region.device;
457 ktime_t t, setup_time, trans_time;
458 u32 total_bytes;
459 u32 setup_us, trans_us, total_us;
460
461 if (!dsi_perf)
462 return;
463
464 t = ktime_get();
465
466 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
467 setup_us = (u32)ktime_to_us(setup_time);
468 if (setup_us == 0)
469 setup_us = 1;
470
471 trans_time = ktime_sub(t, dsi->perf_start_time);
472 trans_us = (u32)ktime_to_us(trans_time);
473 if (trans_us == 0)
474 trans_us = 1;
475
476 total_us = setup_us + trans_us;
477
478 total_bytes = dsi->update_region.w *
479 dsi->update_region.h *
480 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
481
482 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
483 "%u bytes, %u kbytes/sec\n",
484 name,
485 setup_us,
486 trans_us,
487 total_us,
488 1000*1000 / total_us,
489 total_bytes,
490 total_bytes * 1000 / total_us);
491 }
492 #else
493 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
494 {
495 }
496
497 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
498 {
499 }
500
501 static inline void dsi_perf_show(struct platform_device *dsidev,
502 const char *name)
503 {
504 }
505 #endif
506
507 static void print_irq_status(u32 status)
508 {
509 if (status == 0)
510 return;
511
512 #ifndef VERBOSE_IRQ
513 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
514 return;
515 #endif
516 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
517
518 #define PIS(x) \
519 if (status & DSI_IRQ_##x) \
520 printk(#x " ");
521 #ifdef VERBOSE_IRQ
522 PIS(VC0);
523 PIS(VC1);
524 PIS(VC2);
525 PIS(VC3);
526 #endif
527 PIS(WAKEUP);
528 PIS(RESYNC);
529 PIS(PLL_LOCK);
530 PIS(PLL_UNLOCK);
531 PIS(PLL_RECALL);
532 PIS(COMPLEXIO_ERR);
533 PIS(HS_TX_TIMEOUT);
534 PIS(LP_RX_TIMEOUT);
535 PIS(TE_TRIGGER);
536 PIS(ACK_TRIGGER);
537 PIS(SYNC_LOST);
538 PIS(LDO_POWER_GOOD);
539 PIS(TA_TIMEOUT);
540 #undef PIS
541
542 printk("\n");
543 }
544
545 static void print_irq_status_vc(int channel, u32 status)
546 {
547 if (status == 0)
548 return;
549
550 #ifndef VERBOSE_IRQ
551 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
552 return;
553 #endif
554 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
555
556 #define PIS(x) \
557 if (status & DSI_VC_IRQ_##x) \
558 printk(#x " ");
559 PIS(CS);
560 PIS(ECC_CORR);
561 #ifdef VERBOSE_IRQ
562 PIS(PACKET_SENT);
563 #endif
564 PIS(FIFO_TX_OVF);
565 PIS(FIFO_RX_OVF);
566 PIS(BTA);
567 PIS(ECC_NO_CORR);
568 PIS(FIFO_TX_UDF);
569 PIS(PP_BUSY_CHANGE);
570 #undef PIS
571 printk("\n");
572 }
573
574 static void print_irq_status_cio(u32 status)
575 {
576 if (status == 0)
577 return;
578
579 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
580
581 #define PIS(x) \
582 if (status & DSI_CIO_IRQ_##x) \
583 printk(#x " ");
584 PIS(ERRSYNCESC1);
585 PIS(ERRSYNCESC2);
586 PIS(ERRSYNCESC3);
587 PIS(ERRESC1);
588 PIS(ERRESC2);
589 PIS(ERRESC3);
590 PIS(ERRCONTROL1);
591 PIS(ERRCONTROL2);
592 PIS(ERRCONTROL3);
593 PIS(STATEULPS1);
594 PIS(STATEULPS2);
595 PIS(STATEULPS3);
596 PIS(ERRCONTENTIONLP0_1);
597 PIS(ERRCONTENTIONLP1_1);
598 PIS(ERRCONTENTIONLP0_2);
599 PIS(ERRCONTENTIONLP1_2);
600 PIS(ERRCONTENTIONLP0_3);
601 PIS(ERRCONTENTIONLP1_3);
602 PIS(ULPSACTIVENOT_ALL0);
603 PIS(ULPSACTIVENOT_ALL1);
604 #undef PIS
605
606 printk("\n");
607 }
608
609 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
610 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
611 u32 *vcstatus, u32 ciostatus)
612 {
613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
614 int i;
615
616 spin_lock(&dsi->irq_stats_lock);
617
618 dsi->irq_stats.irq_count++;
619 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
620
621 for (i = 0; i < 4; ++i)
622 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
623
624 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
625
626 spin_unlock(&dsi->irq_stats_lock);
627 }
628 #else
629 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
630 #endif
631
632 static int debug_irq;
633
634 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
635 u32 *vcstatus, u32 ciostatus)
636 {
637 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
638 int i;
639
640 if (irqstatus & DSI_IRQ_ERROR_MASK) {
641 DSSERR("DSI error, irqstatus %x\n", irqstatus);
642 print_irq_status(irqstatus);
643 spin_lock(&dsi->errors_lock);
644 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
645 spin_unlock(&dsi->errors_lock);
646 } else if (debug_irq) {
647 print_irq_status(irqstatus);
648 }
649
650 for (i = 0; i < 4; ++i) {
651 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
652 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
653 i, vcstatus[i]);
654 print_irq_status_vc(i, vcstatus[i]);
655 } else if (debug_irq) {
656 print_irq_status_vc(i, vcstatus[i]);
657 }
658 }
659
660 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
661 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
662 print_irq_status_cio(ciostatus);
663 } else if (debug_irq) {
664 print_irq_status_cio(ciostatus);
665 }
666 }
667
668 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
669 unsigned isr_array_size, u32 irqstatus)
670 {
671 struct dsi_isr_data *isr_data;
672 int i;
673
674 for (i = 0; i < isr_array_size; i++) {
675 isr_data = &isr_array[i];
676 if (isr_data->isr && isr_data->mask & irqstatus)
677 isr_data->isr(isr_data->arg, irqstatus);
678 }
679 }
680
681 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
682 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
683 {
684 int i;
685
686 dsi_call_isrs(isr_tables->isr_table,
687 ARRAY_SIZE(isr_tables->isr_table),
688 irqstatus);
689
690 for (i = 0; i < 4; ++i) {
691 if (vcstatus[i] == 0)
692 continue;
693 dsi_call_isrs(isr_tables->isr_table_vc[i],
694 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
695 vcstatus[i]);
696 }
697
698 if (ciostatus != 0)
699 dsi_call_isrs(isr_tables->isr_table_cio,
700 ARRAY_SIZE(isr_tables->isr_table_cio),
701 ciostatus);
702 }
703
704 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
705 {
706 struct platform_device *dsidev;
707 struct dsi_data *dsi;
708 u32 irqstatus, vcstatus[4], ciostatus;
709 int i;
710
711 dsidev = (struct platform_device *) arg;
712 dsi = dsi_get_dsidrv_data(dsidev);
713
714 spin_lock(&dsi->irq_lock);
715
716 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
717
718 /* IRQ is not for us */
719 if (!irqstatus) {
720 spin_unlock(&dsi->irq_lock);
721 return IRQ_NONE;
722 }
723
724 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
725 /* flush posted write */
726 dsi_read_reg(dsidev, DSI_IRQSTATUS);
727
728 for (i = 0; i < 4; ++i) {
729 if ((irqstatus & (1 << i)) == 0) {
730 vcstatus[i] = 0;
731 continue;
732 }
733
734 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
735
736 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
737 /* flush posted write */
738 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
739 }
740
741 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
742 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
743
744 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
745 /* flush posted write */
746 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
747 } else {
748 ciostatus = 0;
749 }
750
751 #ifdef DSI_CATCH_MISSING_TE
752 if (irqstatus & DSI_IRQ_TE_TRIGGER)
753 del_timer(&dsi->te_timer);
754 #endif
755
756 /* make a copy and unlock, so that isrs can unregister
757 * themselves */
758 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
759 sizeof(dsi->isr_tables));
760
761 spin_unlock(&dsi->irq_lock);
762
763 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
764
765 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
766
767 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
768
769 return IRQ_HANDLED;
770 }
771
772 /* dsi->irq_lock has to be locked by the caller */
773 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
774 struct dsi_isr_data *isr_array,
775 unsigned isr_array_size, u32 default_mask,
776 const struct dsi_reg enable_reg,
777 const struct dsi_reg status_reg)
778 {
779 struct dsi_isr_data *isr_data;
780 u32 mask;
781 u32 old_mask;
782 int i;
783
784 mask = default_mask;
785
786 for (i = 0; i < isr_array_size; i++) {
787 isr_data = &isr_array[i];
788
789 if (isr_data->isr == NULL)
790 continue;
791
792 mask |= isr_data->mask;
793 }
794
795 old_mask = dsi_read_reg(dsidev, enable_reg);
796 /* clear the irqstatus for newly enabled irqs */
797 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
798 dsi_write_reg(dsidev, enable_reg, mask);
799
800 /* flush posted writes */
801 dsi_read_reg(dsidev, enable_reg);
802 dsi_read_reg(dsidev, status_reg);
803 }
804
805 /* dsi->irq_lock has to be locked by the caller */
806 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
807 {
808 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
809 u32 mask = DSI_IRQ_ERROR_MASK;
810 #ifdef DSI_CATCH_MISSING_TE
811 mask |= DSI_IRQ_TE_TRIGGER;
812 #endif
813 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
814 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
815 DSI_IRQENABLE, DSI_IRQSTATUS);
816 }
817
818 /* dsi->irq_lock has to be locked by the caller */
819 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
820 {
821 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
822
823 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
824 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
825 DSI_VC_IRQ_ERROR_MASK,
826 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
827 }
828
829 /* dsi->irq_lock has to be locked by the caller */
830 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
831 {
832 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
833
834 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
835 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
836 DSI_CIO_IRQ_ERROR_MASK,
837 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
838 }
839
840 static void _dsi_initialize_irq(struct platform_device *dsidev)
841 {
842 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
843 unsigned long flags;
844 int vc;
845
846 spin_lock_irqsave(&dsi->irq_lock, flags);
847
848 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
849
850 _omap_dsi_set_irqs(dsidev);
851 for (vc = 0; vc < 4; ++vc)
852 _omap_dsi_set_irqs_vc(dsidev, vc);
853 _omap_dsi_set_irqs_cio(dsidev);
854
855 spin_unlock_irqrestore(&dsi->irq_lock, flags);
856 }
857
858 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
859 struct dsi_isr_data *isr_array, unsigned isr_array_size)
860 {
861 struct dsi_isr_data *isr_data;
862 int free_idx;
863 int i;
864
865 BUG_ON(isr == NULL);
866
867 /* check for duplicate entry and find a free slot */
868 free_idx = -1;
869 for (i = 0; i < isr_array_size; i++) {
870 isr_data = &isr_array[i];
871
872 if (isr_data->isr == isr && isr_data->arg == arg &&
873 isr_data->mask == mask) {
874 return -EINVAL;
875 }
876
877 if (isr_data->isr == NULL && free_idx == -1)
878 free_idx = i;
879 }
880
881 if (free_idx == -1)
882 return -EBUSY;
883
884 isr_data = &isr_array[free_idx];
885 isr_data->isr = isr;
886 isr_data->arg = arg;
887 isr_data->mask = mask;
888
889 return 0;
890 }
891
892 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
893 struct dsi_isr_data *isr_array, unsigned isr_array_size)
894 {
895 struct dsi_isr_data *isr_data;
896 int i;
897
898 for (i = 0; i < isr_array_size; i++) {
899 isr_data = &isr_array[i];
900 if (isr_data->isr != isr || isr_data->arg != arg ||
901 isr_data->mask != mask)
902 continue;
903
904 isr_data->isr = NULL;
905 isr_data->arg = NULL;
906 isr_data->mask = 0;
907
908 return 0;
909 }
910
911 return -EINVAL;
912 }
913
914 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
915 void *arg, u32 mask)
916 {
917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
918 unsigned long flags;
919 int r;
920
921 spin_lock_irqsave(&dsi->irq_lock, flags);
922
923 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
924 ARRAY_SIZE(dsi->isr_tables.isr_table));
925
926 if (r == 0)
927 _omap_dsi_set_irqs(dsidev);
928
929 spin_unlock_irqrestore(&dsi->irq_lock, flags);
930
931 return r;
932 }
933
934 static int dsi_unregister_isr(struct platform_device *dsidev,
935 omap_dsi_isr_t isr, void *arg, u32 mask)
936 {
937 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
938 unsigned long flags;
939 int r;
940
941 spin_lock_irqsave(&dsi->irq_lock, flags);
942
943 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
944 ARRAY_SIZE(dsi->isr_tables.isr_table));
945
946 if (r == 0)
947 _omap_dsi_set_irqs(dsidev);
948
949 spin_unlock_irqrestore(&dsi->irq_lock, flags);
950
951 return r;
952 }
953
954 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
955 omap_dsi_isr_t isr, void *arg, u32 mask)
956 {
957 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
958 unsigned long flags;
959 int r;
960
961 spin_lock_irqsave(&dsi->irq_lock, flags);
962
963 r = _dsi_register_isr(isr, arg, mask,
964 dsi->isr_tables.isr_table_vc[channel],
965 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
966
967 if (r == 0)
968 _omap_dsi_set_irqs_vc(dsidev, channel);
969
970 spin_unlock_irqrestore(&dsi->irq_lock, flags);
971
972 return r;
973 }
974
975 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
976 omap_dsi_isr_t isr, void *arg, u32 mask)
977 {
978 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
979 unsigned long flags;
980 int r;
981
982 spin_lock_irqsave(&dsi->irq_lock, flags);
983
984 r = _dsi_unregister_isr(isr, arg, mask,
985 dsi->isr_tables.isr_table_vc[channel],
986 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
987
988 if (r == 0)
989 _omap_dsi_set_irqs_vc(dsidev, channel);
990
991 spin_unlock_irqrestore(&dsi->irq_lock, flags);
992
993 return r;
994 }
995
996 static int dsi_register_isr_cio(struct platform_device *dsidev,
997 omap_dsi_isr_t isr, void *arg, u32 mask)
998 {
999 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1000 unsigned long flags;
1001 int r;
1002
1003 spin_lock_irqsave(&dsi->irq_lock, flags);
1004
1005 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1006 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1007
1008 if (r == 0)
1009 _omap_dsi_set_irqs_cio(dsidev);
1010
1011 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1012
1013 return r;
1014 }
1015
1016 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1017 omap_dsi_isr_t isr, void *arg, u32 mask)
1018 {
1019 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1020 unsigned long flags;
1021 int r;
1022
1023 spin_lock_irqsave(&dsi->irq_lock, flags);
1024
1025 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1026 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1027
1028 if (r == 0)
1029 _omap_dsi_set_irqs_cio(dsidev);
1030
1031 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1032
1033 return r;
1034 }
1035
1036 static u32 dsi_get_errors(struct platform_device *dsidev)
1037 {
1038 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1039 unsigned long flags;
1040 u32 e;
1041 spin_lock_irqsave(&dsi->errors_lock, flags);
1042 e = dsi->errors;
1043 dsi->errors = 0;
1044 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1045 return e;
1046 }
1047
1048 int dsi_runtime_get(struct platform_device *dsidev)
1049 {
1050 int r;
1051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1052
1053 DSSDBG("dsi_runtime_get\n");
1054
1055 r = pm_runtime_get_sync(&dsi->pdev->dev);
1056 WARN_ON(r < 0);
1057 return r < 0 ? r : 0;
1058 }
1059
1060 void dsi_runtime_put(struct platform_device *dsidev)
1061 {
1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 int r;
1064
1065 DSSDBG("dsi_runtime_put\n");
1066
1067 r = pm_runtime_put(&dsi->pdev->dev);
1068 WARN_ON(r < 0);
1069 }
1070
1071 /* source clock for DSI PLL. this could also be PCLKFREE */
1072 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1073 bool enable)
1074 {
1075 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1076
1077 if (enable)
1078 clk_enable(dsi->sys_clk);
1079 else
1080 clk_disable(dsi->sys_clk);
1081
1082 if (enable && dsi->pll_locked) {
1083 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1084 DSSERR("cannot lock PLL when enabling clocks\n");
1085 }
1086 }
1087
1088 #ifdef DEBUG
1089 static void _dsi_print_reset_status(struct platform_device *dsidev)
1090 {
1091 u32 l;
1092 int b0, b1, b2;
1093
1094 if (!dss_debug)
1095 return;
1096
1097 /* A dummy read using the SCP interface to any DSIPHY register is
1098 * required after DSIPHY reset to complete the reset of the DSI complex
1099 * I/O. */
1100 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1101
1102 printk(KERN_DEBUG "DSI resets: ");
1103
1104 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1105 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1106
1107 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1108 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1109
1110 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1111 b0 = 28;
1112 b1 = 27;
1113 b2 = 26;
1114 } else {
1115 b0 = 24;
1116 b1 = 25;
1117 b2 = 26;
1118 }
1119
1120 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1121 printk("PHY (%x%x%x, %d, %d, %d)\n",
1122 FLD_GET(l, b0, b0),
1123 FLD_GET(l, b1, b1),
1124 FLD_GET(l, b2, b2),
1125 FLD_GET(l, 29, 29),
1126 FLD_GET(l, 30, 30),
1127 FLD_GET(l, 31, 31));
1128 }
1129 #else
1130 #define _dsi_print_reset_status(x)
1131 #endif
1132
1133 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1134 {
1135 DSSDBG("dsi_if_enable(%d)\n", enable);
1136
1137 enable = enable ? 1 : 0;
1138 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1139
1140 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1141 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1142 return -EIO;
1143 }
1144
1145 return 0;
1146 }
1147
1148 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1149 {
1150 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1151
1152 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1153 }
1154
1155 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1156 {
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158
1159 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1160 }
1161
1162 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1163 {
1164 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1165
1166 return dsi->current_cinfo.clkin4ddr / 16;
1167 }
1168
1169 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1170 {
1171 unsigned long r;
1172 int dsi_module = dsi_get_dsidev_id(dsidev);
1173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1174
1175 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1176 /* DSI FCLK source is DSS_CLK_FCK */
1177 r = clk_get_rate(dsi->dss_clk);
1178 } else {
1179 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1180 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1181 }
1182
1183 return r;
1184 }
1185
1186 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1187 {
1188 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1189 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1190 unsigned long dsi_fclk;
1191 unsigned lp_clk_div;
1192 unsigned long lp_clk;
1193
1194 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1195
1196 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1197 return -EINVAL;
1198
1199 dsi_fclk = dsi_fclk_rate(dsidev);
1200
1201 lp_clk = dsi_fclk / 2 / lp_clk_div;
1202
1203 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1204 dsi->current_cinfo.lp_clk = lp_clk;
1205 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1206
1207 /* LP_CLK_DIVISOR */
1208 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1209
1210 /* LP_RX_SYNCHRO_ENABLE */
1211 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1212
1213 return 0;
1214 }
1215
1216 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1217 {
1218 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1219
1220 if (dsi->scp_clk_refcount++ == 0)
1221 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1222 }
1223
1224 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1225 {
1226 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1227
1228 WARN_ON(dsi->scp_clk_refcount == 0);
1229 if (--dsi->scp_clk_refcount == 0)
1230 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1231 }
1232
1233 enum dsi_pll_power_state {
1234 DSI_PLL_POWER_OFF = 0x0,
1235 DSI_PLL_POWER_ON_HSCLK = 0x1,
1236 DSI_PLL_POWER_ON_ALL = 0x2,
1237 DSI_PLL_POWER_ON_DIV = 0x3,
1238 };
1239
1240 static int dsi_pll_power(struct platform_device *dsidev,
1241 enum dsi_pll_power_state state)
1242 {
1243 int t = 0;
1244
1245 /* DSI-PLL power command 0x3 is not working */
1246 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1247 state == DSI_PLL_POWER_ON_DIV)
1248 state = DSI_PLL_POWER_ON_ALL;
1249
1250 /* PLL_PWR_CMD */
1251 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1252
1253 /* PLL_PWR_STATUS */
1254 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1255 if (++t > 1000) {
1256 DSSERR("Failed to set DSI PLL power mode to %d\n",
1257 state);
1258 return -ENODEV;
1259 }
1260 udelay(1);
1261 }
1262
1263 return 0;
1264 }
1265
1266 /* calculate clock rates using dividers in cinfo */
1267 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1268 struct dsi_clock_info *cinfo)
1269 {
1270 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1271 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1272
1273 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1274 return -EINVAL;
1275
1276 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1277 return -EINVAL;
1278
1279 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1280 return -EINVAL;
1281
1282 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1283 return -EINVAL;
1284
1285 if (cinfo->use_sys_clk) {
1286 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1287 /* XXX it is unclear if highfreq should be used
1288 * with DSS_SYS_CLK source also */
1289 cinfo->highfreq = 0;
1290 } else {
1291 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1292
1293 if (cinfo->clkin < 32000000)
1294 cinfo->highfreq = 0;
1295 else
1296 cinfo->highfreq = 1;
1297 }
1298
1299 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1300
1301 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1302 return -EINVAL;
1303
1304 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1305
1306 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1307 return -EINVAL;
1308
1309 if (cinfo->regm_dispc > 0)
1310 cinfo->dsi_pll_hsdiv_dispc_clk =
1311 cinfo->clkin4ddr / cinfo->regm_dispc;
1312 else
1313 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1314
1315 if (cinfo->regm_dsi > 0)
1316 cinfo->dsi_pll_hsdiv_dsi_clk =
1317 cinfo->clkin4ddr / cinfo->regm_dsi;
1318 else
1319 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1320
1321 return 0;
1322 }
1323
1324 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1325 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1326 struct dispc_clock_info *dispc_cinfo)
1327 {
1328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1329 struct dsi_clock_info cur, best;
1330 struct dispc_clock_info best_dispc;
1331 int min_fck_per_pck;
1332 int match = 0;
1333 unsigned long dss_sys_clk, max_dss_fck;
1334
1335 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1336
1337 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1338
1339 if (req_pck == dsi->cache_req_pck &&
1340 dsi->cache_cinfo.clkin == dss_sys_clk) {
1341 DSSDBG("DSI clock info found from cache\n");
1342 *dsi_cinfo = dsi->cache_cinfo;
1343 dispc_find_clk_divs(is_tft, req_pck,
1344 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1345 return 0;
1346 }
1347
1348 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1349
1350 if (min_fck_per_pck &&
1351 req_pck * min_fck_per_pck > max_dss_fck) {
1352 DSSERR("Requested pixel clock not possible with the current "
1353 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1354 "the constraint off.\n");
1355 min_fck_per_pck = 0;
1356 }
1357
1358 DSSDBG("dsi_pll_calc\n");
1359
1360 retry:
1361 memset(&best, 0, sizeof(best));
1362 memset(&best_dispc, 0, sizeof(best_dispc));
1363
1364 memset(&cur, 0, sizeof(cur));
1365 cur.clkin = dss_sys_clk;
1366 cur.use_sys_clk = 1;
1367 cur.highfreq = 0;
1368
1369 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1370 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1371 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1372 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1373 if (cur.highfreq == 0)
1374 cur.fint = cur.clkin / cur.regn;
1375 else
1376 cur.fint = cur.clkin / (2 * cur.regn);
1377
1378 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1379 continue;
1380
1381 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1382 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1383 unsigned long a, b;
1384
1385 a = 2 * cur.regm * (cur.clkin/1000);
1386 b = cur.regn * (cur.highfreq + 1);
1387 cur.clkin4ddr = a / b * 1000;
1388
1389 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1390 break;
1391
1392 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1393 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1394 for (cur.regm_dispc = 1; cur.regm_dispc <
1395 dsi->regm_dispc_max; ++cur.regm_dispc) {
1396 struct dispc_clock_info cur_dispc;
1397 cur.dsi_pll_hsdiv_dispc_clk =
1398 cur.clkin4ddr / cur.regm_dispc;
1399
1400 /* this will narrow down the search a bit,
1401 * but still give pixclocks below what was
1402 * requested */
1403 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1404 break;
1405
1406 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1407 continue;
1408
1409 if (min_fck_per_pck &&
1410 cur.dsi_pll_hsdiv_dispc_clk <
1411 req_pck * min_fck_per_pck)
1412 continue;
1413
1414 match = 1;
1415
1416 dispc_find_clk_divs(is_tft, req_pck,
1417 cur.dsi_pll_hsdiv_dispc_clk,
1418 &cur_dispc);
1419
1420 if (abs(cur_dispc.pck - req_pck) <
1421 abs(best_dispc.pck - req_pck)) {
1422 best = cur;
1423 best_dispc = cur_dispc;
1424
1425 if (cur_dispc.pck == req_pck)
1426 goto found;
1427 }
1428 }
1429 }
1430 }
1431 found:
1432 if (!match) {
1433 if (min_fck_per_pck) {
1434 DSSERR("Could not find suitable clock settings.\n"
1435 "Turning FCK/PCK constraint off and"
1436 "trying again.\n");
1437 min_fck_per_pck = 0;
1438 goto retry;
1439 }
1440
1441 DSSERR("Could not find suitable clock settings.\n");
1442
1443 return -EINVAL;
1444 }
1445
1446 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1447 best.regm_dsi = 0;
1448 best.dsi_pll_hsdiv_dsi_clk = 0;
1449
1450 if (dsi_cinfo)
1451 *dsi_cinfo = best;
1452 if (dispc_cinfo)
1453 *dispc_cinfo = best_dispc;
1454
1455 dsi->cache_req_pck = req_pck;
1456 dsi->cache_clk_freq = 0;
1457 dsi->cache_cinfo = best;
1458
1459 return 0;
1460 }
1461
1462 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1463 struct dsi_clock_info *cinfo)
1464 {
1465 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1466 int r = 0;
1467 u32 l;
1468 int f = 0;
1469 u8 regn_start, regn_end, regm_start, regm_end;
1470 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1471
1472 DSSDBGF();
1473
1474 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1475 dsi->current_cinfo.highfreq = cinfo->highfreq;
1476
1477 dsi->current_cinfo.fint = cinfo->fint;
1478 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1479 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1480 cinfo->dsi_pll_hsdiv_dispc_clk;
1481 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1482 cinfo->dsi_pll_hsdiv_dsi_clk;
1483
1484 dsi->current_cinfo.regn = cinfo->regn;
1485 dsi->current_cinfo.regm = cinfo->regm;
1486 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1487 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1488
1489 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1490
1491 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1492 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1493 cinfo->clkin,
1494 cinfo->highfreq);
1495
1496 /* DSIPHY == CLKIN4DDR */
1497 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1498 cinfo->regm,
1499 cinfo->regn,
1500 cinfo->clkin,
1501 cinfo->highfreq + 1,
1502 cinfo->clkin4ddr);
1503
1504 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1505 cinfo->clkin4ddr / 1000 / 1000 / 2);
1506
1507 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1508
1509 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1510 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1511 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1512 cinfo->dsi_pll_hsdiv_dispc_clk);
1513 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1514 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1515 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1516 cinfo->dsi_pll_hsdiv_dsi_clk);
1517
1518 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1520 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1521 &regm_dispc_end);
1522 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1523 &regm_dsi_end);
1524
1525 /* DSI_PLL_AUTOMODE = manual */
1526 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1527
1528 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1529 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1530 /* DSI_PLL_REGN */
1531 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1532 /* DSI_PLL_REGM */
1533 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1534 /* DSI_CLOCK_DIV */
1535 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1536 regm_dispc_start, regm_dispc_end);
1537 /* DSIPROTO_CLOCK_DIV */
1538 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1539 regm_dsi_start, regm_dsi_end);
1540 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1541
1542 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1543
1544 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1545 f = cinfo->fint < 1000000 ? 0x3 :
1546 cinfo->fint < 1250000 ? 0x4 :
1547 cinfo->fint < 1500000 ? 0x5 :
1548 cinfo->fint < 1750000 ? 0x6 :
1549 0x7;
1550 }
1551
1552 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1553
1554 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1555 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1556 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1557 11, 11); /* DSI_PLL_CLKSEL */
1558 l = FLD_MOD(l, cinfo->highfreq,
1559 12, 12); /* DSI_PLL_HIGHFREQ */
1560 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1561 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1562 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1563 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1564
1565 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1566
1567 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1568 DSSERR("dsi pll go bit not going down.\n");
1569 r = -EIO;
1570 goto err;
1571 }
1572
1573 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1574 DSSERR("cannot lock PLL\n");
1575 r = -EIO;
1576 goto err;
1577 }
1578
1579 dsi->pll_locked = 1;
1580
1581 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1582 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1583 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1584 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1585 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1586 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1587 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1588 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1589 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1590 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1591 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1592 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1593 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1594 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1595 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1596 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1597
1598 DSSDBG("PLL config done\n");
1599 err:
1600 return r;
1601 }
1602
1603 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1604 bool enable_hsdiv)
1605 {
1606 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1607 int r = 0;
1608 enum dsi_pll_power_state pwstate;
1609
1610 DSSDBG("PLL init\n");
1611
1612 if (dsi->vdds_dsi_reg == NULL) {
1613 struct regulator *vdds_dsi;
1614
1615 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1616
1617 if (IS_ERR(vdds_dsi)) {
1618 DSSERR("can't get VDDS_DSI regulator\n");
1619 return PTR_ERR(vdds_dsi);
1620 }
1621
1622 dsi->vdds_dsi_reg = vdds_dsi;
1623 }
1624
1625 dsi_enable_pll_clock(dsidev, 1);
1626 /*
1627 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1628 */
1629 dsi_enable_scp_clk(dsidev);
1630
1631 if (!dsi->vdds_dsi_enabled) {
1632 r = regulator_enable(dsi->vdds_dsi_reg);
1633 if (r)
1634 goto err0;
1635 dsi->vdds_dsi_enabled = true;
1636 }
1637
1638 /* XXX PLL does not come out of reset without this... */
1639 dispc_pck_free_enable(1);
1640
1641 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1642 DSSERR("PLL not coming out of reset.\n");
1643 r = -ENODEV;
1644 dispc_pck_free_enable(0);
1645 goto err1;
1646 }
1647
1648 /* XXX ... but if left on, we get problems when planes do not
1649 * fill the whole display. No idea about this */
1650 dispc_pck_free_enable(0);
1651
1652 if (enable_hsclk && enable_hsdiv)
1653 pwstate = DSI_PLL_POWER_ON_ALL;
1654 else if (enable_hsclk)
1655 pwstate = DSI_PLL_POWER_ON_HSCLK;
1656 else if (enable_hsdiv)
1657 pwstate = DSI_PLL_POWER_ON_DIV;
1658 else
1659 pwstate = DSI_PLL_POWER_OFF;
1660
1661 r = dsi_pll_power(dsidev, pwstate);
1662
1663 if (r)
1664 goto err1;
1665
1666 DSSDBG("PLL init done\n");
1667
1668 return 0;
1669 err1:
1670 if (dsi->vdds_dsi_enabled) {
1671 regulator_disable(dsi->vdds_dsi_reg);
1672 dsi->vdds_dsi_enabled = false;
1673 }
1674 err0:
1675 dsi_disable_scp_clk(dsidev);
1676 dsi_enable_pll_clock(dsidev, 0);
1677 return r;
1678 }
1679
1680 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1681 {
1682 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1683
1684 dsi->pll_locked = 0;
1685 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1686 if (disconnect_lanes) {
1687 WARN_ON(!dsi->vdds_dsi_enabled);
1688 regulator_disable(dsi->vdds_dsi_reg);
1689 dsi->vdds_dsi_enabled = false;
1690 }
1691
1692 dsi_disable_scp_clk(dsidev);
1693 dsi_enable_pll_clock(dsidev, 0);
1694
1695 DSSDBG("PLL uninit done\n");
1696 }
1697
1698 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1699 struct seq_file *s)
1700 {
1701 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1702 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1703 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1704 int dsi_module = dsi_get_dsidev_id(dsidev);
1705
1706 dispc_clk_src = dss_get_dispc_clk_source();
1707 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1708
1709 if (dsi_runtime_get(dsidev))
1710 return;
1711
1712 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1713
1714 seq_printf(s, "dsi pll source = %s\n",
1715 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1716
1717 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1718
1719 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1720 cinfo->clkin4ddr, cinfo->regm);
1721
1722 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1723 dss_get_generic_clk_source_name(dispc_clk_src),
1724 dss_feat_get_clk_source_name(dispc_clk_src),
1725 cinfo->dsi_pll_hsdiv_dispc_clk,
1726 cinfo->regm_dispc,
1727 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1728 "off" : "on");
1729
1730 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1731 dss_get_generic_clk_source_name(dsi_clk_src),
1732 dss_feat_get_clk_source_name(dsi_clk_src),
1733 cinfo->dsi_pll_hsdiv_dsi_clk,
1734 cinfo->regm_dsi,
1735 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1736 "off" : "on");
1737
1738 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1739
1740 seq_printf(s, "dsi fclk source = %s (%s)\n",
1741 dss_get_generic_clk_source_name(dsi_clk_src),
1742 dss_feat_get_clk_source_name(dsi_clk_src));
1743
1744 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1745
1746 seq_printf(s, "DDR_CLK\t\t%lu\n",
1747 cinfo->clkin4ddr / 4);
1748
1749 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1750
1751 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1752
1753 dsi_runtime_put(dsidev);
1754 }
1755
1756 void dsi_dump_clocks(struct seq_file *s)
1757 {
1758 struct platform_device *dsidev;
1759 int i;
1760
1761 for (i = 0; i < MAX_NUM_DSI; i++) {
1762 dsidev = dsi_get_dsidev_from_id(i);
1763 if (dsidev)
1764 dsi_dump_dsidev_clocks(dsidev, s);
1765 }
1766 }
1767
1768 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1769 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1770 struct seq_file *s)
1771 {
1772 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1773 unsigned long flags;
1774 struct dsi_irq_stats stats;
1775 int dsi_module = dsi_get_dsidev_id(dsidev);
1776
1777 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1778
1779 stats = dsi->irq_stats;
1780 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1781 dsi->irq_stats.last_reset = jiffies;
1782
1783 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1784
1785 seq_printf(s, "period %u ms\n",
1786 jiffies_to_msecs(jiffies - stats.last_reset));
1787
1788 seq_printf(s, "irqs %d\n", stats.irq_count);
1789 #define PIS(x) \
1790 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1791
1792 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1793 PIS(VC0);
1794 PIS(VC1);
1795 PIS(VC2);
1796 PIS(VC3);
1797 PIS(WAKEUP);
1798 PIS(RESYNC);
1799 PIS(PLL_LOCK);
1800 PIS(PLL_UNLOCK);
1801 PIS(PLL_RECALL);
1802 PIS(COMPLEXIO_ERR);
1803 PIS(HS_TX_TIMEOUT);
1804 PIS(LP_RX_TIMEOUT);
1805 PIS(TE_TRIGGER);
1806 PIS(ACK_TRIGGER);
1807 PIS(SYNC_LOST);
1808 PIS(LDO_POWER_GOOD);
1809 PIS(TA_TIMEOUT);
1810 #undef PIS
1811
1812 #define PIS(x) \
1813 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1814 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1815 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1816 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1817 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1818
1819 seq_printf(s, "-- VC interrupts --\n");
1820 PIS(CS);
1821 PIS(ECC_CORR);
1822 PIS(PACKET_SENT);
1823 PIS(FIFO_TX_OVF);
1824 PIS(FIFO_RX_OVF);
1825 PIS(BTA);
1826 PIS(ECC_NO_CORR);
1827 PIS(FIFO_TX_UDF);
1828 PIS(PP_BUSY_CHANGE);
1829 #undef PIS
1830
1831 #define PIS(x) \
1832 seq_printf(s, "%-20s %10d\n", #x, \
1833 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1834
1835 seq_printf(s, "-- CIO interrupts --\n");
1836 PIS(ERRSYNCESC1);
1837 PIS(ERRSYNCESC2);
1838 PIS(ERRSYNCESC3);
1839 PIS(ERRESC1);
1840 PIS(ERRESC2);
1841 PIS(ERRESC3);
1842 PIS(ERRCONTROL1);
1843 PIS(ERRCONTROL2);
1844 PIS(ERRCONTROL3);
1845 PIS(STATEULPS1);
1846 PIS(STATEULPS2);
1847 PIS(STATEULPS3);
1848 PIS(ERRCONTENTIONLP0_1);
1849 PIS(ERRCONTENTIONLP1_1);
1850 PIS(ERRCONTENTIONLP0_2);
1851 PIS(ERRCONTENTIONLP1_2);
1852 PIS(ERRCONTENTIONLP0_3);
1853 PIS(ERRCONTENTIONLP1_3);
1854 PIS(ULPSACTIVENOT_ALL0);
1855 PIS(ULPSACTIVENOT_ALL1);
1856 #undef PIS
1857 }
1858
1859 static void dsi1_dump_irqs(struct seq_file *s)
1860 {
1861 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1862
1863 dsi_dump_dsidev_irqs(dsidev, s);
1864 }
1865
1866 static void dsi2_dump_irqs(struct seq_file *s)
1867 {
1868 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1869
1870 dsi_dump_dsidev_irqs(dsidev, s);
1871 }
1872
1873 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1874 const struct file_operations *debug_fops)
1875 {
1876 struct platform_device *dsidev;
1877
1878 dsidev = dsi_get_dsidev_from_id(0);
1879 if (dsidev)
1880 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1881 &dsi1_dump_irqs, debug_fops);
1882
1883 dsidev = dsi_get_dsidev_from_id(1);
1884 if (dsidev)
1885 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1886 &dsi2_dump_irqs, debug_fops);
1887 }
1888 #endif
1889
1890 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1891 struct seq_file *s)
1892 {
1893 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1894
1895 if (dsi_runtime_get(dsidev))
1896 return;
1897 dsi_enable_scp_clk(dsidev);
1898
1899 DUMPREG(DSI_REVISION);
1900 DUMPREG(DSI_SYSCONFIG);
1901 DUMPREG(DSI_SYSSTATUS);
1902 DUMPREG(DSI_IRQSTATUS);
1903 DUMPREG(DSI_IRQENABLE);
1904 DUMPREG(DSI_CTRL);
1905 DUMPREG(DSI_COMPLEXIO_CFG1);
1906 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1907 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1908 DUMPREG(DSI_CLK_CTRL);
1909 DUMPREG(DSI_TIMING1);
1910 DUMPREG(DSI_TIMING2);
1911 DUMPREG(DSI_VM_TIMING1);
1912 DUMPREG(DSI_VM_TIMING2);
1913 DUMPREG(DSI_VM_TIMING3);
1914 DUMPREG(DSI_CLK_TIMING);
1915 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1916 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1917 DUMPREG(DSI_COMPLEXIO_CFG2);
1918 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1919 DUMPREG(DSI_VM_TIMING4);
1920 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1921 DUMPREG(DSI_VM_TIMING5);
1922 DUMPREG(DSI_VM_TIMING6);
1923 DUMPREG(DSI_VM_TIMING7);
1924 DUMPREG(DSI_STOPCLK_TIMING);
1925
1926 DUMPREG(DSI_VC_CTRL(0));
1927 DUMPREG(DSI_VC_TE(0));
1928 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1929 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1930 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1931 DUMPREG(DSI_VC_IRQSTATUS(0));
1932 DUMPREG(DSI_VC_IRQENABLE(0));
1933
1934 DUMPREG(DSI_VC_CTRL(1));
1935 DUMPREG(DSI_VC_TE(1));
1936 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1937 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1938 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1939 DUMPREG(DSI_VC_IRQSTATUS(1));
1940 DUMPREG(DSI_VC_IRQENABLE(1));
1941
1942 DUMPREG(DSI_VC_CTRL(2));
1943 DUMPREG(DSI_VC_TE(2));
1944 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1945 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1946 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1947 DUMPREG(DSI_VC_IRQSTATUS(2));
1948 DUMPREG(DSI_VC_IRQENABLE(2));
1949
1950 DUMPREG(DSI_VC_CTRL(3));
1951 DUMPREG(DSI_VC_TE(3));
1952 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1953 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1954 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1955 DUMPREG(DSI_VC_IRQSTATUS(3));
1956 DUMPREG(DSI_VC_IRQENABLE(3));
1957
1958 DUMPREG(DSI_DSIPHY_CFG0);
1959 DUMPREG(DSI_DSIPHY_CFG1);
1960 DUMPREG(DSI_DSIPHY_CFG2);
1961 DUMPREG(DSI_DSIPHY_CFG5);
1962
1963 DUMPREG(DSI_PLL_CONTROL);
1964 DUMPREG(DSI_PLL_STATUS);
1965 DUMPREG(DSI_PLL_GO);
1966 DUMPREG(DSI_PLL_CONFIGURATION1);
1967 DUMPREG(DSI_PLL_CONFIGURATION2);
1968
1969 dsi_disable_scp_clk(dsidev);
1970 dsi_runtime_put(dsidev);
1971 #undef DUMPREG
1972 }
1973
1974 static void dsi1_dump_regs(struct seq_file *s)
1975 {
1976 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1977
1978 dsi_dump_dsidev_regs(dsidev, s);
1979 }
1980
1981 static void dsi2_dump_regs(struct seq_file *s)
1982 {
1983 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1984
1985 dsi_dump_dsidev_regs(dsidev, s);
1986 }
1987
1988 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1989 const struct file_operations *debug_fops)
1990 {
1991 struct platform_device *dsidev;
1992
1993 dsidev = dsi_get_dsidev_from_id(0);
1994 if (dsidev)
1995 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1996 &dsi1_dump_regs, debug_fops);
1997
1998 dsidev = dsi_get_dsidev_from_id(1);
1999 if (dsidev)
2000 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2001 &dsi2_dump_regs, debug_fops);
2002 }
2003 enum dsi_cio_power_state {
2004 DSI_COMPLEXIO_POWER_OFF = 0x0,
2005 DSI_COMPLEXIO_POWER_ON = 0x1,
2006 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2007 };
2008
2009 static int dsi_cio_power(struct platform_device *dsidev,
2010 enum dsi_cio_power_state state)
2011 {
2012 int t = 0;
2013
2014 /* PWR_CMD */
2015 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2016
2017 /* PWR_STATUS */
2018 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2019 26, 25) != state) {
2020 if (++t > 1000) {
2021 DSSERR("failed to set complexio power state to "
2022 "%d\n", state);
2023 return -ENODEV;
2024 }
2025 udelay(1);
2026 }
2027
2028 return 0;
2029 }
2030
2031 /* Number of data lanes present on DSI interface */
2032 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2033 {
2034 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2035 * of data lanes as 2 by default */
2036 if (dss_has_feature(FEAT_DSI_GNQ))
2037 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2038 else
2039 return 2;
2040 }
2041
2042 /* Number of data lanes used by the dss device */
2043 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2044 {
2045 int num_data_lanes = 0;
2046
2047 if (dssdev->phy.dsi.data1_lane != 0)
2048 num_data_lanes++;
2049 if (dssdev->phy.dsi.data2_lane != 0)
2050 num_data_lanes++;
2051 if (dssdev->phy.dsi.data3_lane != 0)
2052 num_data_lanes++;
2053 if (dssdev->phy.dsi.data4_lane != 0)
2054 num_data_lanes++;
2055
2056 return num_data_lanes;
2057 }
2058
2059 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2060 {
2061 int val;
2062
2063 /* line buffer on OMAP3 is 1024 x 24bits */
2064 /* XXX: for some reason using full buffer size causes
2065 * considerable TX slowdown with update sizes that fill the
2066 * whole buffer */
2067 if (!dss_has_feature(FEAT_DSI_GNQ))
2068 return 1023 * 3;
2069
2070 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2071
2072 switch (val) {
2073 case 1:
2074 return 512 * 3; /* 512x24 bits */
2075 case 2:
2076 return 682 * 3; /* 682x24 bits */
2077 case 3:
2078 return 853 * 3; /* 853x24 bits */
2079 case 4:
2080 return 1024 * 3; /* 1024x24 bits */
2081 case 5:
2082 return 1194 * 3; /* 1194x24 bits */
2083 case 6:
2084 return 1365 * 3; /* 1365x24 bits */
2085 default:
2086 BUG();
2087 }
2088 }
2089
2090 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2091 {
2092 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2093 u32 r;
2094 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2095
2096 int clk_lane = dssdev->phy.dsi.clk_lane;
2097 int data1_lane = dssdev->phy.dsi.data1_lane;
2098 int data2_lane = dssdev->phy.dsi.data2_lane;
2099 int clk_pol = dssdev->phy.dsi.clk_pol;
2100 int data1_pol = dssdev->phy.dsi.data1_pol;
2101 int data2_pol = dssdev->phy.dsi.data2_pol;
2102
2103 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2104 r = FLD_MOD(r, clk_lane, 2, 0);
2105 r = FLD_MOD(r, clk_pol, 3, 3);
2106 r = FLD_MOD(r, data1_lane, 6, 4);
2107 r = FLD_MOD(r, data1_pol, 7, 7);
2108 r = FLD_MOD(r, data2_lane, 10, 8);
2109 r = FLD_MOD(r, data2_pol, 11, 11);
2110 if (num_data_lanes_dssdev > 2) {
2111 int data3_lane = dssdev->phy.dsi.data3_lane;
2112 int data3_pol = dssdev->phy.dsi.data3_pol;
2113
2114 r = FLD_MOD(r, data3_lane, 14, 12);
2115 r = FLD_MOD(r, data3_pol, 15, 15);
2116 }
2117 if (num_data_lanes_dssdev > 3) {
2118 int data4_lane = dssdev->phy.dsi.data4_lane;
2119 int data4_pol = dssdev->phy.dsi.data4_pol;
2120
2121 r = FLD_MOD(r, data4_lane, 18, 16);
2122 r = FLD_MOD(r, data4_pol, 19, 19);
2123 }
2124 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2125
2126 /* The configuration of the DSI complex I/O (number of data lanes,
2127 position, differential order) should not be changed while
2128 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2129 the hardware to take into account a new configuration of the complex
2130 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2131 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2132 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2133 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2134 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2135 DSI complex I/O configuration is unknown. */
2136
2137 /*
2138 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2139 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2140 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2141 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2142 */
2143 }
2144
2145 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2146 {
2147 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2148
2149 /* convert time in ns to ddr ticks, rounding up */
2150 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2151 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2152 }
2153
2154 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2155 {
2156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2157
2158 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2159 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2160 }
2161
2162 static void dsi_cio_timings(struct platform_device *dsidev)
2163 {
2164 u32 r;
2165 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2166 u32 tlpx_half, tclk_trail, tclk_zero;
2167 u32 tclk_prepare;
2168
2169 /* calculate timings */
2170
2171 /* 1 * DDR_CLK = 2 * UI */
2172
2173 /* min 40ns + 4*UI max 85ns + 6*UI */
2174 ths_prepare = ns2ddr(dsidev, 70) + 2;
2175
2176 /* min 145ns + 10*UI */
2177 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2178
2179 /* min max(8*UI, 60ns+4*UI) */
2180 ths_trail = ns2ddr(dsidev, 60) + 5;
2181
2182 /* min 100ns */
2183 ths_exit = ns2ddr(dsidev, 145);
2184
2185 /* tlpx min 50n */
2186 tlpx_half = ns2ddr(dsidev, 25);
2187
2188 /* min 60ns */
2189 tclk_trail = ns2ddr(dsidev, 60) + 2;
2190
2191 /* min 38ns, max 95ns */
2192 tclk_prepare = ns2ddr(dsidev, 65);
2193
2194 /* min tclk-prepare + tclk-zero = 300ns */
2195 tclk_zero = ns2ddr(dsidev, 260);
2196
2197 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2198 ths_prepare, ddr2ns(dsidev, ths_prepare),
2199 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2200 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2201 ths_trail, ddr2ns(dsidev, ths_trail),
2202 ths_exit, ddr2ns(dsidev, ths_exit));
2203
2204 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2205 "tclk_zero %u (%uns)\n",
2206 tlpx_half, ddr2ns(dsidev, tlpx_half),
2207 tclk_trail, ddr2ns(dsidev, tclk_trail),
2208 tclk_zero, ddr2ns(dsidev, tclk_zero));
2209 DSSDBG("tclk_prepare %u (%uns)\n",
2210 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2211
2212 /* program timings */
2213
2214 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2215 r = FLD_MOD(r, ths_prepare, 31, 24);
2216 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2217 r = FLD_MOD(r, ths_trail, 15, 8);
2218 r = FLD_MOD(r, ths_exit, 7, 0);
2219 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2220
2221 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2222 r = FLD_MOD(r, tlpx_half, 22, 16);
2223 r = FLD_MOD(r, tclk_trail, 15, 8);
2224 r = FLD_MOD(r, tclk_zero, 7, 0);
2225 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2226
2227 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2228 r = FLD_MOD(r, tclk_prepare, 7, 0);
2229 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2230 }
2231
2232 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2233 enum dsi_lane lanes)
2234 {
2235 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2236 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2237 int clk_lane = dssdev->phy.dsi.clk_lane;
2238 int data1_lane = dssdev->phy.dsi.data1_lane;
2239 int data2_lane = dssdev->phy.dsi.data2_lane;
2240 int data3_lane = dssdev->phy.dsi.data3_lane;
2241 int data4_lane = dssdev->phy.dsi.data4_lane;
2242 int clk_pol = dssdev->phy.dsi.clk_pol;
2243 int data1_pol = dssdev->phy.dsi.data1_pol;
2244 int data2_pol = dssdev->phy.dsi.data2_pol;
2245 int data3_pol = dssdev->phy.dsi.data3_pol;
2246 int data4_pol = dssdev->phy.dsi.data4_pol;
2247
2248 u32 l = 0;
2249 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2250
2251 if (lanes & DSI_CLK_P)
2252 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2253 if (lanes & DSI_CLK_N)
2254 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2255
2256 if (lanes & DSI_DATA1_P)
2257 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2258 if (lanes & DSI_DATA1_N)
2259 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2260
2261 if (lanes & DSI_DATA2_P)
2262 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2263 if (lanes & DSI_DATA2_N)
2264 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2265
2266 if (lanes & DSI_DATA3_P)
2267 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2268 if (lanes & DSI_DATA3_N)
2269 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2270
2271 if (lanes & DSI_DATA4_P)
2272 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2273 if (lanes & DSI_DATA4_N)
2274 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2275 /*
2276 * Bits in REGLPTXSCPDAT4TO0DXDY:
2277 * 17: DY0 18: DX0
2278 * 19: DY1 20: DX1
2279 * 21: DY2 22: DX2
2280 * 23: DY3 24: DX3
2281 * 25: DY4 26: DX4
2282 */
2283
2284 /* Set the lane override configuration */
2285
2286 /* REGLPTXSCPDAT4TO0DXDY */
2287 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2288
2289 /* Enable lane override */
2290
2291 /* ENLPTXSCPDAT */
2292 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2293 }
2294
2295 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2296 {
2297 /* Disable lane override */
2298 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2299 /* Reset the lane override configuration */
2300 /* REGLPTXSCPDAT4TO0DXDY */
2301 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2302 }
2303
2304 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2305 {
2306 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2307 int t;
2308 int bits[3];
2309 bool in_use[3];
2310
2311 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2312 bits[0] = 28;
2313 bits[1] = 27;
2314 bits[2] = 26;
2315 } else {
2316 bits[0] = 24;
2317 bits[1] = 25;
2318 bits[2] = 26;
2319 }
2320
2321 in_use[0] = false;
2322 in_use[1] = false;
2323 in_use[2] = false;
2324
2325 if (dssdev->phy.dsi.clk_lane != 0)
2326 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2327 if (dssdev->phy.dsi.data1_lane != 0)
2328 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2329 if (dssdev->phy.dsi.data2_lane != 0)
2330 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2331
2332 t = 100000;
2333 while (true) {
2334 u32 l;
2335 int i;
2336 int ok;
2337
2338 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2339
2340 ok = 0;
2341 for (i = 0; i < 3; ++i) {
2342 if (!in_use[i] || (l & (1 << bits[i])))
2343 ok++;
2344 }
2345
2346 if (ok == 3)
2347 break;
2348
2349 if (--t == 0) {
2350 for (i = 0; i < 3; ++i) {
2351 if (!in_use[i] || (l & (1 << bits[i])))
2352 continue;
2353
2354 DSSERR("CIO TXCLKESC%d domain not coming " \
2355 "out of reset\n", i);
2356 }
2357 return -EIO;
2358 }
2359 }
2360
2361 return 0;
2362 }
2363
2364 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2365 {
2366 unsigned lanes = 0;
2367
2368 if (dssdev->phy.dsi.clk_lane != 0)
2369 lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1);
2370 if (dssdev->phy.dsi.data1_lane != 0)
2371 lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1);
2372 if (dssdev->phy.dsi.data2_lane != 0)
2373 lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1);
2374 if (dssdev->phy.dsi.data3_lane != 0)
2375 lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1);
2376 if (dssdev->phy.dsi.data4_lane != 0)
2377 lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1);
2378
2379 return lanes;
2380 }
2381
2382 static int dsi_cio_init(struct omap_dss_device *dssdev)
2383 {
2384 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2386 int r;
2387 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2388 u32 l;
2389
2390 DSSDBGF();
2391
2392 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2393 if (r)
2394 return r;
2395
2396 dsi_enable_scp_clk(dsidev);
2397
2398 /* A dummy read using the SCP interface to any DSIPHY register is
2399 * required after DSIPHY reset to complete the reset of the DSI complex
2400 * I/O. */
2401 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2402
2403 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2404 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2405 r = -EIO;
2406 goto err_scp_clk_dom;
2407 }
2408
2409 dsi_set_lane_config(dssdev);
2410
2411 /* set TX STOP MODE timer to maximum for this operation */
2412 l = dsi_read_reg(dsidev, DSI_TIMING1);
2413 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2414 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2415 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2416 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2417 dsi_write_reg(dsidev, DSI_TIMING1, l);
2418
2419 if (dsi->ulps_enabled) {
2420 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2421
2422 DSSDBG("manual ulps exit\n");
2423
2424 /* ULPS is exited by Mark-1 state for 1ms, followed by
2425 * stop state. DSS HW cannot do this via the normal
2426 * ULPS exit sequence, as after reset the DSS HW thinks
2427 * that we are not in ULPS mode, and refuses to send the
2428 * sequence. So we need to send the ULPS exit sequence
2429 * manually.
2430 */
2431
2432 if (num_data_lanes_dssdev > 2)
2433 lane_mask |= DSI_DATA3_P;
2434
2435 if (num_data_lanes_dssdev > 3)
2436 lane_mask |= DSI_DATA4_P;
2437
2438 dsi_cio_enable_lane_override(dssdev, lane_mask);
2439 }
2440
2441 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2442 if (r)
2443 goto err_cio_pwr;
2444
2445 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2446 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2447 r = -ENODEV;
2448 goto err_cio_pwr_dom;
2449 }
2450
2451 dsi_if_enable(dsidev, true);
2452 dsi_if_enable(dsidev, false);
2453 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2454
2455 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2456 if (r)
2457 goto err_tx_clk_esc_rst;
2458
2459 if (dsi->ulps_enabled) {
2460 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2461 ktime_t wait = ns_to_ktime(1000 * 1000);
2462 set_current_state(TASK_UNINTERRUPTIBLE);
2463 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2464
2465 /* Disable the override. The lanes should be set to Mark-11
2466 * state by the HW */
2467 dsi_cio_disable_lane_override(dsidev);
2468 }
2469
2470 /* FORCE_TX_STOP_MODE_IO */
2471 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2472
2473 dsi_cio_timings(dsidev);
2474
2475 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2476 /* DDR_CLK_ALWAYS_ON */
2477 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2478 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2479 }
2480
2481 dsi->ulps_enabled = false;
2482
2483 DSSDBG("CIO init done\n");
2484
2485 return 0;
2486
2487 err_tx_clk_esc_rst:
2488 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2489 err_cio_pwr_dom:
2490 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2491 err_cio_pwr:
2492 if (dsi->ulps_enabled)
2493 dsi_cio_disable_lane_override(dsidev);
2494 err_scp_clk_dom:
2495 dsi_disable_scp_clk(dsidev);
2496 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2497 return r;
2498 }
2499
2500 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2501 {
2502 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2503 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2504
2505 /* DDR_CLK_ALWAYS_ON */
2506 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2507
2508 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2509 dsi_disable_scp_clk(dsidev);
2510 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2511 }
2512
2513 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2514 enum fifo_size size1, enum fifo_size size2,
2515 enum fifo_size size3, enum fifo_size size4)
2516 {
2517 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2518 u32 r = 0;
2519 int add = 0;
2520 int i;
2521
2522 dsi->vc[0].fifo_size = size1;
2523 dsi->vc[1].fifo_size = size2;
2524 dsi->vc[2].fifo_size = size3;
2525 dsi->vc[3].fifo_size = size4;
2526
2527 for (i = 0; i < 4; i++) {
2528 u8 v;
2529 int size = dsi->vc[i].fifo_size;
2530
2531 if (add + size > 4) {
2532 DSSERR("Illegal FIFO configuration\n");
2533 BUG();
2534 }
2535
2536 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2537 r |= v << (8 * i);
2538 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2539 add += size;
2540 }
2541
2542 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2543 }
2544
2545 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2546 enum fifo_size size1, enum fifo_size size2,
2547 enum fifo_size size3, enum fifo_size size4)
2548 {
2549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2550 u32 r = 0;
2551 int add = 0;
2552 int i;
2553
2554 dsi->vc[0].fifo_size = size1;
2555 dsi->vc[1].fifo_size = size2;
2556 dsi->vc[2].fifo_size = size3;
2557 dsi->vc[3].fifo_size = size4;
2558
2559 for (i = 0; i < 4; i++) {
2560 u8 v;
2561 int size = dsi->vc[i].fifo_size;
2562
2563 if (add + size > 4) {
2564 DSSERR("Illegal FIFO configuration\n");
2565 BUG();
2566 }
2567
2568 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2569 r |= v << (8 * i);
2570 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2571 add += size;
2572 }
2573
2574 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2575 }
2576
2577 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2578 {
2579 u32 r;
2580
2581 r = dsi_read_reg(dsidev, DSI_TIMING1);
2582 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2583 dsi_write_reg(dsidev, DSI_TIMING1, r);
2584
2585 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2586 DSSERR("TX_STOP bit not going down\n");
2587 return -EIO;
2588 }
2589
2590 return 0;
2591 }
2592
2593 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2594 {
2595 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2596 }
2597
2598 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2599 {
2600 struct dsi_packet_sent_handler_data *vp_data =
2601 (struct dsi_packet_sent_handler_data *) data;
2602 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2603 const int channel = dsi->update_channel;
2604 u8 bit = dsi->te_enabled ? 30 : 31;
2605
2606 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2607 complete(vp_data->completion);
2608 }
2609
2610 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2611 {
2612 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2613 DECLARE_COMPLETION_ONSTACK(completion);
2614 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2615 int r = 0;
2616 u8 bit;
2617
2618 bit = dsi->te_enabled ? 30 : 31;
2619
2620 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2621 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2622 if (r)
2623 goto err0;
2624
2625 /* Wait for completion only if TE_EN/TE_START is still set */
2626 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2627 if (wait_for_completion_timeout(&completion,
2628 msecs_to_jiffies(10)) == 0) {
2629 DSSERR("Failed to complete previous frame transfer\n");
2630 r = -EIO;
2631 goto err1;
2632 }
2633 }
2634
2635 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2636 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2637
2638 return 0;
2639 err1:
2640 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2641 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2642 err0:
2643 return r;
2644 }
2645
2646 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2647 {
2648 struct dsi_packet_sent_handler_data *l4_data =
2649 (struct dsi_packet_sent_handler_data *) data;
2650 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2651 const int channel = dsi->update_channel;
2652
2653 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2654 complete(l4_data->completion);
2655 }
2656
2657 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2658 {
2659 DECLARE_COMPLETION_ONSTACK(completion);
2660 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2661 int r = 0;
2662
2663 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2664 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2665 if (r)
2666 goto err0;
2667
2668 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2669 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2670 if (wait_for_completion_timeout(&completion,
2671 msecs_to_jiffies(10)) == 0) {
2672 DSSERR("Failed to complete previous l4 transfer\n");
2673 r = -EIO;
2674 goto err1;
2675 }
2676 }
2677
2678 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2679 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2680
2681 return 0;
2682 err1:
2683 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2684 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2685 err0:
2686 return r;
2687 }
2688
2689 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2690 {
2691 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2692
2693 WARN_ON(!dsi_bus_is_locked(dsidev));
2694
2695 WARN_ON(in_interrupt());
2696
2697 if (!dsi_vc_is_enabled(dsidev, channel))
2698 return 0;
2699
2700 switch (dsi->vc[channel].source) {
2701 case DSI_VC_SOURCE_VP:
2702 return dsi_sync_vc_vp(dsidev, channel);
2703 case DSI_VC_SOURCE_L4:
2704 return dsi_sync_vc_l4(dsidev, channel);
2705 default:
2706 BUG();
2707 }
2708 }
2709
2710 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2711 bool enable)
2712 {
2713 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2714 channel, enable);
2715
2716 enable = enable ? 1 : 0;
2717
2718 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2719
2720 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2721 0, enable) != enable) {
2722 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2723 return -EIO;
2724 }
2725
2726 return 0;
2727 }
2728
2729 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2730 {
2731 u32 r;
2732
2733 DSSDBGF("%d", channel);
2734
2735 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2736
2737 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2738 DSSERR("VC(%d) busy when trying to configure it!\n",
2739 channel);
2740
2741 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2742 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2743 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2744 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2745 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2746 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2747 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2748 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2749 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2750
2751 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2752 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2753
2754 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2755 }
2756
2757 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2758 enum dsi_vc_source source)
2759 {
2760 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2761
2762 if (dsi->vc[channel].source == source)
2763 return 0;
2764
2765 DSSDBGF("%d", channel);
2766
2767 dsi_sync_vc(dsidev, channel);
2768
2769 dsi_vc_enable(dsidev, channel, 0);
2770
2771 /* VC_BUSY */
2772 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2773 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2774 return -EIO;
2775 }
2776
2777 /* SOURCE, 0 = L4, 1 = video port */
2778 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2779
2780 /* DCS_CMD_ENABLE */
2781 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2782 bool enable = source == DSI_VC_SOURCE_VP;
2783 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2784 }
2785
2786 dsi_vc_enable(dsidev, channel, 1);
2787
2788 dsi->vc[channel].source = source;
2789
2790 return 0;
2791 }
2792
2793 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2794 bool enable)
2795 {
2796 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2797
2798 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2799
2800 WARN_ON(!dsi_bus_is_locked(dsidev));
2801
2802 dsi_vc_enable(dsidev, channel, 0);
2803 dsi_if_enable(dsidev, 0);
2804
2805 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2806
2807 dsi_vc_enable(dsidev, channel, 1);
2808 dsi_if_enable(dsidev, 1);
2809
2810 dsi_force_tx_stop_mode_io(dsidev);
2811
2812 /* start the DDR clock by sending a NULL packet */
2813 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2814 dsi_vc_send_null(dssdev, channel);
2815 }
2816 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2817
2818 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2819 {
2820 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2821 u32 val;
2822 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2823 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2824 (val >> 0) & 0xff,
2825 (val >> 8) & 0xff,
2826 (val >> 16) & 0xff,
2827 (val >> 24) & 0xff);
2828 }
2829 }
2830
2831 static void dsi_show_rx_ack_with_err(u16 err)
2832 {
2833 DSSERR("\tACK with ERROR (%#x):\n", err);
2834 if (err & (1 << 0))
2835 DSSERR("\t\tSoT Error\n");
2836 if (err & (1 << 1))
2837 DSSERR("\t\tSoT Sync Error\n");
2838 if (err & (1 << 2))
2839 DSSERR("\t\tEoT Sync Error\n");
2840 if (err & (1 << 3))
2841 DSSERR("\t\tEscape Mode Entry Command Error\n");
2842 if (err & (1 << 4))
2843 DSSERR("\t\tLP Transmit Sync Error\n");
2844 if (err & (1 << 5))
2845 DSSERR("\t\tHS Receive Timeout Error\n");
2846 if (err & (1 << 6))
2847 DSSERR("\t\tFalse Control Error\n");
2848 if (err & (1 << 7))
2849 DSSERR("\t\t(reserved7)\n");
2850 if (err & (1 << 8))
2851 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2852 if (err & (1 << 9))
2853 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2854 if (err & (1 << 10))
2855 DSSERR("\t\tChecksum Error\n");
2856 if (err & (1 << 11))
2857 DSSERR("\t\tData type not recognized\n");
2858 if (err & (1 << 12))
2859 DSSERR("\t\tInvalid VC ID\n");
2860 if (err & (1 << 13))
2861 DSSERR("\t\tInvalid Transmission Length\n");
2862 if (err & (1 << 14))
2863 DSSERR("\t\t(reserved14)\n");
2864 if (err & (1 << 15))
2865 DSSERR("\t\tDSI Protocol Violation\n");
2866 }
2867
2868 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2869 int channel)
2870 {
2871 /* RX_FIFO_NOT_EMPTY */
2872 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2873 u32 val;
2874 u8 dt;
2875 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2876 DSSERR("\trawval %#08x\n", val);
2877 dt = FLD_GET(val, 5, 0);
2878 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2879 u16 err = FLD_GET(val, 23, 8);
2880 dsi_show_rx_ack_with_err(err);
2881 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2882 DSSERR("\tDCS short response, 1 byte: %#x\n",
2883 FLD_GET(val, 23, 8));
2884 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2885 DSSERR("\tDCS short response, 2 byte: %#x\n",
2886 FLD_GET(val, 23, 8));
2887 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2888 DSSERR("\tDCS long response, len %d\n",
2889 FLD_GET(val, 23, 8));
2890 dsi_vc_flush_long_data(dsidev, channel);
2891 } else {
2892 DSSERR("\tunknown datatype 0x%02x\n", dt);
2893 }
2894 }
2895 return 0;
2896 }
2897
2898 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2899 {
2900 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2901
2902 if (dsi->debug_write || dsi->debug_read)
2903 DSSDBG("dsi_vc_send_bta %d\n", channel);
2904
2905 WARN_ON(!dsi_bus_is_locked(dsidev));
2906
2907 /* RX_FIFO_NOT_EMPTY */
2908 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2909 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2910 dsi_vc_flush_receive_data(dsidev, channel);
2911 }
2912
2913 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2914
2915 return 0;
2916 }
2917
2918 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2919 {
2920 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2921 DECLARE_COMPLETION_ONSTACK(completion);
2922 int r = 0;
2923 u32 err;
2924
2925 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2926 &completion, DSI_VC_IRQ_BTA);
2927 if (r)
2928 goto err0;
2929
2930 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2931 DSI_IRQ_ERROR_MASK);
2932 if (r)
2933 goto err1;
2934
2935 r = dsi_vc_send_bta(dsidev, channel);
2936 if (r)
2937 goto err2;
2938
2939 if (wait_for_completion_timeout(&completion,
2940 msecs_to_jiffies(500)) == 0) {
2941 DSSERR("Failed to receive BTA\n");
2942 r = -EIO;
2943 goto err2;
2944 }
2945
2946 err = dsi_get_errors(dsidev);
2947 if (err) {
2948 DSSERR("Error while sending BTA: %x\n", err);
2949 r = -EIO;
2950 goto err2;
2951 }
2952 err2:
2953 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2954 DSI_IRQ_ERROR_MASK);
2955 err1:
2956 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2957 &completion, DSI_VC_IRQ_BTA);
2958 err0:
2959 return r;
2960 }
2961 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2962
2963 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2964 int channel, u8 data_type, u16 len, u8 ecc)
2965 {
2966 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2967 u32 val;
2968 u8 data_id;
2969
2970 WARN_ON(!dsi_bus_is_locked(dsidev));
2971
2972 data_id = data_type | dsi->vc[channel].vc_id << 6;
2973
2974 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2975 FLD_VAL(ecc, 31, 24);
2976
2977 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2978 }
2979
2980 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2981 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2982 {
2983 u32 val;
2984
2985 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2986
2987 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2988 b1, b2, b3, b4, val); */
2989
2990 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2991 }
2992
2993 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2994 u8 data_type, u8 *data, u16 len, u8 ecc)
2995 {
2996 /*u32 val; */
2997 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2998 int i;
2999 u8 *p;
3000 int r = 0;
3001 u8 b1, b2, b3, b4;
3002
3003 if (dsi->debug_write)
3004 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3005
3006 /* len + header */
3007 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3008 DSSERR("unable to send long packet: packet too long.\n");
3009 return -EINVAL;
3010 }
3011
3012 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3013
3014 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3015
3016 p = data;
3017 for (i = 0; i < len >> 2; i++) {
3018 if (dsi->debug_write)
3019 DSSDBG("\tsending full packet %d\n", i);
3020
3021 b1 = *p++;
3022 b2 = *p++;
3023 b3 = *p++;
3024 b4 = *p++;
3025
3026 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3027 }
3028
3029 i = len % 4;
3030 if (i) {
3031 b1 = 0; b2 = 0; b3 = 0;
3032
3033 if (dsi->debug_write)
3034 DSSDBG("\tsending remainder bytes %d\n", i);
3035
3036 switch (i) {
3037 case 3:
3038 b1 = *p++;
3039 b2 = *p++;
3040 b3 = *p++;
3041 break;
3042 case 2:
3043 b1 = *p++;
3044 b2 = *p++;
3045 break;
3046 case 1:
3047 b1 = *p++;
3048 break;
3049 }
3050
3051 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3052 }
3053
3054 return r;
3055 }
3056
3057 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3058 u8 data_type, u16 data, u8 ecc)
3059 {
3060 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3061 u32 r;
3062 u8 data_id;
3063
3064 WARN_ON(!dsi_bus_is_locked(dsidev));
3065
3066 if (dsi->debug_write)
3067 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3068 channel,
3069 data_type, data & 0xff, (data >> 8) & 0xff);
3070
3071 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3072
3073 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3074 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3075 return -EINVAL;
3076 }
3077
3078 data_id = data_type | dsi->vc[channel].vc_id << 6;
3079
3080 r = (data_id << 0) | (data << 8) | (ecc << 24);
3081
3082 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3083
3084 return 0;
3085 }
3086
3087 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3088 {
3089 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3090
3091 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3092 0, 0);
3093 }
3094 EXPORT_SYMBOL(dsi_vc_send_null);
3095
3096 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3097 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3098 {
3099 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3100 int r;
3101
3102 if (len == 0) {
3103 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3104 r = dsi_vc_send_short(dsidev, channel,
3105 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3106 } else if (len == 1) {
3107 r = dsi_vc_send_short(dsidev, channel,
3108 type == DSS_DSI_CONTENT_GENERIC ?
3109 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3110 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3111 } else if (len == 2) {
3112 r = dsi_vc_send_short(dsidev, channel,
3113 type == DSS_DSI_CONTENT_GENERIC ?
3114 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3115 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3116 data[0] | (data[1] << 8), 0);
3117 } else {
3118 r = dsi_vc_send_long(dsidev, channel,
3119 type == DSS_DSI_CONTENT_GENERIC ?
3120 MIPI_DSI_GENERIC_LONG_WRITE :
3121 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3122 }
3123
3124 return r;
3125 }
3126
3127 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3128 u8 *data, int len)
3129 {
3130 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3131 DSS_DSI_CONTENT_DCS);
3132 }
3133 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3134
3135 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3136 u8 *data, int len)
3137 {
3138 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3139 DSS_DSI_CONTENT_GENERIC);
3140 }
3141 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3142
3143 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3144 u8 *data, int len, enum dss_dsi_content_type type)
3145 {
3146 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3147 int r;
3148
3149 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3150 if (r)
3151 goto err;
3152
3153 r = dsi_vc_send_bta_sync(dssdev, channel);
3154 if (r)
3155 goto err;
3156
3157 /* RX_FIFO_NOT_EMPTY */
3158 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3159 DSSERR("rx fifo not empty after write, dumping data:\n");
3160 dsi_vc_flush_receive_data(dsidev, channel);
3161 r = -EIO;
3162 goto err;
3163 }
3164
3165 return 0;
3166 err:
3167 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3168 channel, data[0], len);
3169 return r;
3170 }
3171
3172 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3173 int len)
3174 {
3175 return dsi_vc_write_common(dssdev, channel, data, len,
3176 DSS_DSI_CONTENT_DCS);
3177 }
3178 EXPORT_SYMBOL(dsi_vc_dcs_write);
3179
3180 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3181 int len)
3182 {
3183 return dsi_vc_write_common(dssdev, channel, data, len,
3184 DSS_DSI_CONTENT_GENERIC);
3185 }
3186 EXPORT_SYMBOL(dsi_vc_generic_write);
3187
3188 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3189 {
3190 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3191 }
3192 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3193
3194 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3195 {
3196 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3197 }
3198 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3199
3200 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3201 u8 param)
3202 {
3203 u8 buf[2];
3204 buf[0] = dcs_cmd;
3205 buf[1] = param;
3206 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3207 }
3208 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3209
3210 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3211 u8 param)
3212 {
3213 return dsi_vc_generic_write(dssdev, channel, &param, 1);
3214 }
3215 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3216
3217 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3218 u8 param1, u8 param2)
3219 {
3220 u8 buf[2];
3221 buf[0] = param1;
3222 buf[1] = param2;
3223 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3224 }
3225 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3226
3227 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3228 int channel, u8 dcs_cmd)
3229 {
3230 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3231 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3232 int r;
3233
3234 if (dsi->debug_read)
3235 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3236 channel, dcs_cmd);
3237
3238 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3239 if (r) {
3240 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3241 " failed\n", channel, dcs_cmd);
3242 return r;
3243 }
3244
3245 return 0;
3246 }
3247
3248 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3249 int channel, u8 *reqdata, int reqlen)
3250 {
3251 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3252 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3253 u16 data;
3254 u8 data_type;
3255 int r;
3256
3257 if (dsi->debug_read)
3258 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3259 channel, reqlen);
3260
3261 if (reqlen == 0) {
3262 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3263 data = 0;
3264 } else if (reqlen == 1) {
3265 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3266 data = reqdata[0];
3267 } else if (reqlen == 2) {
3268 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3269 data = reqdata[0] | (reqdata[1] << 8);
3270 } else {
3271 BUG();
3272 }
3273
3274 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3275 if (r) {
3276 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3277 " failed\n", channel, reqlen);
3278 return r;
3279 }
3280
3281 return 0;
3282 }
3283
3284 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3285 u8 *buf, int buflen, enum dss_dsi_content_type type)
3286 {
3287 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3288 u32 val;
3289 u8 dt;
3290 int r;
3291
3292 /* RX_FIFO_NOT_EMPTY */
3293 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3294 DSSERR("RX fifo empty when trying to read.\n");
3295 r = -EIO;
3296 goto err;
3297 }
3298
3299 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3300 if (dsi->debug_read)
3301 DSSDBG("\theader: %08x\n", val);
3302 dt = FLD_GET(val, 5, 0);
3303 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3304 u16 err = FLD_GET(val, 23, 8);
3305 dsi_show_rx_ack_with_err(err);
3306 r = -EIO;
3307 goto err;
3308
3309 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3310 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3311 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3312 u8 data = FLD_GET(val, 15, 8);
3313 if (dsi->debug_read)
3314 DSSDBG("\t%s short response, 1 byte: %02x\n",
3315 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3316 "DCS", data);
3317
3318 if (buflen < 1) {
3319 r = -EIO;
3320 goto err;
3321 }
3322
3323 buf[0] = data;
3324
3325 return 1;
3326 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3327 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3328 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3329 u16 data = FLD_GET(val, 23, 8);
3330 if (dsi->debug_read)
3331 DSSDBG("\t%s short response, 2 byte: %04x\n",
3332 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3333 "DCS", data);
3334
3335 if (buflen < 2) {
3336 r = -EIO;
3337 goto err;
3338 }
3339
3340 buf[0] = data & 0xff;
3341 buf[1] = (data >> 8) & 0xff;
3342
3343 return 2;
3344 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3345 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3346 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3347 int w;
3348 int len = FLD_GET(val, 23, 8);
3349 if (dsi->debug_read)
3350 DSSDBG("\t%s long response, len %d\n",
3351 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3352 "DCS", len);
3353
3354 if (len > buflen) {
3355 r = -EIO;
3356 goto err;
3357 }
3358
3359 /* two byte checksum ends the packet, not included in len */
3360 for (w = 0; w < len + 2;) {
3361 int b;
3362 val = dsi_read_reg(dsidev,
3363 DSI_VC_SHORT_PACKET_HEADER(channel));
3364 if (dsi->debug_read)
3365 DSSDBG("\t\t%02x %02x %02x %02x\n",
3366 (val >> 0) & 0xff,
3367 (val >> 8) & 0xff,
3368 (val >> 16) & 0xff,
3369 (val >> 24) & 0xff);
3370
3371 for (b = 0; b < 4; ++b) {
3372 if (w < len)
3373 buf[w] = (val >> (b * 8)) & 0xff;
3374 /* we discard the 2 byte checksum */
3375 ++w;
3376 }
3377 }
3378
3379 return len;
3380 } else {
3381 DSSERR("\tunknown datatype 0x%02x\n", dt);
3382 r = -EIO;
3383 goto err;
3384 }
3385
3386 BUG();
3387 err:
3388 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3389 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3390
3391 return r;
3392 }
3393
3394 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3395 u8 *buf, int buflen)
3396 {
3397 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3398 int r;
3399
3400 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3401 if (r)
3402 goto err;
3403
3404 r = dsi_vc_send_bta_sync(dssdev, channel);
3405 if (r)
3406 goto err;
3407
3408 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3409 DSS_DSI_CONTENT_DCS);
3410 if (r < 0)
3411 goto err;
3412
3413 if (r != buflen) {
3414 r = -EIO;
3415 goto err;
3416 }
3417
3418 return 0;
3419 err:
3420 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3421 return r;
3422 }
3423 EXPORT_SYMBOL(dsi_vc_dcs_read);
3424
3425 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3426 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3427 {
3428 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3429 int r;
3430
3431 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3432 if (r)
3433 return r;
3434
3435 r = dsi_vc_send_bta_sync(dssdev, channel);
3436 if (r)
3437 return r;
3438
3439 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3440 DSS_DSI_CONTENT_GENERIC);
3441 if (r < 0)
3442 return r;
3443
3444 if (r != buflen) {
3445 r = -EIO;
3446 return r;
3447 }
3448
3449 return 0;
3450 }
3451
3452 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3453 int buflen)
3454 {
3455 int r;
3456
3457 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3458 if (r) {
3459 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3460 return r;
3461 }
3462
3463 return 0;
3464 }
3465 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3466
3467 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3468 u8 *buf, int buflen)
3469 {
3470 int r;
3471
3472 r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3473 if (r) {
3474 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3475 return r;
3476 }
3477
3478 return 0;
3479 }
3480 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3481
3482 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3483 u8 param1, u8 param2, u8 *buf, int buflen)
3484 {
3485 int r;
3486 u8 reqdata[2];
3487
3488 reqdata[0] = param1;
3489 reqdata[1] = param2;
3490
3491 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3492 if (r) {
3493 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3494 return r;
3495 }
3496
3497 return 0;
3498 }
3499 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3500
3501 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3502 u16 len)
3503 {
3504 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3505
3506 return dsi_vc_send_short(dsidev, channel,
3507 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3508 }
3509 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3510
3511 static int dsi_enter_ulps(struct platform_device *dsidev)
3512 {
3513 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3514 DECLARE_COMPLETION_ONSTACK(completion);
3515 int r;
3516
3517 DSSDBGF();
3518
3519 WARN_ON(!dsi_bus_is_locked(dsidev));
3520
3521 WARN_ON(dsi->ulps_enabled);
3522
3523 if (dsi->ulps_enabled)
3524 return 0;
3525
3526 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3527 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3528 return -EIO;
3529 }
3530
3531 dsi_sync_vc(dsidev, 0);
3532 dsi_sync_vc(dsidev, 1);
3533 dsi_sync_vc(dsidev, 2);
3534 dsi_sync_vc(dsidev, 3);
3535
3536 dsi_force_tx_stop_mode_io(dsidev);
3537
3538 dsi_vc_enable(dsidev, 0, false);
3539 dsi_vc_enable(dsidev, 1, false);
3540 dsi_vc_enable(dsidev, 2, false);
3541 dsi_vc_enable(dsidev, 3, false);
3542
3543 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3544 DSSERR("HS busy when enabling ULPS\n");
3545 return -EIO;
3546 }
3547
3548 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3549 DSSERR("LP busy when enabling ULPS\n");
3550 return -EIO;
3551 }
3552
3553 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3554 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3555 if (r)
3556 return r;
3557
3558 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3559 /* LANEx_ULPS_SIG2 */
3560 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3561 7, 5);
3562
3563 if (wait_for_completion_timeout(&completion,
3564 msecs_to_jiffies(1000)) == 0) {
3565 DSSERR("ULPS enable timeout\n");
3566 r = -EIO;
3567 goto err;
3568 }
3569
3570 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3571 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3572
3573 /* Reset LANEx_ULPS_SIG2 */
3574 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3575 7, 5);
3576
3577 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3578
3579 dsi_if_enable(dsidev, false);
3580
3581 dsi->ulps_enabled = true;
3582
3583 return 0;
3584
3585 err:
3586 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3587 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3588 return r;
3589 }
3590
3591 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3592 unsigned ticks, bool x4, bool x16)
3593 {
3594 unsigned long fck;
3595 unsigned long total_ticks;
3596 u32 r;
3597
3598 BUG_ON(ticks > 0x1fff);
3599
3600 /* ticks in DSI_FCK */
3601 fck = dsi_fclk_rate(dsidev);
3602
3603 r = dsi_read_reg(dsidev, DSI_TIMING2);
3604 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3605 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3606 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3607 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3608 dsi_write_reg(dsidev, DSI_TIMING2, r);
3609
3610 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3611
3612 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3613 total_ticks,
3614 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3615 (total_ticks * 1000) / (fck / 1000 / 1000));
3616 }
3617
3618 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3619 bool x8, bool x16)
3620 {
3621 unsigned long fck;
3622 unsigned long total_ticks;
3623 u32 r;
3624
3625 BUG_ON(ticks > 0x1fff);
3626
3627 /* ticks in DSI_FCK */
3628 fck = dsi_fclk_rate(dsidev);
3629
3630 r = dsi_read_reg(dsidev, DSI_TIMING1);
3631 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3632 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3633 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3634 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3635 dsi_write_reg(dsidev, DSI_TIMING1, r);
3636
3637 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3638
3639 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3640 total_ticks,
3641 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3642 (total_ticks * 1000) / (fck / 1000 / 1000));
3643 }
3644
3645 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3646 unsigned ticks, bool x4, bool x16)
3647 {
3648 unsigned long fck;
3649 unsigned long total_ticks;
3650 u32 r;
3651
3652 BUG_ON(ticks > 0x1fff);
3653
3654 /* ticks in DSI_FCK */
3655 fck = dsi_fclk_rate(dsidev);
3656
3657 r = dsi_read_reg(dsidev, DSI_TIMING1);
3658 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3659 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3660 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3661 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3662 dsi_write_reg(dsidev, DSI_TIMING1, r);
3663
3664 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3665
3666 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3667 total_ticks,
3668 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3669 (total_ticks * 1000) / (fck / 1000 / 1000));
3670 }
3671
3672 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3673 unsigned ticks, bool x4, bool x16)
3674 {
3675 unsigned long fck;
3676 unsigned long total_ticks;
3677 u32 r;
3678
3679 BUG_ON(ticks > 0x1fff);
3680
3681 /* ticks in TxByteClkHS */
3682 fck = dsi_get_txbyteclkhs(dsidev);
3683
3684 r = dsi_read_reg(dsidev, DSI_TIMING2);
3685 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3686 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3687 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3688 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3689 dsi_write_reg(dsidev, DSI_TIMING2, r);
3690
3691 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3692
3693 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3694 total_ticks,
3695 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3696 (total_ticks * 1000) / (fck / 1000 / 1000));
3697 }
3698
3699 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3700 {
3701 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3702 int num_line_buffers;
3703
3704 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3705 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3706 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3707 struct omap_video_timings *timings = &dssdev->panel.timings;
3708 /*
3709 * Don't use line buffers if width is greater than the video
3710 * port's line buffer size
3711 */
3712 if (line_buf_size <= timings->x_res * bpp / 8)
3713 num_line_buffers = 0;
3714 else
3715 num_line_buffers = 2;
3716 } else {
3717 /* Use maximum number of line buffers in command mode */
3718 num_line_buffers = 2;
3719 }
3720
3721 /* LINE_BUFFER */
3722 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3723 }
3724
3725 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3726 {
3727 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3728 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3729 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3730 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3731 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3732 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3733 u32 r;
3734
3735 r = dsi_read_reg(dsidev, DSI_CTRL);
3736 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3737 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3738 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3739 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3740 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3741 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3742 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3743 dsi_write_reg(dsidev, DSI_CTRL, r);
3744 }
3745
3746 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3747 {
3748 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3749 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3750 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3751 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3752 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3753 u32 r;
3754
3755 /*
3756 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3757 * 1 = Long blanking packets are sent in corresponding blanking periods
3758 */
3759 r = dsi_read_reg(dsidev, DSI_CTRL);
3760 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3761 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3762 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3763 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3764 dsi_write_reg(dsidev, DSI_CTRL, r);
3765 }
3766
3767 static int dsi_proto_config(struct omap_dss_device *dssdev)
3768 {
3769 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3770 u32 r;
3771 int buswidth = 0;
3772
3773 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3774 DSI_FIFO_SIZE_32,
3775 DSI_FIFO_SIZE_32,
3776 DSI_FIFO_SIZE_32);
3777
3778 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3779 DSI_FIFO_SIZE_32,
3780 DSI_FIFO_SIZE_32,
3781 DSI_FIFO_SIZE_32);
3782
3783 /* XXX what values for the timeouts? */
3784 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3785 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3786 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3787 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3788
3789 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3790 case 16:
3791 buswidth = 0;
3792 break;
3793 case 18:
3794 buswidth = 1;
3795 break;
3796 case 24:
3797 buswidth = 2;
3798 break;
3799 default:
3800 BUG();
3801 }
3802
3803 r = dsi_read_reg(dsidev, DSI_CTRL);
3804 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3805 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3806 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3807 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3808 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3809 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3810 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3811 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3812 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3813 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3814 /* DCS_CMD_CODE, 1=start, 0=continue */
3815 r = FLD_MOD(r, 0, 25, 25);
3816 }
3817
3818 dsi_write_reg(dsidev, DSI_CTRL, r);
3819
3820 dsi_config_vp_num_line_buffers(dssdev);
3821
3822 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3823 dsi_config_vp_sync_events(dssdev);
3824 dsi_config_blanking_modes(dssdev);
3825 }
3826
3827 dsi_vc_initial_config(dsidev, 0);
3828 dsi_vc_initial_config(dsidev, 1);
3829 dsi_vc_initial_config(dsidev, 2);
3830 dsi_vc_initial_config(dsidev, 3);
3831
3832 return 0;
3833 }
3834
3835 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3836 {
3837 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3838 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3839 unsigned tclk_pre, tclk_post;
3840 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3841 unsigned ths_trail, ths_exit;
3842 unsigned ddr_clk_pre, ddr_clk_post;
3843 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3844 unsigned ths_eot;
3845 int ndl = dsi_get_num_data_lanes_dssdev(dssdev);
3846 u32 r;
3847
3848 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3849 ths_prepare = FLD_GET(r, 31, 24);
3850 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3851 ths_zero = ths_prepare_ths_zero - ths_prepare;
3852 ths_trail = FLD_GET(r, 15, 8);
3853 ths_exit = FLD_GET(r, 7, 0);
3854
3855 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3856 tlpx = FLD_GET(r, 22, 16) * 2;
3857 tclk_trail = FLD_GET(r, 15, 8);
3858 tclk_zero = FLD_GET(r, 7, 0);
3859
3860 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3861 tclk_prepare = FLD_GET(r, 7, 0);
3862
3863 /* min 8*UI */
3864 tclk_pre = 20;
3865 /* min 60ns + 52*UI */
3866 tclk_post = ns2ddr(dsidev, 60) + 26;
3867
3868 ths_eot = DIV_ROUND_UP(4, ndl);
3869
3870 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3871 4);
3872 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3873
3874 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3875 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3876
3877 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3878 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3879 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3880 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3881
3882 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3883 ddr_clk_pre,
3884 ddr_clk_post);
3885
3886 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3887 DIV_ROUND_UP(ths_prepare, 4) +
3888 DIV_ROUND_UP(ths_zero + 3, 4);
3889
3890 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3891
3892 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3893 FLD_VAL(exit_hs_mode_lat, 15, 0);
3894 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3895
3896 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3897 enter_hs_mode_lat, exit_hs_mode_lat);
3898
3899 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3900 /* TODO: Implement a video mode check_timings function */
3901 int hsa = dssdev->panel.dsi_vm_data.hsa;
3902 int hfp = dssdev->panel.dsi_vm_data.hfp;
3903 int hbp = dssdev->panel.dsi_vm_data.hbp;
3904 int vsa = dssdev->panel.dsi_vm_data.vsa;
3905 int vfp = dssdev->panel.dsi_vm_data.vfp;
3906 int vbp = dssdev->panel.dsi_vm_data.vbp;
3907 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3908 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3909 struct omap_video_timings *timings = &dssdev->panel.timings;
3910 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3911 int tl, t_he, width_bytes;
3912
3913 t_he = hsync_end ?
3914 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3915
3916 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3917
3918 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3919 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3920 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3921
3922 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3923 hfp, hsync_end ? hsa : 0, tl);
3924 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3925 vsa, timings->y_res);
3926
3927 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3928 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3929 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3930 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3931 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3932
3933 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3934 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3935 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3936 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3937 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3938 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3939
3940 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3941 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3942 r = FLD_MOD(r, tl, 31, 16); /* TL */
3943 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3944 }
3945 }
3946
3947 int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
3948 {
3949 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3950 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3951 u8 data_type;
3952 u16 word_count;
3953
3954 switch (dssdev->panel.dsi_pix_fmt) {
3955 case OMAP_DSS_DSI_FMT_RGB888:
3956 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3957 break;
3958 case OMAP_DSS_DSI_FMT_RGB666:
3959 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3960 break;
3961 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3962 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3963 break;
3964 case OMAP_DSS_DSI_FMT_RGB565:
3965 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3966 break;
3967 default:
3968 BUG();
3969 };
3970
3971 dsi_if_enable(dsidev, false);
3972 dsi_vc_enable(dsidev, channel, false);
3973
3974 /* MODE, 1 = video mode */
3975 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3976
3977 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3978
3979 dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
3980
3981 dsi_vc_enable(dsidev, channel, true);
3982 dsi_if_enable(dsidev, true);
3983
3984 dssdev->manager->enable(dssdev->manager);
3985
3986 return 0;
3987 }
3988 EXPORT_SYMBOL(dsi_video_mode_enable);
3989
3990 void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
3991 {
3992 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3993
3994 dsi_if_enable(dsidev, false);
3995 dsi_vc_enable(dsidev, channel, false);
3996
3997 /* MODE, 0 = command mode */
3998 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3999
4000 dsi_vc_enable(dsidev, channel, true);
4001 dsi_if_enable(dsidev, true);
4002
4003 dssdev->manager->disable(dssdev->manager);
4004 }
4005 EXPORT_SYMBOL(dsi_video_mode_disable);
4006
4007 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4008 u16 x, u16 y, u16 w, u16 h)
4009 {
4010 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4011 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4012 unsigned bytespp;
4013 unsigned bytespl;
4014 unsigned bytespf;
4015 unsigned total_len;
4016 unsigned packet_payload;
4017 unsigned packet_len;
4018 u32 l;
4019 int r;
4020 const unsigned channel = dsi->update_channel;
4021 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4022
4023 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4024 x, y, w, h);
4025
4026 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4027
4028 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4029 bytespl = w * bytespp;
4030 bytespf = bytespl * h;
4031
4032 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4033 * number of lines in a packet. See errata about VP_CLK_RATIO */
4034
4035 if (bytespf < line_buf_size)
4036 packet_payload = bytespf;
4037 else
4038 packet_payload = (line_buf_size) / bytespl * bytespl;
4039
4040 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4041 total_len = (bytespf / packet_payload) * packet_len;
4042
4043 if (bytespf % packet_payload)
4044 total_len += (bytespf % packet_payload) + 1;
4045
4046 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4047 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4048
4049 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4050 packet_len, 0);
4051
4052 if (dsi->te_enabled)
4053 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4054 else
4055 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4056 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4057
4058 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4059 * because DSS interrupts are not capable of waking up the CPU and the
4060 * framedone interrupt could be delayed for quite a long time. I think
4061 * the same goes for any DSS interrupts, but for some reason I have not
4062 * seen the problem anywhere else than here.
4063 */
4064 dispc_disable_sidle();
4065
4066 dsi_perf_mark_start(dsidev);
4067
4068 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4069 msecs_to_jiffies(250));
4070 BUG_ON(r == 0);
4071
4072 dss_start_update(dssdev);
4073
4074 if (dsi->te_enabled) {
4075 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4076 * for TE is longer than the timer allows */
4077 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4078
4079 dsi_vc_send_bta(dsidev, channel);
4080
4081 #ifdef DSI_CATCH_MISSING_TE
4082 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4083 #endif
4084 }
4085 }
4086
4087 #ifdef DSI_CATCH_MISSING_TE
4088 static void dsi_te_timeout(unsigned long arg)
4089 {
4090 DSSERR("TE not received for 250ms!\n");
4091 }
4092 #endif
4093
4094 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4095 {
4096 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4097
4098 /* SIDLEMODE back to smart-idle */
4099 dispc_enable_sidle();
4100
4101 if (dsi->te_enabled) {
4102 /* enable LP_RX_TO again after the TE */
4103 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4104 }
4105
4106 dsi->framedone_callback(error, dsi->framedone_data);
4107
4108 if (!error)
4109 dsi_perf_show(dsidev, "DISPC");
4110 }
4111
4112 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4113 {
4114 struct dsi_data *dsi = container_of(work, struct dsi_data,
4115 framedone_timeout_work.work);
4116 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4117 * 250ms which would conflict with this timeout work. What should be
4118 * done is first cancel the transfer on the HW, and then cancel the
4119 * possibly scheduled framedone work. However, cancelling the transfer
4120 * on the HW is buggy, and would probably require resetting the whole
4121 * DSI */
4122
4123 DSSERR("Framedone not received for 250ms!\n");
4124
4125 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4126 }
4127
4128 static void dsi_framedone_irq_callback(void *data, u32 mask)
4129 {
4130 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4131 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4132 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4133
4134 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4135 * turns itself off. However, DSI still has the pixels in its buffers,
4136 * and is sending the data.
4137 */
4138
4139 __cancel_delayed_work(&dsi->framedone_timeout_work);
4140
4141 dsi_handle_framedone(dsidev, 0);
4142
4143 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4144 dispc_fake_vsync_irq();
4145 #endif
4146 }
4147
4148 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4149 u16 *x, u16 *y, u16 *w, u16 *h,
4150 bool enlarge_update_area)
4151 {
4152 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4153 u16 dw, dh;
4154
4155 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4156
4157 if (*x > dw || *y > dh)
4158 return -EINVAL;
4159
4160 if (*x + *w > dw)
4161 return -EINVAL;
4162
4163 if (*y + *h > dh)
4164 return -EINVAL;
4165
4166 if (*w == 1)
4167 return -EINVAL;
4168
4169 if (*w == 0 || *h == 0)
4170 return -EINVAL;
4171
4172 dsi_perf_mark_setup(dsidev);
4173
4174 dss_setup_partial_planes(dssdev, x, y, w, h,
4175 enlarge_update_area);
4176 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
4177
4178 return 0;
4179 }
4180 EXPORT_SYMBOL(omap_dsi_prepare_update);
4181
4182 int omap_dsi_update(struct omap_dss_device *dssdev,
4183 int channel,
4184 u16 x, u16 y, u16 w, u16 h,
4185 void (*callback)(int, void *), void *data)
4186 {
4187 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4188 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4189
4190 dsi->update_channel = channel;
4191
4192 /* OMAP DSS cannot send updates of odd widths.
4193 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4194 * here to make sure we catch erroneous updates. Otherwise we'll only
4195 * see rather obscure HW error happening, as DSS halts. */
4196 BUG_ON(x % 2 == 1);
4197
4198 dsi->framedone_callback = callback;
4199 dsi->framedone_data = data;
4200
4201 dsi->update_region.x = x;
4202 dsi->update_region.y = y;
4203 dsi->update_region.w = w;
4204 dsi->update_region.h = h;
4205 dsi->update_region.device = dssdev;
4206
4207 dsi_update_screen_dispc(dssdev, x, y, w, h);
4208
4209 return 0;
4210 }
4211 EXPORT_SYMBOL(omap_dsi_update);
4212
4213 /* Display funcs */
4214
4215 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4216 {
4217 int r;
4218
4219 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4220 u32 irq;
4221 struct omap_video_timings timings = {
4222 .hsw = 1,
4223 .hfp = 1,
4224 .hbp = 1,
4225 .vsw = 1,
4226 .vfp = 0,
4227 .vbp = 0,
4228 };
4229
4230 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4231 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4232
4233 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4234 (void *) dssdev, irq);
4235 if (r) {
4236 DSSERR("can't get FRAMEDONE irq\n");
4237 return r;
4238 }
4239
4240 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4241 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4242
4243 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4244 } else {
4245 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4246 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4247
4248 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4249 &dssdev->panel.timings);
4250 }
4251
4252 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4253 OMAP_DSS_LCD_DISPLAY_TFT);
4254 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4255 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4256 return 0;
4257 }
4258
4259 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4260 {
4261 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4262 u32 irq;
4263
4264 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4265 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4266
4267 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4268 (void *) dssdev, irq);
4269 }
4270 }
4271
4272 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4273 {
4274 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4275 struct dsi_clock_info cinfo;
4276 int r;
4277
4278 /* we always use DSS_CLK_SYSCK as input clock */
4279 cinfo.use_sys_clk = true;
4280 cinfo.regn = dssdev->clocks.dsi.regn;
4281 cinfo.regm = dssdev->clocks.dsi.regm;
4282 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4283 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4284 r = dsi_calc_clock_rates(dssdev, &cinfo);
4285 if (r) {
4286 DSSERR("Failed to calc dsi clocks\n");
4287 return r;
4288 }
4289
4290 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4291 if (r) {
4292 DSSERR("Failed to set dsi clocks\n");
4293 return r;
4294 }
4295
4296 return 0;
4297 }
4298
4299 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4300 {
4301 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4302 struct dispc_clock_info dispc_cinfo;
4303 int r;
4304 unsigned long long fck;
4305
4306 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4307
4308 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4309 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4310
4311 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4312 if (r) {
4313 DSSERR("Failed to calc dispc clocks\n");
4314 return r;
4315 }
4316
4317 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4318 if (r) {
4319 DSSERR("Failed to set dispc clocks\n");
4320 return r;
4321 }
4322
4323 return 0;
4324 }
4325
4326 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4327 {
4328 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4329 int dsi_module = dsi_get_dsidev_id(dsidev);
4330 int r;
4331
4332 r = dsi_pll_init(dsidev, true, true);
4333 if (r)
4334 goto err0;
4335
4336 r = dsi_configure_dsi_clocks(dssdev);
4337 if (r)
4338 goto err1;
4339
4340 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4341 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4342 dss_select_lcd_clk_source(dssdev->manager->id,
4343 dssdev->clocks.dispc.channel.lcd_clk_src);
4344
4345 DSSDBG("PLL OK\n");
4346
4347 r = dsi_configure_dispc_clocks(dssdev);
4348 if (r)
4349 goto err2;
4350
4351 r = dsi_cio_init(dssdev);
4352 if (r)
4353 goto err2;
4354
4355 _dsi_print_reset_status(dsidev);
4356
4357 dsi_proto_timings(dssdev);
4358 dsi_set_lp_clk_divisor(dssdev);
4359
4360 if (1)
4361 _dsi_print_reset_status(dsidev);
4362
4363 r = dsi_proto_config(dssdev);
4364 if (r)
4365 goto err3;
4366
4367 /* enable interface */
4368 dsi_vc_enable(dsidev, 0, 1);
4369 dsi_vc_enable(dsidev, 1, 1);
4370 dsi_vc_enable(dsidev, 2, 1);
4371 dsi_vc_enable(dsidev, 3, 1);
4372 dsi_if_enable(dsidev, 1);
4373 dsi_force_tx_stop_mode_io(dsidev);
4374
4375 return 0;
4376 err3:
4377 dsi_cio_uninit(dssdev);
4378 err2:
4379 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4380 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4381 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4382
4383 err1:
4384 dsi_pll_uninit(dsidev, true);
4385 err0:
4386 return r;
4387 }
4388
4389 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4390 bool disconnect_lanes, bool enter_ulps)
4391 {
4392 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4393 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4394 int dsi_module = dsi_get_dsidev_id(dsidev);
4395
4396 if (enter_ulps && !dsi->ulps_enabled)
4397 dsi_enter_ulps(dsidev);
4398
4399 /* disable interface */
4400 dsi_if_enable(dsidev, 0);
4401 dsi_vc_enable(dsidev, 0, 0);
4402 dsi_vc_enable(dsidev, 1, 0);
4403 dsi_vc_enable(dsidev, 2, 0);
4404 dsi_vc_enable(dsidev, 3, 0);
4405
4406 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4407 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4408 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4409 dsi_cio_uninit(dssdev);
4410 dsi_pll_uninit(dsidev, disconnect_lanes);
4411 }
4412
4413 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4414 {
4415 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4416 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4417 int r = 0;
4418
4419 DSSDBG("dsi_display_enable\n");
4420
4421 WARN_ON(!dsi_bus_is_locked(dsidev));
4422
4423 mutex_lock(&dsi->lock);
4424
4425 if (dssdev->manager == NULL) {
4426 DSSERR("failed to enable display: no manager\n");
4427 r = -ENODEV;
4428 goto err_start_dev;
4429 }
4430
4431 r = omap_dss_start_device(dssdev);
4432 if (r) {
4433 DSSERR("failed to start device\n");
4434 goto err_start_dev;
4435 }
4436
4437 r = dsi_runtime_get(dsidev);
4438 if (r)
4439 goto err_get_dsi;
4440
4441 dsi_enable_pll_clock(dsidev, 1);
4442
4443 _dsi_initialize_irq(dsidev);
4444
4445 r = dsi_display_init_dispc(dssdev);
4446 if (r)
4447 goto err_init_dispc;
4448
4449 r = dsi_display_init_dsi(dssdev);
4450 if (r)
4451 goto err_init_dsi;
4452
4453 mutex_unlock(&dsi->lock);
4454
4455 return 0;
4456
4457 err_init_dsi:
4458 dsi_display_uninit_dispc(dssdev);
4459 err_init_dispc:
4460 dsi_enable_pll_clock(dsidev, 0);
4461 dsi_runtime_put(dsidev);
4462 err_get_dsi:
4463 omap_dss_stop_device(dssdev);
4464 err_start_dev:
4465 mutex_unlock(&dsi->lock);
4466 DSSDBG("dsi_display_enable FAILED\n");
4467 return r;
4468 }
4469 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4470
4471 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4472 bool disconnect_lanes, bool enter_ulps)
4473 {
4474 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4475 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4476
4477 DSSDBG("dsi_display_disable\n");
4478
4479 WARN_ON(!dsi_bus_is_locked(dsidev));
4480
4481 mutex_lock(&dsi->lock);
4482
4483 dsi_sync_vc(dsidev, 0);
4484 dsi_sync_vc(dsidev, 1);
4485 dsi_sync_vc(dsidev, 2);
4486 dsi_sync_vc(dsidev, 3);
4487
4488 dsi_display_uninit_dispc(dssdev);
4489
4490 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4491
4492 dsi_runtime_put(dsidev);
4493 dsi_enable_pll_clock(dsidev, 0);
4494
4495 omap_dss_stop_device(dssdev);
4496
4497 mutex_unlock(&dsi->lock);
4498 }
4499 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4500
4501 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4502 {
4503 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4504 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4505
4506 dsi->te_enabled = enable;
4507 return 0;
4508 }
4509 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4510
4511 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4512 u32 fifo_size, u32 burst_size,
4513 u32 *fifo_low, u32 *fifo_high)
4514 {
4515 *fifo_high = fifo_size - burst_size;
4516 *fifo_low = fifo_size - burst_size * 2;
4517 }
4518
4519 int dsi_init_display(struct omap_dss_device *dssdev)
4520 {
4521 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4522 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4523 int dsi_module = dsi_get_dsidev_id(dsidev);
4524
4525 DSSDBG("DSI init\n");
4526
4527 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4528 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4529 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4530 }
4531
4532 if (dsi->vdds_dsi_reg == NULL) {
4533 struct regulator *vdds_dsi;
4534
4535 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4536
4537 if (IS_ERR(vdds_dsi)) {
4538 DSSERR("can't get VDDS_DSI regulator\n");
4539 return PTR_ERR(vdds_dsi);
4540 }
4541
4542 dsi->vdds_dsi_reg = vdds_dsi;
4543 }
4544
4545 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4546 DSSERR("DSI%d can't support more than %d data lanes\n",
4547 dsi_module + 1, dsi->num_data_lanes);
4548 return -EINVAL;
4549 }
4550
4551 return 0;
4552 }
4553
4554 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4555 {
4556 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4557 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4558 int i;
4559
4560 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4561 if (!dsi->vc[i].dssdev) {
4562 dsi->vc[i].dssdev = dssdev;
4563 *channel = i;
4564 return 0;
4565 }
4566 }
4567
4568 DSSERR("cannot get VC for display %s", dssdev->name);
4569 return -ENOSPC;
4570 }
4571 EXPORT_SYMBOL(omap_dsi_request_vc);
4572
4573 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4574 {
4575 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4576 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4577
4578 if (vc_id < 0 || vc_id > 3) {
4579 DSSERR("VC ID out of range\n");
4580 return -EINVAL;
4581 }
4582
4583 if (channel < 0 || channel > 3) {
4584 DSSERR("Virtual Channel out of range\n");
4585 return -EINVAL;
4586 }
4587
4588 if (dsi->vc[channel].dssdev != dssdev) {
4589 DSSERR("Virtual Channel not allocated to display %s\n",
4590 dssdev->name);
4591 return -EINVAL;
4592 }
4593
4594 dsi->vc[channel].vc_id = vc_id;
4595
4596 return 0;
4597 }
4598 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4599
4600 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4601 {
4602 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4603 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4604
4605 if ((channel >= 0 && channel <= 3) &&
4606 dsi->vc[channel].dssdev == dssdev) {
4607 dsi->vc[channel].dssdev = NULL;
4608 dsi->vc[channel].vc_id = 0;
4609 }
4610 }
4611 EXPORT_SYMBOL(omap_dsi_release_vc);
4612
4613 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4614 {
4615 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4616 DSSERR("%s (%s) not active\n",
4617 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4618 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4619 }
4620
4621 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4622 {
4623 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4624 DSSERR("%s (%s) not active\n",
4625 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4626 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4627 }
4628
4629 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4630 {
4631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4632
4633 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4634 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4635 dsi->regm_dispc_max =
4636 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4637 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4638 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4639 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4640 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4641 }
4642
4643 static int dsi_get_clocks(struct platform_device *dsidev)
4644 {
4645 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4646 struct clk *clk;
4647
4648 clk = clk_get(&dsidev->dev, "fck");
4649 if (IS_ERR(clk)) {
4650 DSSERR("can't get fck\n");
4651 return PTR_ERR(clk);
4652 }
4653
4654 dsi->dss_clk = clk;
4655
4656 clk = clk_get(&dsidev->dev, "sys_clk");
4657 if (IS_ERR(clk)) {
4658 DSSERR("can't get sys_clk\n");
4659 clk_put(dsi->dss_clk);
4660 dsi->dss_clk = NULL;
4661 return PTR_ERR(clk);
4662 }
4663
4664 dsi->sys_clk = clk;
4665
4666 return 0;
4667 }
4668
4669 static void dsi_put_clocks(struct platform_device *dsidev)
4670 {
4671 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4672
4673 if (dsi->dss_clk)
4674 clk_put(dsi->dss_clk);
4675 if (dsi->sys_clk)
4676 clk_put(dsi->sys_clk);
4677 }
4678
4679 /* DSI1 HW IP initialisation */
4680 static int omap_dsihw_probe(struct platform_device *dsidev)
4681 {
4682 struct omap_display_platform_data *dss_plat_data;
4683 struct omap_dss_board_info *board_info;
4684 u32 rev;
4685 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4686 struct resource *dsi_mem;
4687 struct dsi_data *dsi;
4688
4689 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4690 if (!dsi) {
4691 r = -ENOMEM;
4692 goto err_alloc;
4693 }
4694
4695 dsi->pdev = dsidev;
4696 dsi_pdev_map[dsi_module] = dsidev;
4697 dev_set_drvdata(&dsidev->dev, dsi);
4698
4699 dss_plat_data = dsidev->dev.platform_data;
4700 board_info = dss_plat_data->board_data;
4701 dsi->enable_pads = board_info->dsi_enable_pads;
4702 dsi->disable_pads = board_info->dsi_disable_pads;
4703
4704 spin_lock_init(&dsi->irq_lock);
4705 spin_lock_init(&dsi->errors_lock);
4706 dsi->errors = 0;
4707
4708 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4709 spin_lock_init(&dsi->irq_stats_lock);
4710 dsi->irq_stats.last_reset = jiffies;
4711 #endif
4712
4713 mutex_init(&dsi->lock);
4714 sema_init(&dsi->bus_lock, 1);
4715
4716 r = dsi_get_clocks(dsidev);
4717 if (r)
4718 goto err_get_clk;
4719
4720 pm_runtime_enable(&dsidev->dev);
4721
4722 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4723 dsi_framedone_timeout_work_callback);
4724
4725 #ifdef DSI_CATCH_MISSING_TE
4726 init_timer(&dsi->te_timer);
4727 dsi->te_timer.function = dsi_te_timeout;
4728 dsi->te_timer.data = 0;
4729 #endif
4730 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4731 if (!dsi_mem) {
4732 DSSERR("can't get IORESOURCE_MEM DSI\n");
4733 r = -EINVAL;
4734 goto err_ioremap;
4735 }
4736 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4737 if (!dsi->base) {
4738 DSSERR("can't ioremap DSI\n");
4739 r = -ENOMEM;
4740 goto err_ioremap;
4741 }
4742 dsi->irq = platform_get_irq(dsi->pdev, 0);
4743 if (dsi->irq < 0) {
4744 DSSERR("platform_get_irq failed\n");
4745 r = -ENODEV;
4746 goto err_get_irq;
4747 }
4748
4749 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4750 dev_name(&dsidev->dev), dsi->pdev);
4751 if (r < 0) {
4752 DSSERR("request_irq failed\n");
4753 goto err_get_irq;
4754 }
4755
4756 /* DSI VCs initialization */
4757 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4758 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4759 dsi->vc[i].dssdev = NULL;
4760 dsi->vc[i].vc_id = 0;
4761 }
4762
4763 dsi_calc_clock_param_ranges(dsidev);
4764
4765 r = dsi_runtime_get(dsidev);
4766 if (r)
4767 goto err_get_dsi;
4768
4769 rev = dsi_read_reg(dsidev, DSI_REVISION);
4770 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4771 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4772
4773 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4774
4775 dsi_runtime_put(dsidev);
4776
4777 return 0;
4778
4779 err_get_dsi:
4780 free_irq(dsi->irq, dsi->pdev);
4781 err_get_irq:
4782 iounmap(dsi->base);
4783 err_ioremap:
4784 pm_runtime_disable(&dsidev->dev);
4785 err_get_clk:
4786 kfree(dsi);
4787 err_alloc:
4788 return r;
4789 }
4790
4791 static int omap_dsihw_remove(struct platform_device *dsidev)
4792 {
4793 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4794
4795 WARN_ON(dsi->scp_clk_refcount > 0);
4796
4797 pm_runtime_disable(&dsidev->dev);
4798
4799 dsi_put_clocks(dsidev);
4800
4801 if (dsi->vdds_dsi_reg != NULL) {
4802 if (dsi->vdds_dsi_enabled) {
4803 regulator_disable(dsi->vdds_dsi_reg);
4804 dsi->vdds_dsi_enabled = false;
4805 }
4806
4807 regulator_put(dsi->vdds_dsi_reg);
4808 dsi->vdds_dsi_reg = NULL;
4809 }
4810
4811 free_irq(dsi->irq, dsi->pdev);
4812 iounmap(dsi->base);
4813
4814 kfree(dsi);
4815
4816 return 0;
4817 }
4818
4819 static int dsi_runtime_suspend(struct device *dev)
4820 {
4821 dispc_runtime_put();
4822 dss_runtime_put();
4823
4824 return 0;
4825 }
4826
4827 static int dsi_runtime_resume(struct device *dev)
4828 {
4829 int r;
4830
4831 r = dss_runtime_get();
4832 if (r)
4833 goto err_get_dss;
4834
4835 r = dispc_runtime_get();
4836 if (r)
4837 goto err_get_dispc;
4838
4839 return 0;
4840
4841 err_get_dispc:
4842 dss_runtime_put();
4843 err_get_dss:
4844 return r;
4845 }
4846
4847 static const struct dev_pm_ops dsi_pm_ops = {
4848 .runtime_suspend = dsi_runtime_suspend,
4849 .runtime_resume = dsi_runtime_resume,
4850 };
4851
4852 static struct platform_driver omap_dsihw_driver = {
4853 .probe = omap_dsihw_probe,
4854 .remove = omap_dsihw_remove,
4855 .driver = {
4856 .name = "omapdss_dsi",
4857 .owner = THIS_MODULE,
4858 .pm = &dsi_pm_ops,
4859 },
4860 };
4861
4862 int dsi_init_platform_driver(void)
4863 {
4864 return platform_driver_register(&omap_dsihw_driver);
4865 }
4866
4867 void dsi_uninit_platform_driver(void)
4868 {
4869 return platform_driver_unregister(&omap_dsihw_driver);
4870 }
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