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MIPS: JZ4740: GPIO: Use shared irq chip for all gpios
[linux-2.6/linux-mips.git] / arch / mips / jz4740 / gpio.c
blob9bb0770fa76e326772de7f05ab56d4ccaa6cd97b
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19
20 #include <linux/spinlock.h>
21 #include <linux/sysdev.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27
28 #include <linux/debugfs.h>
29 #include <linux/seq_file.h>
30
31 #include <asm/mach-jz4740/base.h>
32
33 #define JZ4740_GPIO_BASE_A (32*0)
34 #define JZ4740_GPIO_BASE_B (32*1)
35 #define JZ4740_GPIO_BASE_C (32*2)
36 #define JZ4740_GPIO_BASE_D (32*3)
37
38 #define JZ4740_GPIO_NUM_A 32
39 #define JZ4740_GPIO_NUM_B 32
40 #define JZ4740_GPIO_NUM_C 31
41 #define JZ4740_GPIO_NUM_D 32
42
43 #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44 #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45 #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46 #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
47
48 #define JZ_REG_GPIO_PIN 0x00
49 #define JZ_REG_GPIO_DATA 0x10
50 #define JZ_REG_GPIO_DATA_SET 0x14
51 #define JZ_REG_GPIO_DATA_CLEAR 0x18
52 #define JZ_REG_GPIO_MASK 0x20
53 #define JZ_REG_GPIO_MASK_SET 0x24
54 #define JZ_REG_GPIO_MASK_CLEAR 0x28
55 #define JZ_REG_GPIO_PULL 0x30
56 #define JZ_REG_GPIO_PULL_SET 0x34
57 #define JZ_REG_GPIO_PULL_CLEAR 0x38
58 #define JZ_REG_GPIO_FUNC 0x40
59 #define JZ_REG_GPIO_FUNC_SET 0x44
60 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
61 #define JZ_REG_GPIO_SELECT 0x50
62 #define JZ_REG_GPIO_SELECT_SET 0x54
63 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
64 #define JZ_REG_GPIO_DIRECTION 0x60
65 #define JZ_REG_GPIO_DIRECTION_SET 0x64
66 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67 #define JZ_REG_GPIO_TRIGGER 0x70
68 #define JZ_REG_GPIO_TRIGGER_SET 0x74
69 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70 #define JZ_REG_GPIO_FLAG 0x80
71 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
74 #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
75 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
76
77 struct jz_gpio_chip {
78 unsigned int irq;
79 unsigned int irq_base;
80 uint32_t wakeup;
81 uint32_t suspend_mask;
82 uint32_t edge_trigger_both;
83
84 void __iomem *base;
85
86 spinlock_t lock;
87
88 struct gpio_chip gpio_chip;
89 struct sys_device sysdev;
90 };
91
92 static struct jz_gpio_chip jz4740_gpio_chips[];
93
94 static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
95 {
96 return &jz4740_gpio_chips[gpio >> 5];
97 }
98
99 static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
100 {
101 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
102 }
103
104 static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
105 {
106 return irq_data_get_irq_chip_data(data);
107 }
108
109 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
110 {
111 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
112 }
113
114 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
115 {
116 if (function == JZ_GPIO_FUNC_NONE) {
117 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
119 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
120 } else {
121 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
122 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
123 switch (function) {
124 case JZ_GPIO_FUNC1:
125 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
126 break;
127 case JZ_GPIO_FUNC3:
128 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
129 case JZ_GPIO_FUNC2: /* Falltrough */
130 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
131 break;
132 default:
133 BUG();
134 break;
135 }
136 }
137
138 return 0;
139 }
140 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
141
142 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
143 {
144 size_t i;
145 int ret;
146
147 for (i = 0; i < num; ++i, ++request) {
148 ret = gpio_request(request->gpio, request->name);
149 if (ret)
150 goto err;
151 jz_gpio_set_function(request->gpio, request->function);
152 }
153
154 return 0;
155
156 err:
157 for (--request; i > 0; --i, --request) {
158 gpio_free(request->gpio);
159 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
160 }
161
162 return ret;
163 }
164 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
165
166 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
167 {
168 size_t i;
169
170 for (i = 0; i < num; ++i, ++request) {
171 gpio_free(request->gpio);
172 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
173 }
174
175 }
176 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
177
178 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
179 {
180 size_t i;
181
182 for (i = 0; i < num; ++i, ++request) {
183 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
184 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
185 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
186 }
187 }
188 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
189
190 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
191 {
192 size_t i;
193
194 for (i = 0; i < num; ++i, ++request)
195 jz_gpio_set_function(request->gpio, request->function);
196 }
197 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
198
199 void jz_gpio_enable_pullup(unsigned gpio)
200 {
201 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
202 }
203 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
204
205 void jz_gpio_disable_pullup(unsigned gpio)
206 {
207 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
208 }
209 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
210
211 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
212 {
213 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
214 }
215
216 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
217 {
218 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
219 reg += !value;
220 writel(BIT(gpio), reg);
221 }
222
223 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
224 int value)
225 {
226 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
227 jz_gpio_set_value(chip, gpio, value);
228
229 return 0;
230 }
231
232 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
233 {
234 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
235
236 return 0;
237 }
238
239 int jz_gpio_port_direction_input(int port, uint32_t mask)
240 {
241 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
242
243 return 0;
244 }
245 EXPORT_SYMBOL(jz_gpio_port_direction_input);
246
247 int jz_gpio_port_direction_output(int port, uint32_t mask)
248 {
249 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
250
251 return 0;
252 }
253 EXPORT_SYMBOL(jz_gpio_port_direction_output);
254
255 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
256 {
257 writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
258 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
259 }
260 EXPORT_SYMBOL(jz_gpio_port_set_value);
261
262 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
263 {
264 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
265
266 return value & mask;
267 }
268 EXPORT_SYMBOL(jz_gpio_port_get_value);
269
270 int gpio_to_irq(unsigned gpio)
271 {
272 return JZ4740_IRQ_GPIO(0) + gpio;
273 }
274 EXPORT_SYMBOL_GPL(gpio_to_irq);
275
276 int irq_to_gpio(unsigned irq)
277 {
278 return irq - JZ4740_IRQ_GPIO(0);
279 }
280 EXPORT_SYMBOL_GPL(irq_to_gpio);
281
282 #define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
283
284 static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
285 {
286 uint32_t value;
287 void __iomem *reg;
288 uint32_t mask = IRQ_TO_BIT(irq);
289
290 if (!(chip->edge_trigger_both & mask))
291 return;
292
293 reg = chip->base;
294
295 value = readl(chip->base + JZ_REG_GPIO_PIN);
296 if (value & mask)
297 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
298 else
299 reg += JZ_REG_GPIO_DIRECTION_SET;
300
301 writel(mask, reg);
302 }
303
304 static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
305 {
306 uint32_t flag;
307 unsigned int gpio_irq;
308 unsigned int gpio_bank;
309 struct jz_gpio_chip *chip = get_irq_desc_data(desc);
310
311 gpio_bank = JZ4740_IRQ_GPIO0 - irq;
312
313 flag = readl(chip->base + JZ_REG_GPIO_FLAG);
314
315 if (!flag)
316 return;
317
318 gpio_irq = __fls(flag);
319
320 jz_gpio_check_trigger_both(chip, irq);
321
322 gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
323
324 generic_handle_irq(gpio_irq);
325 };
326
327 static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
328 {
329 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
330 writel(IRQ_TO_BIT(data->irq), chip->base + reg);
331 }
332
333 static void jz_gpio_irq_mask(struct irq_data *data)
334 {
335 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
336 };
337
338 static void jz_gpio_irq_unmask(struct irq_data *data)
339 {
340 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
341
342 jz_gpio_check_trigger_both(chip, data->irq);
343
344 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
345 };
346
347 /* TODO: Check if function is gpio */
348 static unsigned int jz_gpio_irq_startup(struct irq_data *data)
349 {
350 struct irq_desc *desc = irq_to_desc(data->irq);
351
352 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
353
354 desc->status &= ~IRQ_MASKED;
355 jz_gpio_irq_unmask(data);
356
357 return 0;
358 }
359
360 static void jz_gpio_irq_shutdown(struct irq_data *data)
361 {
362 struct irq_desc *desc = irq_to_desc(data->irq);
363
364 jz_gpio_irq_mask(data);
365 desc->status |= IRQ_MASKED;
366
367 /* Set direction to input */
368 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
369 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
370 }
371
372 static void jz_gpio_irq_ack(struct irq_data *data)
373 {
374 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
375 };
376
377 static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
378 {
379 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
380 struct irq_desc *desc = irq_to_desc(data->irq);
381 unsigned int irq = data->irq;
382
383 jz_gpio_irq_mask(data);
384
385 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
386 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
387 if (value & IRQ_TO_BIT(irq))
388 flow_type = IRQ_TYPE_EDGE_FALLING;
389 else
390 flow_type = IRQ_TYPE_EDGE_RISING;
391 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
392 } else {
393 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
394 }
395
396 switch (flow_type) {
397 case IRQ_TYPE_EDGE_RISING:
398 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
399 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
400 break;
401 case IRQ_TYPE_EDGE_FALLING:
402 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
403 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
404 break;
405 case IRQ_TYPE_LEVEL_HIGH:
406 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
407 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
408 break;
409 case IRQ_TYPE_LEVEL_LOW:
410 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
411 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 if (!(desc->status & IRQ_MASKED))
418 jz_gpio_irq_unmask(data);
419
420 return 0;
421 }
422
423 static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
424 {
425 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
426 spin_lock(&chip->lock);
427 if (on)
428 chip->wakeup |= IRQ_TO_BIT(data->irq);
429 else
430 chip->wakeup &= ~IRQ_TO_BIT(data->irq);
431 spin_unlock(&chip->lock);
432
433 set_irq_wake(chip->irq, on);
434 return 0;
435 }
436
437 static struct irq_chip jz_gpio_irq_chip = {
438 .name = "GPIO",
439 .irq_mask = jz_gpio_irq_mask,
440 .irq_unmask = jz_gpio_irq_unmask,
441 .irq_ack = jz_gpio_irq_ack,
442 .irq_startup = jz_gpio_irq_startup,
443 .irq_shutdown = jz_gpio_irq_shutdown,
444 .irq_set_type = jz_gpio_irq_set_type,
445 .irq_set_wake = jz_gpio_irq_set_wake,
446 };
447
448 /*
449 * This lock class tells lockdep that GPIO irqs are in a different
450 * category than their parents, so it won't report false recursion.
451 */
452 static struct lock_class_key gpio_lock_class;
453
454 #define JZ4740_GPIO_CHIP(_bank) { \
455 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
456 .gpio_chip = { \
457 .label = "Bank " # _bank, \
458 .owner = THIS_MODULE, \
459 .set = jz_gpio_set_value, \
460 .get = jz_gpio_get_value, \
461 .direction_output = jz_gpio_direction_output, \
462 .direction_input = jz_gpio_direction_input, \
463 .base = JZ4740_GPIO_BASE_ ## _bank, \
464 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
465 }, \
466 }
467
468 static struct jz_gpio_chip jz4740_gpio_chips[] = {
469 JZ4740_GPIO_CHIP(A),
470 JZ4740_GPIO_CHIP(B),
471 JZ4740_GPIO_CHIP(C),
472 JZ4740_GPIO_CHIP(D),
473 };
474
475 static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
476 {
477 return container_of(dev, struct jz_gpio_chip, sysdev);
478 }
479
480 static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
481 {
482 struct jz_gpio_chip *chip = sysdev_to_chip(dev);
483
484 chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
485 writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
486 writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
487
488 return 0;
489 }
490
491 static int jz4740_gpio_resume(struct sys_device *dev)
492 {
493 struct jz_gpio_chip *chip = sysdev_to_chip(dev);
494 uint32_t mask = chip->suspend_mask;
495
496 writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
497 writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
498
499 return 0;
500 }
501
502 static struct sysdev_class jz4740_gpio_sysdev_class = {
503 .name = "gpio",
504 .suspend = jz4740_gpio_suspend,
505 .resume = jz4740_gpio_resume,
506 };
507
508 static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
509 {
510 int ret, irq;
511
512 chip->sysdev.id = id;
513 chip->sysdev.cls = &jz4740_gpio_sysdev_class;
514 ret = sysdev_register(&chip->sysdev);
515
516 if (ret)
517 return ret;
518
519 spin_lock_init(&chip->lock);
520
521 chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
522
523 gpiochip_add(&chip->gpio_chip);
524
525 chip->irq = JZ4740_IRQ_INTC_GPIO(id);
526 set_irq_data(chip->irq, chip);
527 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
528
529 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
530 lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
531 set_irq_chip_data(irq, chip);
532 set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
533 handle_level_irq);
534 }
535
536 return 0;
537 }
538
539 static int __init jz4740_gpio_init(void)
540 {
541 unsigned int i;
542 int ret;
543
544 ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
545 if (ret)
546 return ret;
547
548 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
549 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
550
551 printk(KERN_INFO "JZ4740 GPIO initialized\n");
552
553 return 0;
554 }
555 arch_initcall(jz4740_gpio_init);
556
557 #ifdef CONFIG_DEBUG_FS
558
559 static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
560 const char *name, unsigned int reg)
561 {
562 seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
563 }
564
565 static int gpio_regs_show(struct seq_file *s, void *unused)
566 {
567 struct jz_gpio_chip *chip = jz4740_gpio_chips;
568 int i;
569
570 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
571 seq_printf(s, "==GPIO %d==\n", i);
572 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
573 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
574 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
575 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
576 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
577 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
578 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
579 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
580 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
581 }
582
583 return 0;
584 }
585
586 static int gpio_regs_open(struct inode *inode, struct file *file)
587 {
588 return single_open(file, gpio_regs_show, NULL);
589 }
590
591 static const struct file_operations gpio_regs_operations = {
592 .open = gpio_regs_open,
593 .read = seq_read,
594 .llseek = seq_lseek,
595 .release = single_release,
596 };
597
598 static int __init gpio_debugfs_init(void)
599 {
600 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
601 NULL, NULL, &gpio_regs_operations);
602 return 0;
603 }
604 subsys_initcall(gpio_debugfs_init);
605
606 #endif
Mirror of the linux-mips.org kernel tree