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vmxnet3: Fix inconsistent LRO state after initialization
[linux-2.6/linux-mips.git] / sound / soc / codecs / tlv320dac33.c
blob082e9d51963fd457261143aa6d50d679731c22d6
1 /*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
44
45 /*
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
50 */
51 #define DAC33_FIFO_SIZE_16BIT 6144
52 #define DAC33_FIFO_SIZE_24BIT 4096
53 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
54
55 #define BURST_BASEFREQ_HZ 49152000
56
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
62
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65
66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
68
69 enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74 };
75
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
79 DAC33_FIFO_MODE7,
80 DAC33_FIFO_LAST_MODE,
81 };
82
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88 };
89
90 struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec *codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
104 unsigned int fifo_size; /* Size of the FIFO in samples */
105 unsigned int nsample; /* burst read amount from host */
106 int mode1_latency; /* latency caused by the i2c writes in
107 * us */
108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
109 unsigned int burst_rate; /* Interface speed in Burst modes */
110
111 int keep_bclk; /* Keep the BCLK continuously running
112 * in FIFO modes */
113 spinlock_t lock;
114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
116
117 unsigned int mode1_us_burst; /* Time to burst read n number of
118 * samples */
119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
120
121 unsigned int uthr;
122
123 enum dac33_state state;
124 enum snd_soc_control_type control_type;
125 void *control_data;
126 };
127
128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
143 0x00, 0x00, /* 0x38 - 0x39 */
144 /* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
149 0x00, 0x80, /* 0x44 - 0x45 */
150 /* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
153 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
154 /* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
168 0x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171 };
172
173 /* Register read and write */
174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176 {
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182 }
183
184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186 {
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192 }
193
194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196 {
197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
198 int val, ret = 0;
199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
208 ret = val;
209 } else {
210 value[0] = val;
211 dac33_write_reg_cache(codec, reg, val);
212 }
213 } else {
214 value[0] = dac33_read_reg_cache(codec, reg);
215 }
216
217 return ret;
218 }
219
220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
221 unsigned int value)
222 {
223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
224 u8 data[2];
225 int ret = 0;
226
227 /*
228 * data is
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
231 */
232 data[0] = reg & 0xff;
233 data[1] = value & 0xff;
234
235 dac33_write_reg_cache(codec, data[0], data[1]);
236 if (dac33->chip_power) {
237 ret = codec->hw_write(codec->control_data, data, 2);
238 if (ret != 2)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245 }
246
247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
248 unsigned int value)
249 {
250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
251 int ret;
252
253 mutex_lock(&dac33->mutex);
254 ret = dac33_write(codec, reg, value);
255 mutex_unlock(&dac33->mutex);
256
257 return ret;
258 }
259
260 #define DAC33_I2C_ADDR_AUTOINC 0x80
261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
262 unsigned int value)
263 {
264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
265 u8 data[3];
266 int ret = 0;
267
268 /*
269 * data is
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
273 */
274 data[0] = reg & 0xff;
275 data[1] = (value >> 8) & 0xff;
276 data[2] = value & 0xff;
277
278 dac33_write_reg_cache(codec, data[0], data[1]);
279 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
280
281 if (dac33->chip_power) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data[0] |= DAC33_I2C_ADDR_AUTOINC;
284 ret = codec->hw_write(codec->control_data, data, 3);
285 if (ret != 3)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 else
288 ret = 0;
289 }
290
291 return ret;
292 }
293
294 static void dac33_init_chip(struct snd_soc_codec *codec)
295 {
296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
297
298 if (unlikely(!dac33->chip_power))
299 return;
300
301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
313 /* Restore only selected registers (gains mostly) */
314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
318
319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
323
324 dac33_write(codec, DAC33_OUT_AMP_CTRL,
325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
326
327 dac33_write(codec, DAC33_LDAC_PWR_CTRL,
328 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
329 dac33_write(codec, DAC33_RDAC_PWR_CTRL,
330 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
331 }
332
333 static inline int dac33_read_id(struct snd_soc_codec *codec)
334 {
335 int i, ret = 0;
336 u8 reg;
337
338 for (i = 0; i < 3; i++) {
339 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
340 if (ret < 0)
341 break;
342 }
343
344 return ret;
345 }
346
347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
348 {
349 u8 reg;
350
351 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
352 if (power)
353 reg |= DAC33_PDNALLB;
354 else
355 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
356 DAC33_DACRPDNB | DAC33_DACLPDNB);
357 dac33_write(codec, DAC33_PWR_CTRL, reg);
358 }
359
360 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
361 {
362 u8 reg;
363
364 /* Stop the DAI clock */
365 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
366 reg &= ~DAC33_BCLKON;
367 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
368
369 /* Power down the Oscillator, and DACs */
370 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
371 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
372 dac33_write(codec, DAC33_PWR_CTRL, reg);
373 }
374
375 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
376 {
377 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
378 int ret = 0;
379
380 mutex_lock(&dac33->mutex);
381
382 /* Safety check */
383 if (unlikely(power == dac33->chip_power)) {
384 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
385 power ? "ON" : "OFF");
386 goto exit;
387 }
388
389 if (power) {
390 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
391 dac33->supplies);
392 if (ret != 0) {
393 dev_err(codec->dev,
394 "Failed to enable supplies: %d\n", ret);
395 goto exit;
396 }
397
398 if (dac33->power_gpio >= 0)
399 gpio_set_value(dac33->power_gpio, 1);
400
401 dac33->chip_power = 1;
402 } else {
403 dac33_soft_power(codec, 0);
404 if (dac33->power_gpio >= 0)
405 gpio_set_value(dac33->power_gpio, 0);
406
407 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
408 dac33->supplies);
409 if (ret != 0) {
410 dev_err(codec->dev,
411 "Failed to disable supplies: %d\n", ret);
412 goto exit;
413 }
414
415 dac33->chip_power = 0;
416 }
417
418 exit:
419 mutex_unlock(&dac33->mutex);
420 return ret;
421 }
422
423 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
424 struct snd_kcontrol *kcontrol, int event)
425 {
426 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
427
428 switch (event) {
429 case SND_SOC_DAPM_PRE_PMU:
430 if (likely(dac33->substream)) {
431 dac33_calculate_times(dac33->substream);
432 dac33_prepare_chip(dac33->substream);
433 }
434 break;
435 case SND_SOC_DAPM_POST_PMD:
436 dac33_disable_digital(w->codec);
437 break;
438 }
439 return 0;
440 }
441
442 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_value *ucontrol)
444 {
445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
447
448 ucontrol->value.integer.value[0] = dac33->fifo_mode;
449
450 return 0;
451 }
452
453 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_value *ucontrol)
455 {
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
458 int ret = 0;
459
460 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
461 return 0;
462 /* Do not allow changes while stream is running*/
463 if (codec->active)
464 return -EPERM;
465
466 if (ucontrol->value.integer.value[0] < 0 ||
467 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
468 ret = -EINVAL;
469 else
470 dac33->fifo_mode = ucontrol->value.integer.value[0];
471
472 return ret;
473 }
474
475 /* Codec operation modes */
476 static const char *dac33_fifo_mode_texts[] = {
477 "Bypass", "Mode 1", "Mode 7"
478 };
479
480 static const struct soc_enum dac33_fifo_mode_enum =
481 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
482 dac33_fifo_mode_texts);
483
484 /* L/R Line Output Gain */
485 static const char *lr_lineout_gain_texts[] = {
486 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
487 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
488 };
489
490 static const struct soc_enum l_lineout_gain_enum =
491 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
492 ARRAY_SIZE(lr_lineout_gain_texts),
493 lr_lineout_gain_texts);
494
495 static const struct soc_enum r_lineout_gain_enum =
496 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
497 ARRAY_SIZE(lr_lineout_gain_texts),
498 lr_lineout_gain_texts);
499
500 /*
501 * DACL/R digital volume control:
502 * from 0 dB to -63.5 in 0.5 dB steps
503 * Need to be inverted later on:
504 * 0x00 == 0 dB
505 * 0x7f == -63.5 dB
506 */
507 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
508
509 static const struct snd_kcontrol_new dac33_snd_controls[] = {
510 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
511 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
512 0, 0x7f, 1, dac_digivol_tlv),
513 SOC_DOUBLE_R("DAC Digital Playback Switch",
514 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
515 SOC_DOUBLE_R("Line to Line Out Volume",
516 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
517 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
518 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
519 };
520
521 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
522 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
523 dac33_get_fifo_mode, dac33_set_fifo_mode),
524 };
525
526 /* Analog bypass */
527 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
528 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
529
530 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
531 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
532
533 /* LOP L/R invert selection */
534 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
535
536 static const struct soc_enum dac33_left_lom_enum =
537 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
538 ARRAY_SIZE(dac33_lr_lom_texts),
539 dac33_lr_lom_texts);
540
541 static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
542 SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
543
544 static const struct soc_enum dac33_right_lom_enum =
545 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
546 ARRAY_SIZE(dac33_lr_lom_texts),
547 dac33_lr_lom_texts);
548
549 static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
550 SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
551
552 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
553 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
554 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
555
556 SND_SOC_DAPM_INPUT("LINEL"),
557 SND_SOC_DAPM_INPUT("LINER"),
558
559 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
560 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
561
562 /* Analog bypass */
563 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
564 &dac33_dapm_abypassl_control),
565 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
566 &dac33_dapm_abypassr_control),
567
568 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
569 &dac33_dapm_left_lom_control),
570 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
571 &dac33_dapm_right_lom_control),
572 /*
573 * For DAPM path, when only the anlog bypass path is enabled, and the
574 * LOP inverted from the corresponding DAC side.
575 * This is needed, so we can attach the DAC power supply in this case.
576 */
577 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
578 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
579
580 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
581 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
582 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
583 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
584
585 SND_SOC_DAPM_SUPPLY("Left DAC Power",
586 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
587 SND_SOC_DAPM_SUPPLY("Right DAC Power",
588 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
589
590 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
591 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
592 };
593
594 static const struct snd_soc_dapm_route audio_map[] = {
595 /* Analog bypass */
596 {"Analog Left Bypass", "Switch", "LINEL"},
597 {"Analog Right Bypass", "Switch", "LINER"},
598
599 {"Output Left Amplifier", NULL, "DACL"},
600 {"Output Right Amplifier", NULL, "DACR"},
601
602 {"Left Bypass PGA", NULL, "Analog Left Bypass"},
603 {"Right Bypass PGA", NULL, "Analog Right Bypass"},
604
605 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
606 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
607 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
608 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
609
610 {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
611 {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
612
613 {"DACL", NULL, "Left DAC Power"},
614 {"DACR", NULL, "Right DAC Power"},
615
616 {"Left Bypass PGA", NULL, "Left DAC Power"},
617 {"Right Bypass PGA", NULL, "Right DAC Power"},
618
619 /* output */
620 {"LEFT_LO", NULL, "Output Left Amplifier"},
621 {"RIGHT_LO", NULL, "Output Right Amplifier"},
622 };
623
624 static int dac33_add_widgets(struct snd_soc_codec *codec)
625 {
626 struct snd_soc_dapm_context *dapm = &codec->dapm;
627
628 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
629 ARRAY_SIZE(dac33_dapm_widgets));
630 /* set up audio path interconnects */
631 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
632
633 return 0;
634 }
635
636 static int dac33_set_bias_level(struct snd_soc_codec *codec,
637 enum snd_soc_bias_level level)
638 {
639 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
640 int ret;
641
642 switch (level) {
643 case SND_SOC_BIAS_ON:
644 if (!dac33->substream)
645 dac33_soft_power(codec, 1);
646 break;
647 case SND_SOC_BIAS_PREPARE:
648 break;
649 case SND_SOC_BIAS_STANDBY:
650 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
651 /* Coming from OFF, switch on the codec */
652 ret = dac33_hard_power(codec, 1);
653 if (ret != 0)
654 return ret;
655
656 dac33_init_chip(codec);
657 }
658 break;
659 case SND_SOC_BIAS_OFF:
660 /* Do not power off, when the codec is already off */
661 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
662 return 0;
663 ret = dac33_hard_power(codec, 0);
664 if (ret != 0)
665 return ret;
666 break;
667 }
668 codec->dapm.bias_level = level;
669
670 return 0;
671 }
672
673 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
674 {
675 struct snd_soc_codec *codec = dac33->codec;
676 unsigned int delay;
677 unsigned long flags;
678
679 switch (dac33->fifo_mode) {
680 case DAC33_FIFO_MODE1:
681 dac33_write16(codec, DAC33_NSAMPLE_MSB,
682 DAC33_THRREG(dac33->nsample));
683
684 /* Take the timestamps */
685 spin_lock_irqsave(&dac33->lock, flags);
686 dac33->t_stamp2 = ktime_to_us(ktime_get());
687 dac33->t_stamp1 = dac33->t_stamp2;
688 spin_unlock_irqrestore(&dac33->lock, flags);
689
690 dac33_write16(codec, DAC33_PREFILL_MSB,
691 DAC33_THRREG(dac33->alarm_threshold));
692 /* Enable Alarm Threshold IRQ with a delay */
693 delay = SAMPLES_TO_US(dac33->burst_rate,
694 dac33->alarm_threshold) + 1000;
695 usleep_range(delay, delay + 500);
696 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
697 break;
698 case DAC33_FIFO_MODE7:
699 /* Take the timestamp */
700 spin_lock_irqsave(&dac33->lock, flags);
701 dac33->t_stamp1 = ktime_to_us(ktime_get());
702 /* Move back the timestamp with drain time */
703 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
704 spin_unlock_irqrestore(&dac33->lock, flags);
705
706 dac33_write16(codec, DAC33_PREFILL_MSB,
707 DAC33_THRREG(DAC33_MODE7_MARGIN));
708
709 /* Enable Upper Threshold IRQ */
710 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
711 break;
712 default:
713 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
714 dac33->fifo_mode);
715 break;
716 }
717 }
718
719 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
720 {
721 struct snd_soc_codec *codec = dac33->codec;
722 unsigned long flags;
723
724 switch (dac33->fifo_mode) {
725 case DAC33_FIFO_MODE1:
726 /* Take the timestamp */
727 spin_lock_irqsave(&dac33->lock, flags);
728 dac33->t_stamp2 = ktime_to_us(ktime_get());
729 spin_unlock_irqrestore(&dac33->lock, flags);
730
731 dac33_write16(codec, DAC33_NSAMPLE_MSB,
732 DAC33_THRREG(dac33->nsample));
733 break;
734 case DAC33_FIFO_MODE7:
735 /* At the moment we are not using interrupts in mode7 */
736 break;
737 default:
738 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
739 dac33->fifo_mode);
740 break;
741 }
742 }
743
744 static void dac33_work(struct work_struct *work)
745 {
746 struct snd_soc_codec *codec;
747 struct tlv320dac33_priv *dac33;
748 u8 reg;
749
750 dac33 = container_of(work, struct tlv320dac33_priv, work);
751 codec = dac33->codec;
752
753 mutex_lock(&dac33->mutex);
754 switch (dac33->state) {
755 case DAC33_PREFILL:
756 dac33->state = DAC33_PLAYBACK;
757 dac33_prefill_handler(dac33);
758 break;
759 case DAC33_PLAYBACK:
760 dac33_playback_handler(dac33);
761 break;
762 case DAC33_IDLE:
763 break;
764 case DAC33_FLUSH:
765 dac33->state = DAC33_IDLE;
766 /* Mask all interrupts from dac33 */
767 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
768
769 /* flush fifo */
770 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
771 reg |= DAC33_FIFOFLUSH;
772 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
773 break;
774 }
775 mutex_unlock(&dac33->mutex);
776 }
777
778 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
779 {
780 struct snd_soc_codec *codec = dev;
781 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
782 unsigned long flags;
783
784 spin_lock_irqsave(&dac33->lock, flags);
785 dac33->t_stamp1 = ktime_to_us(ktime_get());
786 spin_unlock_irqrestore(&dac33->lock, flags);
787
788 /* Do not schedule the workqueue in Mode7 */
789 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
790 queue_work(dac33->dac33_wq, &dac33->work);
791
792 return IRQ_HANDLED;
793 }
794
795 static void dac33_oscwait(struct snd_soc_codec *codec)
796 {
797 int timeout = 60;
798 u8 reg;
799
800 do {
801 usleep_range(1000, 2000);
802 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
803 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
804 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
805 dev_err(codec->dev,
806 "internal oscillator calibration failed\n");
807 }
808
809 static int dac33_startup(struct snd_pcm_substream *substream,
810 struct snd_soc_dai *dai)
811 {
812 struct snd_soc_pcm_runtime *rtd = substream->private_data;
813 struct snd_soc_codec *codec = rtd->codec;
814 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
815
816 /* Stream started, save the substream pointer */
817 dac33->substream = substream;
818
819 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
820
821 return 0;
822 }
823
824 static void dac33_shutdown(struct snd_pcm_substream *substream,
825 struct snd_soc_dai *dai)
826 {
827 struct snd_soc_pcm_runtime *rtd = substream->private_data;
828 struct snd_soc_codec *codec = rtd->codec;
829 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
830
831 dac33->substream = NULL;
832 }
833
834 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
835 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
836 static int dac33_hw_params(struct snd_pcm_substream *substream,
837 struct snd_pcm_hw_params *params,
838 struct snd_soc_dai *dai)
839 {
840 struct snd_soc_pcm_runtime *rtd = substream->private_data;
841 struct snd_soc_codec *codec = rtd->codec;
842 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
843
844 /* Check parameters for validity */
845 switch (params_rate(params)) {
846 case 44100:
847 case 48000:
848 break;
849 default:
850 dev_err(codec->dev, "unsupported rate %d\n",
851 params_rate(params));
852 return -EINVAL;
853 }
854
855 switch (params_format(params)) {
856 case SNDRV_PCM_FORMAT_S16_LE:
857 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
858 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
859 break;
860 case SNDRV_PCM_FORMAT_S32_LE:
861 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
862 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
863 break;
864 default:
865 dev_err(codec->dev, "unsupported format %d\n",
866 params_format(params));
867 return -EINVAL;
868 }
869
870 return 0;
871 }
872
873 #define CALC_OSCSET(rate, refclk) ( \
874 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
875 #define CALC_RATIOSET(rate, refclk) ( \
876 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
877
878 /*
879 * tlv320dac33 is strict on the sequence of the register writes, if the register
880 * writes happens in different order, than dac33 might end up in unknown state.
881 * Use the known, working sequence of register writes to initialize the dac33.
882 */
883 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
884 {
885 struct snd_soc_pcm_runtime *rtd = substream->private_data;
886 struct snd_soc_codec *codec = rtd->codec;
887 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
888 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
889 u8 aictrl_a, aictrl_b, fifoctrl_a;
890
891 switch (substream->runtime->rate) {
892 case 44100:
893 case 48000:
894 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
895 ratioset = CALC_RATIOSET(substream->runtime->rate,
896 dac33->refclk);
897 break;
898 default:
899 dev_err(codec->dev, "unsupported rate %d\n",
900 substream->runtime->rate);
901 return -EINVAL;
902 }
903
904
905 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
906 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
907 /* Read FIFO control A, and clear FIFO flush bit */
908 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
909 fifoctrl_a &= ~DAC33_FIFOFLUSH;
910
911 fifoctrl_a &= ~DAC33_WIDTH;
912 switch (substream->runtime->format) {
913 case SNDRV_PCM_FORMAT_S16_LE:
914 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
915 fifoctrl_a |= DAC33_WIDTH;
916 break;
917 case SNDRV_PCM_FORMAT_S32_LE:
918 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
919 break;
920 default:
921 dev_err(codec->dev, "unsupported format %d\n",
922 substream->runtime->format);
923 return -EINVAL;
924 }
925
926 mutex_lock(&dac33->mutex);
927
928 if (!dac33->chip_power) {
929 /*
930 * Chip is not powered yet.
931 * Do the init in the dac33_set_bias_level later.
932 */
933 mutex_unlock(&dac33->mutex);
934 return 0;
935 }
936
937 dac33_soft_power(codec, 0);
938 dac33_soft_power(codec, 1);
939
940 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
941 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
942
943 /* Write registers 0x08 and 0x09 (MSB, LSB) */
944 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
945
946 /* calib time: 128 is a nice number ;) */
947 dac33_write(codec, DAC33_CALIB_TIME, 128);
948
949 /* adjustment treshold & step */
950 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
951 DAC33_ADJSTEP(1));
952
953 /* div=4 / gain=1 / div */
954 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
955
956 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
957 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
958 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
959
960 dac33_oscwait(codec);
961
962 if (dac33->fifo_mode) {
963 /* Generic for all FIFO modes */
964 /* 50-51 : ASRC Control registers */
965 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
966 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
967
968 /* Write registers 0x34 and 0x35 (MSB, LSB) */
969 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
970
971 /* Set interrupts to high active */
972 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
973 } else {
974 /* FIFO bypass mode */
975 /* 50-51 : ASRC Control registers */
976 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
977 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
978 }
979
980 /* Interrupt behaviour configuration */
981 switch (dac33->fifo_mode) {
982 case DAC33_FIFO_MODE1:
983 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
984 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
985 break;
986 case DAC33_FIFO_MODE7:
987 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
988 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
989 break;
990 default:
991 /* in FIFO bypass mode, the interrupts are not used */
992 break;
993 }
994
995 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
996
997 switch (dac33->fifo_mode) {
998 case DAC33_FIFO_MODE1:
999 /*
1000 * For mode1:
1001 * Disable the FIFO bypass (Enable the use of FIFO)
1002 * Select nSample mode
1003 * BCLK is only running when data is needed by DAC33
1004 */
1005 fifoctrl_a &= ~DAC33_FBYPAS;
1006 fifoctrl_a &= ~DAC33_FAUTO;
1007 if (dac33->keep_bclk)
1008 aictrl_b |= DAC33_BCLKON;
1009 else
1010 aictrl_b &= ~DAC33_BCLKON;
1011 break;
1012 case DAC33_FIFO_MODE7:
1013 /*
1014 * For mode1:
1015 * Disable the FIFO bypass (Enable the use of FIFO)
1016 * Select Threshold mode
1017 * BCLK is only running when data is needed by DAC33
1018 */
1019 fifoctrl_a &= ~DAC33_FBYPAS;
1020 fifoctrl_a |= DAC33_FAUTO;
1021 if (dac33->keep_bclk)
1022 aictrl_b |= DAC33_BCLKON;
1023 else
1024 aictrl_b &= ~DAC33_BCLKON;
1025 break;
1026 default:
1027 /*
1028 * For FIFO bypass mode:
1029 * Enable the FIFO bypass (Disable the FIFO use)
1030 * Set the BCLK as continuous
1031 */
1032 fifoctrl_a |= DAC33_FBYPAS;
1033 aictrl_b |= DAC33_BCLKON;
1034 break;
1035 }
1036
1037 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1038 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1039 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1040
1041 /*
1042 * BCLK divide ratio
1043 * 0: 1.5
1044 * 1: 1
1045 * 2: 2
1046 * ...
1047 * 254: 254
1048 * 255: 255
1049 */
1050 if (dac33->fifo_mode)
1051 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1052 dac33->burst_bclkdiv);
1053 else
1054 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1055 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1056 else
1057 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
1058
1059 switch (dac33->fifo_mode) {
1060 case DAC33_FIFO_MODE1:
1061 dac33_write16(codec, DAC33_ATHR_MSB,
1062 DAC33_THRREG(dac33->alarm_threshold));
1063 break;
1064 case DAC33_FIFO_MODE7:
1065 /*
1066 * Configure the threshold levels, and leave 10 sample space
1067 * at the bottom, and also at the top of the FIFO
1068 */
1069 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1070 dac33_write16(codec, DAC33_LTHR_MSB,
1071 DAC33_THRREG(DAC33_MODE7_MARGIN));
1072 break;
1073 default:
1074 break;
1075 }
1076
1077 mutex_unlock(&dac33->mutex);
1078
1079 return 0;
1080 }
1081
1082 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1083 {
1084 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1085 struct snd_soc_codec *codec = rtd->codec;
1086 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1087 unsigned int period_size = substream->runtime->period_size;
1088 unsigned int rate = substream->runtime->rate;
1089 unsigned int nsample_limit;
1090
1091 /* In bypass mode we don't need to calculate */
1092 if (!dac33->fifo_mode)
1093 return;
1094
1095 switch (dac33->fifo_mode) {
1096 case DAC33_FIFO_MODE1:
1097 /* Number of samples under i2c latency */
1098 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1099 dac33->mode1_latency);
1100 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1101
1102 if (period_size <= dac33->alarm_threshold)
1103 /*
1104 * Configure nSamaple to number of periods,
1105 * which covers the latency requironment.
1106 */
1107 dac33->nsample = period_size *
1108 ((dac33->alarm_threshold / period_size) +
1109 (dac33->alarm_threshold % period_size ?
1110 1 : 0));
1111 else if (period_size > nsample_limit)
1112 dac33->nsample = nsample_limit;
1113 else
1114 dac33->nsample = period_size;
1115
1116 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1117 dac33->nsample);
1118 dac33->t_stamp1 = 0;
1119 dac33->t_stamp2 = 0;
1120 break;
1121 case DAC33_FIFO_MODE7:
1122 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1123 dac33->burst_rate) + 9;
1124 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1125 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1126 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1127 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1128
1129 dac33->mode7_us_to_lthr =
1130 SAMPLES_TO_US(substream->runtime->rate,
1131 dac33->uthr - DAC33_MODE7_MARGIN + 1);
1132 dac33->t_stamp1 = 0;
1133 break;
1134 default:
1135 break;
1136 }
1137
1138 }
1139
1140 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1141 struct snd_soc_dai *dai)
1142 {
1143 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1144 struct snd_soc_codec *codec = rtd->codec;
1145 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1146 int ret = 0;
1147
1148 switch (cmd) {
1149 case SNDRV_PCM_TRIGGER_START:
1150 case SNDRV_PCM_TRIGGER_RESUME:
1151 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1152 if (dac33->fifo_mode) {
1153 dac33->state = DAC33_PREFILL;
1154 queue_work(dac33->dac33_wq, &dac33->work);
1155 }
1156 break;
1157 case SNDRV_PCM_TRIGGER_STOP:
1158 case SNDRV_PCM_TRIGGER_SUSPEND:
1159 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1160 if (dac33->fifo_mode) {
1161 dac33->state = DAC33_FLUSH;
1162 queue_work(dac33->dac33_wq, &dac33->work);
1163 }
1164 break;
1165 default:
1166 ret = -EINVAL;
1167 }
1168
1169 return ret;
1170 }
1171
1172 static snd_pcm_sframes_t dac33_dai_delay(
1173 struct snd_pcm_substream *substream,
1174 struct snd_soc_dai *dai)
1175 {
1176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1177 struct snd_soc_codec *codec = rtd->codec;
1178 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1179 unsigned long long t0, t1, t_now;
1180 unsigned int time_delta, uthr;
1181 int samples_out, samples_in, samples;
1182 snd_pcm_sframes_t delay = 0;
1183 unsigned long flags;
1184
1185 switch (dac33->fifo_mode) {
1186 case DAC33_FIFO_BYPASS:
1187 break;
1188 case DAC33_FIFO_MODE1:
1189 spin_lock_irqsave(&dac33->lock, flags);
1190 t0 = dac33->t_stamp1;
1191 t1 = dac33->t_stamp2;
1192 spin_unlock_irqrestore(&dac33->lock, flags);
1193 t_now = ktime_to_us(ktime_get());
1194
1195 /* We have not started to fill the FIFO yet, delay is 0 */
1196 if (!t1)
1197 goto out;
1198
1199 if (t0 > t1) {
1200 /*
1201 * Phase 1:
1202 * After Alarm threshold, and before nSample write
1203 */
1204 time_delta = t_now - t0;
1205 samples_out = time_delta ? US_TO_SAMPLES(
1206 substream->runtime->rate,
1207 time_delta) : 0;
1208
1209 if (likely(dac33->alarm_threshold > samples_out))
1210 delay = dac33->alarm_threshold - samples_out;
1211 else
1212 delay = 0;
1213 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1214 /*
1215 * Phase 2:
1216 * After nSample write (during burst operation)
1217 */
1218 time_delta = t_now - t0;
1219 samples_out = time_delta ? US_TO_SAMPLES(
1220 substream->runtime->rate,
1221 time_delta) : 0;
1222
1223 time_delta = t_now - t1;
1224 samples_in = time_delta ? US_TO_SAMPLES(
1225 dac33->burst_rate,
1226 time_delta) : 0;
1227
1228 samples = dac33->alarm_threshold;
1229 samples += (samples_in - samples_out);
1230
1231 if (likely(samples > 0))
1232 delay = samples;
1233 else
1234 delay = 0;
1235 } else {
1236 /*
1237 * Phase 3:
1238 * After burst operation, before next alarm threshold
1239 */
1240 time_delta = t_now - t0;
1241 samples_out = time_delta ? US_TO_SAMPLES(
1242 substream->runtime->rate,
1243 time_delta) : 0;
1244
1245 samples_in = dac33->nsample;
1246 samples = dac33->alarm_threshold;
1247 samples += (samples_in - samples_out);
1248
1249 if (likely(samples > 0))
1250 delay = samples > dac33->fifo_size ?
1251 dac33->fifo_size : samples;
1252 else
1253 delay = 0;
1254 }
1255 break;
1256 case DAC33_FIFO_MODE7:
1257 spin_lock_irqsave(&dac33->lock, flags);
1258 t0 = dac33->t_stamp1;
1259 uthr = dac33->uthr;
1260 spin_unlock_irqrestore(&dac33->lock, flags);
1261 t_now = ktime_to_us(ktime_get());
1262
1263 /* We have not started to fill the FIFO yet, delay is 0 */
1264 if (!t0)
1265 goto out;
1266
1267 if (t_now <= t0) {
1268 /*
1269 * Either the timestamps are messed or equal. Report
1270 * maximum delay
1271 */
1272 delay = uthr;
1273 goto out;
1274 }
1275
1276 time_delta = t_now - t0;
1277 if (time_delta <= dac33->mode7_us_to_lthr) {
1278 /*
1279 * Phase 1:
1280 * After burst (draining phase)
1281 */
1282 samples_out = US_TO_SAMPLES(
1283 substream->runtime->rate,
1284 time_delta);
1285
1286 if (likely(uthr > samples_out))
1287 delay = uthr - samples_out;
1288 else
1289 delay = 0;
1290 } else {
1291 /*
1292 * Phase 2:
1293 * During burst operation
1294 */
1295 time_delta = time_delta - dac33->mode7_us_to_lthr;
1296
1297 samples_out = US_TO_SAMPLES(
1298 substream->runtime->rate,
1299 time_delta);
1300 samples_in = US_TO_SAMPLES(
1301 dac33->burst_rate,
1302 time_delta);
1303 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1304
1305 if (unlikely(delay > uthr))
1306 delay = uthr;
1307 }
1308 break;
1309 default:
1310 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1311 dac33->fifo_mode);
1312 break;
1313 }
1314 out:
1315 return delay;
1316 }
1317
1318 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1319 int clk_id, unsigned int freq, int dir)
1320 {
1321 struct snd_soc_codec *codec = codec_dai->codec;
1322 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1323 u8 ioc_reg, asrcb_reg;
1324
1325 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1326 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1327 switch (clk_id) {
1328 case TLV320DAC33_MCLK:
1329 ioc_reg |= DAC33_REFSEL;
1330 asrcb_reg |= DAC33_SRCREFSEL;
1331 break;
1332 case TLV320DAC33_SLEEPCLK:
1333 ioc_reg &= ~DAC33_REFSEL;
1334 asrcb_reg &= ~DAC33_SRCREFSEL;
1335 break;
1336 default:
1337 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1338 break;
1339 }
1340 dac33->refclk = freq;
1341
1342 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1343 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1344
1345 return 0;
1346 }
1347
1348 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1349 unsigned int fmt)
1350 {
1351 struct snd_soc_codec *codec = codec_dai->codec;
1352 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1353 u8 aictrl_a, aictrl_b;
1354
1355 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1356 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1357 /* set master/slave audio interface */
1358 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1359 case SND_SOC_DAIFMT_CBM_CFM:
1360 /* Codec Master */
1361 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1362 break;
1363 case SND_SOC_DAIFMT_CBS_CFS:
1364 /* Codec Slave */
1365 if (dac33->fifo_mode) {
1366 dev_err(codec->dev, "FIFO mode requires master mode\n");
1367 return -EINVAL;
1368 } else
1369 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1370 break;
1371 default:
1372 return -EINVAL;
1373 }
1374
1375 aictrl_a &= ~DAC33_AFMT_MASK;
1376 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1377 case SND_SOC_DAIFMT_I2S:
1378 aictrl_a |= DAC33_AFMT_I2S;
1379 break;
1380 case SND_SOC_DAIFMT_DSP_A:
1381 aictrl_a |= DAC33_AFMT_DSP;
1382 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1383 aictrl_b |= DAC33_DATA_DELAY(0);
1384 break;
1385 case SND_SOC_DAIFMT_RIGHT_J:
1386 aictrl_a |= DAC33_AFMT_RIGHT_J;
1387 break;
1388 case SND_SOC_DAIFMT_LEFT_J:
1389 aictrl_a |= DAC33_AFMT_LEFT_J;
1390 break;
1391 default:
1392 dev_err(codec->dev, "Unsupported format (%u)\n",
1393 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1394 return -EINVAL;
1395 }
1396
1397 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1398 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1399
1400 return 0;
1401 }
1402
1403 static int dac33_soc_probe(struct snd_soc_codec *codec)
1404 {
1405 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1406 int ret = 0;
1407
1408 codec->control_data = dac33->control_data;
1409 codec->hw_write = (hw_write_t) i2c_master_send;
1410 codec->dapm.idle_bias_off = 1;
1411 dac33->codec = codec;
1412
1413 /* Read the tlv320dac33 ID registers */
1414 ret = dac33_hard_power(codec, 1);
1415 if (ret != 0) {
1416 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1417 goto err_power;
1418 }
1419 ret = dac33_read_id(codec);
1420 dac33_hard_power(codec, 0);
1421
1422 if (ret < 0) {
1423 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1424 ret = -ENODEV;
1425 goto err_power;
1426 }
1427
1428 /* Check if the IRQ number is valid and request it */
1429 if (dac33->irq >= 0) {
1430 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1431 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1432 codec->name, codec);
1433 if (ret < 0) {
1434 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1435 dac33->irq, ret);
1436 dac33->irq = -1;
1437 }
1438 if (dac33->irq != -1) {
1439 /* Setup work queue */
1440 dac33->dac33_wq =
1441 create_singlethread_workqueue("tlv320dac33");
1442 if (dac33->dac33_wq == NULL) {
1443 free_irq(dac33->irq, codec);
1444 return -ENOMEM;
1445 }
1446
1447 INIT_WORK(&dac33->work, dac33_work);
1448 }
1449 }
1450
1451 snd_soc_add_controls(codec, dac33_snd_controls,
1452 ARRAY_SIZE(dac33_snd_controls));
1453 /* Only add the FIFO controls, if we have valid IRQ number */
1454 if (dac33->irq >= 0)
1455 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1456 ARRAY_SIZE(dac33_mode_snd_controls));
1457
1458 dac33_add_widgets(codec);
1459
1460 err_power:
1461 return ret;
1462 }
1463
1464 static int dac33_soc_remove(struct snd_soc_codec *codec)
1465 {
1466 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1467
1468 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1469
1470 if (dac33->irq >= 0) {
1471 free_irq(dac33->irq, dac33->codec);
1472 destroy_workqueue(dac33->dac33_wq);
1473 }
1474 return 0;
1475 }
1476
1477 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1478 {
1479 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1480
1481 return 0;
1482 }
1483
1484 static int dac33_soc_resume(struct snd_soc_codec *codec)
1485 {
1486 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1487
1488 return 0;
1489 }
1490
1491 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1492 .read = dac33_read_reg_cache,
1493 .write = dac33_write_locked,
1494 .set_bias_level = dac33_set_bias_level,
1495 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1496 .reg_word_size = sizeof(u8),
1497 .reg_cache_default = dac33_reg,
1498 .probe = dac33_soc_probe,
1499 .remove = dac33_soc_remove,
1500 .suspend = dac33_soc_suspend,
1501 .resume = dac33_soc_resume,
1502 };
1503
1504 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1505 SNDRV_PCM_RATE_48000)
1506 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1507
1508 static struct snd_soc_dai_ops dac33_dai_ops = {
1509 .startup = dac33_startup,
1510 .shutdown = dac33_shutdown,
1511 .hw_params = dac33_hw_params,
1512 .trigger = dac33_pcm_trigger,
1513 .delay = dac33_dai_delay,
1514 .set_sysclk = dac33_set_dai_sysclk,
1515 .set_fmt = dac33_set_dai_fmt,
1516 };
1517
1518 static struct snd_soc_dai_driver dac33_dai = {
1519 .name = "tlv320dac33-hifi",
1520 .playback = {
1521 .stream_name = "Playback",
1522 .channels_min = 2,
1523 .channels_max = 2,
1524 .rates = DAC33_RATES,
1525 .formats = DAC33_FORMATS,},
1526 .ops = &dac33_dai_ops,
1527 };
1528
1529 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1530 const struct i2c_device_id *id)
1531 {
1532 struct tlv320dac33_platform_data *pdata;
1533 struct tlv320dac33_priv *dac33;
1534 int ret, i;
1535
1536 if (client->dev.platform_data == NULL) {
1537 dev_err(&client->dev, "Platform data not set\n");
1538 return -ENODEV;
1539 }
1540 pdata = client->dev.platform_data;
1541
1542 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1543 if (dac33 == NULL)
1544 return -ENOMEM;
1545
1546 dac33->control_data = client;
1547 mutex_init(&dac33->mutex);
1548 spin_lock_init(&dac33->lock);
1549
1550 i2c_set_clientdata(client, dac33);
1551
1552 dac33->power_gpio = pdata->power_gpio;
1553 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1554 dac33->keep_bclk = pdata->keep_bclk;
1555 dac33->mode1_latency = pdata->mode1_latency;
1556 if (!dac33->mode1_latency)
1557 dac33->mode1_latency = 10000; /* 10ms */
1558 dac33->irq = client->irq;
1559 /* Disable FIFO use by default */
1560 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1561
1562 /* Check if the reset GPIO number is valid and request it */
1563 if (dac33->power_gpio >= 0) {
1564 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1565 if (ret < 0) {
1566 dev_err(&client->dev,
1567 "Failed to request reset GPIO (%d)\n",
1568 dac33->power_gpio);
1569 goto err_gpio;
1570 }
1571 gpio_direction_output(dac33->power_gpio, 0);
1572 }
1573
1574 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1575 dac33->supplies[i].supply = dac33_supply_names[i];
1576
1577 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1578 dac33->supplies);
1579
1580 if (ret != 0) {
1581 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1582 goto err_get;
1583 }
1584
1585 ret = snd_soc_register_codec(&client->dev,
1586 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1587 if (ret < 0)
1588 goto err_register;
1589
1590 return ret;
1591 err_register:
1592 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1593 err_get:
1594 if (dac33->power_gpio >= 0)
1595 gpio_free(dac33->power_gpio);
1596 err_gpio:
1597 kfree(dac33);
1598 return ret;
1599 }
1600
1601 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1602 {
1603 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1604
1605 if (unlikely(dac33->chip_power))
1606 dac33_hard_power(dac33->codec, 0);
1607
1608 if (dac33->power_gpio >= 0)
1609 gpio_free(dac33->power_gpio);
1610
1611 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1612
1613 snd_soc_unregister_codec(&client->dev);
1614 kfree(dac33);
1615
1616 return 0;
1617 }
1618
1619 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1620 {
1621 .name = "tlv320dac33",
1622 .driver_data = 0,
1623 },
1624 { },
1625 };
1626 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
1627
1628 static struct i2c_driver tlv320dac33_i2c_driver = {
1629 .driver = {
1630 .name = "tlv320dac33-codec",
1631 .owner = THIS_MODULE,
1632 },
1633 .probe = dac33_i2c_probe,
1634 .remove = __devexit_p(dac33_i2c_remove),
1635 .id_table = tlv320dac33_i2c_id,
1636 };
1637
1638 static int __init dac33_module_init(void)
1639 {
1640 int r;
1641 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1642 if (r < 0) {
1643 printk(KERN_ERR "DAC33: driver registration failed\n");
1644 return r;
1645 }
1646 return 0;
1647 }
1648 module_init(dac33_module_init);
1649
1650 static void __exit dac33_module_exit(void)
1651 {
1652 i2c_del_driver(&tlv320dac33_i2c_driver);
1653 }
1654 module_exit(dac33_module_exit);
1655
1656
1657 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1658 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1659 MODULE_LICENSE("GPL");
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