arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/sched.h>
  20
  21 #include <asm/div64.h>
  22 #include <asm/mach/irq.h>
  23 #include <asm/mach/time.h>
  24 #include <asm/sched_clock.h>
  25 #include <mach/regs-ost.h>
  26
  27 /*
  28  * This is PXA's sched_clock implementation. This has a resolution
  29  * of at least 308 ns and a maximum value of 208 days.
  30  *
  31  * The return value is guaranteed to be monotonic in that range as
  32  * long as there is always less than 582 seconds between successive
  33  * calls to sched_clock() which should always be the case in practice.
  34  */
  35 static DEFINE_CLOCK_DATA(cd);
  36
  37 unsigned long long notrace sched_clock(void)
  38 {
  39         u32 cyc = OSCR;
  40         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  41 }
  42
  43 static void notrace pxa_update_sched_clock(void)
  44 {
  45         u32 cyc = OSCR;
  46         update_sched_clock(&cd, cyc, (u32)~0);
  47 }
  48
  49
  50 #define MIN_OSCR_DELTA 16
  51
  52 static irqreturn_t
  53 pxa_ost0_interrupt(int irq, void *dev_id)
  54 {
  55         struct clock_event_device *c = dev_id;
  56
  57         /* Disarm the compare/match, signal the event. */
  58         OIER &= ~OIER_E0;
  59         OSSR = OSSR_M0;
  60         c->event_handler(c);
  61
  62         return IRQ_HANDLED;
  63 }
  64
  65 static int
  66 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
  67 {
  68         unsigned long next, oscr;
  69
  70         OIER |= OIER_E0;
  71         next = OSCR + delta;
  72         OSMR0 = next;
  73         oscr = OSCR;
  74
  75         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  76 }
  77
  78 static void
  79 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  80 {
  81         switch (mode) {
  82         case CLOCK_EVT_MODE_ONESHOT:
  83                 OIER &= ~OIER_E0;
  84                 OSSR = OSSR_M0;
  85                 break;
  86
  87         case CLOCK_EVT_MODE_UNUSED:
  88         case CLOCK_EVT_MODE_SHUTDOWN:
  89                 /* initializing, released, or preparing for suspend */
  90                 OIER &= ~OIER_E0;
  91                 OSSR = OSSR_M0;
  92                 break;
  93
  94         case CLOCK_EVT_MODE_RESUME:
  95         case CLOCK_EVT_MODE_PERIODIC:
  96                 break;
  97         }
  98 }
  99
 100 static struct clock_event_device ckevt_pxa_osmr0 = {
 101         .name           = "osmr0",
 102         .features       = CLOCK_EVT_FEAT_ONESHOT,
 103         .rating         = 200,
 104         .set_next_event = pxa_osmr0_set_next_event,
 105         .set_mode       = pxa_osmr0_set_mode,
 106 };
 107
 108 static struct irqaction pxa_ost0_irq = {
 109         .name           = "ost0",
 110         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 111         .handler        = pxa_ost0_interrupt,
 112         .dev_id         = &ckevt_pxa_osmr0,
 113 };
 114
 115 static void __init pxa_timer_init(void)
 116 {
 117         unsigned long clock_tick_rate = get_clock_tick_rate();
 118
 119         OIER = 0;
 120         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 121
 122         init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
 123
 124         clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
 125         ckevt_pxa_osmr0.max_delta_ns =
 126                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 127         ckevt_pxa_osmr0.min_delta_ns =
 128                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
 129         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 130
 131         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 132
 133         clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
 134                 clocksource_mmio_readl_up);
 135         clockevents_register_device(&ckevt_pxa_osmr0);
 136 }
 137
 138 #ifdef CONFIG_PM
 139 static unsigned long osmr[4], oier, oscr;
 140
 141 static void pxa_timer_suspend(void)
 142 {
 143         osmr[0] = OSMR0;
 144         osmr[1] = OSMR1;
 145         osmr[2] = OSMR2;
 146         osmr[3] = OSMR3;
 147         oier = OIER;
 148         oscr = OSCR;
 149 }
 150
 151 static void pxa_timer_resume(void)
 152 {
 153         /*
 154          * Ensure that we have at least MIN_OSCR_DELTA between match
 155          * register 0 and the OSCR, to guarantee that we will receive
 156          * the one-shot timer interrupt.  We adjust OSMR0 in preference
 157          * to OSCR to guarantee that OSCR is monotonically incrementing.
 158          */
 159         if (osmr[0] - oscr < MIN_OSCR_DELTA)
 160                 osmr[0] += MIN_OSCR_DELTA;
 161
 162         OSMR0 = osmr[0];
 163         OSMR1 = osmr[1];
 164         OSMR2 = osmr[2];
 165         OSMR3 = osmr[3];
 166         OIER = oier;
 167         OSCR = oscr;
 168 }
 169 #else
 170 #define pxa_timer_suspend NULL
 171 #define pxa_timer_resume NULL
 172 #endif
 173
 174 struct sys_timer pxa_timer = {
 175         .init           = pxa_timer_init,
 176         .suspend        = pxa_timer_suspend,
 177         .resume         = pxa_timer_resume,
 178 };