arch/arm/mach-s3c2440/s3c2442.c

   1 /* linux/arch/arm/mach-s3c2442/s3c2442.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C2442 core and lock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/errno.h>
  29 #include <linux/err.h>
  30 #include <linux/device.h>
  31 #include <linux/sysdev.h>
  32 #include <linux/syscore_ops.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ioport.h>
  35 #include <linux/mutex.h>
  36 #include <linux/gpio.h>
  37 #include <linux/clk.h>
  38 #include <linux/io.h>
  39
  40 #include <mach/hardware.h>
  41 #include <linux/atomic.h>
  42 #include <asm/irq.h>
  43
  44 #include <mach/regs-clock.h>
  45
  46 #include <plat/clock.h>
  47 #include <plat/cpu.h>
  48 #include <plat/s3c244x.h>
  49 #include <plat/pm.h>
  50
  51 #include <plat/gpio-core.h>
  52 #include <plat/gpio-cfg.h>
  53 #include <plat/gpio-cfg-helpers.h>
  54
  55 /* S3C2442 extended clock support */
  56
  57 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
  58                                               unsigned long rate)
  59 {
  60         unsigned long parent_rate = clk_get_rate(clk->parent);
  61         int div;
  62
  63         if (rate > parent_rate)
  64                 return parent_rate;
  65
  66         div = parent_rate / rate;
  67
  68         if (div == 3)
  69                 return parent_rate / 3;
  70
  71         /* note, we remove the +/- 1 calculations for the divisor */
  72
  73         div /= 2;
  74
  75         if (div < 1)
  76                 div = 1;
  77         else if (div > 16)
  78                 div = 16;
  79
  80         return parent_rate / (div * 2);
  81 }
  82
  83 static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
  84 {
  85         unsigned long parent_rate = clk_get_rate(clk->parent);
  86         unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
  87
  88         rate = s3c2442_camif_upll_round(clk, rate);
  89
  90         camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
  91
  92         if (rate == parent_rate) {
  93                 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
  94         } else if ((parent_rate / rate) == 3) {
  95                 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  96                 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
  97         } else {
  98                 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
  99                 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
 100                 camdivn |= (((parent_rate / rate) / 2) - 1);
 101         }
 102
 103         __raw_writel(camdivn, S3C2440_CAMDIVN);
 104
 105         return 0;
 106 }
 107
 108 /* Extra S3C2442 clocks */
 109
 110 static struct clk s3c2442_clk_cam = {
 111         .name           = "camif",
 112         .id             = -1,
 113         .enable         = s3c2410_clkcon_enable,
 114         .ctrlbit        = S3C2440_CLKCON_CAMERA,
 115 };
 116
 117 static struct clk s3c2442_clk_cam_upll = {
 118         .name           = "camif-upll",
 119         .id             = -1,
 120         .ops            = &(struct clk_ops) {
 121                 .set_rate       = s3c2442_camif_upll_setrate,
 122                 .round_rate     = s3c2442_camif_upll_round,
 123         },
 124 };
 125
 126 static int s3c2442_clk_add(struct sys_device *sysdev)
 127 {
 128         struct clk *clock_upll;
 129         struct clk *clock_h;
 130         struct clk *clock_p;
 131
 132         clock_p = clk_get(NULL, "pclk");
 133         clock_h = clk_get(NULL, "hclk");
 134         clock_upll = clk_get(NULL, "upll");
 135
 136         if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
 137                 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
 138                 return -EINVAL;
 139         }
 140
 141         s3c2442_clk_cam.parent = clock_h;
 142         s3c2442_clk_cam_upll.parent = clock_upll;
 143
 144         s3c24xx_register_clock(&s3c2442_clk_cam);
 145         s3c24xx_register_clock(&s3c2442_clk_cam_upll);
 146
 147         clk_disable(&s3c2442_clk_cam);
 148
 149         return 0;
 150 }
 151
 152 static struct sysdev_driver s3c2442_clk_driver = {
 153         .add    = s3c2442_clk_add,
 154 };
 155
 156 static __init int s3c2442_clk_init(void)
 157 {
 158         return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
 159 }
 160
 161 arch_initcall(s3c2442_clk_init);
 162
 163
 164 static struct sys_device s3c2442_sysdev = {
 165         .cls            = &s3c2442_sysclass,
 166 };
 167
 168 int __init s3c2442_init(void)
 169 {
 170         printk("S3C2442: Initialising architecture\n");
 171
 172         register_syscore_ops(&s3c2410_pm_syscore_ops);
 173         register_syscore_ops(&s3c244x_pm_syscore_ops);
 174         register_syscore_ops(&s3c24xx_irq_syscore_ops);
 175
 176         return sysdev_register(&s3c2442_sysdev);
 177 }
 178
 179 void __init s3c2442_map_io(void)
 180 {
 181         s3c244x_map_io();
 182
 183         s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
 184         s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
 185 }