arch/arm/plat-iop/time.c

   1 /*
   2  * arch/arm/plat-iop/time.c
   3  *
   4  * Timer code for IOP32x and IOP33x based systems
   5  *
   6  * Author: Deepak Saxena <dsaxena@mvista.com>
   7  *
   8  * Copyright 2002-2003 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/time.h>
  19 #include <linux/init.h>
  20 #include <linux/timex.h>
  21 #include <linux/sched.h>
  22 #include <linux/io.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <mach/hardware.h>
  26 #include <asm/irq.h>
  27 #include <asm/sched_clock.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/mach/irq.h>
  30 #include <asm/mach/time.h>
  31 #include <mach/time.h>
  32
  33 /*
  34  * Minimum clocksource/clockevent timer range in seconds
  35  */
  36 #define IOP_MIN_RANGE 4
  37
  38 /*
  39  * IOP clocksource (free-running timer 1).
  40  */
  41 static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
  42 {
  43         return 0xffffffffu - read_tcr1();
  44 }
  45
  46 static struct clocksource iop_clocksource = {
  47         .name           = "iop_timer1",
  48         .rating         = 300,
  49         .read           = iop_clocksource_read,
  50         .mask           = CLOCKSOURCE_MASK(32),
  51         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  52 };
  53
  54 static DEFINE_CLOCK_DATA(cd);
  55
  56 /*
  57  * IOP sched_clock() implementation via its clocksource.
  58  */
  59 unsigned long long notrace sched_clock(void)
  60 {
  61         u32 cyc = 0xffffffffu - read_tcr1();
  62         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  63 }
  64
  65 static void notrace iop_update_sched_clock(void)
  66 {
  67         u32 cyc = 0xffffffffu - read_tcr1();
  68         update_sched_clock(&cd, cyc, (u32)~0);
  69 }
  70
  71 /*
  72  * IOP clockevents (interrupting timer 0).
  73  */
  74 static int iop_set_next_event(unsigned long delta,
  75                               struct clock_event_device *unused)
  76 {
  77         u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
  78
  79         BUG_ON(delta == 0);
  80         write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
  81         write_tcr0(delta);
  82         write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
  83
  84         return 0;
  85 }
  86
  87 static unsigned long ticks_per_jiffy;
  88
  89 static void iop_set_mode(enum clock_event_mode mode,
  90                          struct clock_event_device *unused)
  91 {
  92         u32 tmr = read_tmr0();
  93
  94         switch (mode) {
  95         case CLOCK_EVT_MODE_PERIODIC:
  96                 write_tmr0(tmr & ~IOP_TMR_EN);
  97                 write_tcr0(ticks_per_jiffy - 1);
  98                 write_trr0(ticks_per_jiffy - 1);
  99                 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
 100                 break;
 101         case CLOCK_EVT_MODE_ONESHOT:
 102                 /* ->set_next_event sets period and enables timer */
 103                 tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
 104                 break;
 105         case CLOCK_EVT_MODE_RESUME:
 106                 tmr |= IOP_TMR_EN;
 107                 break;
 108         case CLOCK_EVT_MODE_SHUTDOWN:
 109         case CLOCK_EVT_MODE_UNUSED:
 110         default:
 111                 tmr &= ~IOP_TMR_EN;
 112                 break;
 113         }
 114
 115         write_tmr0(tmr);
 116 }
 117
 118 static struct clock_event_device iop_clockevent = {
 119         .name           = "iop_timer0",
 120         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 121         .rating         = 300,
 122         .set_next_event = iop_set_next_event,
 123         .set_mode       = iop_set_mode,
 124 };
 125
 126 static irqreturn_t
 127 iop_timer_interrupt(int irq, void *dev_id)
 128 {
 129         struct clock_event_device *evt = dev_id;
 130
 131         write_tisr(1);
 132         evt->event_handler(evt);
 133         return IRQ_HANDLED;
 134 }
 135
 136 static struct irqaction iop_timer_irq = {
 137         .name           = "IOP Timer Tick",
 138         .handler        = iop_timer_interrupt,
 139         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 140         .dev_id         = &iop_clockevent,
 141 };
 142
 143 static unsigned long iop_tick_rate;
 144 unsigned long get_iop_tick_rate(void)
 145 {
 146         return iop_tick_rate;
 147 }
 148 EXPORT_SYMBOL(get_iop_tick_rate);
 149
 150 void __init iop_init_time(unsigned long tick_rate)
 151 {
 152         u32 timer_ctl;
 153
 154         init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);
 155
 156         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
 157         iop_tick_rate = tick_rate;
 158
 159         timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
 160                         IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
 161
 162         /*
 163          * Set up interrupting clockevent timer 0.
 164          */
 165         write_tmr0(timer_ctl & ~IOP_TMR_EN);
 166         write_tisr(1);
 167         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
 168         clockevents_calc_mult_shift(&iop_clockevent,
 169                                     tick_rate, IOP_MIN_RANGE);
 170         iop_clockevent.max_delta_ns =
 171                 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
 172         iop_clockevent.min_delta_ns =
 173                 clockevent_delta2ns(0xf, &iop_clockevent);
 174         iop_clockevent.cpumask = cpumask_of(0);
 175         clockevents_register_device(&iop_clockevent);
 176
 177         /*
 178          * Set up free-running clocksource timer 1.
 179          */
 180         write_trr1(0xffffffff);
 181         write_tcr1(0xffffffff);
 182         write_tmr1(timer_ctl);
 183         clocksource_register_hz(&iop_clocksource, tick_rate);
 184 }