[MIPS] Fix another trap decoding issue
[linux-2.6/linux-mips/linux-dm7025.git] / include / asm-x86 / io_32.h
blob509045f5fda29ecc4b4216ff0e2d0825695f34d9
1 #ifndef _ASM_IO_H
2 #define _ASM_IO_H
4 #include <linux/string.h>
5 #include <linux/compiler.h>
7 /*
8 * This file contains the definitions for the x86 IO instructions
9 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
10 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
11 * versions of the single-IO instructions (inb_p/inw_p/..).
13 * This file is not meant to be obfuscating: it's just complicated
14 * to (a) handle it all in a way that makes gcc able to optimize it
15 * as well as possible and (b) trying to avoid writing the same thing
16 * over and over again with slight variations and possibly making a
17 * mistake somewhere.
21 * Thanks to James van Artsdalen for a better timing-fix than
22 * the two short jumps: using outb's to a nonexistent port seems
23 * to guarantee better timings even on fast machines.
25 * On the other hand, I'd like to be sure of a non-existent port:
26 * I feel a bit unsafe about using 0x80 (should be safe, though)
28 * Linus
32 * Bit simplified and optimized by Jan Hubicka
33 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
35 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
36 * isa_read[wl] and isa_write[wl] fixed
37 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
40 #define IO_SPACE_LIMIT 0xffff
42 #define XQUAD_PORTIO_BASE 0xfe400000
43 #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
45 #ifdef __KERNEL__
47 #include <asm-generic/iomap.h>
49 #include <linux/vmalloc.h>
52 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
53 * access
55 #define xlate_dev_mem_ptr(p) __va(p)
58 * Convert a virtual cached pointer to an uncached pointer
60 #define xlate_dev_kmem_ptr(p) p
62 /**
63 * virt_to_phys - map virtual addresses to physical
64 * @address: address to remap
66 * The returned physical address is the physical (CPU) mapping for
67 * the memory address given. It is only valid to use this function on
68 * addresses directly mapped or allocated via kmalloc.
70 * This function does not give bus mappings for DMA transfers. In
71 * almost all conceivable cases a device driver should not be using
72 * this function
75 static inline unsigned long virt_to_phys(volatile void *address)
77 return __pa(address);
80 /**
81 * phys_to_virt - map physical address to virtual
82 * @address: address to remap
84 * The returned virtual address is a current CPU mapping for
85 * the memory address given. It is only valid to use this function on
86 * addresses that have a kernel mapping
88 * This function does not handle bus mappings for DMA transfers. In
89 * almost all conceivable cases a device driver should not be using
90 * this function
93 static inline void *phys_to_virt(unsigned long address)
95 return __va(address);
99 * Change "struct page" to physical address.
101 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
104 * ioremap - map bus memory into CPU space
105 * @offset: bus address of the memory
106 * @size: size of the resource to map
108 * ioremap performs a platform specific sequence of operations to
109 * make bus memory CPU accessible via the readb/readw/readl/writeb/
110 * writew/writel functions and the other mmio helpers. The returned
111 * address is not guaranteed to be usable directly as a virtual
112 * address.
114 * If the area you are trying to map is a PCI BAR you should have a
115 * look at pci_iomap().
117 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
118 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
121 * The default ioremap() behavior is non-cached:
123 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
125 return ioremap_nocache(offset, size);
128 extern void iounmap(volatile void __iomem *addr);
131 * early_ioremap() and early_iounmap() are for temporary early boot-time
132 * mappings, before the real ioremap() is functional.
133 * A boot-time mapping is currently limited to at most 16 pages.
135 extern void early_ioremap_init(void);
136 extern void early_ioremap_clear(void);
137 extern void early_ioremap_reset(void);
138 extern void *early_ioremap(unsigned long offset, unsigned long size);
139 extern void early_iounmap(void *addr, unsigned long size);
140 extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
142 /* Use early IO mappings for DMI because it's initialized early */
143 #define dmi_ioremap early_ioremap
144 #define dmi_iounmap early_iounmap
145 #define dmi_alloc alloc_bootmem
148 * ISA I/O bus memory addresses are 1:1 with the physical address.
150 #define isa_virt_to_bus virt_to_phys
151 #define isa_page_to_bus page_to_phys
152 #define isa_bus_to_virt phys_to_virt
155 * However PCI ones are not necessarily 1:1 and therefore these interfaces
156 * are forbidden in portable PCI drivers.
158 * Allow them on x86 for legacy drivers, though.
160 #define virt_to_bus virt_to_phys
161 #define bus_to_virt phys_to_virt
164 * readX/writeX() are used to access memory mapped devices. On some
165 * architectures the memory mapped IO stuff needs to be accessed
166 * differently. On the x86 architecture, we just read/write the
167 * memory location directly.
170 static inline unsigned char readb(const volatile void __iomem *addr)
172 return *(volatile unsigned char __force *)addr;
175 static inline unsigned short readw(const volatile void __iomem *addr)
177 return *(volatile unsigned short __force *)addr;
180 static inline unsigned int readl(const volatile void __iomem *addr)
182 return *(volatile unsigned int __force *) addr;
185 #define readb_relaxed(addr) readb(addr)
186 #define readw_relaxed(addr) readw(addr)
187 #define readl_relaxed(addr) readl(addr)
188 #define __raw_readb readb
189 #define __raw_readw readw
190 #define __raw_readl readl
192 static inline void writeb(unsigned char b, volatile void __iomem *addr)
194 *(volatile unsigned char __force *)addr = b;
197 static inline void writew(unsigned short b, volatile void __iomem *addr)
199 *(volatile unsigned short __force *)addr = b;
202 static inline void writel(unsigned int b, volatile void __iomem *addr)
204 *(volatile unsigned int __force *)addr = b;
206 #define __raw_writeb writeb
207 #define __raw_writew writew
208 #define __raw_writel writel
210 #define mmiowb()
212 static inline void
213 memset_io(volatile void __iomem *addr, unsigned char val, int count)
215 memset((void __force *)addr, val, count);
218 static inline void
219 memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
221 __memcpy(dst, (const void __force *)src, count);
224 static inline void
225 memcpy_toio(volatile void __iomem *dst, const void *src, int count)
227 __memcpy((void __force *)dst, src, count);
231 * ISA space is 'always mapped' on a typical x86 system, no need to
232 * explicitly ioremap() it. The fact that the ISA IO space is mapped
233 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
234 * are physical addresses. The following constant pointer can be
235 * used as the IO-area pointer (it can be iounmapped as well, so the
236 * analogy with PCI is quite large):
238 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
241 * Cache management
243 * This needed for two cases
244 * 1. Out of order aware processors
245 * 2. Accidentally out of order processors (PPro errata #51)
248 #if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
250 static inline void flush_write_buffers(void)
252 asm volatile("lock; addl $0,0(%%esp)": : :"memory");
255 #else
257 #define flush_write_buffers() do { } while (0)
259 #endif
261 #endif /* __KERNEL__ */
263 extern void native_io_delay(void);
265 extern int io_delay_type;
266 extern void io_delay_init(void);
268 #if defined(CONFIG_PARAVIRT)
269 #include <asm/paravirt.h>
270 #else
272 static inline void slow_down_io(void)
274 native_io_delay();
275 #ifdef REALLY_SLOW_IO
276 native_io_delay();
277 native_io_delay();
278 native_io_delay();
279 #endif
282 #endif
284 #define __BUILDIO(bwl, bw, type) \
285 static inline void out##bwl(unsigned type value, int port) \
287 out##bwl##_local(value, port); \
290 static inline unsigned type in##bwl(int port) \
292 return in##bwl##_local(port); \
295 #define BUILDIO(bwl, bw, type) \
296 static inline void out##bwl##_local(unsigned type value, int port) \
298 asm volatile("out" #bwl " %" #bw "0, %w1" \
299 : : "a"(value), "Nd"(port)); \
302 static inline unsigned type in##bwl##_local(int port) \
304 unsigned type value; \
305 asm volatile("in" #bwl " %w1, %" #bw "0" \
306 : "=a"(value) : "Nd"(port)); \
307 return value; \
310 static inline void out##bwl##_local_p(unsigned type value, int port) \
312 out##bwl##_local(value, port); \
313 slow_down_io(); \
316 static inline unsigned type in##bwl##_local_p(int port) \
318 unsigned type value = in##bwl##_local(port); \
319 slow_down_io(); \
320 return value; \
323 __BUILDIO(bwl, bw, type) \
325 static inline void out##bwl##_p(unsigned type value, int port) \
327 out##bwl(value, port); \
328 slow_down_io(); \
331 static inline unsigned type in##bwl##_p(int port) \
333 unsigned type value = in##bwl(port); \
334 slow_down_io(); \
335 return value; \
338 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
340 asm volatile("rep; outs" #bwl \
341 : "+S"(addr), "+c"(count) : "d"(port)); \
344 static inline void ins##bwl(int port, void *addr, unsigned long count) \
346 asm volatile("rep; ins" #bwl \
347 : "+D"(addr), "+c"(count) : "d"(port)); \
350 BUILDIO(b, b, char)
351 BUILDIO(w, w, short)
352 BUILDIO(l, , int)
354 #endif