include/asm-s390/pgtable.h

   1 /*
   2  *  include/asm-s390/pgtable.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Hartmut Penner (hp@de.ibm.com)
   7  *               Ulrich Weigand (weigand@de.ibm.com)
   8  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   9  *
  10  *  Derived from "include/asm-i386/pgtable.h"
  11  */
  12
  13 #ifndef _ASM_S390_PGTABLE_H
  14 #define _ASM_S390_PGTABLE_H
  15
  16 /*
  17  * The Linux memory management assumes a three-level page table setup. For
  18  * s390 31 bit we "fold" the mid level into the top-level page table, so
  19  * that we physically have the same two-level page table as the s390 mmu
  20  * expects in 31 bit mode. For s390 64 bit we use three of the five levels
  21  * the hardware provides (region first and region second tables are not
  22  * used).
  23  *
  24  * The "pgd_xxx()" functions are trivial for a folded two-level
  25  * setup: the pgd is never bad, and a pmd always exists (as it's folded
  26  * into the pgd entry)
  27  *
  28  * This file contains the functions and defines necessary to modify and use
  29  * the S390 page table tree.
  30  */
  31 #ifndef __ASSEMBLY__
  32 #include <linux/mm_types.h>
  33 #include <asm/bug.h>
  34 #include <asm/processor.h>
  35
  36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
  37 extern void paging_init(void);
  38 extern void vmem_map_init(void);
  39
  40 /*
  41  * The S390 doesn't have any external MMU info: the kernel page
  42  * tables contain all the necessary information.
  43  */
  44 #define update_mmu_cache(vma, address, pte)     do { } while (0)
  45
  46 /*
  47  * ZERO_PAGE is a global shared page that is always zero: used
  48  * for zero-mapped memory areas etc..
  49  */
  50 extern char empty_zero_page[PAGE_SIZE];
  51 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  52 #endif /* !__ASSEMBLY__ */
  53
  54 /*
  55  * PMD_SHIFT determines the size of the area a second-level page
  56  * table can map
  57  * PGDIR_SHIFT determines what a third-level page table entry can map
  58  */
  59 #ifndef __s390x__
  60 # define PMD_SHIFT      20
  61 # define PUD_SHIFT      20
  62 # define PGDIR_SHIFT    20
  63 #else /* __s390x__ */
  64 # define PMD_SHIFT      20
  65 # define PUD_SHIFT      31
  66 # define PGDIR_SHIFT    42
  67 #endif /* __s390x__ */
  68
  69 #define PMD_SIZE        (1UL << PMD_SHIFT)
  70 #define PMD_MASK        (~(PMD_SIZE-1))
  71 #define PUD_SIZE        (1UL << PUD_SHIFT)
  72 #define PUD_MASK        (~(PUD_SIZE-1))
  73 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  74 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  75
  76 /*
  77  * entries per page directory level: the S390 is two-level, so
  78  * we don't really have any PMD directory physically.
  79  * for S390 segment-table entries are combined to one PGD
  80  * that leads to 1024 pte per pgd
  81  */
  82 #define PTRS_PER_PTE    256
  83 #ifndef __s390x__
  84 #define PTRS_PER_PMD    1
  85 #define PTRS_PER_PUD    1
  86 #else /* __s390x__ */
  87 #define PTRS_PER_PMD    2048
  88 #define PTRS_PER_PUD    2048
  89 #endif /* __s390x__ */
  90 #define PTRS_PER_PGD    2048
  91
  92 #define FIRST_USER_ADDRESS  0
  93
  94 #define pte_ERROR(e) \
  95         printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
  96 #define pmd_ERROR(e) \
  97         printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
  98 #define pud_ERROR(e) \
  99         printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
 100 #define pgd_ERROR(e) \
 101         printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
 102
 103 #ifndef __ASSEMBLY__
 104 /*
 105  * The vmalloc area will always be on the topmost area of the kernel
 106  * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
 107  * which should be enough for any sane case.
 108  * By putting vmalloc at the top, we maximise the gap between physical
 109  * memory and vmalloc to catch misplaced memory accesses. As a side
 110  * effect, this also makes sure that 64 bit module code cannot be used
 111  * as system call address.
 112  */
 113 #ifndef __s390x__
 114 #define VMALLOC_START   0x78000000UL
 115 #define VMALLOC_END     0x7e000000UL
 116 #define VMEM_MAP_END    0x80000000UL
 117 #else /* __s390x__ */
 118 #define VMALLOC_START   0x3e000000000UL
 119 #define VMALLOC_END     0x3e040000000UL
 120 #define VMEM_MAP_END    0x40000000000UL
 121 #endif /* __s390x__ */
 122
 123 /*
 124  * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
 125  * mapping. This needs to be calculated at compile time since the size of the
 126  * VMEM_MAP is static but the size of struct page can change.
 127  */
 128 #define VMEM_MAX_PAGES  ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
 129 #define VMEM_MAX_PFN    min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
 130 #define VMEM_MAX_PHYS   ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
 131 #define VMEM_MAP        ((struct page *) VMALLOC_END)
 132
 133 /*
 134  * A 31 bit pagetable entry of S390 has following format:
 135  *  |   PFRA          |    |  OS  |
 136  * 0                   0IP0
 137  * 00000000001111111111222222222233
 138  * 01234567890123456789012345678901
 139  *
 140  * I Page-Invalid Bit:    Page is not available for address-translation
 141  * P Page-Protection Bit: Store access not possible for page
 142  *
 143  * A 31 bit segmenttable entry of S390 has following format:
 144  *  |   P-table origin      |  |PTL
 145  * 0                         IC
 146  * 00000000001111111111222222222233
 147  * 01234567890123456789012345678901
 148  *
 149  * I Segment-Invalid Bit:    Segment is not available for address-translation
 150  * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 151  * PTL Page-Table-Length:    Page-table length (PTL+1*16 entries -> up to 256)
 152  *
 153  * The 31 bit segmenttable origin of S390 has following format:
 154  *
 155  *  |S-table origin   |     | STL |
 156  * X                   **GPS
 157  * 00000000001111111111222222222233
 158  * 01234567890123456789012345678901
 159  *
 160  * X Space-Switch event:
 161  * G Segment-Invalid Bit:     *
 162  * P Private-Space Bit:       Segment is not private (PoP 3-30)
 163  * S Storage-Alteration:
 164  * STL Segment-Table-Length:  Segment-table length (STL+1*16 entries -> up to 2048)
 165  *
 166  * A 64 bit pagetable entry of S390 has following format:
 167  * |                     PFRA                         |0IP0|  OS  |
 168  * 0000000000111111111122222222223333333333444444444455555555556666
 169  * 0123456789012345678901234567890123456789012345678901234567890123
 170  *
 171  * I Page-Invalid Bit:    Page is not available for address-translation
 172  * P Page-Protection Bit: Store access not possible for page
 173  *
 174  * A 64 bit segmenttable entry of S390 has following format:
 175  * |        P-table origin                              |      TT
 176  * 0000000000111111111122222222223333333333444444444455555555556666
 177  * 0123456789012345678901234567890123456789012345678901234567890123
 178  *
 179  * I Segment-Invalid Bit:    Segment is not available for address-translation
 180  * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 181  * P Page-Protection Bit: Store access not possible for page
 182  * TT Type 00
 183  *
 184  * A 64 bit region table entry of S390 has following format:
 185  * |        S-table origin                             |   TF  TTTL
 186  * 0000000000111111111122222222223333333333444444444455555555556666
 187  * 0123456789012345678901234567890123456789012345678901234567890123
 188  *
 189  * I Segment-Invalid Bit:    Segment is not available for address-translation
 190  * TT Type 01
 191  * TF
 192  * TL Table length
 193  *
 194  * The 64 bit regiontable origin of S390 has following format:
 195  * |      region table origon                          |       DTTL
 196  * 0000000000111111111122222222223333333333444444444455555555556666
 197  * 0123456789012345678901234567890123456789012345678901234567890123
 198  *
 199  * X Space-Switch event:
 200  * G Segment-Invalid Bit:
 201  * P Private-Space Bit:
 202  * S Storage-Alteration:
 203  * R Real space
 204  * TL Table-Length:
 205  *
 206  * A storage key has the following format:
 207  * | ACC |F|R|C|0|
 208  *  0   3 4 5 6 7
 209  * ACC: access key
 210  * F  : fetch protection bit
 211  * R  : referenced bit
 212  * C  : changed bit
 213  */
 214
 215 /* Hardware bits in the page table entry */
 216 #define _PAGE_RO        0x200           /* HW read-only bit  */
 217 #define _PAGE_INVALID   0x400           /* HW invalid bit    */
 218
 219 /* Software bits in the page table entry */
 220 #define _PAGE_SWT       0x001           /* SW pte type bit t */
 221 #define _PAGE_SWX       0x002           /* SW pte type bit x */
 222
 223 /* Six different types of pages. */
 224 #define _PAGE_TYPE_EMPTY        0x400
 225 #define _PAGE_TYPE_NONE         0x401
 226 #define _PAGE_TYPE_SWAP         0x403
 227 #define _PAGE_TYPE_FILE         0x601   /* bit 0x002 is used for offset !! */
 228 #define _PAGE_TYPE_RO           0x200
 229 #define _PAGE_TYPE_RW           0x000
 230 #define _PAGE_TYPE_EX_RO        0x202
 231 #define _PAGE_TYPE_EX_RW        0x002
 232
 233 /*
 234  * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
 235  * pte_none and pte_file to find out the pte type WITHOUT holding the page
 236  * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
 237  * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
 238  * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
 239  * This change is done while holding the lock, but the intermediate step
 240  * of a previously valid pte with the hw invalid bit set can be observed by
 241  * handle_pte_fault. That makes it necessary that all valid pte types with
 242  * the hw invalid bit set must be distinguishable from the four pte types
 243  * empty, none, swap and file.
 244  *
 245  *                      irxt  ipte  irxt
 246  * _PAGE_TYPE_EMPTY     1000   ->   1000
 247  * _PAGE_TYPE_NONE      1001   ->   1001
 248  * _PAGE_TYPE_SWAP      1011   ->   1011
 249  * _PAGE_TYPE_FILE      11?1   ->   11?1
 250  * _PAGE_TYPE_RO        0100   ->   1100
 251  * _PAGE_TYPE_RW        0000   ->   1000
 252  * _PAGE_TYPE_EX_RO     0110   ->   1110
 253  * _PAGE_TYPE_EX_RW     0010   ->   1010
 254  *
 255  * pte_none is true for bits combinations 1000, 1010, 1100, 1110
 256  * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
 257  * pte_file is true for bits combinations 1101, 1111
 258  * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
 259  */
 260
 261 #ifndef __s390x__
 262
 263 /* Bits in the segment table address-space-control-element */
 264 #define _ASCE_SPACE_SWITCH      0x80000000UL    /* space switch event       */
 265 #define _ASCE_ORIGIN_MASK       0x7ffff000UL    /* segment table origin     */
 266 #define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
 267 #define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
 268 #define _ASCE_TABLE_LENGTH      0x7f    /* 128 x 64 entries = 8k            */
 269
 270 /* Bits in the segment table entry */
 271 #define _SEGMENT_ENTRY_ORIGIN   0x7fffffc0UL    /* page table origin        */
 272 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
 273 #define _SEGMENT_ENTRY_COMMON   0x10    /* common segment bit               */
 274 #define _SEGMENT_ENTRY_PTL      0x0f    /* page table length                */
 275
 276 #define _SEGMENT_ENTRY          (_SEGMENT_ENTRY_PTL)
 277 #define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
 278
 279 #else /* __s390x__ */
 280
 281 /* Bits in the segment/region table address-space-control-element */
 282 #define _ASCE_ORIGIN            ~0xfffUL/* segment table origin             */
 283 #define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
 284 #define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
 285 #define _ASCE_SPACE_SWITCH      0x40    /* space switch event               */
 286 #define _ASCE_REAL_SPACE        0x20    /* real space control               */
 287 #define _ASCE_TYPE_MASK         0x0c    /* asce table type mask             */
 288 #define _ASCE_TYPE_REGION1      0x0c    /* region first table type          */
 289 #define _ASCE_TYPE_REGION2      0x08    /* region second table type         */
 290 #define _ASCE_TYPE_REGION3      0x04    /* region third table type          */
 291 #define _ASCE_TYPE_SEGMENT      0x00    /* segment table type               */
 292 #define _ASCE_TABLE_LENGTH      0x03    /* region table length              */
 293
 294 /* Bits in the region table entry */
 295 #define _REGION_ENTRY_ORIGIN    ~0xfffUL/* region/segment table origin      */
 296 #define _REGION_ENTRY_INV       0x20    /* invalid region table entry       */
 297 #define _REGION_ENTRY_TYPE_MASK 0x0c    /* region/segment table type mask   */
 298 #define _REGION_ENTRY_TYPE_R1   0x0c    /* region first table type          */
 299 #define _REGION_ENTRY_TYPE_R2   0x08    /* region second table type         */
 300 #define _REGION_ENTRY_TYPE_R3   0x04    /* region third table type          */
 301 #define _REGION_ENTRY_LENGTH    0x03    /* region third length              */
 302
 303 #define _REGION1_ENTRY          (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
 304 #define _REGION1_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
 305 #define _REGION2_ENTRY          (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
 306 #define _REGION2_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
 307 #define _REGION3_ENTRY          (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
 308 #define _REGION3_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
 309
 310 /* Bits in the segment table entry */
 311 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffUL/* segment table origin             */
 312 #define _SEGMENT_ENTRY_RO       0x200   /* page protection bit              */
 313 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
 314
 315 #define _SEGMENT_ENTRY          (0)
 316 #define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
 317
 318 #endif /* __s390x__ */
 319
 320 /*
 321  * A user page table pointer has the space-switch-event bit, the
 322  * private-space-control bit and the storage-alteration-event-control
 323  * bit set. A kernel page table pointer doesn't need them.
 324  */
 325 #define _ASCE_USER_BITS         (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
 326                                  _ASCE_ALT_EVENT)
 327
 328 /* Bits int the storage key */
 329 #define _PAGE_CHANGED    0x02          /* HW changed bit                   */
 330 #define _PAGE_REFERENCED 0x04          /* HW referenced bit                */
 331
 332 /*
 333  * Page protection definitions.
 334  */
 335 #define PAGE_NONE       __pgprot(_PAGE_TYPE_NONE)
 336 #define PAGE_RO         __pgprot(_PAGE_TYPE_RO)
 337 #define PAGE_RW         __pgprot(_PAGE_TYPE_RW)
 338 #define PAGE_EX_RO      __pgprot(_PAGE_TYPE_EX_RO)
 339 #define PAGE_EX_RW      __pgprot(_PAGE_TYPE_EX_RW)
 340
 341 #define PAGE_KERNEL     PAGE_RW
 342 #define PAGE_COPY       PAGE_RO
 343
 344 /*
 345  * Dependent on the EXEC_PROTECT option s390 can do execute protection.
 346  * Write permission always implies read permission. In theory with a
 347  * primary/secondary page table execute only can be implemented but
 348  * it would cost an additional bit in the pte to distinguish all the
 349  * different pte types. To avoid that execute permission currently
 350  * implies read permission as well.
 351  */
 352          /*xwr*/
 353 #define __P000  PAGE_NONE
 354 #define __P001  PAGE_RO
 355 #define __P010  PAGE_RO
 356 #define __P011  PAGE_RO
 357 #define __P100  PAGE_EX_RO
 358 #define __P101  PAGE_EX_RO
 359 #define __P110  PAGE_EX_RO
 360 #define __P111  PAGE_EX_RO
 361
 362 #define __S000  PAGE_NONE
 363 #define __S001  PAGE_RO
 364 #define __S010  PAGE_RW
 365 #define __S011  PAGE_RW
 366 #define __S100  PAGE_EX_RO
 367 #define __S101  PAGE_EX_RO
 368 #define __S110  PAGE_EX_RW
 369 #define __S111  PAGE_EX_RW
 370
 371 #ifndef __s390x__
 372 # define PxD_SHADOW_SHIFT       1
 373 #else /* __s390x__ */
 374 # define PxD_SHADOW_SHIFT       2
 375 #endif /* __s390x__ */
 376
 377 static inline void *get_shadow_table(void *table)
 378 {
 379         unsigned long addr, offset;
 380         struct page *page;
 381
 382         addr = (unsigned long) table;
 383         offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
 384         page = virt_to_page((void *)(addr ^ offset));
 385         return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
 386 }
 387
 388 /*
 389  * Certain architectures need to do special things when PTEs
 390  * within a page table are directly modified.  Thus, the following
 391  * hook is made available.
 392  */
 393 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 394                               pte_t *ptep, pte_t entry)
 395 {
 396         *ptep = entry;
 397         if (mm->context.noexec) {
 398                 if (!(pte_val(entry) & _PAGE_INVALID) &&
 399                     (pte_val(entry) & _PAGE_SWX))
 400                         pte_val(entry) |= _PAGE_RO;
 401                 else
 402                         pte_val(entry) = _PAGE_TYPE_EMPTY;
 403                 ptep[PTRS_PER_PTE] = entry;
 404         }
 405 }
 406
 407 /*
 408  * pgd/pmd/pte query functions
 409  */
 410 #ifndef __s390x__
 411
 412 static inline int pgd_present(pgd_t pgd) { return 1; }
 413 static inline int pgd_none(pgd_t pgd)    { return 0; }
 414 static inline int pgd_bad(pgd_t pgd)     { return 0; }
 415
 416 static inline int pud_present(pud_t pud) { return 1; }
 417 static inline int pud_none(pud_t pud)    { return 0; }
 418 static inline int pud_bad(pud_t pud)     { return 0; }
 419
 420 #else /* __s390x__ */
 421
 422 static inline int pgd_present(pgd_t pgd)
 423 {
 424         if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
 425                 return 1;
 426         return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
 427 }
 428
 429 static inline int pgd_none(pgd_t pgd)
 430 {
 431         if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
 432                 return 0;
 433         return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
 434 }
 435
 436 static inline int pgd_bad(pgd_t pgd)
 437 {
 438         /*
 439          * With dynamic page table levels the pgd can be a region table
 440          * entry or a segment table entry. Check for the bit that are
 441          * invalid for either table entry.
 442          */
 443         unsigned long mask =
 444                 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
 445                 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
 446         return (pgd_val(pgd) & mask) != 0;
 447 }
 448
 449 static inline int pud_present(pud_t pud)
 450 {
 451         if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
 452                 return 1;
 453         return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
 454 }
 455
 456 static inline int pud_none(pud_t pud)
 457 {
 458         if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
 459                 return 0;
 460         return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
 461 }
 462
 463 static inline int pud_bad(pud_t pud)
 464 {
 465         /*
 466          * With dynamic page table levels the pud can be a region table
 467          * entry or a segment table entry. Check for the bit that are
 468          * invalid for either table entry.
 469          */
 470         unsigned long mask =
 471                 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
 472                 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
 473         return (pud_val(pud) & mask) != 0;
 474 }
 475
 476 #endif /* __s390x__ */
 477
 478 static inline int pmd_present(pmd_t pmd)
 479 {
 480         return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
 481 }
 482
 483 static inline int pmd_none(pmd_t pmd)
 484 {
 485         return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
 486 }
 487
 488 static inline int pmd_bad(pmd_t pmd)
 489 {
 490         unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
 491         return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
 492 }
 493
 494 static inline int pte_none(pte_t pte)
 495 {
 496         return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
 497 }
 498
 499 static inline int pte_present(pte_t pte)
 500 {
 501         unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
 502         return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
 503                 (!(pte_val(pte) & _PAGE_INVALID) &&
 504                  !(pte_val(pte) & _PAGE_SWT));
 505 }
 506
 507 static inline int pte_file(pte_t pte)
 508 {
 509         unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
 510         return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
 511 }
 512
 513 #define __HAVE_ARCH_PTE_SAME
 514 #define pte_same(a,b)  (pte_val(a) == pte_val(b))
 515
 516 /*
 517  * query functions pte_write/pte_dirty/pte_young only work if
 518  * pte_present() is true. Undefined behaviour if not..
 519  */
 520 static inline int pte_write(pte_t pte)
 521 {
 522         return (pte_val(pte) & _PAGE_RO) == 0;
 523 }
 524
 525 static inline int pte_dirty(pte_t pte)
 526 {
 527         /* A pte is neither clean nor dirty on s/390. The dirty bit
 528          * is in the storage key. See page_test_and_clear_dirty for
 529          * details.
 530          */
 531         return 0;
 532 }
 533
 534 static inline int pte_young(pte_t pte)
 535 {
 536         /* A pte is neither young nor old on s/390. The young bit
 537          * is in the storage key. See page_test_and_clear_young for
 538          * details.
 539          */
 540         return 0;
 541 }
 542
 543 /*
 544  * pgd/pmd/pte modification functions
 545  */
 546
 547 #ifndef __s390x__
 548
 549 #define pgd_clear(pgd)          do { } while (0)
 550 #define pud_clear(pud)          do { } while (0)
 551
 552 #else /* __s390x__ */
 553
 554 static inline void pgd_clear_kernel(pgd_t * pgd)
 555 {
 556         if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
 557                 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
 558 }
 559
 560 static inline void pgd_clear(pgd_t * pgd)
 561 {
 562         pgd_t *shadow = get_shadow_table(pgd);
 563
 564         pgd_clear_kernel(pgd);
 565         if (shadow)
 566                 pgd_clear_kernel(shadow);
 567 }
 568
 569 static inline void pud_clear_kernel(pud_t *pud)
 570 {
 571         if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
 572                 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
 573 }
 574
 575 static inline void pud_clear(pud_t *pud)
 576 {
 577         pud_t *shadow = get_shadow_table(pud);
 578
 579         pud_clear_kernel(pud);
 580         if (shadow)
 581                 pud_clear_kernel(shadow);
 582 }
 583
 584 #endif /* __s390x__ */
 585
 586 static inline void pmd_clear_kernel(pmd_t * pmdp)
 587 {
 588         pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
 589 }
 590
 591 static inline void pmd_clear(pmd_t *pmd)
 592 {
 593         pmd_t *shadow = get_shadow_table(pmd);
 594
 595         pmd_clear_kernel(pmd);
 596         if (shadow)
 597                 pmd_clear_kernel(shadow);
 598 }
 599
 600 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 601 {
 602         pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 603         if (mm->context.noexec)
 604                 pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
 605 }
 606
 607 /*
 608  * The following pte modification functions only work if
 609  * pte_present() is true. Undefined behaviour if not..
 610  */
 611 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 612 {
 613         pte_val(pte) &= PAGE_MASK;
 614         pte_val(pte) |= pgprot_val(newprot);
 615         return pte;
 616 }
 617
 618 static inline pte_t pte_wrprotect(pte_t pte)
 619 {
 620         /* Do not clobber _PAGE_TYPE_NONE pages!  */
 621         if (!(pte_val(pte) & _PAGE_INVALID))
 622                 pte_val(pte) |= _PAGE_RO;
 623         return pte;
 624 }
 625
 626 static inline pte_t pte_mkwrite(pte_t pte)
 627 {
 628         pte_val(pte) &= ~_PAGE_RO;
 629         return pte;
 630 }
 631
 632 static inline pte_t pte_mkclean(pte_t pte)
 633 {
 634         /* The only user of pte_mkclean is the fork() code.
 635            We must *not* clear the *physical* page dirty bit
 636            just because fork() wants to clear the dirty bit in
 637            *one* of the page's mappings.  So we just do nothing. */
 638         return pte;
 639 }
 640
 641 static inline pte_t pte_mkdirty(pte_t pte)
 642 {
 643         /* We do not explicitly set the dirty bit because the
 644          * sske instruction is slow. It is faster to let the
 645          * next instruction set the dirty bit.
 646          */
 647         return pte;
 648 }
 649
 650 static inline pte_t pte_mkold(pte_t pte)
 651 {
 652         /* S/390 doesn't keep its dirty/referenced bit in the pte.
 653          * There is no point in clearing the real referenced bit.
 654          */
 655         return pte;
 656 }
 657
 658 static inline pte_t pte_mkyoung(pte_t pte)
 659 {
 660         /* S/390 doesn't keep its dirty/referenced bit in the pte.
 661          * There is no point in setting the real referenced bit.
 662          */
 663         return pte;
 664 }
 665
 666 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 667 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 668                                             unsigned long addr, pte_t *ptep)
 669 {
 670         return 0;
 671 }
 672
 673 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 674 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 675                                          unsigned long address, pte_t *ptep)
 676 {
 677         /* No need to flush TLB; bits are in storage key */
 678         return 0;
 679 }
 680
 681 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
 682 {
 683         if (!(pte_val(*ptep) & _PAGE_INVALID)) {
 684 #ifndef __s390x__
 685                 /* pto must point to the start of the segment table */
 686                 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
 687 #else
 688                 /* ipte in zarch mode can do the math */
 689                 pte_t *pto = ptep;
 690 #endif
 691                 asm volatile(
 692                         "       ipte    %2,%3"
 693                         : "=m" (*ptep) : "m" (*ptep),
 694                           "a" (pto), "a" (address));
 695         }
 696         pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 697 }
 698
 699 static inline void ptep_invalidate(struct mm_struct *mm,
 700                                    unsigned long address, pte_t *ptep)
 701 {
 702         __ptep_ipte(address, ptep);
 703         if (mm->context.noexec)
 704                 __ptep_ipte(address, ptep + PTRS_PER_PTE);
 705 }
 706
 707 /*
 708  * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
 709  * both clear the TLB for the unmapped pte. The reason is that
 710  * ptep_get_and_clear is used in common code (e.g. change_pte_range)
 711  * to modify an active pte. The sequence is
 712  *   1) ptep_get_and_clear
 713  *   2) set_pte_at
 714  *   3) flush_tlb_range
 715  * On s390 the tlb needs to get flushed with the modification of the pte
 716  * if the pte is active. The only way how this can be implemented is to
 717  * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
 718  * is a nop.
 719  */
 720 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 721 #define ptep_get_and_clear(__mm, __address, __ptep)                     \
 722 ({                                                                      \
 723         pte_t __pte = *(__ptep);                                        \
 724         if (atomic_read(&(__mm)->mm_users) > 1 ||                       \
 725             (__mm) != current->active_mm)                               \
 726                 ptep_invalidate(__mm, __address, __ptep);               \
 727         else                                                            \
 728                 pte_clear((__mm), (__address), (__ptep));               \
 729         __pte;                                                          \
 730 })
 731
 732 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
 733 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
 734                                      unsigned long address, pte_t *ptep)
 735 {
 736         pte_t pte = *ptep;
 737         ptep_invalidate(vma->vm_mm, address, ptep);
 738         return pte;
 739 }
 740
 741 /*
 742  * The batched pte unmap code uses ptep_get_and_clear_full to clear the
 743  * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
 744  * tlbs of an mm if it can guarantee that the ptes of the mm_struct
 745  * cannot be accessed while the batched unmap is running. In this case
 746  * full==1 and a simple pte_clear is enough. See tlb.h.
 747  */
 748 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 749 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
 750                                             unsigned long addr,
 751                                             pte_t *ptep, int full)
 752 {
 753         pte_t pte = *ptep;
 754
 755         if (full)
 756                 pte_clear(mm, addr, ptep);
 757         else
 758                 ptep_invalidate(mm, addr, ptep);
 759         return pte;
 760 }
 761
 762 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 763 #define ptep_set_wrprotect(__mm, __addr, __ptep)                        \
 764 ({                                                                      \
 765         pte_t __pte = *(__ptep);                                        \
 766         if (pte_write(__pte)) {                                         \
 767                 if (atomic_read(&(__mm)->mm_users) > 1 ||               \
 768                     (__mm) != current->active_mm)                       \
 769                         ptep_invalidate(__mm, __addr, __ptep);          \
 770                 set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
 771         }                                                               \
 772 })
 773
 774 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 775 #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty)  \
 776 ({                                                                      \
 777         int __changed = !pte_same(*(__ptep), __entry);                  \
 778         if (__changed) {                                                \
 779                 ptep_invalidate((__vma)->vm_mm, __addr, __ptep);        \
 780                 set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry);    \
 781         }                                                               \
 782         __changed;                                                      \
 783 })
 784
 785 /*
 786  * Test and clear dirty bit in storage key.
 787  * We can't clear the changed bit atomically. This is a potential
 788  * race against modification of the referenced bit. This function
 789  * should therefore only be called if it is not mapped in any
 790  * address space.
 791  */
 792 #define __HAVE_ARCH_PAGE_TEST_DIRTY
 793 static inline int page_test_dirty(struct page *page)
 794 {
 795         return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
 796 }
 797
 798 #define __HAVE_ARCH_PAGE_CLEAR_DIRTY
 799 static inline void page_clear_dirty(struct page *page)
 800 {
 801         page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
 802 }
 803
 804 /*
 805  * Test and clear referenced bit in storage key.
 806  */
 807 #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
 808 static inline int page_test_and_clear_young(struct page *page)
 809 {
 810         unsigned long physpage = page_to_phys(page);
 811         int ccode;
 812
 813         asm volatile(
 814                 "       rrbe    0,%1\n"
 815                 "       ipm     %0\n"
 816                 "       srl     %0,28\n"
 817                 : "=d" (ccode) : "a" (physpage) : "cc" );
 818         return ccode & 2;
 819 }
 820
 821 /*
 822  * Conversion functions: convert a page and protection to a page entry,
 823  * and a page entry and page directory to the page they refer to.
 824  */
 825 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 826 {
 827         pte_t __pte;
 828         pte_val(__pte) = physpage + pgprot_val(pgprot);
 829         return __pte;
 830 }
 831
 832 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
 833 {
 834         unsigned long physpage = page_to_phys(page);
 835
 836         return mk_pte_phys(physpage, pgprot);
 837 }
 838
 839 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 840 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 841 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 842 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
 843
 844 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 845 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 846
 847 #ifndef __s390x__
 848
 849 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
 850 #define pud_deref(pmd) ({ BUG(); 0UL; })
 851 #define pgd_deref(pmd) ({ BUG(); 0UL; })
 852
 853 #define pud_offset(pgd, address) ((pud_t *) pgd)
 854 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
 855
 856 #else /* __s390x__ */
 857
 858 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
 859 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
 860 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
 861
 862 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
 863 {
 864         pud_t *pud = (pud_t *) pgd;
 865         if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
 866                 pud = (pud_t *) pgd_deref(*pgd);
 867         return pud  + pud_index(address);
 868 }
 869
 870 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
 871 {
 872         pmd_t *pmd = (pmd_t *) pud;
 873         if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
 874                 pmd = (pmd_t *) pud_deref(*pud);
 875         return pmd + pmd_index(address);
 876 }
 877
 878 #endif /* __s390x__ */
 879
 880 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
 881 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
 882 #define pte_page(x) pfn_to_page(pte_pfn(x))
 883
 884 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
 885
 886 /* Find an entry in the lowest level page table.. */
 887 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
 888 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
 889 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
 890 #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
 891 #define pte_unmap(pte) do { } while (0)
 892 #define pte_unmap_nested(pte) do { } while (0)
 893
 894 /*
 895  * 31 bit swap entry format:
 896  * A page-table entry has some bits we have to treat in a special way.
 897  * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
 898  * exception will occur instead of a page translation exception. The
 899  * specifiation exception has the bad habit not to store necessary
 900  * information in the lowcore.
 901  * Bit 21 and bit 22 are the page invalid bit and the page protection
 902  * bit. We set both to indicate a swapped page.
 903  * Bit 30 and 31 are used to distinguish the different page types. For
 904  * a swapped page these bits need to be zero.
 905  * This leaves the bits 1-19 and bits 24-29 to store type and offset.
 906  * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
 907  * plus 24 for the offset.
 908  * 0|     offset        |0110|o|type |00|
 909  * 0 0000000001111111111 2222 2 22222 33
 910  * 0 1234567890123456789 0123 4 56789 01
 911  *
 912  * 64 bit swap entry format:
 913  * A page-table entry has some bits we have to treat in a special way.
 914  * Bits 52 and bit 55 have to be zero, otherwise an specification
 915  * exception will occur instead of a page translation exception. The
 916  * specifiation exception has the bad habit not to store necessary
 917  * information in the lowcore.
 918  * Bit 53 and bit 54 are the page invalid bit and the page protection
 919  * bit. We set both to indicate a swapped page.
 920  * Bit 62 and 63 are used to distinguish the different page types. For
 921  * a swapped page these bits need to be zero.
 922  * This leaves the bits 0-51 and bits 56-61 to store type and offset.
 923  * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
 924  * plus 56 for the offset.
 925  * |                      offset                        |0110|o|type |00|
 926  *  0000000000111111111122222222223333333333444444444455 5555 5 55566 66
 927  *  0123456789012345678901234567890123456789012345678901 2345 6 78901 23
 928  */
 929 #ifndef __s390x__
 930 #define __SWP_OFFSET_MASK (~0UL >> 12)
 931 #else
 932 #define __SWP_OFFSET_MASK (~0UL >> 11)
 933 #endif
 934 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 935 {
 936         pte_t pte;
 937         offset &= __SWP_OFFSET_MASK;
 938         pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
 939                 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
 940         return pte;
 941 }
 942
 943 #define __swp_type(entry)       (((entry).val >> 2) & 0x1f)
 944 #define __swp_offset(entry)     (((entry).val >> 11) | (((entry).val >> 7) & 1))
 945 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
 946
 947 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 948 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 949
 950 #ifndef __s390x__
 951 # define PTE_FILE_MAX_BITS      26
 952 #else /* __s390x__ */
 953 # define PTE_FILE_MAX_BITS      59
 954 #endif /* __s390x__ */
 955
 956 #define pte_to_pgoff(__pte) \
 957         ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
 958
 959 #define pgoff_to_pte(__off) \
 960         ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
 961                    | _PAGE_TYPE_FILE })
 962
 963 #endif /* !__ASSEMBLY__ */
 964
 965 #define kern_addr_valid(addr)   (1)
 966
 967 extern int add_shared_memory(unsigned long start, unsigned long size);
 968 extern int remove_shared_memory(unsigned long start, unsigned long size);
 969
 970 /*
 971  * No page table caches to initialise
 972  */
 973 #define pgtable_cache_init()    do { } while (0)
 974
 975 #define __HAVE_ARCH_MEMMAP_INIT
 976 extern void memmap_init(unsigned long, int, unsigned long, unsigned long);
 977
 978 #include <asm-generic/pgtable.h>
 979
 980 #endif /* _S390_PAGE_H */