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cmd64x: don't clear the other channel's interrupt
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / ata / pata_sil680.c
blob5c1e9cb59ecb66ed07ace0e1739516300e7c0280
1 /*
2 * pata_sil680.c - SIL680 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
9 *
10 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat <alan@redhat.com>
12 *
13 * May be copied or modified under the terms of the GNU General Public License
14 *
15 * Documentation publically available.
16 *
17 * If you have strange problems with nVidia chipset systems please
18 * see the SI support documentation and update your system BIOS
19 * if necessary
20 *
21 * TODO
22 * If we know all our devices are LBA28 (or LBA28 sized) we could use
23 * the command fifo mode.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34
35 #define DRV_NAME "pata_sil680"
36 #define DRV_VERSION "0.4.7"
37
38 #define SIL680_MMIO_BAR 5
39
40 /**
41 * sil680_selreg - return register base
42 * @hwif: interface
43 * @r: config offset
44 *
45 * Turn a config register offset into the right address in either
46 * PCI space or MMIO space to access the control register in question
47 * Thankfully this is a configuration operation so isnt performance
48 * criticial.
49 */
50
51 static unsigned long sil680_selreg(struct ata_port *ap, int r)
52 {
53 unsigned long base = 0xA0 + r;
54 base += (ap->port_no << 4);
55 return base;
56 }
57
58 /**
59 * sil680_seldev - return register base
60 * @hwif: interface
61 * @r: config offset
62 *
63 * Turn a config register offset into the right address in either
64 * PCI space or MMIO space to access the control register in question
65 * including accounting for the unit shift.
66 */
67
68 static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
69 {
70 unsigned long base = 0xA0 + r;
71 base += (ap->port_no << 4);
72 base |= adev->devno ? 2 : 0;
73 return base;
74 }
75
76
77 /**
78 * sil680_cable_detect - cable detection
79 * @ap: ATA port
80 *
81 * Perform cable detection. The SIL680 stores this in PCI config
82 * space for us.
83 */
84
85 static int sil680_cable_detect(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87 unsigned long addr = sil680_selreg(ap, 0);
88 u8 ata66;
89 pci_read_config_byte(pdev, addr, &ata66);
90 if (ata66 & 1)
91 return ATA_CBL_PATA80;
92 else
93 return ATA_CBL_PATA40;
94 }
95
96 /**
97 * sil680_bus_reset - reset the SIL680 bus
98 * @link: ATA link to reset
99 * @deadline: deadline jiffies for the operation
100 *
101 * Perform the SIL680 housekeeping when doing an ATA bus reset
102 */
103
104 static int sil680_bus_reset(struct ata_link *link, unsigned int *classes,
105 unsigned long deadline)
106 {
107 struct ata_port *ap = link->ap;
108 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
109 unsigned long addr = sil680_selreg(ap, 0);
110 u8 reset;
111
112 pci_read_config_byte(pdev, addr, &reset);
113 pci_write_config_byte(pdev, addr, reset | 0x03);
114 udelay(25);
115 pci_write_config_byte(pdev, addr, reset);
116 return ata_std_softreset(link, classes, deadline);
117 }
118
119 static void sil680_error_handler(struct ata_port *ap)
120 {
121 ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset);
122 }
123
124 /**
125 * sil680_set_piomode - set initial PIO mode data
126 * @ap: ATA interface
127 * @adev: ATA device
128 *
129 * Program the SIL680 registers for PIO mode. Note that the task speed
130 * registers are shared between the devices so we must pick the lowest
131 * mode for command work.
132 */
133
134 static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
135 {
136 static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
137 static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
138
139 unsigned long tfaddr = sil680_selreg(ap, 0x02);
140 unsigned long addr = sil680_seldev(ap, adev, 0x04);
141 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
142 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
143 int pio = adev->pio_mode - XFER_PIO_0;
144 int lowest_pio = pio;
145 int port_shift = 4 * adev->devno;
146 u16 reg;
147 u8 mode;
148
149 struct ata_device *pair = ata_dev_pair(adev);
150
151 if (pair != NULL && adev->pio_mode > pair->pio_mode)
152 lowest_pio = pair->pio_mode - XFER_PIO_0;
153
154 pci_write_config_word(pdev, addr, speed_p[pio]);
155 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
156
157 pci_read_config_word(pdev, tfaddr-2, &reg);
158 pci_read_config_byte(pdev, addr_mask, &mode);
159
160 reg &= ~0x0200; /* Clear IORDY */
161 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
162
163 if (ata_pio_need_iordy(adev)) {
164 reg |= 0x0200; /* Enable IORDY */
165 mode |= 1 << port_shift;
166 }
167 pci_write_config_word(pdev, tfaddr-2, reg);
168 pci_write_config_byte(pdev, addr_mask, mode);
169 }
170
171 /**
172 * sil680_set_dmamode - set initial DMA mode data
173 * @ap: ATA interface
174 * @adev: ATA device
175 *
176 * Program the MWDMA/UDMA modes for the sil680 k
177 * chipset. The MWDMA mode values are pulled from a lookup table
178 * while the chipset uses mode number for UDMA.
179 */
180
181 static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
182 {
183 static u8 ultra_table[2][7] = {
184 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
185 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
186 };
187 static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
188
189 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
190 unsigned long ma = sil680_seldev(ap, adev, 0x08);
191 unsigned long ua = sil680_seldev(ap, adev, 0x0C);
192 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
193 int port_shift = adev->devno * 4;
194 u8 scsc, mode;
195 u16 multi, ultra;
196
197 pci_read_config_byte(pdev, 0x8A, &scsc);
198 pci_read_config_byte(pdev, addr_mask, &mode);
199 pci_read_config_word(pdev, ma, &multi);
200 pci_read_config_word(pdev, ua, &ultra);
201
202 /* Mask timing bits */
203 ultra &= ~0x3F;
204 mode &= ~(0x03 << port_shift);
205
206 /* Extract scsc */
207 scsc = (scsc & 0x30) ? 1: 0;
208
209 if (adev->dma_mode >= XFER_UDMA_0) {
210 multi = 0x10C1;
211 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
212 mode |= (0x03 << port_shift);
213 } else {
214 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
215 mode |= (0x02 << port_shift);
216 }
217 pci_write_config_byte(pdev, addr_mask, mode);
218 pci_write_config_word(pdev, ma, multi);
219 pci_write_config_word(pdev, ua, ultra);
220 }
221
222 static struct scsi_host_template sil680_sht = {
223 .module = THIS_MODULE,
224 .name = DRV_NAME,
225 .ioctl = ata_scsi_ioctl,
226 .queuecommand = ata_scsi_queuecmd,
227 .can_queue = ATA_DEF_QUEUE,
228 .this_id = ATA_SHT_THIS_ID,
229 .sg_tablesize = LIBATA_MAX_PRD,
230 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
231 .emulated = ATA_SHT_EMULATED,
232 .use_clustering = ATA_SHT_USE_CLUSTERING,
233 .proc_name = DRV_NAME,
234 .dma_boundary = ATA_DMA_BOUNDARY,
235 .slave_configure = ata_scsi_slave_config,
236 .slave_destroy = ata_scsi_slave_destroy,
237 .bios_param = ata_std_bios_param,
238 };
239
240 static struct ata_port_operations sil680_port_ops = {
241 .set_piomode = sil680_set_piomode,
242 .set_dmamode = sil680_set_dmamode,
243 .mode_filter = ata_pci_default_filter,
244 .tf_load = ata_tf_load,
245 .tf_read = ata_tf_read,
246 .check_status = ata_check_status,
247 .exec_command = ata_exec_command,
248 .dev_select = ata_std_dev_select,
249
250 .freeze = ata_bmdma_freeze,
251 .thaw = ata_bmdma_thaw,
252 .error_handler = sil680_error_handler,
253 .post_internal_cmd = ata_bmdma_post_internal_cmd,
254 .cable_detect = sil680_cable_detect,
255
256 .bmdma_setup = ata_bmdma_setup,
257 .bmdma_start = ata_bmdma_start,
258 .bmdma_stop = ata_bmdma_stop,
259 .bmdma_status = ata_bmdma_status,
260
261 .qc_prep = ata_qc_prep,
262 .qc_issue = ata_qc_issue_prot,
263
264 .data_xfer = ata_data_xfer,
265
266 .irq_handler = ata_interrupt,
267 .irq_clear = ata_bmdma_irq_clear,
268 .irq_on = ata_irq_on,
269
270 .port_start = ata_sff_port_start,
271 };
272
273 /**
274 * sil680_init_chip - chip setup
275 * @pdev: PCI device
276 *
277 * Perform all the chip setup which must be done both when the device
278 * is powered up on boot and when we resume in case we resumed from RAM.
279 * Returns the final clock settings.
280 */
281
282 static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
283 {
284 u32 class_rev = 0;
285 u8 tmpbyte = 0;
286
287 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
288 class_rev &= 0xff;
289 /* FIXME: double check */
290 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
291
292 pci_write_config_byte(pdev, 0x80, 0x00);
293 pci_write_config_byte(pdev, 0x84, 0x00);
294
295 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
296
297 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
298 tmpbyte & 1, tmpbyte & 0x30);
299
300 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
301
302 switch(tmpbyte & 0x30) {
303 case 0x00:
304 /* 133 clock attempt to force it on */
305 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
306 break;
307 case 0x30:
308 /* if clocking is disabled */
309 /* 133 clock attempt to force it on */
310 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
311 break;
312 case 0x10:
313 /* 133 already */
314 break;
315 case 0x20:
316 /* BIOS set PCI x2 clocking */
317 break;
318 }
319
320 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
321 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
322 tmpbyte & 1, tmpbyte & 0x30);
323
324 pci_write_config_byte(pdev, 0xA1, 0x72);
325 pci_write_config_word(pdev, 0xA2, 0x328A);
326 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
327 pci_write_config_dword(pdev, 0xA8, 0x43924392);
328 pci_write_config_dword(pdev, 0xAC, 0x40094009);
329 pci_write_config_byte(pdev, 0xB1, 0x72);
330 pci_write_config_word(pdev, 0xB2, 0x328A);
331 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
332 pci_write_config_dword(pdev, 0xB8, 0x43924392);
333 pci_write_config_dword(pdev, 0xBC, 0x40094009);
334
335 switch(tmpbyte & 0x30) {
336 case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
337 case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
338 case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
339 /* This last case is _NOT_ ok */
340 case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
341 }
342 return tmpbyte & 0x30;
343 }
344
345 static int __devinit sil680_init_one(struct pci_dev *pdev,
346 const struct pci_device_id *id)
347 {
348 static const struct ata_port_info info = {
349 .sht = &sil680_sht,
350 .flags = ATA_FLAG_SLAVE_POSS,
351 .pio_mask = 0x1f,
352 .mwdma_mask = 0x07,
353 .udma_mask = ATA_UDMA6,
354 .port_ops = &sil680_port_ops
355 };
356 static const struct ata_port_info info_slow = {
357 .sht = &sil680_sht,
358 .flags = ATA_FLAG_SLAVE_POSS,
359 .pio_mask = 0x1f,
360 .mwdma_mask = 0x07,
361 .udma_mask = ATA_UDMA5,
362 .port_ops = &sil680_port_ops
363 };
364 const struct ata_port_info *ppi[] = { &info, NULL };
365 static int printed_version;
366 struct ata_host *host;
367 void __iomem *mmio_base;
368 int rc, try_mmio;
369
370 if (!printed_version++)
371 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
372
373 switch (sil680_init_chip(pdev, &try_mmio)) {
374 case 0:
375 ppi[0] = &info_slow;
376 break;
377 case 0x30:
378 return -ENODEV;
379 }
380
381 if (!try_mmio)
382 goto use_ioports;
383
384 /* Try to acquire MMIO resources and fallback to PIO if
385 * that fails
386 */
387 rc = pcim_enable_device(pdev);
388 if (rc)
389 return rc;
390 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
391 if (rc)
392 goto use_ioports;
393
394 /* Allocate host and set it up */
395 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
396 if (!host)
397 return -ENOMEM;
398 host->iomap = pcim_iomap_table(pdev);
399
400 /* Setup DMA masks */
401 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
402 if (rc)
403 return rc;
404 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
405 if (rc)
406 return rc;
407 pci_set_master(pdev);
408
409 /* Get MMIO base and initialize port addresses */
410 mmio_base = host->iomap[SIL680_MMIO_BAR];
411 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
412 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
413 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
414 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
415 ata_std_ports(&host->ports[0]->ioaddr);
416 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
417 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
418 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
419 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
420 ata_std_ports(&host->ports[1]->ioaddr);
421
422 /* Register & activate */
423 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
424 &sil680_sht);
425
426 use_ioports:
427 return ata_pci_init_one(pdev, ppi);
428 }
429
430 #ifdef CONFIG_PM
431 static int sil680_reinit_one(struct pci_dev *pdev)
432 {
433 int try_mmio;
434
435 sil680_init_chip(pdev, &try_mmio);
436 return ata_pci_device_resume(pdev);
437 }
438 #endif
439
440 static const struct pci_device_id sil680[] = {
441 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
442
443 { },
444 };
445
446 static struct pci_driver sil680_pci_driver = {
447 .name = DRV_NAME,
448 .id_table = sil680,
449 .probe = sil680_init_one,
450 .remove = ata_pci_remove_one,
451 #ifdef CONFIG_PM
452 .suspend = ata_pci_device_suspend,
453 .resume = sil680_reinit_one,
454 #endif
455 };
456
457 static int __init sil680_init(void)
458 {
459 return pci_register_driver(&sil680_pci_driver);
460 }
461
462 static void __exit sil680_exit(void)
463 {
464 pci_unregister_driver(&sil680_pci_driver);
465 }
466
467 MODULE_AUTHOR("Alan Cox");
468 MODULE_DESCRIPTION("low-level driver for SI680 PATA");
469 MODULE_LICENSE("GPL");
470 MODULE_DEVICE_TABLE(pci, sil680);
471 MODULE_VERSION(DRV_VERSION);
472
473 module_init(sil680_init);
474 module_exit(sil680_exit);
A Kernel for the Dreambox dm7025.