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cmd64x: don't clear the other channel's interrupt
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / ata / sata_inic162x.c
blob323c087e8cc122bb04189ee361952147c6b8faa8
1 /*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
12 *
13 * - ATA disks work.
14 * - Hotplug works.
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
18 * my guest.
19 * - Both STR and STD work.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
29
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
32
33 enum {
34 MMIO_BAR = 5,
35
36 NR_PORTS = 2,
37
38 HOST_CTL = 0x7c,
39 HOST_STAT = 0x7e,
40 HOST_IRQ_STAT = 0xbc,
41 HOST_IRQ_MASK = 0xbe,
42
43 PORT_SIZE = 0x40,
44
45 /* registers for ATA TF operation */
46 PORT_TF = 0x00,
47 PORT_ALT_STAT = 0x08,
48 PORT_IRQ_STAT = 0x09,
49 PORT_IRQ_MASK = 0x0a,
50 PORT_PRD_CTL = 0x0b,
51 PORT_PRD_ADDR = 0x0c,
52 PORT_PRD_XFERLEN = 0x10,
53
54 /* IDMA register */
55 PORT_IDMA_CTL = 0x14,
56
57 PORT_SCR = 0x20,
58
59 /* HOST_CTL bits */
60 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
61 HCTL_PWRDWN = (1 << 13), /* power down PHYs */
62 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
63 HCTL_RPGSEL = (1 << 15), /* register page select */
64
65 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
66 HCTL_RPGSEL,
67
68 /* HOST_IRQ_(STAT|MASK) bits */
69 HIRQ_PORT0 = (1 << 0),
70 HIRQ_PORT1 = (1 << 1),
71 HIRQ_SOFT = (1 << 14),
72 HIRQ_GLOBAL = (1 << 15), /* STAT only */
73
74 /* PORT_IRQ_(STAT|MASK) bits */
75 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
76 PIRQ_ONLINE = (1 << 1), /* device plugged */
77 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
78 PIRQ_FATAL = (1 << 3), /* fatal error */
79 PIRQ_ATA = (1 << 4), /* ATA interrupt */
80 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
81 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
82
83 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
84
85 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
86 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
87 PIRQ_MASK_FREEZE = 0xff,
88
89 /* PORT_PRD_CTL bits */
90 PRD_CTL_START = (1 << 0),
91 PRD_CTL_WR = (1 << 3),
92 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
93
94 /* PORT_IDMA_CTL bits */
95 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
96 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
97 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
98 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
99 };
100
101 struct inic_host_priv {
102 u16 cached_hctl;
103 };
104
105 struct inic_port_priv {
106 u8 dfl_prdctl;
107 u8 cached_prdctl;
108 u8 cached_pirq_mask;
109 };
110
111 static int inic_slave_config(struct scsi_device *sdev)
112 {
113 /* This controller is braindamaged. dma_boundary is 0xffff
114 * like others but it will lock up the whole machine HARD if
115 * 65536 byte PRD entry is fed. Reduce maximum segment size.
116 */
117 blk_queue_max_segment_size(sdev->request_queue, 65536 - 512);
118
119 return ata_scsi_slave_config(sdev);
120 }
121
122 static struct scsi_host_template inic_sht = {
123 .module = THIS_MODULE,
124 .name = DRV_NAME,
125 .ioctl = ata_scsi_ioctl,
126 .queuecommand = ata_scsi_queuecmd,
127 .can_queue = ATA_DEF_QUEUE,
128 .this_id = ATA_SHT_THIS_ID,
129 .sg_tablesize = LIBATA_MAX_PRD,
130 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
131 .emulated = ATA_SHT_EMULATED,
132 .use_clustering = ATA_SHT_USE_CLUSTERING,
133 .proc_name = DRV_NAME,
134 .dma_boundary = ATA_DMA_BOUNDARY,
135 .slave_configure = inic_slave_config,
136 .slave_destroy = ata_scsi_slave_destroy,
137 .bios_param = ata_std_bios_param,
138 };
139
140 static const int scr_map[] = {
141 [SCR_STATUS] = 0,
142 [SCR_ERROR] = 1,
143 [SCR_CONTROL] = 2,
144 };
145
146 static void __iomem *inic_port_base(struct ata_port *ap)
147 {
148 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
149 }
150
151 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
152 {
153 void __iomem *port_base = inic_port_base(ap);
154 struct inic_port_priv *pp = ap->private_data;
155
156 writeb(mask, port_base + PORT_IRQ_MASK);
157 pp->cached_pirq_mask = mask;
158 }
159
160 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
161 {
162 struct inic_port_priv *pp = ap->private_data;
163
164 if (pp->cached_pirq_mask != mask)
165 __inic_set_pirq_mask(ap, mask);
166 }
167
168 static void inic_reset_port(void __iomem *port_base)
169 {
170 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
171 u16 ctl;
172
173 ctl = readw(idma_ctl);
174 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
175
176 /* mask IRQ and assert reset */
177 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
178 readw(idma_ctl); /* flush */
179
180 /* give it some time */
181 msleep(1);
182
183 /* release reset */
184 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
185
186 /* clear irq */
187 writeb(0xff, port_base + PORT_IRQ_STAT);
188
189 /* reenable ATA IRQ, turn off IDMA mode */
190 writew(ctl, idma_ctl);
191 }
192
193 static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
194 {
195 void __iomem *scr_addr = ap->ioaddr.scr_addr;
196 void __iomem *addr;
197
198 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
199 return -EINVAL;
200
201 addr = scr_addr + scr_map[sc_reg] * 4;
202 *val = readl(scr_addr + scr_map[sc_reg] * 4);
203
204 /* this controller has stuck DIAG.N, ignore it */
205 if (sc_reg == SCR_ERROR)
206 *val &= ~SERR_PHYRDY_CHG;
207 return 0;
208 }
209
210 static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
211 {
212 void __iomem *scr_addr = ap->ioaddr.scr_addr;
213 void __iomem *addr;
214
215 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
216 return -EINVAL;
217
218 addr = scr_addr + scr_map[sc_reg] * 4;
219 writel(val, scr_addr + scr_map[sc_reg] * 4);
220 return 0;
221 }
222
223 /*
224 * In TF mode, inic162x is very similar to SFF device. TF registers
225 * function the same. DMA engine behaves similary using the same PRD
226 * format as BMDMA but different command register, interrupt and event
227 * notification methods are used. The following inic_bmdma_*()
228 * functions do the impedance matching.
229 */
230 static void inic_bmdma_setup(struct ata_queued_cmd *qc)
231 {
232 struct ata_port *ap = qc->ap;
233 struct inic_port_priv *pp = ap->private_data;
234 void __iomem *port_base = inic_port_base(ap);
235 int rw = qc->tf.flags & ATA_TFLAG_WRITE;
236
237 /* make sure device sees PRD table writes */
238 wmb();
239
240 /* load transfer length */
241 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
242
243 /* turn on DMA and specify data direction */
244 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
245 if (!rw)
246 pp->cached_prdctl |= PRD_CTL_WR;
247 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
248
249 /* issue r/w command */
250 ap->ops->exec_command(ap, &qc->tf);
251 }
252
253 static void inic_bmdma_start(struct ata_queued_cmd *qc)
254 {
255 struct ata_port *ap = qc->ap;
256 struct inic_port_priv *pp = ap->private_data;
257 void __iomem *port_base = inic_port_base(ap);
258
259 /* start host DMA transaction */
260 pp->cached_prdctl |= PRD_CTL_START;
261 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
262 }
263
264 static void inic_bmdma_stop(struct ata_queued_cmd *qc)
265 {
266 struct ata_port *ap = qc->ap;
267 struct inic_port_priv *pp = ap->private_data;
268 void __iomem *port_base = inic_port_base(ap);
269
270 /* stop DMA engine */
271 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
272 }
273
274 static u8 inic_bmdma_status(struct ata_port *ap)
275 {
276 /* event is already verified by the interrupt handler */
277 return ATA_DMA_INTR;
278 }
279
280 static void inic_irq_clear(struct ata_port *ap)
281 {
282 /* noop */
283 }
284
285 static void inic_host_intr(struct ata_port *ap)
286 {
287 void __iomem *port_base = inic_port_base(ap);
288 struct ata_eh_info *ehi = &ap->link.eh_info;
289 u8 irq_stat;
290
291 /* fetch and clear irq */
292 irq_stat = readb(port_base + PORT_IRQ_STAT);
293 writeb(irq_stat, port_base + PORT_IRQ_STAT);
294
295 if (likely(!(irq_stat & PIRQ_ERR))) {
296 struct ata_queued_cmd *qc =
297 ata_qc_from_tag(ap, ap->link.active_tag);
298
299 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
300 ata_chk_status(ap); /* clear ATA interrupt */
301 return;
302 }
303
304 if (likely(ata_host_intr(ap, qc)))
305 return;
306
307 ata_chk_status(ap); /* clear ATA interrupt */
308 ata_port_printk(ap, KERN_WARNING, "unhandled "
309 "interrupt, irq_stat=%x\n", irq_stat);
310 return;
311 }
312
313 /* error */
314 ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat);
315
316 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
317 ata_ehi_hotplugged(ehi);
318 ata_port_freeze(ap);
319 } else
320 ata_port_abort(ap);
321 }
322
323 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
324 {
325 struct ata_host *host = dev_instance;
326 void __iomem *mmio_base = host->iomap[MMIO_BAR];
327 u16 host_irq_stat;
328 int i, handled = 0;;
329
330 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
331
332 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
333 goto out;
334
335 spin_lock(&host->lock);
336
337 for (i = 0; i < NR_PORTS; i++) {
338 struct ata_port *ap = host->ports[i];
339
340 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
341 continue;
342
343 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
344 inic_host_intr(ap);
345 handled++;
346 } else {
347 if (ata_ratelimit())
348 dev_printk(KERN_ERR, host->dev, "interrupt "
349 "from disabled port %d (0x%x)\n",
350 i, host_irq_stat);
351 }
352 }
353
354 spin_unlock(&host->lock);
355
356 out:
357 return IRQ_RETVAL(handled);
358 }
359
360 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
361 {
362 struct ata_port *ap = qc->ap;
363
364 /* ATA IRQ doesn't wait for DMA transfer completion and vice
365 * versa. Mask IRQ selectively to detect command completion.
366 * Without it, ATA DMA read command can cause data corruption.
367 *
368 * Something similar might be needed for ATAPI writes. I
369 * tried a lot of combinations but couldn't find the solution.
370 */
371 if (qc->tf.protocol == ATA_PROT_DMA &&
372 !(qc->tf.flags & ATA_TFLAG_WRITE))
373 inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ);
374 else
375 inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
376
377 /* Issuing a command to yet uninitialized port locks up the
378 * controller. Most of the time, this happens for the first
379 * command after reset which are ATA and ATAPI IDENTIFYs.
380 * Fast fail if stat is 0x7f or 0xff for those commands.
381 */
382 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
383 qc->tf.command == ATA_CMD_ID_ATAPI)) {
384 u8 stat = ata_chk_status(ap);
385 if (stat == 0x7f || stat == 0xff)
386 return AC_ERR_HSM;
387 }
388
389 return ata_qc_issue_prot(qc);
390 }
391
392 static void inic_freeze(struct ata_port *ap)
393 {
394 void __iomem *port_base = inic_port_base(ap);
395
396 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
397
398 ata_chk_status(ap);
399 writeb(0xff, port_base + PORT_IRQ_STAT);
400
401 readb(port_base + PORT_IRQ_STAT); /* flush */
402 }
403
404 static void inic_thaw(struct ata_port *ap)
405 {
406 void __iomem *port_base = inic_port_base(ap);
407
408 ata_chk_status(ap);
409 writeb(0xff, port_base + PORT_IRQ_STAT);
410
411 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
412
413 readb(port_base + PORT_IRQ_STAT); /* flush */
414 }
415
416 /*
417 * SRST and SControl hardreset don't give valid signature on this
418 * controller. Only controller specific hardreset mechanism works.
419 */
420 static int inic_hardreset(struct ata_link *link, unsigned int *class,
421 unsigned long deadline)
422 {
423 struct ata_port *ap = link->ap;
424 void __iomem *port_base = inic_port_base(ap);
425 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
426 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
427 u16 val;
428 int rc;
429
430 /* hammer it into sane state */
431 inic_reset_port(port_base);
432
433 val = readw(idma_ctl);
434 writew(val | IDMA_CTL_RST_ATA, idma_ctl);
435 readw(idma_ctl); /* flush */
436 msleep(1);
437 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
438
439 rc = sata_link_resume(link, timing, deadline);
440 if (rc) {
441 ata_link_printk(link, KERN_WARNING, "failed to resume "
442 "link after reset (errno=%d)\n", rc);
443 return rc;
444 }
445
446 *class = ATA_DEV_NONE;
447 if (ata_link_online(link)) {
448 struct ata_taskfile tf;
449
450 /* wait a while before checking status */
451 ata_wait_after_reset(ap, deadline);
452
453 rc = ata_wait_ready(ap, deadline);
454 /* link occupied, -ENODEV too is an error */
455 if (rc) {
456 ata_link_printk(link, KERN_WARNING, "device not ready "
457 "after hardreset (errno=%d)\n", rc);
458 return rc;
459 }
460
461 ata_tf_read(ap, &tf);
462 *class = ata_dev_classify(&tf);
463 if (*class == ATA_DEV_UNKNOWN)
464 *class = ATA_DEV_NONE;
465 }
466
467 return 0;
468 }
469
470 static void inic_error_handler(struct ata_port *ap)
471 {
472 void __iomem *port_base = inic_port_base(ap);
473 struct inic_port_priv *pp = ap->private_data;
474 unsigned long flags;
475
476 /* reset PIO HSM and stop DMA engine */
477 inic_reset_port(port_base);
478
479 spin_lock_irqsave(ap->lock, flags);
480 ap->hsm_task_state = HSM_ST_IDLE;
481 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
482 spin_unlock_irqrestore(ap->lock, flags);
483
484 /* PIO and DMA engines have been stopped, perform recovery */
485 ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset,
486 ata_std_postreset);
487 }
488
489 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
490 {
491 /* make DMA engine forget about the failed command */
492 if (qc->flags & ATA_QCFLAG_FAILED)
493 inic_reset_port(inic_port_base(qc->ap));
494 }
495
496 static void inic_dev_config(struct ata_device *dev)
497 {
498 /* inic can only handle upto LBA28 max sectors */
499 if (dev->max_sectors > ATA_MAX_SECTORS)
500 dev->max_sectors = ATA_MAX_SECTORS;
501
502 if (dev->n_sectors >= 1 << 28) {
503 ata_dev_printk(dev, KERN_ERR,
504 "ERROR: This driver doesn't support LBA48 yet and may cause\n"
505 " data corruption on such devices. Disabling.\n");
506 ata_dev_disable(dev);
507 }
508 }
509
510 static void init_port(struct ata_port *ap)
511 {
512 void __iomem *port_base = inic_port_base(ap);
513
514 /* Setup PRD address */
515 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
516 }
517
518 static int inic_port_resume(struct ata_port *ap)
519 {
520 init_port(ap);
521 return 0;
522 }
523
524 static int inic_port_start(struct ata_port *ap)
525 {
526 void __iomem *port_base = inic_port_base(ap);
527 struct inic_port_priv *pp;
528 u8 tmp;
529 int rc;
530
531 /* alloc and initialize private data */
532 pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL);
533 if (!pp)
534 return -ENOMEM;
535 ap->private_data = pp;
536
537 /* default PRD_CTL value, DMAEN, WR and START off */
538 tmp = readb(port_base + PORT_PRD_CTL);
539 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
540 pp->dfl_prdctl = tmp;
541
542 /* Alloc resources */
543 rc = ata_port_start(ap);
544 if (rc) {
545 kfree(pp);
546 return rc;
547 }
548
549 init_port(ap);
550
551 return 0;
552 }
553
554 static struct ata_port_operations inic_port_ops = {
555 .tf_load = ata_tf_load,
556 .tf_read = ata_tf_read,
557 .check_status = ata_check_status,
558 .exec_command = ata_exec_command,
559 .dev_select = ata_std_dev_select,
560
561 .scr_read = inic_scr_read,
562 .scr_write = inic_scr_write,
563
564 .bmdma_setup = inic_bmdma_setup,
565 .bmdma_start = inic_bmdma_start,
566 .bmdma_stop = inic_bmdma_stop,
567 .bmdma_status = inic_bmdma_status,
568
569 .irq_clear = inic_irq_clear,
570 .irq_on = ata_irq_on,
571
572 .qc_prep = ata_qc_prep,
573 .qc_issue = inic_qc_issue,
574 .data_xfer = ata_data_xfer,
575
576 .freeze = inic_freeze,
577 .thaw = inic_thaw,
578 .error_handler = inic_error_handler,
579 .post_internal_cmd = inic_post_internal_cmd,
580 .dev_config = inic_dev_config,
581
582 .port_resume = inic_port_resume,
583
584 .port_start = inic_port_start,
585 };
586
587 static struct ata_port_info inic_port_info = {
588 /* For some reason, ATA_PROT_ATAPI is broken on this
589 * controller, and no, PIO_POLLING does't fix it. It somehow
590 * manages to report the wrong ireason and ignoring ireason
591 * results in machine lock up. Tell libata to always prefer
592 * DMA.
593 */
594 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
595 .pio_mask = 0x1f, /* pio0-4 */
596 .mwdma_mask = 0x07, /* mwdma0-2 */
597 .udma_mask = ATA_UDMA6,
598 .port_ops = &inic_port_ops
599 };
600
601 static int init_controller(void __iomem *mmio_base, u16 hctl)
602 {
603 int i;
604 u16 val;
605
606 hctl &= ~HCTL_KNOWN_BITS;
607
608 /* Soft reset whole controller. Spec says reset duration is 3
609 * PCI clocks, be generous and give it 10ms.
610 */
611 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
612 readw(mmio_base + HOST_CTL); /* flush */
613
614 for (i = 0; i < 10; i++) {
615 msleep(1);
616 val = readw(mmio_base + HOST_CTL);
617 if (!(val & HCTL_SOFTRST))
618 break;
619 }
620
621 if (val & HCTL_SOFTRST)
622 return -EIO;
623
624 /* mask all interrupts and reset ports */
625 for (i = 0; i < NR_PORTS; i++) {
626 void __iomem *port_base = mmio_base + i * PORT_SIZE;
627
628 writeb(0xff, port_base + PORT_IRQ_MASK);
629 inic_reset_port(port_base);
630 }
631
632 /* port IRQ is masked now, unmask global IRQ */
633 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
634 val = readw(mmio_base + HOST_IRQ_MASK);
635 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
636 writew(val, mmio_base + HOST_IRQ_MASK);
637
638 return 0;
639 }
640
641 #ifdef CONFIG_PM
642 static int inic_pci_device_resume(struct pci_dev *pdev)
643 {
644 struct ata_host *host = dev_get_drvdata(&pdev->dev);
645 struct inic_host_priv *hpriv = host->private_data;
646 void __iomem *mmio_base = host->iomap[MMIO_BAR];
647 int rc;
648
649 rc = ata_pci_device_do_resume(pdev);
650 if (rc)
651 return rc;
652
653 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
654 rc = init_controller(mmio_base, hpriv->cached_hctl);
655 if (rc)
656 return rc;
657 }
658
659 ata_host_resume(host);
660
661 return 0;
662 }
663 #endif
664
665 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
666 {
667 static int printed_version;
668 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
669 struct ata_host *host;
670 struct inic_host_priv *hpriv;
671 void __iomem * const *iomap;
672 int i, rc;
673
674 if (!printed_version++)
675 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
676
677 /* alloc host */
678 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
679 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
680 if (!host || !hpriv)
681 return -ENOMEM;
682
683 host->private_data = hpriv;
684
685 /* acquire resources and fill host */
686 rc = pcim_enable_device(pdev);
687 if (rc)
688 return rc;
689
690 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
691 if (rc)
692 return rc;
693 host->iomap = iomap = pcim_iomap_table(pdev);
694
695 for (i = 0; i < NR_PORTS; i++) {
696 struct ata_port *ap = host->ports[i];
697 struct ata_ioports *port = &ap->ioaddr;
698 unsigned int offset = i * PORT_SIZE;
699
700 port->cmd_addr = iomap[2 * i];
701 port->altstatus_addr =
702 port->ctl_addr = (void __iomem *)
703 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
704 port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR;
705
706 ata_std_ports(port);
707
708 ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
709 ata_port_pbar_desc(ap, MMIO_BAR, offset, "port");
710 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
711 (unsigned long long)pci_resource_start(pdev, 2 * i),
712 (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) |
713 ATA_PCI_CTL_OFS);
714 }
715
716 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
717
718 /* Set dma_mask. This devices doesn't support 64bit addressing. */
719 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
720 if (rc) {
721 dev_printk(KERN_ERR, &pdev->dev,
722 "32-bit DMA enable failed\n");
723 return rc;
724 }
725
726 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
727 if (rc) {
728 dev_printk(KERN_ERR, &pdev->dev,
729 "32-bit consistent DMA enable failed\n");
730 return rc;
731 }
732
733 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
734 if (rc) {
735 dev_printk(KERN_ERR, &pdev->dev,
736 "failed to initialize controller\n");
737 return rc;
738 }
739
740 pci_set_master(pdev);
741 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
742 &inic_sht);
743 }
744
745 static const struct pci_device_id inic_pci_tbl[] = {
746 { PCI_VDEVICE(INIT, 0x1622), },
747 { },
748 };
749
750 static struct pci_driver inic_pci_driver = {
751 .name = DRV_NAME,
752 .id_table = inic_pci_tbl,
753 #ifdef CONFIG_PM
754 .suspend = ata_pci_device_suspend,
755 .resume = inic_pci_device_resume,
756 #endif
757 .probe = inic_init_one,
758 .remove = ata_pci_remove_one,
759 };
760
761 static int __init inic_init(void)
762 {
763 return pci_register_driver(&inic_pci_driver);
764 }
765
766 static void __exit inic_exit(void)
767 {
768 pci_unregister_driver(&inic_pci_driver);
769 }
770
771 MODULE_AUTHOR("Tejun Heo");
772 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
773 MODULE_LICENSE("GPL v2");
774 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
775 MODULE_VERSION(DRV_VERSION);
776
777 module_init(inic_init);
778 module_exit(inic_exit);
A Kernel for the Dreambox dm7025.