drivers/net/cxgb3/adapter.h

   1 /*
   2  * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 /* This file should not be included directly.  Include common.h instead. */
  34
  35 #ifndef __T3_ADAPTER_H__
  36 #define __T3_ADAPTER_H__
  37
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/timer.h>
  42 #include <linux/cache.h>
  43 #include <linux/mutex.h>
  44 #include <linux/bitops.h>
  45 #include "t3cdev.h"
  46 #include <asm/semaphore.h>
  47 #include <asm/io.h>
  48
  49 struct vlan_group;
  50 struct adapter;
  51 struct sge_qset;
  52
  53 struct port_info {
  54         struct adapter *adapter;
  55         struct vlan_group *vlan_grp;
  56         struct sge_qset *qs;
  57         const struct port_type_info *port_type;
  58         u8 port_id;
  59         u8 rx_csum_offload;
  60         u8 nqsets;
  61         u8 first_qset;
  62         struct cphy phy;
  63         struct cmac mac;
  64         struct link_config link_config;
  65         struct net_device_stats netstats;
  66         int activity;
  67 };
  68
  69 enum {                          /* adapter flags */
  70         FULL_INIT_DONE = (1 << 0),
  71         USING_MSI = (1 << 1),
  72         USING_MSIX = (1 << 2),
  73         QUEUES_BOUND = (1 << 3),
  74 };
  75
  76 struct fl_pg_chunk {
  77         struct page *page;
  78         void *va;
  79         unsigned int offset;
  80 };
  81
  82 struct rx_desc;
  83 struct rx_sw_desc;
  84
  85 struct sge_fl {                     /* SGE per free-buffer list state */
  86         unsigned int buf_size;      /* size of each Rx buffer */
  87         unsigned int credits;       /* # of available Rx buffers */
  88         unsigned int size;          /* capacity of free list */
  89         unsigned int cidx;          /* consumer index */
  90         unsigned int pidx;          /* producer index */
  91         unsigned int gen;           /* free list generation */
  92         struct fl_pg_chunk pg_chunk;/* page chunk cache */
  93         unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
  94         struct rx_desc *desc;       /* address of HW Rx descriptor ring */
  95         struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
  96         dma_addr_t   phys_addr;     /* physical address of HW ring start */
  97         unsigned int cntxt_id;      /* SGE context id for the free list */
  98         unsigned long empty;        /* # of times queue ran out of buffers */
  99         unsigned long alloc_failed; /* # of times buffer allocation failed */
 100 };
 101
 102 /*
 103  * Bundle size for grouping offload RX packets for delivery to the stack.
 104  * Don't make this too big as we do prefetch on each packet in a bundle.
 105  */
 106 # define RX_BUNDLE_SIZE 8
 107
 108 struct rsp_desc;
 109
 110 struct sge_rspq {               /* state for an SGE response queue */
 111         unsigned int credits;   /* # of pending response credits */
 112         unsigned int size;      /* capacity of response queue */
 113         unsigned int cidx;      /* consumer index */
 114         unsigned int gen;       /* current generation bit */
 115         unsigned int polling;   /* is the queue serviced through NAPI? */
 116         unsigned int holdoff_tmr;       /* interrupt holdoff timer in 100ns */
 117         unsigned int next_holdoff;      /* holdoff time for next interrupt */
 118         struct rsp_desc *desc;  /* address of HW response ring */
 119         dma_addr_t phys_addr;   /* physical address of the ring */
 120         unsigned int cntxt_id;  /* SGE context id for the response q */
 121         spinlock_t lock;        /* guards response processing */
 122         struct sk_buff *rx_head;        /* offload packet receive queue head */
 123         struct sk_buff *rx_tail;        /* offload packet receive queue tail */
 124
 125         unsigned long offload_pkts;
 126         unsigned long offload_bundles;
 127         unsigned long eth_pkts; /* # of ethernet packets */
 128         unsigned long pure_rsps;        /* # of pure (non-data) responses */
 129         unsigned long imm_data; /* responses with immediate data */
 130         unsigned long rx_drops; /* # of packets dropped due to no mem */
 131         unsigned long async_notif; /* # of asynchronous notification events */
 132         unsigned long empty;    /* # of times queue ran out of credits */
 133         unsigned long nomem;    /* # of responses deferred due to no mem */
 134         unsigned long unhandled_irqs;   /* # of spurious intrs */
 135         unsigned long starved;
 136         unsigned long restarted;
 137 };
 138
 139 struct tx_desc;
 140 struct tx_sw_desc;
 141
 142 struct sge_txq {                /* state for an SGE Tx queue */
 143         unsigned long flags;    /* HW DMA fetch status */
 144         unsigned int in_use;    /* # of in-use Tx descriptors */
 145         unsigned int size;      /* # of descriptors */
 146         unsigned int processed; /* total # of descs HW has processed */
 147         unsigned int cleaned;   /* total # of descs SW has reclaimed */
 148         unsigned int stop_thres;        /* SW TX queue suspend threshold */
 149         unsigned int cidx;      /* consumer index */
 150         unsigned int pidx;      /* producer index */
 151         unsigned int gen;       /* current value of generation bit */
 152         unsigned int unacked;   /* Tx descriptors used since last COMPL */
 153         struct tx_desc *desc;   /* address of HW Tx descriptor ring */
 154         struct tx_sw_desc *sdesc;       /* address of SW Tx descriptor ring */
 155         spinlock_t lock;        /* guards enqueueing of new packets */
 156         unsigned int token;     /* WR token */
 157         dma_addr_t phys_addr;   /* physical address of the ring */
 158         struct sk_buff_head sendq;      /* List of backpressured offload packets */
 159         struct tasklet_struct qresume_tsk;      /* restarts the queue */
 160         unsigned int cntxt_id;  /* SGE context id for the Tx q */
 161         unsigned long stops;    /* # of times q has been stopped */
 162         unsigned long restarts; /* # of queue restarts */
 163 };
 164
 165 enum {                          /* per port SGE statistics */
 166         SGE_PSTAT_TSO,          /* # of TSO requests */
 167         SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
 168         SGE_PSTAT_TX_CSUM,      /* # of TX checksum offloads */
 169         SGE_PSTAT_VLANEX,       /* # of VLAN tag extractions */
 170         SGE_PSTAT_VLANINS,      /* # of VLAN tag insertions */
 171
 172         SGE_PSTAT_MAX           /* must be last */
 173 };
 174
 175 struct sge_qset {               /* an SGE queue set */
 176         struct adapter *adap;
 177         struct napi_struct napi;
 178         struct sge_rspq rspq;
 179         struct sge_fl fl[SGE_RXQ_PER_SET];
 180         struct sge_txq txq[SGE_TXQ_PER_SET];
 181         struct net_device *netdev;
 182         unsigned long txq_stopped;      /* which Tx queues are stopped */
 183         struct timer_list tx_reclaim_timer;     /* reclaims TX buffers */
 184         unsigned long port_stats[SGE_PSTAT_MAX];
 185 } ____cacheline_aligned;
 186
 187 struct sge {
 188         struct sge_qset qs[SGE_QSETS];
 189         spinlock_t reg_lock;    /* guards non-atomic SGE registers (eg context) */
 190 };
 191
 192 struct adapter {
 193         struct t3cdev tdev;
 194         struct list_head adapter_list;
 195         void __iomem *regs;
 196         struct pci_dev *pdev;
 197         unsigned long registered_device_map;
 198         unsigned long open_device_map;
 199         unsigned long flags;
 200
 201         const char *name;
 202         int msg_enable;
 203         unsigned int mmio_len;
 204
 205         struct adapter_params params;
 206         unsigned int slow_intr_mask;
 207         unsigned long irq_stats[IRQ_NUM_STATS];
 208
 209         struct {
 210                 unsigned short vec;
 211                 char desc[22];
 212         } msix_info[SGE_QSETS + 1];
 213
 214         /* T3 modules */
 215         struct sge sge;
 216         struct mc7 pmrx;
 217         struct mc7 pmtx;
 218         struct mc7 cm;
 219         struct mc5 mc5;
 220
 221         struct net_device *port[MAX_NPORTS];
 222         unsigned int check_task_cnt;
 223         struct delayed_work adap_check_task;
 224         struct work_struct ext_intr_handler_task;
 225
 226         struct dentry *debugfs_root;
 227
 228         struct mutex mdio_lock;
 229         spinlock_t stats_lock;
 230         spinlock_t work_lock;
 231 };
 232
 233 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
 234 {
 235         u32 val = readl(adapter->regs + reg_addr);
 236
 237         CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
 238         return val;
 239 }
 240
 241 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
 242 {
 243         CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
 244         writel(val, adapter->regs + reg_addr);
 245 }
 246
 247 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
 248 {
 249         return netdev_priv(adap->port[idx]);
 250 }
 251
 252 #define OFFLOAD_DEVMAP_BIT 15
 253
 254 #define tdev2adap(d) container_of(d, struct adapter, tdev)
 255
 256 static inline int offload_running(struct adapter *adapter)
 257 {
 258         return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
 259 }
 260
 261 int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
 262
 263 void t3_os_ext_intr_handler(struct adapter *adapter);
 264 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
 265                         int speed, int duplex, int fc);
 266
 267 void t3_sge_start(struct adapter *adap);
 268 void t3_sge_stop(struct adapter *adap);
 269 void t3_free_sge_resources(struct adapter *adap);
 270 void t3_sge_err_intr_handler(struct adapter *adapter);
 271 irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
 272 int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
 273 int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
 274 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
 275 int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
 276                       int irq_vec_idx, const struct qset_params *p,
 277                       int ntxq, struct net_device *dev);
 278 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
 279                 unsigned char *data);
 280 irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
 281
 282 #endif                          /* __T3_ADAPTER_H__ */