arch/mips/au1000/pb1000/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28
  29 #include <asm/mach-au1x00/au1000.h>
  30 #include <asm/mach-pb1x00/pb1000.h>
  31
  32 void board_reset(void)
  33 {
  34 }
  35
  36 void __init board_setup(void)
  37 {
  38         u32 pin_func, static_cfg0;
  39         u32 sys_freqctrl, sys_clksrc;
  40         u32 prid = read_c0_prid();
  41
  42         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  43         au_writel(8, SYS_AUXPLL);
  44         au_writel(0, SYS_PINSTATERD);
  45         udelay(100);
  46
  47 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  48         /* Zero and disable FREQ2 */
  49         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  50         sys_freqctrl &= ~0xFFF00000;
  51         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  52
  53         /* Zero and disable USBH/USBD clocks */
  54         sys_clksrc = au_readl(SYS_CLKSRC);
  55         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  56                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  57         au_writel(sys_clksrc, SYS_CLKSRC);
  58
  59         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  60         sys_freqctrl &= ~0xFFF00000;
  61
  62         sys_clksrc = au_readl(SYS_CLKSRC);
  63         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  64                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  65
  66         switch (prid & 0x000000FF) {
  67         case 0x00: /* DA */
  68         case 0x01: /* HA */
  69         case 0x02: /* HB */
  70                 /* CPU core freq to 48 MHz to slow it way down... */
  71                 au_writel(4, SYS_CPUPLL);
  72
  73                 /*
  74                  * Setup 48 MHz FREQ2 from CPUPLL for USB Host
  75                  * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
  76                  */
  77                 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
  78                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
  79
  80                 /* CPU core freq to 384 MHz */
  81                 au_writel(0x20, SYS_CPUPLL);
  82
  83                 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
  84                 break;
  85
  86         default: /* HC and newer */
  87                 /* FREQ2 = aux / 2 = 48 MHz */
  88                 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
  89                                  SYS_FC_FE2 | SYS_FC_FS2;
  90                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
  91                 break;
  92         }
  93
  94         /*
  95          * Route 48 MHz FREQ2 into USB Host and/or Device
  96          */
  97         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  98         au_writel(sys_clksrc, SYS_CLKSRC);
  99
 100         /* Configure pins GPIO[14:9] as GPIO */
 101         pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
 102
 103         /* 2nd USB port is USB host */
 104         pin_func |= SYS_PF_USB;
 105
 106         au_writel(pin_func, SYS_PINFUNC);
 107         au_writel(0x2800, SYS_TRIOUTCLR);
 108         au_writel(0x0030, SYS_OUTPUTCLR);
 109 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 110
 111         /* Make GPIO 15 an input (for interrupt line) */
 112         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
 113         /* We don't need I2S, so make it available for GPIO[31:29] */
 114         pin_func |= SYS_PF_I2S;
 115         au_writel(pin_func, SYS_PINFUNC);
 116
 117         au_writel(0x8000, SYS_TRIOUTCLR);
 118
 119         static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
 120         au_writel(static_cfg0, MEM_STCFG0);
 121
 122         /* configure RCE2* for LCD */
 123         au_writel(0x00000004, MEM_STCFG2);
 124
 125         /* MEM_STTIME2 */
 126         au_writel(0x09000000, MEM_STTIME2);
 127
 128         /* Set 32-bit base address decoding for RCE2* */
 129         au_writel(0x10003ff0, MEM_STADDR2);
 130
 131         /*
 132          * PCI CPLD setup
 133          * Expand CE0 to cover PCI
 134          */
 135         au_writel(0x11803e40, MEM_STADDR1);
 136
 137         /* Burst visibility on */
 138         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 139
 140         au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
 141         au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
 142
 143         /* Setup the static bus controller */
 144         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 145         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 146         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 147
 148 #ifdef CONFIG_PCI
 149         au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
 150         au_writel(0, SDRAM_MBAR);        // set mbar to 0
 151         au_writel(0x2, SDRAM_CMD);       // enable memory accesses
 152         au_sync_delay(1);
 153 #endif
 154
 155         /*
 156          * Enable Au1000 BCLK switching - note: sed1356 must not use
 157          * its BCLK (Au1000 LCLK) for any timings
 158          */
 159         switch (prid & 0x000000FF) {
 160         case 0x00: /* DA */
 161         case 0x01: /* HA */
 162         case 0x02: /* HB */
 163                 break;
 164         default:  /* HC and newer */
 165                 /*
 166                  * Enable sys bus clock divider when IDLE state or no bus
 167                  * activity.
 168                  */
 169                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 170                 break;
 171         }
 172 }