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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / ata / sata_sil24.c
blob27a110110077847b65e630cd11896b2e6195f75b
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
113
114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
119
120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
122
123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
128 /* 32 bit regs */
129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
150 PORT_CONTEXT = 0x1e04,
151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
183
184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
187
188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
220
221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
244
245 SIL24_MAX_CMDS = 31,
246
247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
250 BID_SIL3131 = 2,
251
252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
256 ATA_FLAG_AN | ATA_FLAG_PMP,
257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
258
259 IRQ_STAT_4PORTS = 0xf,
260 };
261
262 struct sil24_ata_block {
263 struct sil24_prb prb;
264 struct sil24_sge sge[SIL24_MAX_SGE];
265 };
266
267 struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
270 struct sil24_sge sge[SIL24_MAX_SGE];
271 };
272
273 union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276 };
277
278 static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281 } sil24_cerr_db[] = {
282 [0] = { AC_ERR_DEV, 0,
283 "device error" },
284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
285 "device error via D2H FIS" },
286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
287 "device error via SDB FIS" },
288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
289 "error in data FIS" },
290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
291 "failed to transmit command FIS" },
292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
293 "protocol mismatch" },
294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
295 "data directon mismatch" },
296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
297 "ran out of SGEs while writing" },
298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
299 "ran out of SGEs while reading" },
300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
301 "invalid data directon for ATAPI CDB" },
302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
303 "SGT not on qword boundary" },
304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
305 "PCI target abort while fetching SGT" },
306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
307 "PCI master abort while fetching SGT" },
308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
309 "PCI parity error while fetching SGT" },
310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
311 "PRB not on qword boundary" },
312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
313 "PCI target abort while fetching PRB" },
314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
315 "PCI master abort while fetching PRB" },
316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
317 "PCI parity error while fetching PRB" },
318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
319 "undefined error while transferring data" },
320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
321 "PCI target abort while transferring data" },
322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
323 "PCI master abort while transferring data" },
324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
325 "PCI parity error while transferring data" },
326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
327 "FIS received while sending service FIS" },
328 };
329
330 /*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336 struct sil24_port_priv {
337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
339 int do_port_rst;
340 };
341
342 static void sil24_dev_config(struct ata_device *dev);
343 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
344 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
345 static int sil24_qc_defer(struct ata_queued_cmd *qc);
346 static void sil24_qc_prep(struct ata_queued_cmd *qc);
347 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
348 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
349 static void sil24_pmp_attach(struct ata_port *ap);
350 static void sil24_pmp_detach(struct ata_port *ap);
351 static void sil24_freeze(struct ata_port *ap);
352 static void sil24_thaw(struct ata_port *ap);
353 static int sil24_softreset(struct ata_link *link, unsigned int *class,
354 unsigned long deadline);
355 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
356 unsigned long deadline);
357 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
358 unsigned long deadline);
359 static void sil24_error_handler(struct ata_port *ap);
360 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
361 static int sil24_port_start(struct ata_port *ap);
362 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
363 #ifdef CONFIG_PM
364 static int sil24_pci_device_resume(struct pci_dev *pdev);
365 static int sil24_port_resume(struct ata_port *ap);
366 #endif
367
368 static const struct pci_device_id sil24_pci_tbl[] = {
369 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
370 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
371 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
372 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
373 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
374 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
375
376 { } /* terminate list */
377 };
378
379 static struct pci_driver sil24_pci_driver = {
380 .name = DRV_NAME,
381 .id_table = sil24_pci_tbl,
382 .probe = sil24_init_one,
383 .remove = ata_pci_remove_one,
384 #ifdef CONFIG_PM
385 .suspend = ata_pci_device_suspend,
386 .resume = sil24_pci_device_resume,
387 #endif
388 };
389
390 static struct scsi_host_template sil24_sht = {
391 ATA_NCQ_SHT(DRV_NAME),
392 .can_queue = SIL24_MAX_CMDS,
393 .sg_tablesize = SIL24_MAX_SGE,
394 .dma_boundary = ATA_DMA_BOUNDARY,
395 };
396
397 static struct ata_port_operations sil24_ops = {
398 .inherits = &sata_pmp_port_ops,
399
400 .qc_defer = sil24_qc_defer,
401 .qc_prep = sil24_qc_prep,
402 .qc_issue = sil24_qc_issue,
403 .qc_fill_rtf = sil24_qc_fill_rtf,
404
405 .freeze = sil24_freeze,
406 .thaw = sil24_thaw,
407 .softreset = sil24_softreset,
408 .hardreset = sil24_hardreset,
409 .pmp_softreset = sil24_softreset,
410 .pmp_hardreset = sil24_pmp_hardreset,
411 .error_handler = sil24_error_handler,
412 .post_internal_cmd = sil24_post_internal_cmd,
413 .dev_config = sil24_dev_config,
414
415 .scr_read = sil24_scr_read,
416 .scr_write = sil24_scr_write,
417 .pmp_attach = sil24_pmp_attach,
418 .pmp_detach = sil24_pmp_detach,
419
420 .port_start = sil24_port_start,
421 #ifdef CONFIG_PM
422 .port_resume = sil24_port_resume,
423 #endif
424 };
425
426 /*
427 * Use bits 30-31 of port_flags to encode available port numbers.
428 * Current maxium is 4.
429 */
430 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
431 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
432
433 static const struct ata_port_info sil24_port_info[] = {
434 /* sil_3124 */
435 {
436 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
437 SIL24_FLAG_PCIX_IRQ_WOC,
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = ATA_UDMA5, /* udma0-5 */
441 .port_ops = &sil24_ops,
442 },
443 /* sil_3132 */
444 {
445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
446 .pio_mask = 0x1f, /* pio0-4 */
447 .mwdma_mask = 0x07, /* mwdma0-2 */
448 .udma_mask = ATA_UDMA5, /* udma0-5 */
449 .port_ops = &sil24_ops,
450 },
451 /* sil_3131/sil_3531 */
452 {
453 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
454 .pio_mask = 0x1f, /* pio0-4 */
455 .mwdma_mask = 0x07, /* mwdma0-2 */
456 .udma_mask = ATA_UDMA5, /* udma0-5 */
457 .port_ops = &sil24_ops,
458 },
459 };
460
461 static int sil24_tag(int tag)
462 {
463 if (unlikely(ata_tag_internal(tag)))
464 return 0;
465 return tag;
466 }
467
468 static unsigned long sil24_port_offset(struct ata_port *ap)
469 {
470 return ap->port_no * PORT_REGS_SIZE;
471 }
472
473 static void __iomem *sil24_port_base(struct ata_port *ap)
474 {
475 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
476 }
477
478 static void sil24_dev_config(struct ata_device *dev)
479 {
480 void __iomem *port = sil24_port_base(dev->link->ap);
481
482 if (dev->cdb_len == 16)
483 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
484 else
485 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
486 }
487
488 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
489 {
490 void __iomem *port = sil24_port_base(ap);
491 struct sil24_prb __iomem *prb;
492 u8 fis[6 * 4];
493
494 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
495 memcpy_fromio(fis, prb->fis, sizeof(fis));
496 ata_tf_from_fis(fis, tf);
497 }
498
499 static int sil24_scr_map[] = {
500 [SCR_CONTROL] = 0,
501 [SCR_STATUS] = 1,
502 [SCR_ERROR] = 2,
503 [SCR_ACTIVE] = 3,
504 };
505
506 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
507 {
508 void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
509
510 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
511 void __iomem *addr;
512 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
513 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
514 return 0;
515 }
516 return -EINVAL;
517 }
518
519 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
520 {
521 void __iomem *scr_addr = sil24_port_base(ap) + PORT_SCONTROL;
522
523 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
524 void __iomem *addr;
525 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
526 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
527 return 0;
528 }
529 return -EINVAL;
530 }
531
532 static void sil24_config_port(struct ata_port *ap)
533 {
534 void __iomem *port = sil24_port_base(ap);
535
536 /* configure IRQ WoC */
537 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
538 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
539 else
540 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
541
542 /* zero error counters. */
543 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
544 writel(0x8000, port + PORT_CRC_ERR_THRESH);
545 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
546 writel(0x0000, port + PORT_DECODE_ERR_CNT);
547 writel(0x0000, port + PORT_CRC_ERR_CNT);
548 writel(0x0000, port + PORT_HSHK_ERR_CNT);
549
550 /* always use 64bit activation */
551 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
552
553 /* clear port multiplier enable and resume bits */
554 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
555 }
556
557 static void sil24_config_pmp(struct ata_port *ap, int attached)
558 {
559 void __iomem *port = sil24_port_base(ap);
560
561 if (attached)
562 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
563 else
564 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
565 }
566
567 static void sil24_clear_pmp(struct ata_port *ap)
568 {
569 void __iomem *port = sil24_port_base(ap);
570 int i;
571
572 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
573
574 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
575 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
576
577 writel(0, pmp_base + PORT_PMP_STATUS);
578 writel(0, pmp_base + PORT_PMP_QACTIVE);
579 }
580 }
581
582 static int sil24_init_port(struct ata_port *ap)
583 {
584 void __iomem *port = sil24_port_base(ap);
585 struct sil24_port_priv *pp = ap->private_data;
586 u32 tmp;
587
588 /* clear PMP error status */
589 if (sata_pmp_attached(ap))
590 sil24_clear_pmp(ap);
591
592 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
593 ata_wait_register(port + PORT_CTRL_STAT,
594 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
595 tmp = ata_wait_register(port + PORT_CTRL_STAT,
596 PORT_CS_RDY, 0, 10, 100);
597
598 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
599 pp->do_port_rst = 1;
600 ap->link.eh_context.i.action |= ATA_EH_RESET;
601 return -EIO;
602 }
603
604 return 0;
605 }
606
607 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
608 const struct ata_taskfile *tf,
609 int is_cmd, u32 ctrl,
610 unsigned long timeout_msec)
611 {
612 void __iomem *port = sil24_port_base(ap);
613 struct sil24_port_priv *pp = ap->private_data;
614 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
615 dma_addr_t paddr = pp->cmd_block_dma;
616 u32 irq_enabled, irq_mask, irq_stat;
617 int rc;
618
619 prb->ctrl = cpu_to_le16(ctrl);
620 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
621
622 /* temporarily plug completion and error interrupts */
623 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
624 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
625
626 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
627 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
628
629 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
630 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
631 10, timeout_msec);
632
633 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
634 irq_stat >>= PORT_IRQ_RAW_SHIFT;
635
636 if (irq_stat & PORT_IRQ_COMPLETE)
637 rc = 0;
638 else {
639 /* force port into known state */
640 sil24_init_port(ap);
641
642 if (irq_stat & PORT_IRQ_ERROR)
643 rc = -EIO;
644 else
645 rc = -EBUSY;
646 }
647
648 /* restore IRQ enabled */
649 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
650
651 return rc;
652 }
653
654 static int sil24_softreset(struct ata_link *link, unsigned int *class,
655 unsigned long deadline)
656 {
657 struct ata_port *ap = link->ap;
658 int pmp = sata_srst_pmp(link);
659 unsigned long timeout_msec = 0;
660 struct ata_taskfile tf;
661 const char *reason;
662 int rc;
663
664 DPRINTK("ENTER\n");
665
666 /* put the port into known state */
667 if (sil24_init_port(ap)) {
668 reason = "port not ready";
669 goto err;
670 }
671
672 /* do SRST */
673 if (time_after(deadline, jiffies))
674 timeout_msec = jiffies_to_msecs(deadline - jiffies);
675
676 ata_tf_init(link->device, &tf); /* doesn't really matter */
677 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
678 timeout_msec);
679 if (rc == -EBUSY) {
680 reason = "timeout";
681 goto err;
682 } else if (rc) {
683 reason = "SRST command error";
684 goto err;
685 }
686
687 sil24_read_tf(ap, 0, &tf);
688 *class = ata_dev_classify(&tf);
689
690 DPRINTK("EXIT, class=%u\n", *class);
691 return 0;
692
693 err:
694 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
695 return -EIO;
696 }
697
698 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
699 unsigned long deadline)
700 {
701 struct ata_port *ap = link->ap;
702 void __iomem *port = sil24_port_base(ap);
703 struct sil24_port_priv *pp = ap->private_data;
704 int did_port_rst = 0;
705 const char *reason;
706 int tout_msec, rc;
707 u32 tmp;
708
709 retry:
710 /* Sometimes, DEV_RST is not enough to recover the controller.
711 * This happens often after PM DMA CS errata.
712 */
713 if (pp->do_port_rst) {
714 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
715 "state, performing PORT_RST\n");
716
717 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
718 msleep(10);
719 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
720 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
721 10, 5000);
722
723 /* restore port configuration */
724 sil24_config_port(ap);
725 sil24_config_pmp(ap, ap->nr_pmp_links);
726
727 pp->do_port_rst = 0;
728 did_port_rst = 1;
729 }
730
731 /* sil24 does the right thing(tm) without any protection */
732 sata_set_spd(link);
733
734 tout_msec = 100;
735 if (ata_link_online(link))
736 tout_msec = 5000;
737
738 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
739 tmp = ata_wait_register(port + PORT_CTRL_STAT,
740 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
741 tout_msec);
742
743 /* SStatus oscillates between zero and valid status after
744 * DEV_RST, debounce it.
745 */
746 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
747 if (rc) {
748 reason = "PHY debouncing failed";
749 goto err;
750 }
751
752 if (tmp & PORT_CS_DEV_RST) {
753 if (ata_link_offline(link))
754 return 0;
755 reason = "link not ready";
756 goto err;
757 }
758
759 /* Sil24 doesn't store signature FIS after hardreset, so we
760 * can't wait for BSY to clear. Some devices take a long time
761 * to get ready and those devices will choke if we don't wait
762 * for BSY clearance here. Tell libata to perform follow-up
763 * softreset.
764 */
765 return -EAGAIN;
766
767 err:
768 if (!did_port_rst) {
769 pp->do_port_rst = 1;
770 goto retry;
771 }
772
773 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
774 return -EIO;
775 }
776
777 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
778 struct sil24_sge *sge)
779 {
780 struct scatterlist *sg;
781 struct sil24_sge *last_sge = NULL;
782 unsigned int si;
783
784 for_each_sg(qc->sg, sg, qc->n_elem, si) {
785 sge->addr = cpu_to_le64(sg_dma_address(sg));
786 sge->cnt = cpu_to_le32(sg_dma_len(sg));
787 sge->flags = 0;
788
789 last_sge = sge;
790 sge++;
791 }
792
793 last_sge->flags = cpu_to_le32(SGE_TRM);
794 }
795
796 static int sil24_qc_defer(struct ata_queued_cmd *qc)
797 {
798 struct ata_link *link = qc->dev->link;
799 struct ata_port *ap = link->ap;
800 u8 prot = qc->tf.protocol;
801
802 /*
803 * There is a bug in the chip:
804 * Port LRAM Causes the PRB/SGT Data to be Corrupted
805 * If the host issues a read request for LRAM and SActive registers
806 * while active commands are available in the port, PRB/SGT data in
807 * the LRAM can become corrupted. This issue applies only when
808 * reading from, but not writing to, the LRAM.
809 *
810 * Therefore, reading LRAM when there is no particular error [and
811 * other commands may be outstanding] is prohibited.
812 *
813 * To avoid this bug there are two situations where a command must run
814 * exclusive of any other commands on the port:
815 *
816 * - ATAPI commands which check the sense data
817 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
818 * set.
819 *
820 */
821 int is_excl = (ata_is_atapi(prot) ||
822 (qc->flags & ATA_QCFLAG_RESULT_TF));
823
824 if (unlikely(ap->excl_link)) {
825 if (link == ap->excl_link) {
826 if (ap->nr_active_links)
827 return ATA_DEFER_PORT;
828 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
829 } else
830 return ATA_DEFER_PORT;
831 } else if (unlikely(is_excl)) {
832 ap->excl_link = link;
833 if (ap->nr_active_links)
834 return ATA_DEFER_PORT;
835 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
836 }
837
838 return ata_std_qc_defer(qc);
839 }
840
841 static void sil24_qc_prep(struct ata_queued_cmd *qc)
842 {
843 struct ata_port *ap = qc->ap;
844 struct sil24_port_priv *pp = ap->private_data;
845 union sil24_cmd_block *cb;
846 struct sil24_prb *prb;
847 struct sil24_sge *sge;
848 u16 ctrl = 0;
849
850 cb = &pp->cmd_block[sil24_tag(qc->tag)];
851
852 if (!ata_is_atapi(qc->tf.protocol)) {
853 prb = &cb->ata.prb;
854 sge = cb->ata.sge;
855 } else {
856 prb = &cb->atapi.prb;
857 sge = cb->atapi.sge;
858 memset(cb->atapi.cdb, 0, 32);
859 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
860
861 if (ata_is_data(qc->tf.protocol)) {
862 if (qc->tf.flags & ATA_TFLAG_WRITE)
863 ctrl = PRB_CTRL_PACKET_WRITE;
864 else
865 ctrl = PRB_CTRL_PACKET_READ;
866 }
867 }
868
869 prb->ctrl = cpu_to_le16(ctrl);
870 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
871
872 if (qc->flags & ATA_QCFLAG_DMAMAP)
873 sil24_fill_sg(qc, sge);
874 }
875
876 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
877 {
878 struct ata_port *ap = qc->ap;
879 struct sil24_port_priv *pp = ap->private_data;
880 void __iomem *port = sil24_port_base(ap);
881 unsigned int tag = sil24_tag(qc->tag);
882 dma_addr_t paddr;
883 void __iomem *activate;
884
885 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
886 activate = port + PORT_CMD_ACTIVATE + tag * 8;
887
888 writel((u32)paddr, activate);
889 writel((u64)paddr >> 32, activate + 4);
890
891 return 0;
892 }
893
894 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
895 {
896 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
897 return true;
898 }
899
900 static void sil24_pmp_attach(struct ata_port *ap)
901 {
902 sil24_config_pmp(ap, 1);
903 sil24_init_port(ap);
904 }
905
906 static void sil24_pmp_detach(struct ata_port *ap)
907 {
908 sil24_init_port(ap);
909 sil24_config_pmp(ap, 0);
910 }
911
912 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
913 unsigned long deadline)
914 {
915 int rc;
916
917 rc = sil24_init_port(link->ap);
918 if (rc) {
919 ata_link_printk(link, KERN_ERR,
920 "hardreset failed (port not ready)\n");
921 return rc;
922 }
923
924 return sata_std_hardreset(link, class, deadline);
925 }
926
927 static void sil24_freeze(struct ata_port *ap)
928 {
929 void __iomem *port = sil24_port_base(ap);
930
931 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
932 * PORT_IRQ_ENABLE instead.
933 */
934 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
935 }
936
937 static void sil24_thaw(struct ata_port *ap)
938 {
939 void __iomem *port = sil24_port_base(ap);
940 u32 tmp;
941
942 /* clear IRQ */
943 tmp = readl(port + PORT_IRQ_STAT);
944 writel(tmp, port + PORT_IRQ_STAT);
945
946 /* turn IRQ back on */
947 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
948 }
949
950 static void sil24_error_intr(struct ata_port *ap)
951 {
952 void __iomem *port = sil24_port_base(ap);
953 struct sil24_port_priv *pp = ap->private_data;
954 struct ata_queued_cmd *qc = NULL;
955 struct ata_link *link;
956 struct ata_eh_info *ehi;
957 int abort = 0, freeze = 0;
958 u32 irq_stat;
959
960 /* on error, we need to clear IRQ explicitly */
961 irq_stat = readl(port + PORT_IRQ_STAT);
962 writel(irq_stat, port + PORT_IRQ_STAT);
963
964 /* first, analyze and record host port events */
965 link = &ap->link;
966 ehi = &link->eh_info;
967 ata_ehi_clear_desc(ehi);
968
969 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
970
971 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
972 ata_ehi_push_desc(ehi, "SDB notify");
973 sata_async_notification(ap);
974 }
975
976 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
977 ata_ehi_hotplugged(ehi);
978 ata_ehi_push_desc(ehi, "%s",
979 irq_stat & PORT_IRQ_PHYRDY_CHG ?
980 "PHY RDY changed" : "device exchanged");
981 freeze = 1;
982 }
983
984 if (irq_stat & PORT_IRQ_UNK_FIS) {
985 ehi->err_mask |= AC_ERR_HSM;
986 ehi->action |= ATA_EH_RESET;
987 ata_ehi_push_desc(ehi, "unknown FIS");
988 freeze = 1;
989 }
990
991 /* deal with command error */
992 if (irq_stat & PORT_IRQ_ERROR) {
993 struct sil24_cerr_info *ci = NULL;
994 unsigned int err_mask = 0, action = 0;
995 u32 context, cerr;
996 int pmp;
997
998 abort = 1;
999
1000 /* DMA Context Switch Failure in Port Multiplier Mode
1001 * errata. If we have active commands to 3 or more
1002 * devices, any error condition on active devices can
1003 * corrupt DMA context switching.
1004 */
1005 if (ap->nr_active_links >= 3) {
1006 ehi->err_mask |= AC_ERR_OTHER;
1007 ehi->action |= ATA_EH_RESET;
1008 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1009 pp->do_port_rst = 1;
1010 freeze = 1;
1011 }
1012
1013 /* find out the offending link and qc */
1014 if (sata_pmp_attached(ap)) {
1015 context = readl(port + PORT_CONTEXT);
1016 pmp = (context >> 5) & 0xf;
1017
1018 if (pmp < ap->nr_pmp_links) {
1019 link = &ap->pmp_link[pmp];
1020 ehi = &link->eh_info;
1021 qc = ata_qc_from_tag(ap, link->active_tag);
1022
1023 ata_ehi_clear_desc(ehi);
1024 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1025 irq_stat);
1026 } else {
1027 err_mask |= AC_ERR_HSM;
1028 action |= ATA_EH_RESET;
1029 freeze = 1;
1030 }
1031 } else
1032 qc = ata_qc_from_tag(ap, link->active_tag);
1033
1034 /* analyze CMD_ERR */
1035 cerr = readl(port + PORT_CMD_ERR);
1036 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1037 ci = &sil24_cerr_db[cerr];
1038
1039 if (ci && ci->desc) {
1040 err_mask |= ci->err_mask;
1041 action |= ci->action;
1042 if (action & ATA_EH_RESET)
1043 freeze = 1;
1044 ata_ehi_push_desc(ehi, "%s", ci->desc);
1045 } else {
1046 err_mask |= AC_ERR_OTHER;
1047 action |= ATA_EH_RESET;
1048 freeze = 1;
1049 ata_ehi_push_desc(ehi, "unknown command error %d",
1050 cerr);
1051 }
1052
1053 /* record error info */
1054 if (qc)
1055 qc->err_mask |= err_mask;
1056 else
1057 ehi->err_mask |= err_mask;
1058
1059 ehi->action |= action;
1060
1061 /* if PMP, resume */
1062 if (sata_pmp_attached(ap))
1063 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1064 }
1065
1066 /* freeze or abort */
1067 if (freeze)
1068 ata_port_freeze(ap);
1069 else if (abort) {
1070 if (qc)
1071 ata_link_abort(qc->dev->link);
1072 else
1073 ata_port_abort(ap);
1074 }
1075 }
1076
1077 static inline void sil24_host_intr(struct ata_port *ap)
1078 {
1079 void __iomem *port = sil24_port_base(ap);
1080 u32 slot_stat, qc_active;
1081 int rc;
1082
1083 /* If PCIX_IRQ_WOC, there's an inherent race window between
1084 * clearing IRQ pending status and reading PORT_SLOT_STAT
1085 * which may cause spurious interrupts afterwards. This is
1086 * unavoidable and much better than losing interrupts which
1087 * happens if IRQ pending is cleared after reading
1088 * PORT_SLOT_STAT.
1089 */
1090 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1091 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1092
1093 slot_stat = readl(port + PORT_SLOT_STAT);
1094
1095 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1096 sil24_error_intr(ap);
1097 return;
1098 }
1099
1100 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1101 rc = ata_qc_complete_multiple(ap, qc_active);
1102 if (rc > 0)
1103 return;
1104 if (rc < 0) {
1105 struct ata_eh_info *ehi = &ap->link.eh_info;
1106 ehi->err_mask |= AC_ERR_HSM;
1107 ehi->action |= ATA_EH_RESET;
1108 ata_port_freeze(ap);
1109 return;
1110 }
1111
1112 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1113 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1114 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1115 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1116 slot_stat, ap->link.active_tag, ap->link.sactive);
1117 }
1118
1119 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1120 {
1121 struct ata_host *host = dev_instance;
1122 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1123 unsigned handled = 0;
1124 u32 status;
1125 int i;
1126
1127 status = readl(host_base + HOST_IRQ_STAT);
1128
1129 if (status == 0xffffffff) {
1130 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1131 "PCI fault or device removal?\n");
1132 goto out;
1133 }
1134
1135 if (!(status & IRQ_STAT_4PORTS))
1136 goto out;
1137
1138 spin_lock(&host->lock);
1139
1140 for (i = 0; i < host->n_ports; i++)
1141 if (status & (1 << i)) {
1142 struct ata_port *ap = host->ports[i];
1143 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1144 sil24_host_intr(ap);
1145 handled++;
1146 } else
1147 printk(KERN_ERR DRV_NAME
1148 ": interrupt from disabled port %d\n", i);
1149 }
1150
1151 spin_unlock(&host->lock);
1152 out:
1153 return IRQ_RETVAL(handled);
1154 }
1155
1156 static void sil24_error_handler(struct ata_port *ap)
1157 {
1158 struct sil24_port_priv *pp = ap->private_data;
1159
1160 if (sil24_init_port(ap))
1161 ata_eh_freeze_port(ap);
1162
1163 sata_pmp_error_handler(ap);
1164
1165 pp->do_port_rst = 0;
1166 }
1167
1168 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1169 {
1170 struct ata_port *ap = qc->ap;
1171
1172 /* make DMA engine forget about the failed command */
1173 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1174 ata_eh_freeze_port(ap);
1175 }
1176
1177 static int sil24_port_start(struct ata_port *ap)
1178 {
1179 struct device *dev = ap->host->dev;
1180 struct sil24_port_priv *pp;
1181 union sil24_cmd_block *cb;
1182 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1183 dma_addr_t cb_dma;
1184
1185 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1186 if (!pp)
1187 return -ENOMEM;
1188
1189 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1190 if (!cb)
1191 return -ENOMEM;
1192 memset(cb, 0, cb_size);
1193
1194 pp->cmd_block = cb;
1195 pp->cmd_block_dma = cb_dma;
1196
1197 ap->private_data = pp;
1198
1199 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1200 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1201
1202 return 0;
1203 }
1204
1205 static void sil24_init_controller(struct ata_host *host)
1206 {
1207 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1208 u32 tmp;
1209 int i;
1210
1211 /* GPIO off */
1212 writel(0, host_base + HOST_FLASH_CMD);
1213
1214 /* clear global reset & mask interrupts during initialization */
1215 writel(0, host_base + HOST_CTRL);
1216
1217 /* init ports */
1218 for (i = 0; i < host->n_ports; i++) {
1219 struct ata_port *ap = host->ports[i];
1220 void __iomem *port = sil24_port_base(ap);
1221
1222
1223 /* Initial PHY setting */
1224 writel(0x20c, port + PORT_PHY_CFG);
1225
1226 /* Clear port RST */
1227 tmp = readl(port + PORT_CTRL_STAT);
1228 if (tmp & PORT_CS_PORT_RST) {
1229 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1230 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1231 PORT_CS_PORT_RST,
1232 PORT_CS_PORT_RST, 10, 100);
1233 if (tmp & PORT_CS_PORT_RST)
1234 dev_printk(KERN_ERR, host->dev,
1235 "failed to clear port RST\n");
1236 }
1237
1238 /* configure port */
1239 sil24_config_port(ap);
1240 }
1241
1242 /* Turn on interrupts */
1243 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1244 }
1245
1246 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1247 {
1248 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1249 static int printed_version;
1250 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1251 const struct ata_port_info *ppi[] = { &pi, NULL };
1252 void __iomem * const *iomap;
1253 struct ata_host *host;
1254 int rc;
1255 u32 tmp;
1256
1257 /* cause link error if sil24_cmd_block is sized wrongly */
1258 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1259 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1260
1261 if (!printed_version++)
1262 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1263
1264 /* acquire resources */
1265 rc = pcim_enable_device(pdev);
1266 if (rc)
1267 return rc;
1268
1269 rc = pcim_iomap_regions(pdev,
1270 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1271 DRV_NAME);
1272 if (rc)
1273 return rc;
1274 iomap = pcim_iomap_table(pdev);
1275
1276 /* apply workaround for completion IRQ loss on PCI-X errata */
1277 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1278 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1279 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1280 dev_printk(KERN_INFO, &pdev->dev,
1281 "Applying completion IRQ loss on PCI-X "
1282 "errata fix\n");
1283 else
1284 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1285 }
1286
1287 /* allocate and fill host */
1288 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1289 SIL24_FLAG2NPORTS(ppi[0]->flags));
1290 if (!host)
1291 return -ENOMEM;
1292 host->iomap = iomap;
1293
1294 /* configure and activate the device */
1295 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1296 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1297 if (rc) {
1298 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1299 if (rc) {
1300 dev_printk(KERN_ERR, &pdev->dev,
1301 "64-bit DMA enable failed\n");
1302 return rc;
1303 }
1304 }
1305 } else {
1306 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1307 if (rc) {
1308 dev_printk(KERN_ERR, &pdev->dev,
1309 "32-bit DMA enable failed\n");
1310 return rc;
1311 }
1312 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1313 if (rc) {
1314 dev_printk(KERN_ERR, &pdev->dev,
1315 "32-bit consistent DMA enable failed\n");
1316 return rc;
1317 }
1318 }
1319
1320 sil24_init_controller(host);
1321
1322 pci_set_master(pdev);
1323 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1324 &sil24_sht);
1325 }
1326
1327 #ifdef CONFIG_PM
1328 static int sil24_pci_device_resume(struct pci_dev *pdev)
1329 {
1330 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1331 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1332 int rc;
1333
1334 rc = ata_pci_device_do_resume(pdev);
1335 if (rc)
1336 return rc;
1337
1338 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1339 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1340
1341 sil24_init_controller(host);
1342
1343 ata_host_resume(host);
1344
1345 return 0;
1346 }
1347
1348 static int sil24_port_resume(struct ata_port *ap)
1349 {
1350 sil24_config_pmp(ap, ap->nr_pmp_links);
1351 return 0;
1352 }
1353 #endif
1354
1355 static int __init sil24_init(void)
1356 {
1357 return pci_register_driver(&sil24_pci_driver);
1358 }
1359
1360 static void __exit sil24_exit(void)
1361 {
1362 pci_unregister_driver(&sil24_pci_driver);
1363 }
1364
1365 MODULE_AUTHOR("Tejun Heo");
1366 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1367 MODULE_LICENSE("GPL");
1368 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1369
1370 module_init(sil24_init);
1371 module_exit(sil24_exit);
A Kernel for the Dreambox dm7025.