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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / media / video / cx23885 / cx23885-core.c
blobf24abcd06dea0eb1027630be34ca934daa87d6e8
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
32
33 #include "cx23885.h"
34
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37 MODULE_LICENSE("GPL");
38
39 static unsigned int debug;
40 module_param(debug,int,0644);
41 MODULE_PARM_DESC(debug,"enable debug messages");
42
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card,"card type");
46
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
50 } while (0)
51
52 static unsigned int cx23885_devcount;
53
54 static DEFINE_MUTEX(devlist);
55 LIST_HEAD(cx23885_devlist);
56
57 #define NO_SYNC_LINE (-1U)
58
59 /* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
61 * CX23887 Assumptions
62 * 1 line = 16 bytes of CDT
63 * cmds size = 80
64 * cdt size = 16 * linesize
65 * iqsize = 64
66 * maxlines = 6
67 *
68 * Address Space:
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
77 */
78
79 static struct sram_channel cx23887_sram_channels[] = {
80 [SRAM_CH01] = {
81 .name = "VID A",
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x105b0,
84 .cdt = 0x107b0,
85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10780,
108 .cdt = 0x10400,
109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680,
144 .cdt = 0x108d0,
145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188 };
189
190 static int cx23885_risc_decode(u32 risc)
191 {
192 static char *instr[16] = {
193 [RISC_SYNC >> 28] = "sync",
194 [RISC_WRITE >> 28] = "write",
195 [RISC_WRITEC >> 28] = "writec",
196 [RISC_READ >> 28] = "read",
197 [RISC_READC >> 28] = "readc",
198 [RISC_JUMP >> 28] = "jump",
199 [RISC_SKIP >> 28] = "skip",
200 [RISC_WRITERM >> 28] = "writerm",
201 [RISC_WRITECM >> 28] = "writecm",
202 [RISC_WRITECR >> 28] = "writecr",
203 };
204 static int incr[16] = {
205 [RISC_WRITE >> 28] = 3,
206 [RISC_JUMP >> 28] = 3,
207 [RISC_SKIP >> 28] = 1,
208 [RISC_SYNC >> 28] = 1,
209 [RISC_WRITERM >> 28] = 3,
210 [RISC_WRITECM >> 28] = 3,
211 [RISC_WRITECR >> 28] = 4,
212 };
213 static char *bits[] = {
214 "12", "13", "14", "resync",
215 "cnt0", "cnt1", "18", "19",
216 "20", "21", "22", "23",
217 "irq1", "irq2", "eol", "sol",
218 };
219 int i;
220
221 printk("0x%08x [ %s", risc,
222 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
223 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
224 if (risc & (1 << (i + 12)))
225 printk(" %s", bits[i]);
226 printk(" count=%d ]\n", risc & 0xfff);
227 return incr[risc >> 28] ? incr[risc >> 28] : 1;
228 }
229
230 void cx23885_wakeup(struct cx23885_tsport *port,
231 struct cx23885_dmaqueue *q, u32 count)
232 {
233 struct cx23885_dev *dev = port->dev;
234 struct cx23885_buffer *buf;
235 int bc;
236
237 for (bc = 0;; bc++) {
238 if (list_empty(&q->active))
239 break;
240 buf = list_entry(q->active.next,
241 struct cx23885_buffer, vb.queue);
242
243 /* count comes from the hw and is is 16bit wide --
244 * this trick handles wrap-arounds correctly for
245 * up to 32767 buffers in flight... */
246 if ((s16) (count - buf->count) < 0)
247 break;
248
249 do_gettimeofday(&buf->vb.ts);
250 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
251 count, buf->count);
252 buf->vb.state = VIDEOBUF_DONE;
253 list_del(&buf->vb.queue);
254 wake_up(&buf->vb.done);
255 }
256 if (list_empty(&q->active)) {
257 del_timer(&q->timeout);
258 } else {
259 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
260 }
261 if (bc != 1)
262 printk("%s: %d buffers handled (should be 1)\n",
263 __func__, bc);
264 }
265
266 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
267 struct sram_channel *ch,
268 unsigned int bpl, u32 risc)
269 {
270 unsigned int i, lines;
271 u32 cdt;
272
273 if (ch->cmds_start == 0)
274 {
275 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
276 ch->name);
277 cx_write(ch->ptr1_reg, 0);
278 cx_write(ch->ptr2_reg, 0);
279 cx_write(ch->cnt2_reg, 0);
280 cx_write(ch->cnt1_reg, 0);
281 return 0;
282 } else {
283 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
284 ch->name);
285 }
286
287 bpl = (bpl + 7) & ~7; /* alignment */
288 cdt = ch->cdt;
289 lines = ch->fifo_size / bpl;
290 if (lines > 6)
291 lines = 6;
292 BUG_ON(lines < 2);
293
294 cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
295 cx_write(8 + 4, cpu_to_le32(8) );
296 cx_write(8 + 8, cpu_to_le32(0) );
297
298 /* write CDT */
299 for (i = 0; i < lines; i++) {
300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
301 ch->fifo_start + bpl*i);
302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
303 cx_write(cdt + 16*i + 4, 0);
304 cx_write(cdt + 16*i + 8, 0);
305 cx_write(cdt + 16*i + 12, 0);
306 }
307
308 /* write CMDS */
309 if (ch->jumponly)
310 cx_write(ch->cmds_start + 0, 8);
311 else
312 cx_write(ch->cmds_start + 0, risc);
313 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
314 cx_write(ch->cmds_start + 8, cdt);
315 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
316 cx_write(ch->cmds_start + 16, ch->ctrl_start);
317 if (ch->jumponly)
318 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
319 else
320 cx_write(ch->cmds_start + 20, 64 >> 2);
321 for (i = 24; i < 80; i += 4)
322 cx_write(ch->cmds_start + i, 0);
323
324 /* fill registers */
325 cx_write(ch->ptr1_reg, ch->fifo_start);
326 cx_write(ch->ptr2_reg, cdt);
327 cx_write(ch->cnt2_reg, (lines*16) >> 3);
328 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
329
330 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
331 dev->bridge,
332 ch->name,
333 bpl,
334 lines);
335
336 return 0;
337 }
338
339 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
340 struct sram_channel *ch)
341 {
342 static char *name[] = {
343 "init risc lo",
344 "init risc hi",
345 "cdt base",
346 "cdt size",
347 "iq base",
348 "iq size",
349 "risc pc lo",
350 "risc pc hi",
351 "iq wr ptr",
352 "iq rd ptr",
353 "cdt current",
354 "pci target lo",
355 "pci target hi",
356 "line / byte",
357 };
358 u32 risc;
359 unsigned int i, j, n;
360
361 printk("%s: %s - dma channel status dump\n",
362 dev->name, ch->name);
363 for (i = 0; i < ARRAY_SIZE(name); i++)
364 printk("%s: cmds: %-15s: 0x%08x\n",
365 dev->name, name[i],
366 cx_read(ch->cmds_start + 4*i));
367
368 for (i = 0; i < 4; i++) {
369 risc = cx_read(ch->cmds_start + 4 * (i + 14));
370 printk("%s: risc%d: ", dev->name, i);
371 cx23885_risc_decode(risc);
372 }
373 for (i = 0; i < (64 >> 2); i += n) {
374 risc = cx_read(ch->ctrl_start + 4 * i);
375 /* No consideration for bits 63-32 */
376
377 printk("%s: (0x%08x) iq %x: ", dev->name,
378 ch->ctrl_start + 4 * i, i);
379 n = cx23885_risc_decode(risc);
380 for (j = 1; j < n; j++) {
381 risc = cx_read(ch->ctrl_start + 4 * (i + j));
382 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
383 dev->name, i+j, risc, j);
384 }
385 }
386
387 printk("%s: fifo: 0x%08x -> 0x%x\n",
388 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
389 printk("%s: ctrl: 0x%08x -> 0x%x\n",
390 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
391 printk("%s: ptr1_reg: 0x%08x\n",
392 dev->name, cx_read(ch->ptr1_reg));
393 printk("%s: ptr2_reg: 0x%08x\n",
394 dev->name, cx_read(ch->ptr2_reg));
395 printk("%s: cnt1_reg: 0x%08x\n",
396 dev->name, cx_read(ch->cnt1_reg));
397 printk("%s: cnt2_reg: 0x%08x\n",
398 dev->name, cx_read(ch->cnt2_reg));
399 }
400
401 static void cx23885_risc_disasm(struct cx23885_tsport *port,
402 struct btcx_riscmem *risc)
403 {
404 struct cx23885_dev *dev = port->dev;
405 unsigned int i, j, n;
406
407 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
408 dev->name, risc->cpu, (unsigned long)risc->dma);
409 for (i = 0; i < (risc->size >> 2); i += n) {
410 printk("%s: %04d: ", dev->name, i);
411 n = cx23885_risc_decode(risc->cpu[i]);
412 for (j = 1; j < n; j++)
413 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
414 dev->name, i + j, risc->cpu[i + j], j);
415 if (risc->cpu[i] == RISC_JUMP)
416 break;
417 }
418 }
419
420 static void cx23885_shutdown(struct cx23885_dev *dev)
421 {
422 /* disable RISC controller */
423 cx_write(DEV_CNTRL2, 0);
424
425 /* Disable all IR activity */
426 cx_write(IR_CNTRL_REG, 0);
427
428 /* Disable Video A/B activity */
429 cx_write(VID_A_DMA_CTL, 0);
430 cx_write(VID_B_DMA_CTL, 0);
431 cx_write(VID_C_DMA_CTL, 0);
432
433 /* Disable Audio activity */
434 cx_write(AUD_INT_DMA_CTL, 0);
435 cx_write(AUD_EXT_DMA_CTL, 0);
436
437 /* Disable Serial port */
438 cx_write(UART_CTL, 0);
439
440 /* Disable Interrupts */
441 cx_write(PCI_INT_MSK, 0);
442 cx_write(VID_A_INT_MSK, 0);
443 cx_write(VID_B_INT_MSK, 0);
444 cx_write(VID_C_INT_MSK, 0);
445 cx_write(AUDIO_INT_INT_MSK, 0);
446 cx_write(AUDIO_EXT_INT_MSK, 0);
447
448 }
449
450 static void cx23885_reset(struct cx23885_dev *dev)
451 {
452 dprintk(1, "%s()\n", __func__);
453
454 cx23885_shutdown(dev);
455
456 cx_write(PCI_INT_STAT, 0xffffffff);
457 cx_write(VID_A_INT_STAT, 0xffffffff);
458 cx_write(VID_B_INT_STAT, 0xffffffff);
459 cx_write(VID_C_INT_STAT, 0xffffffff);
460 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
461 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
462 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
463
464 mdelay(100);
465
466 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
467 720*4, 0);
468 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
469 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
470 188*4, 0);
471 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
472 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
473 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
474 188*4, 0);
475 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
476 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
477 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
478
479 cx23885_gpio_setup(dev);
480 }
481
482
483 static int cx23885_pci_quirks(struct cx23885_dev *dev)
484 {
485 dprintk(1, "%s()\n", __func__);
486
487 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
488 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
489 * occur on the cx23887 bridge.
490 */
491 if(dev->bridge == CX23885_BRIDGE_885)
492 cx_clear(RDR_TLCTL0, 1 << 4);
493
494 return 0;
495 }
496
497 static int get_resources(struct cx23885_dev *dev)
498 {
499 if (request_mem_region(pci_resource_start(dev->pci,0),
500 pci_resource_len(dev->pci,0),
501 dev->name))
502 return 0;
503
504 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
505 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
506
507 return -EBUSY;
508 }
509
510 static void cx23885_timeout(unsigned long data);
511 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
512 u32 reg, u32 mask, u32 value);
513
514 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
515 {
516 dprintk(1, "%s(portno=%d)\n", __func__, portno);
517
518 /* Transport bus init dma queue - Common settings */
519 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
520 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
521 port->vld_misc_val = 0x0;
522 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
523
524 spin_lock_init(&port->slock);
525 port->dev = dev;
526 port->nr = portno;
527
528 INIT_LIST_HEAD(&port->mpegq.active);
529 INIT_LIST_HEAD(&port->mpegq.queued);
530 port->mpegq.timeout.function = cx23885_timeout;
531 port->mpegq.timeout.data = (unsigned long)port;
532 init_timer(&port->mpegq.timeout);
533
534 switch(portno) {
535 case 1:
536 port->reg_gpcnt = VID_B_GPCNT;
537 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
538 port->reg_dma_ctl = VID_B_DMA_CTL;
539 port->reg_lngth = VID_B_LNGTH;
540 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
541 port->reg_gen_ctrl = VID_B_GEN_CTL;
542 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
543 port->reg_sop_status = VID_B_SOP_STATUS;
544 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
545 port->reg_vld_misc = VID_B_VLD_MISC;
546 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
547 port->reg_src_sel = VID_B_SRC_SEL;
548 port->reg_ts_int_msk = VID_B_INT_MSK;
549 port->reg_ts_int_stat = VID_B_INT_STAT;
550 port->sram_chno = SRAM_CH03; /* VID_B */
551 port->pci_irqmask = 0x02; /* VID_B bit1 */
552 break;
553 case 2:
554 port->reg_gpcnt = VID_C_GPCNT;
555 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
556 port->reg_dma_ctl = VID_C_DMA_CTL;
557 port->reg_lngth = VID_C_LNGTH;
558 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
559 port->reg_gen_ctrl = VID_C_GEN_CTL;
560 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
561 port->reg_sop_status = VID_C_SOP_STATUS;
562 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
563 port->reg_vld_misc = VID_C_VLD_MISC;
564 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
565 port->reg_src_sel = 0;
566 port->reg_ts_int_msk = VID_C_INT_MSK;
567 port->reg_ts_int_stat = VID_C_INT_STAT;
568 port->sram_chno = SRAM_CH06; /* VID_C */
569 port->pci_irqmask = 0x04; /* VID_C bit2 */
570 break;
571 default:
572 BUG();
573 }
574
575 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
576 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
577
578 return 0;
579 }
580
581 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
582 {
583 switch (cx_read(RDR_CFG2) & 0xff) {
584 case 0x00:
585 /* cx23885 */
586 dev->hwrevision = 0xa0;
587 break;
588 case 0x01:
589 /* CX23885-12Z */
590 dev->hwrevision = 0xa1;
591 break;
592 case 0x02:
593 /* CX23885-13Z */
594 dev->hwrevision = 0xb0;
595 break;
596 case 0x03:
597 /* CX23888-22Z */
598 dev->hwrevision = 0xc0;
599 break;
600 case 0x0e:
601 /* CX23887-15Z */
602 dev->hwrevision = 0xc0;
603 case 0x0f:
604 /* CX23887-14Z */
605 dev->hwrevision = 0xb1;
606 break;
607 default:
608 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
609 __func__, dev->hwrevision);
610 }
611 if (dev->hwrevision)
612 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
613 __func__, dev->hwrevision);
614 else
615 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
616 __func__, dev->hwrevision);
617 }
618
619 static int cx23885_dev_setup(struct cx23885_dev *dev)
620 {
621 int i;
622
623 mutex_init(&dev->lock);
624
625 atomic_inc(&dev->refcount);
626
627 dev->nr = cx23885_devcount++;
628 dev->sram_channels = cx23887_sram_channels;
629 sprintf(dev->name, "cx23885[%d]", dev->nr);
630
631 mutex_lock(&devlist);
632 list_add_tail(&dev->devlist, &cx23885_devlist);
633 mutex_unlock(&devlist);
634
635 /* Configure the internal memory */
636 if(dev->pci->device == 0x8880) {
637 dev->bridge = CX23885_BRIDGE_887;
638 /* Apply a sensible clock frequency for the PCIe bridge */
639 dev->clk_freq = 25000000;
640 } else
641 if(dev->pci->device == 0x8852) {
642 dev->bridge = CX23885_BRIDGE_885;
643 /* Apply a sensible clock frequency for the PCIe bridge */
644 dev->clk_freq = 28000000;
645 } else
646 BUG();
647
648 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
649 __func__, dev->bridge);
650
651 /* board config */
652 dev->board = UNSET;
653 if (card[dev->nr] < cx23885_bcount)
654 dev->board = card[dev->nr];
655 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
656 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
657 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
658 dev->board = cx23885_subids[i].card;
659 if (UNSET == dev->board) {
660 dev->board = CX23885_BOARD_UNKNOWN;
661 cx23885_card_list(dev);
662 }
663
664 /* If the user specific a clk freq override, apply it */
665 if (cx23885_boards[dev->board].clk_freq > 0)
666 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
667
668 dev->pci_bus = dev->pci->bus->number;
669 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
670 dev->pci_irqmask = 0x001f00;
671
672 /* External Master 1 Bus */
673 dev->i2c_bus[0].nr = 0;
674 dev->i2c_bus[0].dev = dev;
675 dev->i2c_bus[0].reg_stat = I2C1_STAT;
676 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
677 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
678 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
679 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
680 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
681
682 /* External Master 2 Bus */
683 dev->i2c_bus[1].nr = 1;
684 dev->i2c_bus[1].dev = dev;
685 dev->i2c_bus[1].reg_stat = I2C2_STAT;
686 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
687 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
688 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
689 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
690 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
691
692 /* Internal Master 3 Bus */
693 dev->i2c_bus[2].nr = 2;
694 dev->i2c_bus[2].dev = dev;
695 dev->i2c_bus[2].reg_stat = I2C3_STAT;
696 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
697 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
698 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
699 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
700 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
701
702 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
703 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
704 cx23885_init_tsport(dev, &dev->ts1, 1);
705
706 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
707 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
708 cx23885_init_tsport(dev, &dev->ts2, 2);
709
710 if (get_resources(dev) < 0) {
711 printk(KERN_ERR "CORE %s No more PCIe resources for "
712 "subsystem: %04x:%04x\n",
713 dev->name, dev->pci->subsystem_vendor,
714 dev->pci->subsystem_device);
715
716 cx23885_devcount--;
717 return -ENODEV;
718 }
719
720 /* PCIe stuff */
721 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
722 pci_resource_len(dev->pci,0));
723
724 dev->bmmio = (u8 __iomem *)dev->lmmio;
725
726 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
727 dev->name, dev->pci->subsystem_vendor,
728 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
729 dev->board, card[dev->nr] == dev->board ?
730 "insmod option" : "autodetected");
731
732 cx23885_pci_quirks(dev);
733
734 /* Assume some sensible defaults */
735 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
736 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
737 dev->radio_type = cx23885_boards[dev->board].radio_type;
738 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
739
740 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
741 __func__, dev->tuner_type, dev->tuner_addr);
742 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
743 __func__, dev->radio_type, dev->radio_addr);
744
745 /* init hardware */
746 cx23885_reset(dev);
747
748 cx23885_i2c_register(&dev->i2c_bus[0]);
749 cx23885_i2c_register(&dev->i2c_bus[1]);
750 cx23885_i2c_register(&dev->i2c_bus[2]);
751 cx23885_card_setup(dev);
752 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
753 cx23885_ir_init(dev);
754
755 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
756 if (cx23885_video_register(dev) < 0) {
757 printk(KERN_ERR "%s() Failed to register analog "
758 "video adapters on VID_A\n", __func__);
759 }
760 }
761
762 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
763 if (cx23885_dvb_register(&dev->ts1) < 0) {
764 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
765 __func__);
766 }
767 } else
768 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
769 if (cx23885_417_register(dev) < 0) {
770 printk(KERN_ERR
771 "%s() Failed to register 417 on VID_B\n",
772 __func__);
773 }
774 }
775
776 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
777 if (cx23885_dvb_register(&dev->ts2) < 0) {
778 printk(KERN_ERR
779 "%s() Failed to register dvb on VID_C\n",
780 __func__);
781 }
782 } else
783 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
784 if (cx23885_417_register(dev) < 0) {
785 printk(KERN_ERR
786 "%s() Failed to register 417 on VID_C\n",
787 __func__);
788 }
789 }
790
791 cx23885_dev_checkrevision(dev);
792
793 return 0;
794 }
795
796 static void cx23885_dev_unregister(struct cx23885_dev *dev)
797 {
798 release_mem_region(pci_resource_start(dev->pci,0),
799 pci_resource_len(dev->pci,0));
800
801 if (!atomic_dec_and_test(&dev->refcount))
802 return;
803
804 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
805 cx23885_video_unregister(dev);
806
807 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
808 cx23885_dvb_unregister(&dev->ts1);
809
810 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
811 cx23885_417_unregister(dev);
812
813 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
814 cx23885_dvb_unregister(&dev->ts2);
815
816 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
817 cx23885_417_unregister(dev);
818
819 cx23885_i2c_unregister(&dev->i2c_bus[2]);
820 cx23885_i2c_unregister(&dev->i2c_bus[1]);
821 cx23885_i2c_unregister(&dev->i2c_bus[0]);
822
823 iounmap(dev->lmmio);
824 }
825
826 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
827 unsigned int offset, u32 sync_line,
828 unsigned int bpl, unsigned int padding,
829 unsigned int lines)
830 {
831 struct scatterlist *sg;
832 unsigned int line, todo;
833
834 /* sync instruction */
835 if (sync_line != NO_SYNC_LINE)
836 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
837
838 /* scan lines */
839 sg = sglist;
840 for (line = 0; line < lines; line++) {
841 while (offset && offset >= sg_dma_len(sg)) {
842 offset -= sg_dma_len(sg);
843 sg++;
844 }
845 if (bpl <= sg_dma_len(sg)-offset) {
846 /* fits into current chunk */
847 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
848 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
849 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
850 offset+=bpl;
851 } else {
852 /* scanline needs to be split */
853 todo = bpl;
854 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
855 (sg_dma_len(sg)-offset));
856 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
857 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
858 todo -= (sg_dma_len(sg)-offset);
859 offset = 0;
860 sg++;
861 while (todo > sg_dma_len(sg)) {
862 *(rp++)=cpu_to_le32(RISC_WRITE|
863 sg_dma_len(sg));
864 *(rp++)=cpu_to_le32(sg_dma_address(sg));
865 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
866 todo -= sg_dma_len(sg);
867 sg++;
868 }
869 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
870 *(rp++)=cpu_to_le32(sg_dma_address(sg));
871 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
872 offset += todo;
873 }
874 offset += padding;
875 }
876
877 return rp;
878 }
879
880 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
881 struct scatterlist *sglist, unsigned int top_offset,
882 unsigned int bottom_offset, unsigned int bpl,
883 unsigned int padding, unsigned int lines)
884 {
885 u32 instructions, fields;
886 u32 *rp;
887 int rc;
888
889 fields = 0;
890 if (UNSET != top_offset)
891 fields++;
892 if (UNSET != bottom_offset)
893 fields++;
894
895 /* estimate risc mem: worst case is one write per page border +
896 one write per scan line + syncs + jump (all 2 dwords). Padding
897 can cause next bpl to start close to a page border. First DMA
898 region may be smaller than PAGE_SIZE */
899 /* write and jump need and extra dword */
900 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
901 instructions += 2;
902 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
903 return rc;
904
905 /* write risc instructions */
906 rp = risc->cpu;
907 if (UNSET != top_offset)
908 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
909 bpl, padding, lines);
910 if (UNSET != bottom_offset)
911 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
912 bpl, padding, lines);
913
914 /* save pointer to jmp instruction address */
915 risc->jmp = rp;
916 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
917 return 0;
918 }
919
920 static int cx23885_risc_databuffer(struct pci_dev *pci,
921 struct btcx_riscmem *risc,
922 struct scatterlist *sglist,
923 unsigned int bpl,
924 unsigned int lines)
925 {
926 u32 instructions;
927 u32 *rp;
928 int rc;
929
930 /* estimate risc mem: worst case is one write per page border +
931 one write per scan line + syncs + jump (all 2 dwords). Here
932 there is no padding and no sync. First DMA region may be smaller
933 than PAGE_SIZE */
934 /* Jump and write need an extra dword */
935 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
936 instructions += 1;
937
938 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
939 return rc;
940
941 /* write risc instructions */
942 rp = risc->cpu;
943 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
944
945 /* save pointer to jmp instruction address */
946 risc->jmp = rp;
947 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
948 return 0;
949 }
950
951 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
952 u32 reg, u32 mask, u32 value)
953 {
954 u32 *rp;
955 int rc;
956
957 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
958 return rc;
959
960 /* write risc instructions */
961 rp = risc->cpu;
962 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
963 *(rp++) = cpu_to_le32(reg);
964 *(rp++) = cpu_to_le32(value);
965 *(rp++) = cpu_to_le32(mask);
966 *(rp++) = cpu_to_le32(RISC_JUMP);
967 *(rp++) = cpu_to_le32(risc->dma);
968 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
969 return 0;
970 }
971
972 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
973 {
974 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
975
976 BUG_ON(in_interrupt());
977 videobuf_waiton(&buf->vb, 0, 0);
978 videobuf_dma_unmap(q, dma);
979 videobuf_dma_free(dma);
980 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
981 buf->vb.state = VIDEOBUF_NEEDS_INIT;
982 }
983
984 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
985 {
986 struct cx23885_dev *dev = port->dev;
987
988 dprintk(1, "%s() Register Dump\n", __func__);
989 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
990 cx_read(DEV_CNTRL2));
991 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
992 cx_read(PCI_INT_MSK));
993 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
994 cx_read(AUDIO_INT_INT_MSK));
995 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
996 cx_read(AUD_INT_DMA_CTL));
997 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
998 cx_read(AUDIO_EXT_INT_MSK));
999 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1000 cx_read(AUD_EXT_DMA_CTL));
1001 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1002 cx_read(PAD_CTRL));
1003 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1004 cx_read(ALT_PIN_OUT_SEL));
1005 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1006 cx_read(GPIO2));
1007 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1008 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1009 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1010 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1011 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1012 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1013 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1014 port->reg_src_sel, cx_read(port->reg_src_sel));
1015 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1016 port->reg_lngth, cx_read(port->reg_lngth));
1017 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1018 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1019 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1020 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1021 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1022 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1023 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1024 port->reg_sop_status, cx_read(port->reg_sop_status));
1025 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1026 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1027 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1028 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1029 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1030 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1031 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1032 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1033 }
1034
1035 static int cx23885_start_dma(struct cx23885_tsport *port,
1036 struct cx23885_dmaqueue *q,
1037 struct cx23885_buffer *buf)
1038 {
1039 struct cx23885_dev *dev = port->dev;
1040 u32 reg;
1041
1042 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1043 buf->vb.width, buf->vb.height, buf->vb.field);
1044
1045 /* setup fifo + format */
1046 cx23885_sram_channel_setup(dev,
1047 &dev->sram_channels[ port->sram_chno ],
1048 port->ts_packet_size, buf->risc.dma);
1049 if(debug > 5) {
1050 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1051 cx23885_risc_disasm(port, &buf->risc);
1052 }
1053
1054 /* write TS length to chip */
1055 cx_write(port->reg_lngth, buf->vb.width);
1056
1057 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1058 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1059 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1060 __func__,
1061 cx23885_boards[dev->board].portb,
1062 cx23885_boards[dev->board].portc );
1063 return -EINVAL;
1064 }
1065
1066 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1067 cx23885_av_clk(dev, 0);
1068
1069 udelay(100);
1070
1071 /* If the port supports SRC SELECT, configure it */
1072 if(port->reg_src_sel)
1073 cx_write(port->reg_src_sel, port->src_sel_val);
1074
1075 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1076 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1077 cx_write(port->reg_vld_misc, port->vld_misc_val);
1078 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1079 udelay(100);
1080
1081 // NOTE: this is 2 (reserved) for portb, does it matter?
1082 /* reset counter to zero */
1083 cx_write(port->reg_gpcnt_ctl, 3);
1084 q->count = 1;
1085
1086 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
1087
1088 reg = cx_read(PAD_CTRL);
1089 reg = reg & ~0x1; /* Clear TS1_OE */
1090
1091 /* FIXME, bit 2 writing here is questionable */
1092 /* set TS1_SOP_OE and TS1_OE_HI */
1093 reg = reg | 0xa;
1094 cx_write(PAD_CTRL, reg);
1095
1096 /* FIXME and these two registers should be documented. */
1097 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1098 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1099 }
1100
1101 switch(dev->bridge) {
1102 case CX23885_BRIDGE_885:
1103 case CX23885_BRIDGE_887:
1104 /* enable irqs */
1105 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
1106 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1107 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1108 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1109 break;
1110 default:
1111 BUG();
1112 }
1113
1114 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1115
1116 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1117 cx23885_av_clk(dev, 1);
1118
1119 if (debug > 4)
1120 cx23885_tsport_reg_dump(port);
1121
1122 return 0;
1123 }
1124
1125 static int cx23885_stop_dma(struct cx23885_tsport *port)
1126 {
1127 struct cx23885_dev *dev = port->dev;
1128 u32 reg;
1129
1130 dprintk(1, "%s()\n", __func__);
1131
1132 /* Stop interrupts and DMA */
1133 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1134 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1135
1136 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
1137
1138 reg = cx_read(PAD_CTRL);
1139
1140 /* Set TS1_OE */
1141 reg = reg | 0x1;
1142
1143 /* clear TS1_SOP_OE and TS1_OE_HI */
1144 reg = reg & ~0xa;
1145 cx_write(PAD_CTRL, reg);
1146 cx_write(port->reg_src_sel, 0);
1147 cx_write(port->reg_gen_ctrl, 8);
1148
1149 }
1150
1151 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1152 cx23885_av_clk(dev, 0);
1153
1154 return 0;
1155 }
1156
1157 int cx23885_restart_queue(struct cx23885_tsport *port,
1158 struct cx23885_dmaqueue *q)
1159 {
1160 struct cx23885_dev *dev = port->dev;
1161 struct cx23885_buffer *buf;
1162
1163 dprintk(5, "%s()\n", __func__);
1164 if (list_empty(&q->active))
1165 {
1166 struct cx23885_buffer *prev;
1167 prev = NULL;
1168
1169 dprintk(5, "%s() queue is empty\n", __func__);
1170
1171 for (;;) {
1172 if (list_empty(&q->queued))
1173 return 0;
1174 buf = list_entry(q->queued.next, struct cx23885_buffer,
1175 vb.queue);
1176 if (NULL == prev) {
1177 list_del(&buf->vb.queue);
1178 list_add_tail(&buf->vb.queue, &q->active);
1179 cx23885_start_dma(port, q, buf);
1180 buf->vb.state = VIDEOBUF_ACTIVE;
1181 buf->count = q->count++;
1182 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1183 dprintk(5, "[%p/%d] restart_queue - first active\n",
1184 buf, buf->vb.i);
1185
1186 } else if (prev->vb.width == buf->vb.width &&
1187 prev->vb.height == buf->vb.height &&
1188 prev->fmt == buf->fmt) {
1189 list_del(&buf->vb.queue);
1190 list_add_tail(&buf->vb.queue, &q->active);
1191 buf->vb.state = VIDEOBUF_ACTIVE;
1192 buf->count = q->count++;
1193 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1194 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1195 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1196 buf, buf->vb.i);
1197 } else {
1198 return 0;
1199 }
1200 prev = buf;
1201 }
1202 return 0;
1203 }
1204
1205 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1206 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1207 buf, buf->vb.i);
1208 cx23885_start_dma(port, q, buf);
1209 list_for_each_entry(buf, &q->active, vb.queue)
1210 buf->count = q->count++;
1211 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1212 return 0;
1213 }
1214
1215 /* ------------------------------------------------------------------ */
1216
1217 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1218 struct cx23885_buffer *buf, enum v4l2_field field)
1219 {
1220 struct cx23885_dev *dev = port->dev;
1221 int size = port->ts_packet_size * port->ts_packet_count;
1222 int rc;
1223
1224 dprintk(1, "%s: %p\n", __func__, buf);
1225 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1226 return -EINVAL;
1227
1228 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1229 buf->vb.width = port->ts_packet_size;
1230 buf->vb.height = port->ts_packet_count;
1231 buf->vb.size = size;
1232 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1233
1234 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1235 goto fail;
1236 cx23885_risc_databuffer(dev->pci, &buf->risc,
1237 videobuf_to_dma(&buf->vb)->sglist,
1238 buf->vb.width, buf->vb.height);
1239 }
1240 buf->vb.state = VIDEOBUF_PREPARED;
1241 return 0;
1242
1243 fail:
1244 cx23885_free_buffer(q, buf);
1245 return rc;
1246 }
1247
1248 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1249 {
1250 struct cx23885_buffer *prev;
1251 struct cx23885_dev *dev = port->dev;
1252 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1253
1254 /* add jump to stopper */
1255 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1256 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1257 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1258
1259 if (list_empty(&cx88q->active)) {
1260 dprintk( 1, "queue is empty - first active\n" );
1261 list_add_tail(&buf->vb.queue, &cx88q->active);
1262 cx23885_start_dma(port, cx88q, buf);
1263 buf->vb.state = VIDEOBUF_ACTIVE;
1264 buf->count = cx88q->count++;
1265 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1266 dprintk(1, "[%p/%d] %s - first active\n",
1267 buf, buf->vb.i, __func__);
1268 } else {
1269 dprintk( 1, "queue is not empty - append to active\n" );
1270 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1271 vb.queue);
1272 list_add_tail(&buf->vb.queue, &cx88q->active);
1273 buf->vb.state = VIDEOBUF_ACTIVE;
1274 buf->count = cx88q->count++;
1275 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1276 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1277 dprintk( 1, "[%p/%d] %s - append to active\n",
1278 buf, buf->vb.i, __func__);
1279 }
1280 }
1281
1282 /* ----------------------------------------------------------- */
1283
1284 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1285 int restart)
1286 {
1287 struct cx23885_dev *dev = port->dev;
1288 struct cx23885_dmaqueue *q = &port->mpegq;
1289 struct cx23885_buffer *buf;
1290 unsigned long flags;
1291
1292 spin_lock_irqsave(&port->slock, flags);
1293 while (!list_empty(&q->active)) {
1294 buf = list_entry(q->active.next, struct cx23885_buffer,
1295 vb.queue);
1296 list_del(&buf->vb.queue);
1297 buf->vb.state = VIDEOBUF_ERROR;
1298 wake_up(&buf->vb.done);
1299 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1300 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1301 }
1302 if (restart) {
1303 dprintk(1, "restarting queue\n" );
1304 cx23885_restart_queue(port, q);
1305 }
1306 spin_unlock_irqrestore(&port->slock, flags);
1307 }
1308
1309 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1310 {
1311 struct cx23885_dev *dev = port->dev;
1312 struct cx23885_dmaqueue *q = &port->mpegq;
1313
1314 dprintk(1, "%s()\n", __FUNCTION__);
1315 del_timer_sync(&q->timeout);
1316 cx23885_stop_dma(port);
1317 do_cancel_buffers(port, "cancel", 0);
1318 }
1319
1320 static void cx23885_timeout(unsigned long data)
1321 {
1322 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1323 struct cx23885_dev *dev = port->dev;
1324
1325 dprintk(1, "%s()\n",__func__);
1326
1327 if (debug > 5)
1328 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1329
1330 cx23885_stop_dma(port);
1331 do_cancel_buffers(port, "timeout", 1);
1332 }
1333
1334 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1335 {
1336 /* FIXME: port1 assumption here. */
1337 struct cx23885_tsport *port = &dev->ts1;
1338 int count = 0;
1339 int handled = 0;
1340
1341 if (status == 0)
1342 return handled;
1343
1344 count = cx_read(port->reg_gpcnt);
1345 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1346 status, cx_read(port->reg_ts_int_msk), count);
1347
1348 if ((status & VID_B_MSK_BAD_PKT) ||
1349 (status & VID_B_MSK_OPC_ERR) ||
1350 (status & VID_B_MSK_VBI_OPC_ERR) ||
1351 (status & VID_B_MSK_SYNC) ||
1352 (status & VID_B_MSK_VBI_SYNC) ||
1353 (status & VID_B_MSK_OF) ||
1354 (status & VID_B_MSK_VBI_OF)) {
1355 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1356 "= 0x%x\n", dev->name, status);
1357 if (status & VID_B_MSK_BAD_PKT)
1358 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1359 if (status & VID_B_MSK_OPC_ERR)
1360 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1361 if (status & VID_B_MSK_VBI_OPC_ERR)
1362 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1363 if (status & VID_B_MSK_SYNC)
1364 dprintk(1, " VID_B_MSK_SYNC\n");
1365 if (status & VID_B_MSK_VBI_SYNC)
1366 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1367 if (status & VID_B_MSK_OF)
1368 dprintk(1, " VID_B_MSK_OF\n");
1369 if (status & VID_B_MSK_VBI_OF)
1370 dprintk(1, " VID_B_MSK_VBI_OF\n");
1371
1372 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1373 cx23885_sram_channel_dump(dev,
1374 &dev->sram_channels[port->sram_chno]);
1375 cx23885_417_check_encoder(dev);
1376 } else if (status & VID_B_MSK_RISCI1) {
1377 dprintk(7, " VID_B_MSK_RISCI1\n");
1378 spin_lock(&port->slock);
1379 cx23885_wakeup(port, &port->mpegq, count);
1380 spin_unlock(&port->slock);
1381 } else if (status & VID_B_MSK_RISCI2) {
1382 dprintk(7, " VID_B_MSK_RISCI2\n");
1383 spin_lock(&port->slock);
1384 cx23885_restart_queue(port, &port->mpegq);
1385 spin_unlock(&port->slock);
1386 }
1387 if (status) {
1388 cx_write(port->reg_ts_int_stat, status);
1389 handled = 1;
1390 }
1391
1392 return handled;
1393 }
1394
1395 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1396 {
1397 struct cx23885_dev *dev = port->dev;
1398 int handled = 0;
1399 u32 count;
1400
1401 if ((status & VID_BC_MSK_OPC_ERR) ||
1402 (status & VID_BC_MSK_BAD_PKT) ||
1403 (status & VID_BC_MSK_SYNC) ||
1404 (status & VID_BC_MSK_OF))
1405 {
1406 if (status & VID_BC_MSK_OPC_ERR)
1407 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1408 if (status & VID_BC_MSK_BAD_PKT)
1409 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1410 if (status & VID_BC_MSK_SYNC)
1411 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1412 if (status & VID_BC_MSK_OF)
1413 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1414
1415 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1416
1417 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1418 cx23885_sram_channel_dump(dev,
1419 &dev->sram_channels[port->sram_chno]);
1420
1421 } else if (status & VID_BC_MSK_RISCI1) {
1422
1423 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1424
1425 spin_lock(&port->slock);
1426 count = cx_read(port->reg_gpcnt);
1427 cx23885_wakeup(port, &port->mpegq, count);
1428 spin_unlock(&port->slock);
1429
1430 } else if (status & VID_BC_MSK_RISCI2) {
1431
1432 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1433
1434 spin_lock(&port->slock);
1435 cx23885_restart_queue(port, &port->mpegq);
1436 spin_unlock(&port->slock);
1437
1438 }
1439 if (status) {
1440 cx_write(port->reg_ts_int_stat, status);
1441 handled = 1;
1442 }
1443
1444 return handled;
1445 }
1446
1447 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1448 {
1449 struct cx23885_dev *dev = dev_id;
1450 struct cx23885_tsport *ts1 = &dev->ts1;
1451 struct cx23885_tsport *ts2 = &dev->ts2;
1452 u32 pci_status, pci_mask;
1453 u32 vida_status, vida_mask;
1454 u32 ts1_status, ts1_mask;
1455 u32 ts2_status, ts2_mask;
1456 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1457
1458 pci_status = cx_read(PCI_INT_STAT);
1459 pci_mask = cx_read(PCI_INT_MSK);
1460 vida_status = cx_read(VID_A_INT_STAT);
1461 vida_mask = cx_read(VID_A_INT_MSK);
1462 ts1_status = cx_read(VID_B_INT_STAT);
1463 ts1_mask = cx_read(VID_B_INT_MSK);
1464 ts2_status = cx_read(VID_C_INT_STAT);
1465 ts2_mask = cx_read(VID_C_INT_MSK);
1466
1467 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1468 goto out;
1469
1470 vida_count = cx_read(VID_A_GPCNT);
1471 ts1_count = cx_read(ts1->reg_gpcnt);
1472 ts2_count = cx_read(ts2->reg_gpcnt);
1473 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1474 pci_status, pci_mask);
1475 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1476 vida_status, vida_mask, vida_count);
1477 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1478 ts1_status, ts1_mask, ts1_count);
1479 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1480 ts2_status, ts2_mask, ts2_count);
1481
1482 if ( (pci_status & PCI_MSK_RISC_RD) ||
1483 (pci_status & PCI_MSK_RISC_WR) ||
1484 (pci_status & PCI_MSK_AL_RD) ||
1485 (pci_status & PCI_MSK_AL_WR) ||
1486 (pci_status & PCI_MSK_APB_DMA) ||
1487 (pci_status & PCI_MSK_VID_C) ||
1488 (pci_status & PCI_MSK_VID_B) ||
1489 (pci_status & PCI_MSK_VID_A) ||
1490 (pci_status & PCI_MSK_AUD_INT) ||
1491 (pci_status & PCI_MSK_AUD_EXT) )
1492 {
1493
1494 if (pci_status & PCI_MSK_RISC_RD)
1495 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1496 if (pci_status & PCI_MSK_RISC_WR)
1497 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1498 if (pci_status & PCI_MSK_AL_RD)
1499 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1500 if (pci_status & PCI_MSK_AL_WR)
1501 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1502 if (pci_status & PCI_MSK_APB_DMA)
1503 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1504 if (pci_status & PCI_MSK_VID_C)
1505 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1506 if (pci_status & PCI_MSK_VID_B)
1507 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1508 if (pci_status & PCI_MSK_VID_A)
1509 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1510 if (pci_status & PCI_MSK_AUD_INT)
1511 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1512 if (pci_status & PCI_MSK_AUD_EXT)
1513 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1514
1515 }
1516
1517 if (ts1_status) {
1518 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1519 handled += cx23885_irq_ts(ts1, ts1_status);
1520 else
1521 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1522 handled += cx23885_irq_417(dev, ts1_status);
1523 }
1524
1525 if (ts2_status) {
1526 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1527 handled += cx23885_irq_ts(ts2, ts2_status);
1528 else
1529 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1530 handled += cx23885_irq_417(dev, ts2_status);
1531 }
1532
1533 if (vida_status)
1534 handled += cx23885_video_irq(dev, vida_status);
1535
1536 if (handled)
1537 cx_write(PCI_INT_STAT, pci_status);
1538 out:
1539 return IRQ_RETVAL(handled);
1540 }
1541
1542 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1543 const struct pci_device_id *pci_id)
1544 {
1545 struct cx23885_dev *dev;
1546 int err;
1547
1548 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1549 if (NULL == dev)
1550 return -ENOMEM;
1551
1552 /* pci init */
1553 dev->pci = pci_dev;
1554 if (pci_enable_device(pci_dev)) {
1555 err = -EIO;
1556 goto fail_free;
1557 }
1558
1559 if (cx23885_dev_setup(dev) < 0) {
1560 err = -EINVAL;
1561 goto fail_free;
1562 }
1563
1564 /* print pci info */
1565 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1566 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1567 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1568 "latency: %d, mmio: 0x%llx\n", dev->name,
1569 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1570 dev->pci_lat,
1571 (unsigned long long)pci_resource_start(pci_dev, 0));
1572
1573 pci_set_master(pci_dev);
1574 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1575 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1576 err = -EIO;
1577 goto fail_irq;
1578 }
1579
1580 err = request_irq(pci_dev->irq, cx23885_irq,
1581 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1582 if (err < 0) {
1583 printk(KERN_ERR "%s: can't get IRQ %d\n",
1584 dev->name, pci_dev->irq);
1585 goto fail_irq;
1586 }
1587
1588 pci_set_drvdata(pci_dev, dev);
1589 return 0;
1590
1591 fail_irq:
1592 cx23885_dev_unregister(dev);
1593 fail_free:
1594 kfree(dev);
1595 return err;
1596 }
1597
1598 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1599 {
1600 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1601
1602 cx23885_shutdown(dev);
1603
1604 pci_disable_device(pci_dev);
1605
1606 /* unregister stuff */
1607 free_irq(pci_dev->irq, dev);
1608 pci_set_drvdata(pci_dev, NULL);
1609
1610 mutex_lock(&devlist);
1611 list_del(&dev->devlist);
1612 mutex_unlock(&devlist);
1613
1614 cx23885_dev_unregister(dev);
1615 kfree(dev);
1616 }
1617
1618 static struct pci_device_id cx23885_pci_tbl[] = {
1619 {
1620 /* CX23885 */
1621 .vendor = 0x14f1,
1622 .device = 0x8852,
1623 .subvendor = PCI_ANY_ID,
1624 .subdevice = PCI_ANY_ID,
1625 },{
1626 /* CX23887 Rev 2 */
1627 .vendor = 0x14f1,
1628 .device = 0x8880,
1629 .subvendor = PCI_ANY_ID,
1630 .subdevice = PCI_ANY_ID,
1631 },{
1632 /* --- end of list --- */
1633 }
1634 };
1635 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1636
1637 static struct pci_driver cx23885_pci_driver = {
1638 .name = "cx23885",
1639 .id_table = cx23885_pci_tbl,
1640 .probe = cx23885_initdev,
1641 .remove = __devexit_p(cx23885_finidev),
1642 /* TODO */
1643 .suspend = NULL,
1644 .resume = NULL,
1645 };
1646
1647 static int cx23885_init(void)
1648 {
1649 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1650 (CX23885_VERSION_CODE >> 16) & 0xff,
1651 (CX23885_VERSION_CODE >> 8) & 0xff,
1652 CX23885_VERSION_CODE & 0xff);
1653 #ifdef SNAPSHOT
1654 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1655 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1656 #endif
1657 return pci_register_driver(&cx23885_pci_driver);
1658 }
1659
1660 static void cx23885_fini(void)
1661 {
1662 pci_unregister_driver(&cx23885_pci_driver);
1663 }
1664
1665 module_init(cx23885_init);
1666 module_exit(cx23885_fini);
1667
1668 /* ----------------------------------------------------------- */
1669 /*
1670 * Local variables:
1671 * c-basic-offset: 8
1672 * End:
1673 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1674 */
A Kernel for the Dreambox dm7025.