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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / net / ucc_geth.c
blob281ce3d395324787c8b986f0dae5648e793aa853
1 /*
2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <linux/workqueue.h>
31
32 #include <asm/of_platform.h>
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "ucc_geth_mii.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
64
65 void uec_set_ethtool_ops(struct net_device *netdev);
66
67 static DEFINE_SPINLOCK(ugeth_lock);
68
69 static struct {
70 u32 msg_enable;
71 } debug = { -1 };
72
73 module_param_named(debug, debug.msg_enable, int, 0);
74 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
75
76 static struct ucc_geth_info ugeth_primary_info = {
77 .uf_info = {
78 .bd_mem_part = MEM_PART_SYSTEM,
79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
80 .max_rx_buf_length = 1536,
81 /* adjusted at startup if max-speed 1000 */
82 .urfs = UCC_GETH_URFS_INIT,
83 .urfet = UCC_GETH_URFET_INIT,
84 .urfset = UCC_GETH_URFSET_INIT,
85 .utfs = UCC_GETH_UTFS_INIT,
86 .utfet = UCC_GETH_UTFET_INIT,
87 .utftt = UCC_GETH_UTFTT_INIT,
88 .ufpt = 256,
89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
91 .tenc = UCC_FAST_TX_ENCODING_NRZ,
92 .renc = UCC_FAST_RX_ENCODING_NRZ,
93 .tcrc = UCC_FAST_16_BIT_CRC,
94 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
95 },
96 .numQueuesTx = 1,
97 .numQueuesRx = 1,
98 .extendedFilteringChainPointer = ((uint32_t) NULL),
99 .typeorlen = 3072 /*1536 */ ,
100 .nonBackToBackIfgPart1 = 0x40,
101 .nonBackToBackIfgPart2 = 0x60,
102 .miminumInterFrameGapEnforcement = 0x50,
103 .backToBackInterFrameGap = 0x60,
104 .mblinterval = 128,
105 .nortsrbytetime = 5,
106 .fracsiz = 1,
107 .strictpriorityq = 0xff,
108 .altBebTruncation = 0xa,
109 .excessDefer = 1,
110 .maxRetransmission = 0xf,
111 .collisionWindow = 0x37,
112 .receiveFlowControl = 1,
113 .transmitFlowControl = 1,
114 .maxGroupAddrInHash = 4,
115 .maxIndAddrInHash = 4,
116 .prel = 7,
117 .maxFrameLength = 1518,
118 .minFrameLength = 64,
119 .maxD1Length = 1520,
120 .maxD2Length = 1520,
121 .vlantype = 0x8100,
122 .ecamptr = ((uint32_t) NULL),
123 .eventRegMask = UCCE_OTHER,
124 .pausePeriod = 0xf000,
125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
126 .bdRingLenTx = {
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN},
135
136 .bdRingLenRx = {
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN},
145
146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
147 .largestexternallookupkeysize =
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161 };
162
163 static struct ucc_geth_info ugeth_info[8];
164
165 #ifdef DEBUG
166 static void mem_disp(u8 *addr, int size)
167 {
168 u8 *i;
169 int size16Aling = (size >> 4) << 4;
170 int size4Aling = (size >> 2) << 2;
171 int notAlign = 0;
172 if (size % 16)
173 notAlign = 1;
174
175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
177 (u32) i,
178 *((u32 *) (i)),
179 *((u32 *) (i + 4)),
180 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
181 if (notAlign == 1)
182 printk("0x%08x: ", (u32) i);
183 for (; (u32) i < (u32) addr + size4Aling; i += 4)
184 printk("%08x ", *((u32 *) (i)));
185 for (; (u32) i < (u32) addr + size; i++)
186 printk("%02x", *((u8 *) (i)));
187 if (notAlign == 1)
188 printk("\r\n");
189 }
190 #endif /* DEBUG */
191
192 #ifdef CONFIG_UGETH_FILTERING
193 static void enqueue(struct list_head *node, struct list_head *lh)
194 {
195 unsigned long flags;
196
197 spin_lock_irqsave(&ugeth_lock, flags);
198 list_add_tail(node, lh);
199 spin_unlock_irqrestore(&ugeth_lock, flags);
200 }
201 #endif /* CONFIG_UGETH_FILTERING */
202
203 static struct list_head *dequeue(struct list_head *lh)
204 {
205 unsigned long flags;
206
207 spin_lock_irqsave(&ugeth_lock, flags);
208 if (!list_empty(lh)) {
209 struct list_head *node = lh->next;
210 list_del(node);
211 spin_unlock_irqrestore(&ugeth_lock, flags);
212 return node;
213 } else {
214 spin_unlock_irqrestore(&ugeth_lock, flags);
215 return NULL;
216 }
217 }
218
219 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
220 {
221 struct sk_buff *skb = NULL;
222
223 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
224 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
225
226 if (skb == NULL)
227 return NULL;
228
229 /* We need the data buffer to be aligned properly. We will reserve
230 * as many bytes as needed to align the data properly
231 */
232 skb_reserve(skb,
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
234 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
235 1)));
236
237 skb->dev = ugeth->dev;
238
239 out_be32(&((struct qe_bd *)bd)->buf,
240 dma_map_single(NULL,
241 skb->data,
242 ugeth->ug_info->uf_info.max_rx_buf_length +
243 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
244 DMA_FROM_DEVICE));
245
246 out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
247
248 return skb;
249 }
250
251 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
252 {
253 u8 *bd;
254 u32 bd_status;
255 struct sk_buff *skb;
256 int i;
257
258 bd = ugeth->p_rx_bd_ring[rxQ];
259 i = 0;
260
261 do {
262 bd_status = in_be32((u32*)bd);
263 skb = get_new_skb(ugeth, bd);
264
265 if (!skb) /* If can not allocate data buffer,
266 abort. Cleanup will be elsewhere */
267 return -ENOMEM;
268
269 ugeth->rx_skbuff[rxQ][i] = skb;
270
271 /* advance the BD pointer */
272 bd += sizeof(struct qe_bd);
273 i++;
274 } while (!(bd_status & R_W));
275
276 return 0;
277 }
278
279 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
280 volatile u32 *p_start,
281 u8 num_entries,
282 u32 thread_size,
283 u32 thread_alignment,
284 enum qe_risc_allocation risc,
285 int skip_page_for_first_entry)
286 {
287 u32 init_enet_offset;
288 u8 i;
289 int snum;
290
291 for (i = 0; i < num_entries; i++) {
292 if ((snum = qe_get_snum()) < 0) {
293 if (netif_msg_ifup(ugeth))
294 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
295 return snum;
296 }
297 if ((i == 0) && skip_page_for_first_entry)
298 /* First entry of Rx does not have page */
299 init_enet_offset = 0;
300 else {
301 init_enet_offset =
302 qe_muram_alloc(thread_size, thread_alignment);
303 if (IS_ERR_VALUE(init_enet_offset)) {
304 if (netif_msg_ifup(ugeth))
305 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
306 qe_put_snum((u8) snum);
307 return -ENOMEM;
308 }
309 }
310 *(p_start++) =
311 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
312 | risc;
313 }
314
315 return 0;
316 }
317
318 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
319 volatile u32 *p_start,
320 u8 num_entries,
321 enum qe_risc_allocation risc,
322 int skip_page_for_first_entry)
323 {
324 u32 init_enet_offset;
325 u8 i;
326 int snum;
327
328 for (i = 0; i < num_entries; i++) {
329 /* Check that this entry was actually valid --
330 needed in case failed in allocations */
331 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
332 snum =
333 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
334 ENET_INIT_PARAM_SNUM_SHIFT;
335 qe_put_snum((u8) snum);
336 if (!((i == 0) && skip_page_for_first_entry)) {
337 /* First entry of Rx does not have page */
338 init_enet_offset =
339 (in_be32(p_start) &
340 ENET_INIT_PARAM_PTR_MASK);
341 qe_muram_free(init_enet_offset);
342 }
343 *(p_start++) = 0; /* Just for cosmetics */
344 }
345 }
346
347 return 0;
348 }
349
350 #ifdef DEBUG
351 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
352 volatile u32 *p_start,
353 u8 num_entries,
354 u32 thread_size,
355 enum qe_risc_allocation risc,
356 int skip_page_for_first_entry)
357 {
358 u32 init_enet_offset;
359 u8 i;
360 int snum;
361
362 for (i = 0; i < num_entries; i++) {
363 /* Check that this entry was actually valid --
364 needed in case failed in allocations */
365 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
366 snum =
367 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
368 ENET_INIT_PARAM_SNUM_SHIFT;
369 qe_put_snum((u8) snum);
370 if (!((i == 0) && skip_page_for_first_entry)) {
371 /* First entry of Rx does not have page */
372 init_enet_offset =
373 (in_be32(p_start) &
374 ENET_INIT_PARAM_PTR_MASK);
375 ugeth_info("Init enet entry %d:", i);
376 ugeth_info("Base address: 0x%08x",
377 (u32)
378 qe_muram_addr(init_enet_offset));
379 mem_disp(qe_muram_addr(init_enet_offset),
380 thread_size);
381 }
382 p_start++;
383 }
384 }
385
386 return 0;
387 }
388 #endif
389
390 #ifdef CONFIG_UGETH_FILTERING
391 static struct enet_addr_container *get_enet_addr_container(void)
392 {
393 struct enet_addr_container *enet_addr_cont;
394
395 /* allocate memory */
396 enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
397 if (!enet_addr_cont) {
398 ugeth_err("%s: No memory for enet_addr_container object.",
399 __FUNCTION__);
400 return NULL;
401 }
402
403 return enet_addr_cont;
404 }
405 #endif /* CONFIG_UGETH_FILTERING */
406
407 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
408 {
409 kfree(enet_addr_cont);
410 }
411
412 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
413 {
414 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
415 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
416 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
417 }
418
419 #ifdef CONFIG_UGETH_FILTERING
420 static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
421 u8 *p_enet_addr, u8 paddr_num)
422 {
423 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
424
425 if (!(paddr_num < NUM_OF_PADDRS)) {
426 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
427 return -EINVAL;
428 }
429
430 p_82xx_addr_filt =
431 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
432 addressfiltering;
433
434 /* Ethernet frames are defined in Little Endian mode, */
435 /* therefore to insert the address we reverse the bytes. */
436 set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
437 return 0;
438 }
439 #endif /* CONFIG_UGETH_FILTERING */
440
441 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
442 {
443 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
444
445 if (!(paddr_num < NUM_OF_PADDRS)) {
446 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
447 return -EINVAL;
448 }
449
450 p_82xx_addr_filt =
451 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
452 addressfiltering;
453
454 /* Writing address ff.ff.ff.ff.ff.ff disables address
455 recognition for this register */
456 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
457 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
458 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
459
460 return 0;
461 }
462
463 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
464 u8 *p_enet_addr)
465 {
466 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
467 u32 cecr_subblock;
468
469 p_82xx_addr_filt =
470 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
471 addressfiltering;
472
473 cecr_subblock =
474 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
475
476 /* Ethernet frames are defined in Little Endian mode,
477 therefor to insert */
478 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
479
480 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
481
482 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
483 QE_CR_PROTOCOL_ETHERNET, 0);
484 }
485
486 #ifdef CONFIG_UGETH_MAGIC_PACKET
487 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
488 {
489 struct ucc_fast_private *uccf;
490 struct ucc_geth *ug_regs;
491 u32 maccfg2, uccm;
492
493 uccf = ugeth->uccf;
494 ug_regs = ugeth->ug_regs;
495
496 /* Enable interrupts for magic packet detection */
497 uccm = in_be32(uccf->p_uccm);
498 uccm |= UCCE_MPD;
499 out_be32(uccf->p_uccm, uccm);
500
501 /* Enable magic packet detection */
502 maccfg2 = in_be32(&ug_regs->maccfg2);
503 maccfg2 |= MACCFG2_MPE;
504 out_be32(&ug_regs->maccfg2, maccfg2);
505 }
506
507 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
508 {
509 struct ucc_fast_private *uccf;
510 struct ucc_geth *ug_regs;
511 u32 maccfg2, uccm;
512
513 uccf = ugeth->uccf;
514 ug_regs = ugeth->ug_regs;
515
516 /* Disable interrupts for magic packet detection */
517 uccm = in_be32(uccf->p_uccm);
518 uccm &= ~UCCE_MPD;
519 out_be32(uccf->p_uccm, uccm);
520
521 /* Disable magic packet detection */
522 maccfg2 = in_be32(&ug_regs->maccfg2);
523 maccfg2 &= ~MACCFG2_MPE;
524 out_be32(&ug_regs->maccfg2, maccfg2);
525 }
526 #endif /* MAGIC_PACKET */
527
528 static inline int compare_addr(u8 **addr1, u8 **addr2)
529 {
530 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
531 }
532
533 #ifdef DEBUG
534 static void get_statistics(struct ucc_geth_private *ugeth,
535 struct ucc_geth_tx_firmware_statistics *
536 tx_firmware_statistics,
537 struct ucc_geth_rx_firmware_statistics *
538 rx_firmware_statistics,
539 struct ucc_geth_hardware_statistics *hardware_statistics)
540 {
541 struct ucc_fast *uf_regs;
542 struct ucc_geth *ug_regs;
543 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
544 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
545
546 ug_regs = ugeth->ug_regs;
547 uf_regs = (struct ucc_fast *) ug_regs;
548 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
549 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
550
551 /* Tx firmware only if user handed pointer and driver actually
552 gathers Tx firmware statistics */
553 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
554 tx_firmware_statistics->sicoltx =
555 in_be32(&p_tx_fw_statistics_pram->sicoltx);
556 tx_firmware_statistics->mulcoltx =
557 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
558 tx_firmware_statistics->latecoltxfr =
559 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
560 tx_firmware_statistics->frabortduecol =
561 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
562 tx_firmware_statistics->frlostinmactxer =
563 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
564 tx_firmware_statistics->carriersenseertx =
565 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
566 tx_firmware_statistics->frtxok =
567 in_be32(&p_tx_fw_statistics_pram->frtxok);
568 tx_firmware_statistics->txfrexcessivedefer =
569 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
570 tx_firmware_statistics->txpkts256 =
571 in_be32(&p_tx_fw_statistics_pram->txpkts256);
572 tx_firmware_statistics->txpkts512 =
573 in_be32(&p_tx_fw_statistics_pram->txpkts512);
574 tx_firmware_statistics->txpkts1024 =
575 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
576 tx_firmware_statistics->txpktsjumbo =
577 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
578 }
579
580 /* Rx firmware only if user handed pointer and driver actually
581 * gathers Rx firmware statistics */
582 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
583 int i;
584 rx_firmware_statistics->frrxfcser =
585 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
586 rx_firmware_statistics->fraligner =
587 in_be32(&p_rx_fw_statistics_pram->fraligner);
588 rx_firmware_statistics->inrangelenrxer =
589 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
590 rx_firmware_statistics->outrangelenrxer =
591 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
592 rx_firmware_statistics->frtoolong =
593 in_be32(&p_rx_fw_statistics_pram->frtoolong);
594 rx_firmware_statistics->runt =
595 in_be32(&p_rx_fw_statistics_pram->runt);
596 rx_firmware_statistics->verylongevent =
597 in_be32(&p_rx_fw_statistics_pram->verylongevent);
598 rx_firmware_statistics->symbolerror =
599 in_be32(&p_rx_fw_statistics_pram->symbolerror);
600 rx_firmware_statistics->dropbsy =
601 in_be32(&p_rx_fw_statistics_pram->dropbsy);
602 for (i = 0; i < 0x8; i++)
603 rx_firmware_statistics->res0[i] =
604 p_rx_fw_statistics_pram->res0[i];
605 rx_firmware_statistics->mismatchdrop =
606 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
607 rx_firmware_statistics->underpkts =
608 in_be32(&p_rx_fw_statistics_pram->underpkts);
609 rx_firmware_statistics->pkts256 =
610 in_be32(&p_rx_fw_statistics_pram->pkts256);
611 rx_firmware_statistics->pkts512 =
612 in_be32(&p_rx_fw_statistics_pram->pkts512);
613 rx_firmware_statistics->pkts1024 =
614 in_be32(&p_rx_fw_statistics_pram->pkts1024);
615 rx_firmware_statistics->pktsjumbo =
616 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
617 rx_firmware_statistics->frlossinmacer =
618 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
619 rx_firmware_statistics->pausefr =
620 in_be32(&p_rx_fw_statistics_pram->pausefr);
621 for (i = 0; i < 0x4; i++)
622 rx_firmware_statistics->res1[i] =
623 p_rx_fw_statistics_pram->res1[i];
624 rx_firmware_statistics->removevlan =
625 in_be32(&p_rx_fw_statistics_pram->removevlan);
626 rx_firmware_statistics->replacevlan =
627 in_be32(&p_rx_fw_statistics_pram->replacevlan);
628 rx_firmware_statistics->insertvlan =
629 in_be32(&p_rx_fw_statistics_pram->insertvlan);
630 }
631
632 /* Hardware only if user handed pointer and driver actually
633 gathers hardware statistics */
634 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
635 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
636 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
637 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
638 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
639 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
640 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
641 hardware_statistics->txok = in_be32(&ug_regs->txok);
642 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
643 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
644 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
645 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
646 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
647 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
648 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
649 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
650 }
651 }
652
653 static void dump_bds(struct ucc_geth_private *ugeth)
654 {
655 int i;
656 int length;
657
658 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
659 if (ugeth->p_tx_bd_ring[i]) {
660 length =
661 (ugeth->ug_info->bdRingLenTx[i] *
662 sizeof(struct qe_bd));
663 ugeth_info("TX BDs[%d]", i);
664 mem_disp(ugeth->p_tx_bd_ring[i], length);
665 }
666 }
667 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
668 if (ugeth->p_rx_bd_ring[i]) {
669 length =
670 (ugeth->ug_info->bdRingLenRx[i] *
671 sizeof(struct qe_bd));
672 ugeth_info("RX BDs[%d]", i);
673 mem_disp(ugeth->p_rx_bd_ring[i], length);
674 }
675 }
676 }
677
678 static void dump_regs(struct ucc_geth_private *ugeth)
679 {
680 int i;
681
682 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
683 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
684
685 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
686 (u32) & ugeth->ug_regs->maccfg1,
687 in_be32(&ugeth->ug_regs->maccfg1));
688 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
689 (u32) & ugeth->ug_regs->maccfg2,
690 in_be32(&ugeth->ug_regs->maccfg2));
691 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
692 (u32) & ugeth->ug_regs->ipgifg,
693 in_be32(&ugeth->ug_regs->ipgifg));
694 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
695 (u32) & ugeth->ug_regs->hafdup,
696 in_be32(&ugeth->ug_regs->hafdup));
697 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
698 (u32) & ugeth->ug_regs->ifctl,
699 in_be32(&ugeth->ug_regs->ifctl));
700 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
701 (u32) & ugeth->ug_regs->ifstat,
702 in_be32(&ugeth->ug_regs->ifstat));
703 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
704 (u32) & ugeth->ug_regs->macstnaddr1,
705 in_be32(&ugeth->ug_regs->macstnaddr1));
706 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
707 (u32) & ugeth->ug_regs->macstnaddr2,
708 in_be32(&ugeth->ug_regs->macstnaddr2));
709 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
710 (u32) & ugeth->ug_regs->uempr,
711 in_be32(&ugeth->ug_regs->uempr));
712 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
713 (u32) & ugeth->ug_regs->utbipar,
714 in_be32(&ugeth->ug_regs->utbipar));
715 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
716 (u32) & ugeth->ug_regs->uescr,
717 in_be16(&ugeth->ug_regs->uescr));
718 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
719 (u32) & ugeth->ug_regs->tx64,
720 in_be32(&ugeth->ug_regs->tx64));
721 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
722 (u32) & ugeth->ug_regs->tx127,
723 in_be32(&ugeth->ug_regs->tx127));
724 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
725 (u32) & ugeth->ug_regs->tx255,
726 in_be32(&ugeth->ug_regs->tx255));
727 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
728 (u32) & ugeth->ug_regs->rx64,
729 in_be32(&ugeth->ug_regs->rx64));
730 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
731 (u32) & ugeth->ug_regs->rx127,
732 in_be32(&ugeth->ug_regs->rx127));
733 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
734 (u32) & ugeth->ug_regs->rx255,
735 in_be32(&ugeth->ug_regs->rx255));
736 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
737 (u32) & ugeth->ug_regs->txok,
738 in_be32(&ugeth->ug_regs->txok));
739 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
740 (u32) & ugeth->ug_regs->txcf,
741 in_be16(&ugeth->ug_regs->txcf));
742 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
743 (u32) & ugeth->ug_regs->tmca,
744 in_be32(&ugeth->ug_regs->tmca));
745 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
746 (u32) & ugeth->ug_regs->tbca,
747 in_be32(&ugeth->ug_regs->tbca));
748 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
749 (u32) & ugeth->ug_regs->rxfok,
750 in_be32(&ugeth->ug_regs->rxfok));
751 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
752 (u32) & ugeth->ug_regs->rxbok,
753 in_be32(&ugeth->ug_regs->rxbok));
754 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
755 (u32) & ugeth->ug_regs->rbyt,
756 in_be32(&ugeth->ug_regs->rbyt));
757 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
758 (u32) & ugeth->ug_regs->rmca,
759 in_be32(&ugeth->ug_regs->rmca));
760 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
761 (u32) & ugeth->ug_regs->rbca,
762 in_be32(&ugeth->ug_regs->rbca));
763 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
764 (u32) & ugeth->ug_regs->scar,
765 in_be32(&ugeth->ug_regs->scar));
766 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
767 (u32) & ugeth->ug_regs->scam,
768 in_be32(&ugeth->ug_regs->scam));
769
770 if (ugeth->p_thread_data_tx) {
771 int numThreadsTxNumerical;
772 switch (ugeth->ug_info->numThreadsTx) {
773 case UCC_GETH_NUM_OF_THREADS_1:
774 numThreadsTxNumerical = 1;
775 break;
776 case UCC_GETH_NUM_OF_THREADS_2:
777 numThreadsTxNumerical = 2;
778 break;
779 case UCC_GETH_NUM_OF_THREADS_4:
780 numThreadsTxNumerical = 4;
781 break;
782 case UCC_GETH_NUM_OF_THREADS_6:
783 numThreadsTxNumerical = 6;
784 break;
785 case UCC_GETH_NUM_OF_THREADS_8:
786 numThreadsTxNumerical = 8;
787 break;
788 default:
789 numThreadsTxNumerical = 0;
790 break;
791 }
792
793 ugeth_info("Thread data TXs:");
794 ugeth_info("Base address: 0x%08x",
795 (u32) ugeth->p_thread_data_tx);
796 for (i = 0; i < numThreadsTxNumerical; i++) {
797 ugeth_info("Thread data TX[%d]:", i);
798 ugeth_info("Base address: 0x%08x",
799 (u32) & ugeth->p_thread_data_tx[i]);
800 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
801 sizeof(struct ucc_geth_thread_data_tx));
802 }
803 }
804 if (ugeth->p_thread_data_rx) {
805 int numThreadsRxNumerical;
806 switch (ugeth->ug_info->numThreadsRx) {
807 case UCC_GETH_NUM_OF_THREADS_1:
808 numThreadsRxNumerical = 1;
809 break;
810 case UCC_GETH_NUM_OF_THREADS_2:
811 numThreadsRxNumerical = 2;
812 break;
813 case UCC_GETH_NUM_OF_THREADS_4:
814 numThreadsRxNumerical = 4;
815 break;
816 case UCC_GETH_NUM_OF_THREADS_6:
817 numThreadsRxNumerical = 6;
818 break;
819 case UCC_GETH_NUM_OF_THREADS_8:
820 numThreadsRxNumerical = 8;
821 break;
822 default:
823 numThreadsRxNumerical = 0;
824 break;
825 }
826
827 ugeth_info("Thread data RX:");
828 ugeth_info("Base address: 0x%08x",
829 (u32) ugeth->p_thread_data_rx);
830 for (i = 0; i < numThreadsRxNumerical; i++) {
831 ugeth_info("Thread data RX[%d]:", i);
832 ugeth_info("Base address: 0x%08x",
833 (u32) & ugeth->p_thread_data_rx[i]);
834 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
835 sizeof(struct ucc_geth_thread_data_rx));
836 }
837 }
838 if (ugeth->p_exf_glbl_param) {
839 ugeth_info("EXF global param:");
840 ugeth_info("Base address: 0x%08x",
841 (u32) ugeth->p_exf_glbl_param);
842 mem_disp((u8 *) ugeth->p_exf_glbl_param,
843 sizeof(*ugeth->p_exf_glbl_param));
844 }
845 if (ugeth->p_tx_glbl_pram) {
846 ugeth_info("TX global param:");
847 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
848 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
849 (u32) & ugeth->p_tx_glbl_pram->temoder,
850 in_be16(&ugeth->p_tx_glbl_pram->temoder));
851 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
852 (u32) & ugeth->p_tx_glbl_pram->sqptr,
853 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
854 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
855 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
856 in_be32(&ugeth->p_tx_glbl_pram->
857 schedulerbasepointer));
858 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
859 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
860 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
861 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
862 (u32) & ugeth->p_tx_glbl_pram->tstate,
863 in_be32(&ugeth->p_tx_glbl_pram->tstate));
864 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
865 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
866 ugeth->p_tx_glbl_pram->iphoffset[0]);
867 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
868 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
869 ugeth->p_tx_glbl_pram->iphoffset[1]);
870 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
871 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
872 ugeth->p_tx_glbl_pram->iphoffset[2]);
873 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
874 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
875 ugeth->p_tx_glbl_pram->iphoffset[3]);
876 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
877 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
878 ugeth->p_tx_glbl_pram->iphoffset[4]);
879 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
880 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
881 ugeth->p_tx_glbl_pram->iphoffset[5]);
882 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
883 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
884 ugeth->p_tx_glbl_pram->iphoffset[6]);
885 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
886 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
887 ugeth->p_tx_glbl_pram->iphoffset[7]);
888 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
890 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
891 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
892 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
893 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
894 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
895 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
896 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
897 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
898 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
899 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
900 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
901 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
902 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
903 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
904 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
905 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
906 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
907 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
908 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
909 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
910 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
911 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
912 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
913 (u32) & ugeth->p_tx_glbl_pram->tqptr,
914 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
915 }
916 if (ugeth->p_rx_glbl_pram) {
917 ugeth_info("RX global param:");
918 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
919 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
920 (u32) & ugeth->p_rx_glbl_pram->remoder,
921 in_be32(&ugeth->p_rx_glbl_pram->remoder));
922 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
923 (u32) & ugeth->p_rx_glbl_pram->rqptr,
924 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
925 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
926 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
927 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
928 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
929 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
930 ugeth->p_rx_glbl_pram->rxgstpack);
931 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
932 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
933 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
934 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
935 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
936 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
937 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
938 (u32) & ugeth->p_rx_glbl_pram->rstate,
939 ugeth->p_rx_glbl_pram->rstate);
940 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
941 (u32) & ugeth->p_rx_glbl_pram->mrblr,
942 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
943 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
944 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
945 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
946 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
947 (u32) & ugeth->p_rx_glbl_pram->mflr,
948 in_be16(&ugeth->p_rx_glbl_pram->mflr));
949 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
950 (u32) & ugeth->p_rx_glbl_pram->minflr,
951 in_be16(&ugeth->p_rx_glbl_pram->minflr));
952 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
953 (u32) & ugeth->p_rx_glbl_pram->maxd1,
954 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
955 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
956 (u32) & ugeth->p_rx_glbl_pram->maxd2,
957 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
958 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
959 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
960 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
961 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
962 (u32) & ugeth->p_rx_glbl_pram->l2qt,
963 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
964 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
965 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
966 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
967 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
968 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
969 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
970 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
971 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
972 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
973 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
974 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
975 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
976 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
977 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
978 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
979 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
980 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
981 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
982 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
983 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
984 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
985 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
986 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
987 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
988 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
989 (u32) & ugeth->p_rx_glbl_pram->vlantype,
990 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
991 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
992 (u32) & ugeth->p_rx_glbl_pram->vlantci,
993 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
994 for (i = 0; i < 64; i++)
995 ugeth_info
996 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
997 i,
998 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
999 ugeth->p_rx_glbl_pram->addressfiltering[i]);
1000 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
1001 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
1002 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
1003 }
1004 if (ugeth->p_send_q_mem_reg) {
1005 ugeth_info("Send Q memory registers:");
1006 ugeth_info("Base address: 0x%08x",
1007 (u32) ugeth->p_send_q_mem_reg);
1008 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1009 ugeth_info("SQQD[%d]:", i);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1012 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1013 sizeof(struct ucc_geth_send_queue_qd));
1014 }
1015 }
1016 if (ugeth->p_scheduler) {
1017 ugeth_info("Scheduler:");
1018 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1019 mem_disp((u8 *) ugeth->p_scheduler,
1020 sizeof(*ugeth->p_scheduler));
1021 }
1022 if (ugeth->p_tx_fw_statistics_pram) {
1023 ugeth_info("TX FW statistics pram:");
1024 ugeth_info("Base address: 0x%08x",
1025 (u32) ugeth->p_tx_fw_statistics_pram);
1026 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1027 sizeof(*ugeth->p_tx_fw_statistics_pram));
1028 }
1029 if (ugeth->p_rx_fw_statistics_pram) {
1030 ugeth_info("RX FW statistics pram:");
1031 ugeth_info("Base address: 0x%08x",
1032 (u32) ugeth->p_rx_fw_statistics_pram);
1033 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1034 sizeof(*ugeth->p_rx_fw_statistics_pram));
1035 }
1036 if (ugeth->p_rx_irq_coalescing_tbl) {
1037 ugeth_info("RX IRQ coalescing tables:");
1038 ugeth_info("Base address: 0x%08x",
1039 (u32) ugeth->p_rx_irq_coalescing_tbl);
1040 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1041 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1042 ugeth_info("Base address: 0x%08x",
1043 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1044 coalescingentry[i]);
1045 ugeth_info
1046 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1047 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1048 coalescingentry[i].interruptcoalescingmaxvalue,
1049 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1050 coalescingentry[i].
1051 interruptcoalescingmaxvalue));
1052 ugeth_info
1053 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1054 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1055 coalescingentry[i].interruptcoalescingcounter,
1056 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1057 coalescingentry[i].
1058 interruptcoalescingcounter));
1059 }
1060 }
1061 if (ugeth->p_rx_bd_qs_tbl) {
1062 ugeth_info("RX BD QS tables:");
1063 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1064 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1065 ugeth_info("RX BD QS table[%d]:", i);
1066 ugeth_info("Base address: 0x%08x",
1067 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1068 ugeth_info
1069 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1070 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1071 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1072 ugeth_info
1073 ("bdptr : addr - 0x%08x, val - 0x%08x",
1074 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1075 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1076 ugeth_info
1077 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1078 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1079 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1080 externalbdbaseptr));
1081 ugeth_info
1082 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1083 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1084 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1085 ugeth_info("ucode RX Prefetched BDs:");
1086 ugeth_info("Base address: 0x%08x",
1087 (u32)
1088 qe_muram_addr(in_be32
1089 (&ugeth->p_rx_bd_qs_tbl[i].
1090 bdbaseptr)));
1091 mem_disp((u8 *)
1092 qe_muram_addr(in_be32
1093 (&ugeth->p_rx_bd_qs_tbl[i].
1094 bdbaseptr)),
1095 sizeof(struct ucc_geth_rx_prefetched_bds));
1096 }
1097 }
1098 if (ugeth->p_init_enet_param_shadow) {
1099 int size;
1100 ugeth_info("Init enet param shadow:");
1101 ugeth_info("Base address: 0x%08x",
1102 (u32) ugeth->p_init_enet_param_shadow);
1103 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1104 sizeof(*ugeth->p_init_enet_param_shadow));
1105
1106 size = sizeof(struct ucc_geth_thread_rx_pram);
1107 if (ugeth->ug_info->rxExtendedFiltering) {
1108 size +=
1109 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1110 if (ugeth->ug_info->largestexternallookupkeysize ==
1111 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1112 size +=
1113 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1114 if (ugeth->ug_info->largestexternallookupkeysize ==
1115 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1116 size +=
1117 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1118 }
1119
1120 dump_init_enet_entries(ugeth,
1121 &(ugeth->p_init_enet_param_shadow->
1122 txthread[0]),
1123 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1124 sizeof(struct ucc_geth_thread_tx_pram),
1125 ugeth->ug_info->riscTx, 0);
1126 dump_init_enet_entries(ugeth,
1127 &(ugeth->p_init_enet_param_shadow->
1128 rxthread[0]),
1129 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1130 ugeth->ug_info->riscRx, 1);
1131 }
1132 }
1133 #endif /* DEBUG */
1134
1135 static void init_default_reg_vals(volatile u32 *upsmr_register,
1136 volatile u32 *maccfg1_register,
1137 volatile u32 *maccfg2_register)
1138 {
1139 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1140 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1141 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1142 }
1143
1144 static int init_half_duplex_params(int alt_beb,
1145 int back_pressure_no_backoff,
1146 int no_backoff,
1147 int excess_defer,
1148 u8 alt_beb_truncation,
1149 u8 max_retransmissions,
1150 u8 collision_window,
1151 volatile u32 *hafdup_register)
1152 {
1153 u32 value = 0;
1154
1155 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1156 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1157 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1158 return -EINVAL;
1159
1160 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1161
1162 if (alt_beb)
1163 value |= HALFDUP_ALT_BEB;
1164 if (back_pressure_no_backoff)
1165 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1166 if (no_backoff)
1167 value |= HALFDUP_NO_BACKOFF;
1168 if (excess_defer)
1169 value |= HALFDUP_EXCESSIVE_DEFER;
1170
1171 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1172
1173 value |= collision_window;
1174
1175 out_be32(hafdup_register, value);
1176 return 0;
1177 }
1178
1179 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1180 u8 non_btb_ipg,
1181 u8 min_ifg,
1182 u8 btb_ipg,
1183 volatile u32 *ipgifg_register)
1184 {
1185 u32 value = 0;
1186
1187 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1188 IPG part 2 */
1189 if (non_btb_cs_ipg > non_btb_ipg)
1190 return -EINVAL;
1191
1192 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1193 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1194 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1195 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1196 return -EINVAL;
1197
1198 value |=
1199 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1200 IPGIFG_NBTB_CS_IPG_MASK);
1201 value |=
1202 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1203 IPGIFG_NBTB_IPG_MASK);
1204 value |=
1205 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1206 IPGIFG_MIN_IFG_MASK);
1207 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1208
1209 out_be32(ipgifg_register, value);
1210 return 0;
1211 }
1212
1213 int init_flow_control_params(u32 automatic_flow_control_mode,
1214 int rx_flow_control_enable,
1215 int tx_flow_control_enable,
1216 u16 pause_period,
1217 u16 extension_field,
1218 volatile u32 *upsmr_register,
1219 volatile u32 *uempr_register,
1220 volatile u32 *maccfg1_register)
1221 {
1222 u32 value = 0;
1223
1224 /* Set UEMPR register */
1225 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1226 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1227 out_be32(uempr_register, value);
1228
1229 /* Set UPSMR register */
1230 value = in_be32(upsmr_register);
1231 value |= automatic_flow_control_mode;
1232 out_be32(upsmr_register, value);
1233
1234 value = in_be32(maccfg1_register);
1235 if (rx_flow_control_enable)
1236 value |= MACCFG1_FLOW_RX;
1237 if (tx_flow_control_enable)
1238 value |= MACCFG1_FLOW_TX;
1239 out_be32(maccfg1_register, value);
1240
1241 return 0;
1242 }
1243
1244 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1245 int auto_zero_hardware_statistics,
1246 volatile u32 *upsmr_register,
1247 volatile u16 *uescr_register)
1248 {
1249 u32 upsmr_value = 0;
1250 u16 uescr_value = 0;
1251 /* Enable hardware statistics gathering if requested */
1252 if (enable_hardware_statistics) {
1253 upsmr_value = in_be32(upsmr_register);
1254 upsmr_value |= UPSMR_HSE;
1255 out_be32(upsmr_register, upsmr_value);
1256 }
1257
1258 /* Clear hardware statistics counters */
1259 uescr_value = in_be16(uescr_register);
1260 uescr_value |= UESCR_CLRCNT;
1261 /* Automatically zero hardware statistics counters on read,
1262 if requested */
1263 if (auto_zero_hardware_statistics)
1264 uescr_value |= UESCR_AUTOZ;
1265 out_be16(uescr_register, uescr_value);
1266
1267 return 0;
1268 }
1269
1270 static int init_firmware_statistics_gathering_mode(int
1271 enable_tx_firmware_statistics,
1272 int enable_rx_firmware_statistics,
1273 volatile u32 *tx_rmon_base_ptr,
1274 u32 tx_firmware_statistics_structure_address,
1275 volatile u32 *rx_rmon_base_ptr,
1276 u32 rx_firmware_statistics_structure_address,
1277 volatile u16 *temoder_register,
1278 volatile u32 *remoder_register)
1279 {
1280 /* Note: this function does not check if */
1281 /* the parameters it receives are NULL */
1282 u16 temoder_value;
1283 u32 remoder_value;
1284
1285 if (enable_tx_firmware_statistics) {
1286 out_be32(tx_rmon_base_ptr,
1287 tx_firmware_statistics_structure_address);
1288 temoder_value = in_be16(temoder_register);
1289 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1290 out_be16(temoder_register, temoder_value);
1291 }
1292
1293 if (enable_rx_firmware_statistics) {
1294 out_be32(rx_rmon_base_ptr,
1295 rx_firmware_statistics_structure_address);
1296 remoder_value = in_be32(remoder_register);
1297 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1298 out_be32(remoder_register, remoder_value);
1299 }
1300
1301 return 0;
1302 }
1303
1304 static int init_mac_station_addr_regs(u8 address_byte_0,
1305 u8 address_byte_1,
1306 u8 address_byte_2,
1307 u8 address_byte_3,
1308 u8 address_byte_4,
1309 u8 address_byte_5,
1310 volatile u32 *macstnaddr1_register,
1311 volatile u32 *macstnaddr2_register)
1312 {
1313 u32 value = 0;
1314
1315 /* Example: for a station address of 0x12345678ABCD, */
1316 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1317
1318 /* MACSTNADDR1 Register: */
1319
1320 /* 0 7 8 15 */
1321 /* station address byte 5 station address byte 4 */
1322 /* 16 23 24 31 */
1323 /* station address byte 3 station address byte 2 */
1324 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1325 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1326 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1327 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1328
1329 out_be32(macstnaddr1_register, value);
1330
1331 /* MACSTNADDR2 Register: */
1332
1333 /* 0 7 8 15 */
1334 /* station address byte 1 station address byte 0 */
1335 /* 16 23 24 31 */
1336 /* reserved reserved */
1337 value = 0;
1338 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1339 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1340
1341 out_be32(macstnaddr2_register, value);
1342
1343 return 0;
1344 }
1345
1346 static int init_check_frame_length_mode(int length_check,
1347 volatile u32 *maccfg2_register)
1348 {
1349 u32 value = 0;
1350
1351 value = in_be32(maccfg2_register);
1352
1353 if (length_check)
1354 value |= MACCFG2_LC;
1355 else
1356 value &= ~MACCFG2_LC;
1357
1358 out_be32(maccfg2_register, value);
1359 return 0;
1360 }
1361
1362 static int init_preamble_length(u8 preamble_length,
1363 volatile u32 *maccfg2_register)
1364 {
1365 u32 value = 0;
1366
1367 if ((preamble_length < 3) || (preamble_length > 7))
1368 return -EINVAL;
1369
1370 value = in_be32(maccfg2_register);
1371 value &= ~MACCFG2_PREL_MASK;
1372 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1373 out_be32(maccfg2_register, value);
1374 return 0;
1375 }
1376
1377 static int init_rx_parameters(int reject_broadcast,
1378 int receive_short_frames,
1379 int promiscuous, volatile u32 *upsmr_register)
1380 {
1381 u32 value = 0;
1382
1383 value = in_be32(upsmr_register);
1384
1385 if (reject_broadcast)
1386 value |= UPSMR_BRO;
1387 else
1388 value &= ~UPSMR_BRO;
1389
1390 if (receive_short_frames)
1391 value |= UPSMR_RSH;
1392 else
1393 value &= ~UPSMR_RSH;
1394
1395 if (promiscuous)
1396 value |= UPSMR_PRO;
1397 else
1398 value &= ~UPSMR_PRO;
1399
1400 out_be32(upsmr_register, value);
1401
1402 return 0;
1403 }
1404
1405 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1406 volatile u16 *mrblr_register)
1407 {
1408 /* max_rx_buf_len value must be a multiple of 128 */
1409 if ((max_rx_buf_len == 0)
1410 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1411 return -EINVAL;
1412
1413 out_be16(mrblr_register, max_rx_buf_len);
1414 return 0;
1415 }
1416
1417 static int init_min_frame_len(u16 min_frame_length,
1418 volatile u16 *minflr_register,
1419 volatile u16 *mrblr_register)
1420 {
1421 u16 mrblr_value = 0;
1422
1423 mrblr_value = in_be16(mrblr_register);
1424 if (min_frame_length >= (mrblr_value - 4))
1425 return -EINVAL;
1426
1427 out_be16(minflr_register, min_frame_length);
1428 return 0;
1429 }
1430
1431 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1432 {
1433 struct ucc_geth_info *ug_info;
1434 struct ucc_geth *ug_regs;
1435 struct ucc_fast *uf_regs;
1436 int ret_val;
1437 u32 upsmr, maccfg2, tbiBaseAddress;
1438 u16 value;
1439
1440 ugeth_vdbg("%s: IN", __FUNCTION__);
1441
1442 ug_info = ugeth->ug_info;
1443 ug_regs = ugeth->ug_regs;
1444 uf_regs = ugeth->uccf->uf_regs;
1445
1446 /* Set MACCFG2 */
1447 maccfg2 = in_be32(&ug_regs->maccfg2);
1448 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1449 if ((ugeth->max_speed == SPEED_10) ||
1450 (ugeth->max_speed == SPEED_100))
1451 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1452 else if (ugeth->max_speed == SPEED_1000)
1453 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1454 maccfg2 |= ug_info->padAndCrc;
1455 out_be32(&ug_regs->maccfg2, maccfg2);
1456
1457 /* Set UPSMR */
1458 upsmr = in_be32(&uf_regs->upsmr);
1459 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1460 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1461 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1462 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1463 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1464 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1465 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1466 upsmr |= UPSMR_RPM;
1467 switch (ugeth->max_speed) {
1468 case SPEED_10:
1469 upsmr |= UPSMR_R10M;
1470 /* FALLTHROUGH */
1471 case SPEED_100:
1472 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1473 upsmr |= UPSMR_RMM;
1474 }
1475 }
1476 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1477 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1478 upsmr |= UPSMR_TBIM;
1479 }
1480 out_be32(&uf_regs->upsmr, upsmr);
1481
1482 /* Disable autonegotiation in tbi mode, because by default it
1483 comes up in autonegotiation mode. */
1484 /* Note that this depends on proper setting in utbipar register. */
1485 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1486 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1487 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1488 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1489 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1490 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1491 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1492 value &= ~0x1000; /* Turn off autonegotiation */
1493 ugeth->phydev->bus->write(ugeth->phydev->bus,
1494 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1495 }
1496
1497 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1498
1499 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1500 if (ret_val != 0) {
1501 if (netif_msg_probe(ugeth))
1502 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1503 __FUNCTION__);
1504 return ret_val;
1505 }
1506
1507 return 0;
1508 }
1509
1510 /* Called every time the controller might need to be made
1511 * aware of new link state. The PHY code conveys this
1512 * information through variables in the ugeth structure, and this
1513 * function converts those variables into the appropriate
1514 * register values, and can bring down the device if needed.
1515 */
1516
1517 static void adjust_link(struct net_device *dev)
1518 {
1519 struct ucc_geth_private *ugeth = netdev_priv(dev);
1520 struct ucc_geth *ug_regs;
1521 struct ucc_fast *uf_regs;
1522 struct phy_device *phydev = ugeth->phydev;
1523 unsigned long flags;
1524 int new_state = 0;
1525
1526 ug_regs = ugeth->ug_regs;
1527 uf_regs = ugeth->uccf->uf_regs;
1528
1529 spin_lock_irqsave(&ugeth->lock, flags);
1530
1531 if (phydev->link) {
1532 u32 tempval = in_be32(&ug_regs->maccfg2);
1533 u32 upsmr = in_be32(&uf_regs->upsmr);
1534 /* Now we make sure that we can be in full duplex mode.
1535 * If not, we operate in half-duplex mode. */
1536 if (phydev->duplex != ugeth->oldduplex) {
1537 new_state = 1;
1538 if (!(phydev->duplex))
1539 tempval &= ~(MACCFG2_FDX);
1540 else
1541 tempval |= MACCFG2_FDX;
1542 ugeth->oldduplex = phydev->duplex;
1543 }
1544
1545 if (phydev->speed != ugeth->oldspeed) {
1546 new_state = 1;
1547 switch (phydev->speed) {
1548 case SPEED_1000:
1549 tempval = ((tempval &
1550 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1551 MACCFG2_INTERFACE_MODE_BYTE);
1552 break;
1553 case SPEED_100:
1554 case SPEED_10:
1555 tempval = ((tempval &
1556 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1557 MACCFG2_INTERFACE_MODE_NIBBLE);
1558 /* if reduced mode, re-set UPSMR.R10M */
1559 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1560 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1561 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1562 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1563 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1564 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1565 if (phydev->speed == SPEED_10)
1566 upsmr |= UPSMR_R10M;
1567 else
1568 upsmr &= ~(UPSMR_R10M);
1569 }
1570 break;
1571 default:
1572 if (netif_msg_link(ugeth))
1573 ugeth_warn(
1574 "%s: Ack! Speed (%d) is not 10/100/1000!",
1575 dev->name, phydev->speed);
1576 break;
1577 }
1578 ugeth->oldspeed = phydev->speed;
1579 }
1580
1581 out_be32(&ug_regs->maccfg2, tempval);
1582 out_be32(&uf_regs->upsmr, upsmr);
1583
1584 if (!ugeth->oldlink) {
1585 new_state = 1;
1586 ugeth->oldlink = 1;
1587 netif_schedule(dev);
1588 }
1589 } else if (ugeth->oldlink) {
1590 new_state = 1;
1591 ugeth->oldlink = 0;
1592 ugeth->oldspeed = 0;
1593 ugeth->oldduplex = -1;
1594 }
1595
1596 if (new_state && netif_msg_link(ugeth))
1597 phy_print_status(phydev);
1598
1599 spin_unlock_irqrestore(&ugeth->lock, flags);
1600 }
1601
1602 /* Configure the PHY for dev.
1603 * returns 0 if success. -1 if failure
1604 */
1605 static int init_phy(struct net_device *dev)
1606 {
1607 struct ucc_geth_private *priv = netdev_priv(dev);
1608 struct phy_device *phydev;
1609 char phy_id[BUS_ID_SIZE];
1610
1611 priv->oldlink = 0;
1612 priv->oldspeed = 0;
1613 priv->oldduplex = -1;
1614
1615 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
1616 priv->ug_info->phy_address);
1617
1618 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
1619
1620 if (IS_ERR(phydev)) {
1621 printk("%s: Could not attach to PHY\n", dev->name);
1622 return PTR_ERR(phydev);
1623 }
1624
1625 phydev->supported &= (ADVERTISED_10baseT_Half |
1626 ADVERTISED_10baseT_Full |
1627 ADVERTISED_100baseT_Half |
1628 ADVERTISED_100baseT_Full);
1629
1630 if (priv->max_speed == SPEED_1000)
1631 phydev->supported |= ADVERTISED_1000baseT_Full;
1632
1633 phydev->advertising = phydev->supported;
1634
1635 priv->phydev = phydev;
1636
1637 return 0;
1638 }
1639
1640
1641
1642 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1643 {
1644 struct ucc_fast_private *uccf;
1645 u32 cecr_subblock;
1646 u32 temp;
1647
1648 uccf = ugeth->uccf;
1649
1650 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1651 temp = in_be32(uccf->p_uccm);
1652 temp &= ~UCCE_GRA;
1653 out_be32(uccf->p_uccm, temp);
1654 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1655
1656 /* Issue host command */
1657 cecr_subblock =
1658 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1659 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1660 QE_CR_PROTOCOL_ETHERNET, 0);
1661
1662 /* Wait for command to complete */
1663 do {
1664 temp = in_be32(uccf->p_ucce);
1665 } while (!(temp & UCCE_GRA));
1666
1667 uccf->stopped_tx = 1;
1668
1669 return 0;
1670 }
1671
1672 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1673 {
1674 struct ucc_fast_private *uccf;
1675 u32 cecr_subblock;
1676 u8 temp;
1677
1678 uccf = ugeth->uccf;
1679
1680 /* Clear acknowledge bit */
1681 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1682 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1683 ugeth->p_rx_glbl_pram->rxgstpack = temp;
1684
1685 /* Keep issuing command and checking acknowledge bit until
1686 it is asserted, according to spec */
1687 do {
1688 /* Issue host command */
1689 cecr_subblock =
1690 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1691 ucc_num);
1692 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1693 QE_CR_PROTOCOL_ETHERNET, 0);
1694
1695 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1696 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1697
1698 uccf->stopped_rx = 1;
1699
1700 return 0;
1701 }
1702
1703 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1704 {
1705 struct ucc_fast_private *uccf;
1706 u32 cecr_subblock;
1707
1708 uccf = ugeth->uccf;
1709
1710 cecr_subblock =
1711 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1712 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1713 uccf->stopped_tx = 0;
1714
1715 return 0;
1716 }
1717
1718 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1719 {
1720 struct ucc_fast_private *uccf;
1721 u32 cecr_subblock;
1722
1723 uccf = ugeth->uccf;
1724
1725 cecr_subblock =
1726 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1727 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1728 0);
1729 uccf->stopped_rx = 0;
1730
1731 return 0;
1732 }
1733
1734 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1735 {
1736 struct ucc_fast_private *uccf;
1737 int enabled_tx, enabled_rx;
1738
1739 uccf = ugeth->uccf;
1740
1741 /* check if the UCC number is in range. */
1742 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1743 if (netif_msg_probe(ugeth))
1744 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1745 return -EINVAL;
1746 }
1747
1748 enabled_tx = uccf->enabled_tx;
1749 enabled_rx = uccf->enabled_rx;
1750
1751 /* Get Tx and Rx going again, in case this channel was actively
1752 disabled. */
1753 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1754 ugeth_restart_tx(ugeth);
1755 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1756 ugeth_restart_rx(ugeth);
1757
1758 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1759
1760 return 0;
1761
1762 }
1763
1764 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1765 {
1766 struct ucc_fast_private *uccf;
1767
1768 uccf = ugeth->uccf;
1769
1770 /* check if the UCC number is in range. */
1771 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1772 if (netif_msg_probe(ugeth))
1773 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1774 return -EINVAL;
1775 }
1776
1777 /* Stop any transmissions */
1778 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1779 ugeth_graceful_stop_tx(ugeth);
1780
1781 /* Stop any receptions */
1782 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1783 ugeth_graceful_stop_rx(ugeth);
1784
1785 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1786
1787 return 0;
1788 }
1789
1790 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1791 {
1792 #ifdef DEBUG
1793 ucc_fast_dump_regs(ugeth->uccf);
1794 dump_regs(ugeth);
1795 dump_bds(ugeth);
1796 #endif
1797 }
1798
1799 #ifdef CONFIG_UGETH_FILTERING
1800 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
1801 p_UccGethTadParams,
1802 struct qe_fltr_tad *qe_fltr_tad)
1803 {
1804 u16 temp;
1805
1806 /* Zero serialized TAD */
1807 memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1808
1809 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
1810 if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1811 (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1812 || (p_UccGethTadParams->vnontag_op !=
1813 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1814 )
1815 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1816 if (p_UccGethTadParams->reject_frame)
1817 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1818 temp =
1819 (u16) (((u16) p_UccGethTadParams->
1820 vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1821 qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1822
1823 qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
1824 if (p_UccGethTadParams->vnontag_op ==
1825 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1826 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1827 qe_fltr_tad->serialized[1] |=
1828 p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1829
1830 qe_fltr_tad->serialized[2] |=
1831 p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1832 /* upper bits */
1833 qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1834 /* lower bits */
1835 qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1836
1837 return 0;
1838 }
1839
1840 static struct enet_addr_container_t
1841 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1842 struct enet_addr *p_enet_addr)
1843 {
1844 struct enet_addr_container *enet_addr_cont;
1845 struct list_head *p_lh;
1846 u16 i, num;
1847 int32_t j;
1848 u8 *p_counter;
1849
1850 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1851 p_lh = &ugeth->group_hash_q;
1852 p_counter = &(ugeth->numGroupAddrInHash);
1853 } else {
1854 p_lh = &ugeth->ind_hash_q;
1855 p_counter = &(ugeth->numIndAddrInHash);
1856 }
1857
1858 if (!p_lh)
1859 return NULL;
1860
1861 num = *p_counter;
1862
1863 for (i = 0; i < num; i++) {
1864 enet_addr_cont =
1865 (struct enet_addr_container *)
1866 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1867 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1868 if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1869 break;
1870 if (j == 0)
1871 return enet_addr_cont; /* Found */
1872 }
1873 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1874 }
1875 return NULL;
1876 }
1877
1878 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1879 struct enet_addr *p_enet_addr)
1880 {
1881 enum ucc_geth_enet_address_recognition_location location;
1882 struct enet_addr_container *enet_addr_cont;
1883 struct list_head *p_lh;
1884 u8 i;
1885 u32 limit;
1886 u8 *p_counter;
1887
1888 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1889 p_lh = &ugeth->group_hash_q;
1890 limit = ugeth->ug_info->maxGroupAddrInHash;
1891 location =
1892 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1893 p_counter = &(ugeth->numGroupAddrInHash);
1894 } else {
1895 p_lh = &ugeth->ind_hash_q;
1896 limit = ugeth->ug_info->maxIndAddrInHash;
1897 location =
1898 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1899 p_counter = &(ugeth->numIndAddrInHash);
1900 }
1901
1902 if ((enet_addr_cont =
1903 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1904 list_add(p_lh, &enet_addr_cont->node); /* Put it back */
1905 return 0;
1906 }
1907 if ((!p_lh) || (!(*p_counter < limit)))
1908 return -EBUSY;
1909 if (!(enet_addr_cont = get_enet_addr_container()))
1910 return -ENOMEM;
1911 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1912 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1913 enet_addr_cont->location = location;
1914 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1915 ++(*p_counter);
1916
1917 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1918 return 0;
1919 }
1920
1921 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1922 struct enet_addr *p_enet_addr)
1923 {
1924 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1925 struct enet_addr_container *enet_addr_cont;
1926 struct ucc_fast_private *uccf;
1927 enum comm_dir comm_dir;
1928 u16 i, num;
1929 struct list_head *p_lh;
1930 u32 *addr_h, *addr_l;
1931 u8 *p_counter;
1932
1933 uccf = ugeth->uccf;
1934
1935 p_82xx_addr_filt =
1936 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1937 addressfiltering;
1938
1939 if (!
1940 (enet_addr_cont =
1941 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1942 return -ENOENT;
1943
1944 /* It's been found and removed from the CQ. */
1945 /* Now destroy its container */
1946 put_enet_addr_container(enet_addr_cont);
1947
1948 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1949 addr_h = &(p_82xx_addr_filt->gaddr_h);
1950 addr_l = &(p_82xx_addr_filt->gaddr_l);
1951 p_lh = &ugeth->group_hash_q;
1952 p_counter = &(ugeth->numGroupAddrInHash);
1953 } else {
1954 addr_h = &(p_82xx_addr_filt->iaddr_h);
1955 addr_l = &(p_82xx_addr_filt->iaddr_l);
1956 p_lh = &ugeth->ind_hash_q;
1957 p_counter = &(ugeth->numIndAddrInHash);
1958 }
1959
1960 comm_dir = 0;
1961 if (uccf->enabled_tx)
1962 comm_dir |= COMM_DIR_TX;
1963 if (uccf->enabled_rx)
1964 comm_dir |= COMM_DIR_RX;
1965 if (comm_dir)
1966 ugeth_disable(ugeth, comm_dir);
1967
1968 /* Clear the hash table. */
1969 out_be32(addr_h, 0x00000000);
1970 out_be32(addr_l, 0x00000000);
1971
1972 /* Add all remaining CQ elements back into hash */
1973 num = --(*p_counter);
1974 for (i = 0; i < num; i++) {
1975 enet_addr_cont =
1976 (struct enet_addr_container *)
1977 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1978 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1979 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1980 }
1981
1982 if (comm_dir)
1983 ugeth_enable(ugeth, comm_dir);
1984
1985 return 0;
1986 }
1987 #endif /* CONFIG_UGETH_FILTERING */
1988
1989 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1990 ugeth,
1991 enum enet_addr_type
1992 enet_addr_type)
1993 {
1994 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1995 struct ucc_fast_private *uccf;
1996 enum comm_dir comm_dir;
1997 struct list_head *p_lh;
1998 u16 i, num;
1999 u32 *addr_h, *addr_l;
2000 u8 *p_counter;
2001
2002 uccf = ugeth->uccf;
2003
2004 p_82xx_addr_filt =
2005 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
2006 addressfiltering;
2007
2008 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2009 addr_h = &(p_82xx_addr_filt->gaddr_h);
2010 addr_l = &(p_82xx_addr_filt->gaddr_l);
2011 p_lh = &ugeth->group_hash_q;
2012 p_counter = &(ugeth->numGroupAddrInHash);
2013 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2014 addr_h = &(p_82xx_addr_filt->iaddr_h);
2015 addr_l = &(p_82xx_addr_filt->iaddr_l);
2016 p_lh = &ugeth->ind_hash_q;
2017 p_counter = &(ugeth->numIndAddrInHash);
2018 } else
2019 return -EINVAL;
2020
2021 comm_dir = 0;
2022 if (uccf->enabled_tx)
2023 comm_dir |= COMM_DIR_TX;
2024 if (uccf->enabled_rx)
2025 comm_dir |= COMM_DIR_RX;
2026 if (comm_dir)
2027 ugeth_disable(ugeth, comm_dir);
2028
2029 /* Clear the hash table. */
2030 out_be32(addr_h, 0x00000000);
2031 out_be32(addr_l, 0x00000000);
2032
2033 if (!p_lh)
2034 return 0;
2035
2036 num = *p_counter;
2037
2038 /* Delete all remaining CQ elements */
2039 for (i = 0; i < num; i++)
2040 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2041
2042 *p_counter = 0;
2043
2044 if (comm_dir)
2045 ugeth_enable(ugeth, comm_dir);
2046
2047 return 0;
2048 }
2049
2050 #ifdef CONFIG_UGETH_FILTERING
2051 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2052 struct enet_addr *p_enet_addr,
2053 u8 paddr_num)
2054 {
2055 int i;
2056
2057 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2058 ugeth_warn
2059 ("%s: multicast address added to paddr will have no "
2060 "effect - is this what you wanted?",
2061 __FUNCTION__);
2062
2063 ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
2064 /* store address in our database */
2065 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2066 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2067 /* put in hardware */
2068 return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2069 }
2070 #endif /* CONFIG_UGETH_FILTERING */
2071
2072 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2073 u8 paddr_num)
2074 {
2075 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2076 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2077 }
2078
2079 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2080 {
2081 u16 i, j;
2082 u8 *bd;
2083
2084 if (!ugeth)
2085 return;
2086
2087 if (ugeth->uccf) {
2088 ucc_fast_free(ugeth->uccf);
2089 ugeth->uccf = NULL;
2090 }
2091
2092 if (ugeth->p_thread_data_tx) {
2093 qe_muram_free(ugeth->thread_dat_tx_offset);
2094 ugeth->p_thread_data_tx = NULL;
2095 }
2096 if (ugeth->p_thread_data_rx) {
2097 qe_muram_free(ugeth->thread_dat_rx_offset);
2098 ugeth->p_thread_data_rx = NULL;
2099 }
2100 if (ugeth->p_exf_glbl_param) {
2101 qe_muram_free(ugeth->exf_glbl_param_offset);
2102 ugeth->p_exf_glbl_param = NULL;
2103 }
2104 if (ugeth->p_rx_glbl_pram) {
2105 qe_muram_free(ugeth->rx_glbl_pram_offset);
2106 ugeth->p_rx_glbl_pram = NULL;
2107 }
2108 if (ugeth->p_tx_glbl_pram) {
2109 qe_muram_free(ugeth->tx_glbl_pram_offset);
2110 ugeth->p_tx_glbl_pram = NULL;
2111 }
2112 if (ugeth->p_send_q_mem_reg) {
2113 qe_muram_free(ugeth->send_q_mem_reg_offset);
2114 ugeth->p_send_q_mem_reg = NULL;
2115 }
2116 if (ugeth->p_scheduler) {
2117 qe_muram_free(ugeth->scheduler_offset);
2118 ugeth->p_scheduler = NULL;
2119 }
2120 if (ugeth->p_tx_fw_statistics_pram) {
2121 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2122 ugeth->p_tx_fw_statistics_pram = NULL;
2123 }
2124 if (ugeth->p_rx_fw_statistics_pram) {
2125 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2126 ugeth->p_rx_fw_statistics_pram = NULL;
2127 }
2128 if (ugeth->p_rx_irq_coalescing_tbl) {
2129 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2130 ugeth->p_rx_irq_coalescing_tbl = NULL;
2131 }
2132 if (ugeth->p_rx_bd_qs_tbl) {
2133 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2134 ugeth->p_rx_bd_qs_tbl = NULL;
2135 }
2136 if (ugeth->p_init_enet_param_shadow) {
2137 return_init_enet_entries(ugeth,
2138 &(ugeth->p_init_enet_param_shadow->
2139 rxthread[0]),
2140 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2141 ugeth->ug_info->riscRx, 1);
2142 return_init_enet_entries(ugeth,
2143 &(ugeth->p_init_enet_param_shadow->
2144 txthread[0]),
2145 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2146 ugeth->ug_info->riscTx, 0);
2147 kfree(ugeth->p_init_enet_param_shadow);
2148 ugeth->p_init_enet_param_shadow = NULL;
2149 }
2150 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2151 bd = ugeth->p_tx_bd_ring[i];
2152 if (!bd)
2153 continue;
2154 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2155 if (ugeth->tx_skbuff[i][j]) {
2156 dma_unmap_single(NULL,
2157 ((struct qe_bd *)bd)->buf,
2158 (in_be32((u32 *)bd) &
2159 BD_LENGTH_MASK),
2160 DMA_TO_DEVICE);
2161 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2162 ugeth->tx_skbuff[i][j] = NULL;
2163 }
2164 }
2165
2166 kfree(ugeth->tx_skbuff[i]);
2167
2168 if (ugeth->p_tx_bd_ring[i]) {
2169 if (ugeth->ug_info->uf_info.bd_mem_part ==
2170 MEM_PART_SYSTEM)
2171 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2172 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2173 MEM_PART_MURAM)
2174 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2175 ugeth->p_tx_bd_ring[i] = NULL;
2176 }
2177 }
2178 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2179 if (ugeth->p_rx_bd_ring[i]) {
2180 /* Return existing data buffers in ring */
2181 bd = ugeth->p_rx_bd_ring[i];
2182 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2183 if (ugeth->rx_skbuff[i][j]) {
2184 dma_unmap_single(NULL,
2185 ((struct qe_bd *)bd)->buf,
2186 ugeth->ug_info->
2187 uf_info.max_rx_buf_length +
2188 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2189 DMA_FROM_DEVICE);
2190 dev_kfree_skb_any(
2191 ugeth->rx_skbuff[i][j]);
2192 ugeth->rx_skbuff[i][j] = NULL;
2193 }
2194 bd += sizeof(struct qe_bd);
2195 }
2196
2197 kfree(ugeth->rx_skbuff[i]);
2198
2199 if (ugeth->ug_info->uf_info.bd_mem_part ==
2200 MEM_PART_SYSTEM)
2201 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2202 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2203 MEM_PART_MURAM)
2204 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2205 ugeth->p_rx_bd_ring[i] = NULL;
2206 }
2207 }
2208 while (!list_empty(&ugeth->group_hash_q))
2209 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2210 (dequeue(&ugeth->group_hash_q)));
2211 while (!list_empty(&ugeth->ind_hash_q))
2212 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2213 (dequeue(&ugeth->ind_hash_q)));
2214
2215 }
2216
2217 static void ucc_geth_set_multi(struct net_device *dev)
2218 {
2219 struct ucc_geth_private *ugeth;
2220 struct dev_mc_list *dmi;
2221 struct ucc_fast *uf_regs;
2222 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2223 int i;
2224
2225 ugeth = netdev_priv(dev);
2226
2227 uf_regs = ugeth->uccf->uf_regs;
2228
2229 if (dev->flags & IFF_PROMISC) {
2230
2231 uf_regs->upsmr |= UPSMR_PRO;
2232
2233 } else {
2234
2235 uf_regs->upsmr &= ~UPSMR_PRO;
2236
2237 p_82xx_addr_filt =
2238 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2239 p_rx_glbl_pram->addressfiltering;
2240
2241 if (dev->flags & IFF_ALLMULTI) {
2242 /* Catch all multicast addresses, so set the
2243 * filter to all 1's.
2244 */
2245 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2246 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2247 } else {
2248 /* Clear filter and add the addresses in the list.
2249 */
2250 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2251 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2252
2253 dmi = dev->mc_list;
2254
2255 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2256
2257 /* Only support group multicast for now.
2258 */
2259 if (!(dmi->dmi_addr[0] & 1))
2260 continue;
2261
2262 /* Ask CPM to run CRC and set bit in
2263 * filter mask.
2264 */
2265 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2266 }
2267 }
2268 }
2269 }
2270
2271 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2272 {
2273 struct ucc_geth *ug_regs = ugeth->ug_regs;
2274 struct phy_device *phydev = ugeth->phydev;
2275 u32 tempval;
2276
2277 ugeth_vdbg("%s: IN", __FUNCTION__);
2278
2279 /* Disable the controller */
2280 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2281
2282 /* Tell the kernel the link is down */
2283 phy_stop(phydev);
2284
2285 /* Mask all interrupts */
2286 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2287
2288 /* Clear all interrupts */
2289 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2290
2291 /* Disable Rx and Tx */
2292 tempval = in_be32(&ug_regs->maccfg1);
2293 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2294 out_be32(&ug_regs->maccfg1, tempval);
2295
2296 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2297
2298 ucc_geth_memclean(ugeth);
2299 }
2300
2301 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2302 {
2303 struct ucc_geth_info *ug_info;
2304 struct ucc_fast_info *uf_info;
2305 int i;
2306
2307 ug_info = ugeth->ug_info;
2308 uf_info = &ug_info->uf_info;
2309
2310 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2311 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2312 if (netif_msg_probe(ugeth))
2313 ugeth_err("%s: Bad memory partition value.",
2314 __FUNCTION__);
2315 return -EINVAL;
2316 }
2317
2318 /* Rx BD lengths */
2319 for (i = 0; i < ug_info->numQueuesRx; i++) {
2320 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2321 (ug_info->bdRingLenRx[i] %
2322 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2323 if (netif_msg_probe(ugeth))
2324 ugeth_err
2325 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2326 __FUNCTION__);
2327 return -EINVAL;
2328 }
2329 }
2330
2331 /* Tx BD lengths */
2332 for (i = 0; i < ug_info->numQueuesTx; i++) {
2333 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2334 if (netif_msg_probe(ugeth))
2335 ugeth_err
2336 ("%s: Tx BD ring length must be no smaller than 2.",
2337 __FUNCTION__);
2338 return -EINVAL;
2339 }
2340 }
2341
2342 /* mrblr */
2343 if ((uf_info->max_rx_buf_length == 0) ||
2344 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2345 if (netif_msg_probe(ugeth))
2346 ugeth_err
2347 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2348 __FUNCTION__);
2349 return -EINVAL;
2350 }
2351
2352 /* num Tx queues */
2353 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2354 if (netif_msg_probe(ugeth))
2355 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2356 return -EINVAL;
2357 }
2358
2359 /* num Rx queues */
2360 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2361 if (netif_msg_probe(ugeth))
2362 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2363 return -EINVAL;
2364 }
2365
2366 /* l2qt */
2367 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2368 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2369 if (netif_msg_probe(ugeth))
2370 ugeth_err
2371 ("%s: VLAN priority table entry must not be"
2372 " larger than number of Rx queues.",
2373 __FUNCTION__);
2374 return -EINVAL;
2375 }
2376 }
2377
2378 /* l3qt */
2379 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2380 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2381 if (netif_msg_probe(ugeth))
2382 ugeth_err
2383 ("%s: IP priority table entry must not be"
2384 " larger than number of Rx queues.",
2385 __FUNCTION__);
2386 return -EINVAL;
2387 }
2388 }
2389
2390 if (ug_info->cam && !ug_info->ecamptr) {
2391 if (netif_msg_probe(ugeth))
2392 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2393 __FUNCTION__);
2394 return -EINVAL;
2395 }
2396
2397 if ((ug_info->numStationAddresses !=
2398 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2399 && ug_info->rxExtendedFiltering) {
2400 if (netif_msg_probe(ugeth))
2401 ugeth_err("%s: Number of station addresses greater than 1 "
2402 "not allowed in extended parsing mode.",
2403 __FUNCTION__);
2404 return -EINVAL;
2405 }
2406
2407 /* Generate uccm_mask for receive */
2408 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2409 for (i = 0; i < ug_info->numQueuesRx; i++)
2410 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2411
2412 for (i = 0; i < ug_info->numQueuesTx; i++)
2413 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2414 /* Initialize the general fast UCC block. */
2415 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2416 if (netif_msg_probe(ugeth))
2417 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2418 ucc_geth_memclean(ugeth);
2419 return -ENOMEM;
2420 }
2421
2422 ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
2423
2424 return 0;
2425 }
2426
2427 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2428 {
2429 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2430 struct ucc_geth_init_pram *p_init_enet_pram;
2431 struct ucc_fast_private *uccf;
2432 struct ucc_geth_info *ug_info;
2433 struct ucc_fast_info *uf_info;
2434 struct ucc_fast *uf_regs;
2435 struct ucc_geth *ug_regs;
2436 int ret_val = -EINVAL;
2437 u32 remoder = UCC_GETH_REMODER_INIT;
2438 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2439 u32 ifstat, i, j, size, l2qt, l3qt, length;
2440 u16 temoder = UCC_GETH_TEMODER_INIT;
2441 u16 test;
2442 u8 function_code = 0;
2443 u8 *bd, *endOfRing;
2444 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2445
2446 ugeth_vdbg("%s: IN", __FUNCTION__);
2447 uccf = ugeth->uccf;
2448 ug_info = ugeth->ug_info;
2449 uf_info = &ug_info->uf_info;
2450 uf_regs = uccf->uf_regs;
2451 ug_regs = ugeth->ug_regs;
2452
2453 switch (ug_info->numThreadsRx) {
2454 case UCC_GETH_NUM_OF_THREADS_1:
2455 numThreadsRxNumerical = 1;
2456 break;
2457 case UCC_GETH_NUM_OF_THREADS_2:
2458 numThreadsRxNumerical = 2;
2459 break;
2460 case UCC_GETH_NUM_OF_THREADS_4:
2461 numThreadsRxNumerical = 4;
2462 break;
2463 case UCC_GETH_NUM_OF_THREADS_6:
2464 numThreadsRxNumerical = 6;
2465 break;
2466 case UCC_GETH_NUM_OF_THREADS_8:
2467 numThreadsRxNumerical = 8;
2468 break;
2469 default:
2470 if (netif_msg_ifup(ugeth))
2471 ugeth_err("%s: Bad number of Rx threads value.",
2472 __FUNCTION__);
2473 ucc_geth_memclean(ugeth);
2474 return -EINVAL;
2475 break;
2476 }
2477
2478 switch (ug_info->numThreadsTx) {
2479 case UCC_GETH_NUM_OF_THREADS_1:
2480 numThreadsTxNumerical = 1;
2481 break;
2482 case UCC_GETH_NUM_OF_THREADS_2:
2483 numThreadsTxNumerical = 2;
2484 break;
2485 case UCC_GETH_NUM_OF_THREADS_4:
2486 numThreadsTxNumerical = 4;
2487 break;
2488 case UCC_GETH_NUM_OF_THREADS_6:
2489 numThreadsTxNumerical = 6;
2490 break;
2491 case UCC_GETH_NUM_OF_THREADS_8:
2492 numThreadsTxNumerical = 8;
2493 break;
2494 default:
2495 if (netif_msg_ifup(ugeth))
2496 ugeth_err("%s: Bad number of Tx threads value.",
2497 __FUNCTION__);
2498 ucc_geth_memclean(ugeth);
2499 return -EINVAL;
2500 break;
2501 }
2502
2503 /* Calculate rx_extended_features */
2504 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2505 ug_info->ipAddressAlignment ||
2506 (ug_info->numStationAddresses !=
2507 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2508
2509 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2510 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2511 || (ug_info->vlanOperationNonTagged !=
2512 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2513
2514 init_default_reg_vals(&uf_regs->upsmr,
2515 &ug_regs->maccfg1, &ug_regs->maccfg2);
2516
2517 /* Set UPSMR */
2518 /* For more details see the hardware spec. */
2519 init_rx_parameters(ug_info->bro,
2520 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2521
2522 /* We're going to ignore other registers for now, */
2523 /* except as needed to get up and running */
2524
2525 /* Set MACCFG1 */
2526 /* For more details see the hardware spec. */
2527 init_flow_control_params(ug_info->aufc,
2528 ug_info->receiveFlowControl,
2529 ug_info->transmitFlowControl,
2530 ug_info->pausePeriod,
2531 ug_info->extensionField,
2532 &uf_regs->upsmr,
2533 &ug_regs->uempr, &ug_regs->maccfg1);
2534
2535 maccfg1 = in_be32(&ug_regs->maccfg1);
2536 maccfg1 |= MACCFG1_ENABLE_RX;
2537 maccfg1 |= MACCFG1_ENABLE_TX;
2538 out_be32(&ug_regs->maccfg1, maccfg1);
2539
2540 /* Set IPGIFG */
2541 /* For more details see the hardware spec. */
2542 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2543 ug_info->nonBackToBackIfgPart2,
2544 ug_info->
2545 miminumInterFrameGapEnforcement,
2546 ug_info->backToBackInterFrameGap,
2547 &ug_regs->ipgifg);
2548 if (ret_val != 0) {
2549 if (netif_msg_ifup(ugeth))
2550 ugeth_err("%s: IPGIFG initialization parameter too large.",
2551 __FUNCTION__);
2552 ucc_geth_memclean(ugeth);
2553 return ret_val;
2554 }
2555
2556 /* Set HAFDUP */
2557 /* For more details see the hardware spec. */
2558 ret_val = init_half_duplex_params(ug_info->altBeb,
2559 ug_info->backPressureNoBackoff,
2560 ug_info->noBackoff,
2561 ug_info->excessDefer,
2562 ug_info->altBebTruncation,
2563 ug_info->maxRetransmission,
2564 ug_info->collisionWindow,
2565 &ug_regs->hafdup);
2566 if (ret_val != 0) {
2567 if (netif_msg_ifup(ugeth))
2568 ugeth_err("%s: Half Duplex initialization parameter too large.",
2569 __FUNCTION__);
2570 ucc_geth_memclean(ugeth);
2571 return ret_val;
2572 }
2573
2574 /* Set IFSTAT */
2575 /* For more details see the hardware spec. */
2576 /* Read only - resets upon read */
2577 ifstat = in_be32(&ug_regs->ifstat);
2578
2579 /* Clear UEMPR */
2580 /* For more details see the hardware spec. */
2581 out_be32(&ug_regs->uempr, 0);
2582
2583 /* Set UESCR */
2584 /* For more details see the hardware spec. */
2585 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2586 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2587 0, &uf_regs->upsmr, &ug_regs->uescr);
2588
2589 /* Allocate Tx bds */
2590 for (j = 0; j < ug_info->numQueuesTx; j++) {
2591 /* Allocate in multiple of
2592 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2593 according to spec */
2594 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2595 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2596 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2597 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2598 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2599 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2600 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2601 u32 align = 4;
2602 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2603 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2604 ugeth->tx_bd_ring_offset[j] =
2605 kmalloc((u32) (length + align), GFP_KERNEL);
2606
2607 if (ugeth->tx_bd_ring_offset[j] != 0)
2608 ugeth->p_tx_bd_ring[j] =
2609 (void*)((ugeth->tx_bd_ring_offset[j] +
2610 align) & ~(align - 1));
2611 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2612 ugeth->tx_bd_ring_offset[j] =
2613 qe_muram_alloc(length,
2614 UCC_GETH_TX_BD_RING_ALIGNMENT);
2615 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2616 ugeth->p_tx_bd_ring[j] =
2617 (u8 *) qe_muram_addr(ugeth->
2618 tx_bd_ring_offset[j]);
2619 }
2620 if (!ugeth->p_tx_bd_ring[j]) {
2621 if (netif_msg_ifup(ugeth))
2622 ugeth_err
2623 ("%s: Can not allocate memory for Tx bd rings.",
2624 __FUNCTION__);
2625 ucc_geth_memclean(ugeth);
2626 return -ENOMEM;
2627 }
2628 /* Zero unused end of bd ring, according to spec */
2629 memset(ugeth->p_tx_bd_ring[j] +
2630 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2631 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2632 }
2633
2634 /* Allocate Rx bds */
2635 for (j = 0; j < ug_info->numQueuesRx; j++) {
2636 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2637 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2638 u32 align = 4;
2639 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2640 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2641 ugeth->rx_bd_ring_offset[j] =
2642 kmalloc((u32) (length + align), GFP_KERNEL);
2643 if (ugeth->rx_bd_ring_offset[j] != 0)
2644 ugeth->p_rx_bd_ring[j] =
2645 (void*)((ugeth->rx_bd_ring_offset[j] +
2646 align) & ~(align - 1));
2647 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2648 ugeth->rx_bd_ring_offset[j] =
2649 qe_muram_alloc(length,
2650 UCC_GETH_RX_BD_RING_ALIGNMENT);
2651 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2652 ugeth->p_rx_bd_ring[j] =
2653 (u8 *) qe_muram_addr(ugeth->
2654 rx_bd_ring_offset[j]);
2655 }
2656 if (!ugeth->p_rx_bd_ring[j]) {
2657 if (netif_msg_ifup(ugeth))
2658 ugeth_err
2659 ("%s: Can not allocate memory for Rx bd rings.",
2660 __FUNCTION__);
2661 ucc_geth_memclean(ugeth);
2662 return -ENOMEM;
2663 }
2664 }
2665
2666 /* Init Tx bds */
2667 for (j = 0; j < ug_info->numQueuesTx; j++) {
2668 /* Setup the skbuff rings */
2669 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2670 ugeth->ug_info->bdRingLenTx[j],
2671 GFP_KERNEL);
2672
2673 if (ugeth->tx_skbuff[j] == NULL) {
2674 if (netif_msg_ifup(ugeth))
2675 ugeth_err("%s: Could not allocate tx_skbuff",
2676 __FUNCTION__);
2677 ucc_geth_memclean(ugeth);
2678 return -ENOMEM;
2679 }
2680
2681 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2682 ugeth->tx_skbuff[j][i] = NULL;
2683
2684 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2685 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2686 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2687 /* clear bd buffer */
2688 out_be32(&((struct qe_bd *)bd)->buf, 0);
2689 /* set bd status and length */
2690 out_be32((u32 *)bd, 0);
2691 bd += sizeof(struct qe_bd);
2692 }
2693 bd -= sizeof(struct qe_bd);
2694 /* set bd status and length */
2695 out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */
2696 }
2697
2698 /* Init Rx bds */
2699 for (j = 0; j < ug_info->numQueuesRx; j++) {
2700 /* Setup the skbuff rings */
2701 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2702 ugeth->ug_info->bdRingLenRx[j],
2703 GFP_KERNEL);
2704
2705 if (ugeth->rx_skbuff[j] == NULL) {
2706 if (netif_msg_ifup(ugeth))
2707 ugeth_err("%s: Could not allocate rx_skbuff",
2708 __FUNCTION__);
2709 ucc_geth_memclean(ugeth);
2710 return -ENOMEM;
2711 }
2712
2713 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2714 ugeth->rx_skbuff[j][i] = NULL;
2715
2716 ugeth->skb_currx[j] = 0;
2717 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2718 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2719 /* set bd status and length */
2720 out_be32((u32 *)bd, R_I);
2721 /* clear bd buffer */
2722 out_be32(&((struct qe_bd *)bd)->buf, 0);
2723 bd += sizeof(struct qe_bd);
2724 }
2725 bd -= sizeof(struct qe_bd);
2726 /* set bd status and length */
2727 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2728 }
2729
2730 /*
2731 * Global PRAM
2732 */
2733 /* Tx global PRAM */
2734 /* Allocate global tx parameter RAM page */
2735 ugeth->tx_glbl_pram_offset =
2736 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2737 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2738 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2739 if (netif_msg_ifup(ugeth))
2740 ugeth_err
2741 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2742 __FUNCTION__);
2743 ucc_geth_memclean(ugeth);
2744 return -ENOMEM;
2745 }
2746 ugeth->p_tx_glbl_pram =
2747 (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
2748 tx_glbl_pram_offset);
2749 /* Zero out p_tx_glbl_pram */
2750 memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2751
2752 /* Fill global PRAM */
2753
2754 /* TQPTR */
2755 /* Size varies with number of Tx threads */
2756 ugeth->thread_dat_tx_offset =
2757 qe_muram_alloc(numThreadsTxNumerical *
2758 sizeof(struct ucc_geth_thread_data_tx) +
2759 32 * (numThreadsTxNumerical == 1),
2760 UCC_GETH_THREAD_DATA_ALIGNMENT);
2761 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2762 if (netif_msg_ifup(ugeth))
2763 ugeth_err
2764 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2765 __FUNCTION__);
2766 ucc_geth_memclean(ugeth);
2767 return -ENOMEM;
2768 }
2769
2770 ugeth->p_thread_data_tx =
2771 (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
2772 thread_dat_tx_offset);
2773 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2774
2775 /* vtagtable */
2776 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2777 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2778 ug_info->vtagtable[i]);
2779
2780 /* iphoffset */
2781 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2782 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
2783
2784 /* SQPTR */
2785 /* Size varies with number of Tx queues */
2786 ugeth->send_q_mem_reg_offset =
2787 qe_muram_alloc(ug_info->numQueuesTx *
2788 sizeof(struct ucc_geth_send_queue_qd),
2789 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2790 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2791 if (netif_msg_ifup(ugeth))
2792 ugeth_err
2793 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2794 __FUNCTION__);
2795 ucc_geth_memclean(ugeth);
2796 return -ENOMEM;
2797 }
2798
2799 ugeth->p_send_q_mem_reg =
2800 (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
2801 send_q_mem_reg_offset);
2802 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2803
2804 /* Setup the table */
2805 /* Assume BD rings are already established */
2806 for (i = 0; i < ug_info->numQueuesTx; i++) {
2807 endOfRing =
2808 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2809 1) * sizeof(struct qe_bd);
2810 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2811 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2812 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2813 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2814 last_bd_completed_address,
2815 (u32) virt_to_phys(endOfRing));
2816 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2817 MEM_PART_MURAM) {
2818 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2819 (u32) immrbar_virt_to_phys(ugeth->
2820 p_tx_bd_ring[i]));
2821 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2822 last_bd_completed_address,
2823 (u32) immrbar_virt_to_phys(endOfRing));
2824 }
2825 }
2826
2827 /* schedulerbasepointer */
2828
2829 if (ug_info->numQueuesTx > 1) {
2830 /* scheduler exists only if more than 1 tx queue */
2831 ugeth->scheduler_offset =
2832 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2833 UCC_GETH_SCHEDULER_ALIGNMENT);
2834 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2835 if (netif_msg_ifup(ugeth))
2836 ugeth_err
2837 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2838 __FUNCTION__);
2839 ucc_geth_memclean(ugeth);
2840 return -ENOMEM;
2841 }
2842
2843 ugeth->p_scheduler =
2844 (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
2845 scheduler_offset);
2846 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2847 ugeth->scheduler_offset);
2848 /* Zero out p_scheduler */
2849 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2850
2851 /* Set values in scheduler */
2852 out_be32(&ugeth->p_scheduler->mblinterval,
2853 ug_info->mblinterval);
2854 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2855 ug_info->nortsrbytetime);
2856 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
2857 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
2858 ugeth->p_scheduler->txasap = ug_info->txasap;
2859 ugeth->p_scheduler->extrabw = ug_info->extrabw;
2860 for (i = 0; i < NUM_TX_QUEUES; i++)
2861 ugeth->p_scheduler->weightfactor[i] =
2862 ug_info->weightfactor[i];
2863
2864 /* Set pointers to cpucount registers in scheduler */
2865 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2866 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2867 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2868 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2869 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2870 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2871 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2872 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2873 }
2874
2875 /* schedulerbasepointer */
2876 /* TxRMON_PTR (statistics) */
2877 if (ug_info->
2878 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2879 ugeth->tx_fw_statistics_pram_offset =
2880 qe_muram_alloc(sizeof
2881 (struct ucc_geth_tx_firmware_statistics_pram),
2882 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2883 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2884 if (netif_msg_ifup(ugeth))
2885 ugeth_err
2886 ("%s: Can not allocate DPRAM memory for"
2887 " p_tx_fw_statistics_pram.",
2888 __FUNCTION__);
2889 ucc_geth_memclean(ugeth);
2890 return -ENOMEM;
2891 }
2892 ugeth->p_tx_fw_statistics_pram =
2893 (struct ucc_geth_tx_firmware_statistics_pram *)
2894 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2895 /* Zero out p_tx_fw_statistics_pram */
2896 memset(ugeth->p_tx_fw_statistics_pram,
2897 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2898 }
2899
2900 /* temoder */
2901 /* Already has speed set */
2902
2903 if (ug_info->numQueuesTx > 1)
2904 temoder |= TEMODER_SCHEDULER_ENABLE;
2905 if (ug_info->ipCheckSumGenerate)
2906 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2907 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2908 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2909
2910 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2911
2912 /* Function code register value to be used later */
2913 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2914 /* Required for QE */
2915
2916 /* function code register */
2917 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2918
2919 /* Rx global PRAM */
2920 /* Allocate global rx parameter RAM page */
2921 ugeth->rx_glbl_pram_offset =
2922 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2923 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2924 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2925 if (netif_msg_ifup(ugeth))
2926 ugeth_err
2927 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2928 __FUNCTION__);
2929 ucc_geth_memclean(ugeth);
2930 return -ENOMEM;
2931 }
2932 ugeth->p_rx_glbl_pram =
2933 (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
2934 rx_glbl_pram_offset);
2935 /* Zero out p_rx_glbl_pram */
2936 memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2937
2938 /* Fill global PRAM */
2939
2940 /* RQPTR */
2941 /* Size varies with number of Rx threads */
2942 ugeth->thread_dat_rx_offset =
2943 qe_muram_alloc(numThreadsRxNumerical *
2944 sizeof(struct ucc_geth_thread_data_rx),
2945 UCC_GETH_THREAD_DATA_ALIGNMENT);
2946 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2947 if (netif_msg_ifup(ugeth))
2948 ugeth_err
2949 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2950 __FUNCTION__);
2951 ucc_geth_memclean(ugeth);
2952 return -ENOMEM;
2953 }
2954
2955 ugeth->p_thread_data_rx =
2956 (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
2957 thread_dat_rx_offset);
2958 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2959
2960 /* typeorlen */
2961 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2962
2963 /* rxrmonbaseptr (statistics) */
2964 if (ug_info->
2965 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2966 ugeth->rx_fw_statistics_pram_offset =
2967 qe_muram_alloc(sizeof
2968 (struct ucc_geth_rx_firmware_statistics_pram),
2969 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2970 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2971 if (netif_msg_ifup(ugeth))
2972 ugeth_err
2973 ("%s: Can not allocate DPRAM memory for"
2974 " p_rx_fw_statistics_pram.", __FUNCTION__);
2975 ucc_geth_memclean(ugeth);
2976 return -ENOMEM;
2977 }
2978 ugeth->p_rx_fw_statistics_pram =
2979 (struct ucc_geth_rx_firmware_statistics_pram *)
2980 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2981 /* Zero out p_rx_fw_statistics_pram */
2982 memset(ugeth->p_rx_fw_statistics_pram, 0,
2983 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2984 }
2985
2986 /* intCoalescingPtr */
2987
2988 /* Size varies with number of Rx queues */
2989 ugeth->rx_irq_coalescing_tbl_offset =
2990 qe_muram_alloc(ug_info->numQueuesRx *
2991 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2992 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2993 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2994 if (netif_msg_ifup(ugeth))
2995 ugeth_err
2996 ("%s: Can not allocate DPRAM memory for"
2997 " p_rx_irq_coalescing_tbl.", __FUNCTION__);
2998 ucc_geth_memclean(ugeth);
2999 return -ENOMEM;
3000 }
3001
3002 ugeth->p_rx_irq_coalescing_tbl =
3003 (struct ucc_geth_rx_interrupt_coalescing_table *)
3004 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
3005 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
3006 ugeth->rx_irq_coalescing_tbl_offset);
3007
3008 /* Fill interrupt coalescing table */
3009 for (i = 0; i < ug_info->numQueuesRx; i++) {
3010 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3011 interruptcoalescingmaxvalue,
3012 ug_info->interruptcoalescingmaxvalue[i]);
3013 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3014 interruptcoalescingcounter,
3015 ug_info->interruptcoalescingmaxvalue[i]);
3016 }
3017
3018 /* MRBLR */
3019 init_max_rx_buff_len(uf_info->max_rx_buf_length,
3020 &ugeth->p_rx_glbl_pram->mrblr);
3021 /* MFLR */
3022 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
3023 /* MINFLR */
3024 init_min_frame_len(ug_info->minFrameLength,
3025 &ugeth->p_rx_glbl_pram->minflr,
3026 &ugeth->p_rx_glbl_pram->mrblr);
3027 /* MAXD1 */
3028 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
3029 /* MAXD2 */
3030 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3031
3032 /* l2qt */
3033 l2qt = 0;
3034 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3035 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3036 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3037
3038 /* l3qt */
3039 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3040 l3qt = 0;
3041 for (i = 0; i < 8; i++)
3042 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3043 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3044 }
3045
3046 /* vlantype */
3047 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3048
3049 /* vlantci */
3050 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3051
3052 /* ecamptr */
3053 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3054
3055 /* RBDQPTR */
3056 /* Size varies with number of Rx queues */
3057 ugeth->rx_bd_qs_tbl_offset =
3058 qe_muram_alloc(ug_info->numQueuesRx *
3059 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3060 sizeof(struct ucc_geth_rx_prefetched_bds)),
3061 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3062 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
3063 if (netif_msg_ifup(ugeth))
3064 ugeth_err
3065 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3066 __FUNCTION__);
3067 ucc_geth_memclean(ugeth);
3068 return -ENOMEM;
3069 }
3070
3071 ugeth->p_rx_bd_qs_tbl =
3072 (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3073 rx_bd_qs_tbl_offset);
3074 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3075 /* Zero out p_rx_bd_qs_tbl */
3076 memset(ugeth->p_rx_bd_qs_tbl,
3077 0,
3078 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3079 sizeof(struct ucc_geth_rx_prefetched_bds)));
3080
3081 /* Setup the table */
3082 /* Assume BD rings are already established */
3083 for (i = 0; i < ug_info->numQueuesRx; i++) {
3084 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3085 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3086 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3087 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3088 MEM_PART_MURAM) {
3089 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3090 (u32) immrbar_virt_to_phys(ugeth->
3091 p_rx_bd_ring[i]));
3092 }
3093 /* rest of fields handled by QE */
3094 }
3095
3096 /* remoder */
3097 /* Already has speed set */
3098
3099 if (ugeth->rx_extended_features)
3100 remoder |= REMODER_RX_EXTENDED_FEATURES;
3101 if (ug_info->rxExtendedFiltering)
3102 remoder |= REMODER_RX_EXTENDED_FILTERING;
3103 if (ug_info->dynamicMaxFrameLength)
3104 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3105 if (ug_info->dynamicMinFrameLength)
3106 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3107 remoder |=
3108 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3109 remoder |=
3110 ug_info->
3111 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3112 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3113 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3114 if (ug_info->ipCheckSumCheck)
3115 remoder |= REMODER_IP_CHECKSUM_CHECK;
3116 if (ug_info->ipAddressAlignment)
3117 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3118 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3119
3120 /* Note that this function must be called */
3121 /* ONLY AFTER p_tx_fw_statistics_pram */
3122 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3123 init_firmware_statistics_gathering_mode((ug_info->
3124 statisticsMode &
3125 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3126 (ug_info->statisticsMode &
3127 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3128 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3129 ugeth->tx_fw_statistics_pram_offset,
3130 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3131 ugeth->rx_fw_statistics_pram_offset,
3132 &ugeth->p_tx_glbl_pram->temoder,
3133 &ugeth->p_rx_glbl_pram->remoder);
3134
3135 /* function code register */
3136 ugeth->p_rx_glbl_pram->rstate = function_code;
3137
3138 /* initialize extended filtering */
3139 if (ug_info->rxExtendedFiltering) {
3140 if (!ug_info->extendedFilteringChainPointer) {
3141 if (netif_msg_ifup(ugeth))
3142 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3143 __FUNCTION__);
3144 ucc_geth_memclean(ugeth);
3145 return -EINVAL;
3146 }
3147
3148 /* Allocate memory for extended filtering Mode Global
3149 Parameters */
3150 ugeth->exf_glbl_param_offset =
3151 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3152 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3153 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
3154 if (netif_msg_ifup(ugeth))
3155 ugeth_err
3156 ("%s: Can not allocate DPRAM memory for"
3157 " p_exf_glbl_param.", __FUNCTION__);
3158 ucc_geth_memclean(ugeth);
3159 return -ENOMEM;
3160 }
3161
3162 ugeth->p_exf_glbl_param =
3163 (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3164 exf_glbl_param_offset);
3165 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3166 ugeth->exf_glbl_param_offset);
3167 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3168 (u32) ug_info->extendedFilteringChainPointer);
3169
3170 } else { /* initialize 82xx style address filtering */
3171
3172 /* Init individual address recognition registers to disabled */
3173
3174 for (j = 0; j < NUM_OF_PADDRS; j++)
3175 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3176
3177 p_82xx_addr_filt =
3178 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3179 p_rx_glbl_pram->addressfiltering;
3180
3181 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3182 ENET_ADDR_TYPE_GROUP);
3183 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3184 ENET_ADDR_TYPE_INDIVIDUAL);
3185 }
3186
3187 /*
3188 * Initialize UCC at QE level
3189 */
3190
3191 command = QE_INIT_TX_RX;
3192
3193 /* Allocate shadow InitEnet command parameter structure.
3194 * This is needed because after the InitEnet command is executed,
3195 * the structure in DPRAM is released, because DPRAM is a premium
3196 * resource.
3197 * This shadow structure keeps a copy of what was done so that the
3198 * allocated resources can be released when the channel is freed.
3199 */
3200 if (!(ugeth->p_init_enet_param_shadow =
3201 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
3202 if (netif_msg_ifup(ugeth))
3203 ugeth_err
3204 ("%s: Can not allocate memory for"
3205 " p_UccInitEnetParamShadows.", __FUNCTION__);
3206 ucc_geth_memclean(ugeth);
3207 return -ENOMEM;
3208 }
3209 /* Zero out *p_init_enet_param_shadow */
3210 memset((char *)ugeth->p_init_enet_param_shadow,
3211 0, sizeof(struct ucc_geth_init_pram));
3212
3213 /* Fill shadow InitEnet command parameter structure */
3214
3215 ugeth->p_init_enet_param_shadow->resinit1 =
3216 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3217 ugeth->p_init_enet_param_shadow->resinit2 =
3218 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3219 ugeth->p_init_enet_param_shadow->resinit3 =
3220 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3221 ugeth->p_init_enet_param_shadow->resinit4 =
3222 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3223 ugeth->p_init_enet_param_shadow->resinit5 =
3224 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3225 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3226 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3227 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3228 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3229
3230 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3231 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3232 if ((ug_info->largestexternallookupkeysize !=
3233 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3234 && (ug_info->largestexternallookupkeysize !=
3235 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3236 && (ug_info->largestexternallookupkeysize !=
3237 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3238 if (netif_msg_ifup(ugeth))
3239 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3240 __FUNCTION__);
3241 ucc_geth_memclean(ugeth);
3242 return -EINVAL;
3243 }
3244 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3245 ug_info->largestexternallookupkeysize;
3246 size = sizeof(struct ucc_geth_thread_rx_pram);
3247 if (ug_info->rxExtendedFiltering) {
3248 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3249 if (ug_info->largestexternallookupkeysize ==
3250 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3251 size +=
3252 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3253 if (ug_info->largestexternallookupkeysize ==
3254 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3255 size +=
3256 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3257 }
3258
3259 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3260 p_init_enet_param_shadow->rxthread[0]),
3261 (u8) (numThreadsRxNumerical + 1)
3262 /* Rx needs one extra for terminator */
3263 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3264 ug_info->riscRx, 1)) != 0) {
3265 if (netif_msg_ifup(ugeth))
3266 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3267 __FUNCTION__);
3268 ucc_geth_memclean(ugeth);
3269 return ret_val;
3270 }
3271
3272 ugeth->p_init_enet_param_shadow->txglobal =
3273 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3274 if ((ret_val =
3275 fill_init_enet_entries(ugeth,
3276 &(ugeth->p_init_enet_param_shadow->
3277 txthread[0]), numThreadsTxNumerical,
3278 sizeof(struct ucc_geth_thread_tx_pram),
3279 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3280 ug_info->riscTx, 0)) != 0) {
3281 if (netif_msg_ifup(ugeth))
3282 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3283 __FUNCTION__);
3284 ucc_geth_memclean(ugeth);
3285 return ret_val;
3286 }
3287
3288 /* Load Rx bds with buffers */
3289 for (i = 0; i < ug_info->numQueuesRx; i++) {
3290 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3291 if (netif_msg_ifup(ugeth))
3292 ugeth_err("%s: Can not fill Rx bds with buffers.",
3293 __FUNCTION__);
3294 ucc_geth_memclean(ugeth);
3295 return ret_val;
3296 }
3297 }
3298
3299 /* Allocate InitEnet command parameter structure */
3300 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3301 if (IS_ERR_VALUE(init_enet_pram_offset)) {
3302 if (netif_msg_ifup(ugeth))
3303 ugeth_err
3304 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3305 __FUNCTION__);
3306 ucc_geth_memclean(ugeth);
3307 return -ENOMEM;
3308 }
3309 p_init_enet_pram =
3310 (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3311
3312 /* Copy shadow InitEnet command parameter structure into PRAM */
3313 p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3314 p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3315 p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3316 p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3317 out_be16(&p_init_enet_pram->resinit5,
3318 ugeth->p_init_enet_param_shadow->resinit5);
3319 p_init_enet_pram->largestexternallookupkeysize =
3320 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3321 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3322 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3323 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3324 out_be32(&p_init_enet_pram->rxthread[i],
3325 ugeth->p_init_enet_param_shadow->rxthread[i]);
3326 out_be32(&p_init_enet_pram->txglobal,
3327 ugeth->p_init_enet_param_shadow->txglobal);
3328 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3329 out_be32(&p_init_enet_pram->txthread[i],
3330 ugeth->p_init_enet_param_shadow->txthread[i]);
3331
3332 /* Issue QE command */
3333 cecr_subblock =
3334 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3335 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3336 init_enet_pram_offset);
3337
3338 /* Free InitEnet command parameter */
3339 qe_muram_free(init_enet_pram_offset);
3340
3341 return 0;
3342 }
3343
3344 /* ucc_geth_timeout gets called when a packet has not been
3345 * transmitted after a set amount of time.
3346 * For now, assume that clearing out all the structures, and
3347 * starting over will fix the problem. */
3348 static void ucc_geth_timeout(struct net_device *dev)
3349 {
3350 struct ucc_geth_private *ugeth = netdev_priv(dev);
3351
3352 ugeth_vdbg("%s: IN", __FUNCTION__);
3353
3354 dev->stats.tx_errors++;
3355
3356 ugeth_dump_regs(ugeth);
3357
3358 if (dev->flags & IFF_UP) {
3359 ucc_geth_stop(ugeth);
3360 ucc_geth_startup(ugeth);
3361 }
3362
3363 netif_schedule(dev);
3364 }
3365
3366 /* This is called by the kernel when a frame is ready for transmission. */
3367 /* It is pointed to by the dev->hard_start_xmit function pointer */
3368 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3369 {
3370 struct ucc_geth_private *ugeth = netdev_priv(dev);
3371 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3372 struct ucc_fast_private *uccf;
3373 #endif
3374 u8 *bd; /* BD pointer */
3375 u32 bd_status;
3376 u8 txQ = 0;
3377
3378 ugeth_vdbg("%s: IN", __FUNCTION__);
3379
3380 spin_lock_irq(&ugeth->lock);
3381
3382 dev->stats.tx_bytes += skb->len;
3383
3384 /* Start from the next BD that should be filled */
3385 bd = ugeth->txBd[txQ];
3386 bd_status = in_be32((u32 *)bd);
3387 /* Save the skb pointer so we can free it later */
3388 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3389
3390 /* Update the current skb pointer (wrapping if this was the last) */
3391 ugeth->skb_curtx[txQ] =
3392 (ugeth->skb_curtx[txQ] +
3393 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3394
3395 /* set up the buffer descriptor */
3396 out_be32(&((struct qe_bd *)bd)->buf,
3397 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3398
3399 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3400
3401 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3402
3403 /* set bd status and length */
3404 out_be32((u32 *)bd, bd_status);
3405
3406 dev->trans_start = jiffies;
3407
3408 /* Move to next BD in the ring */
3409 if (!(bd_status & T_W))
3410 bd += sizeof(struct qe_bd);
3411 else
3412 bd = ugeth->p_tx_bd_ring[txQ];
3413
3414 /* If the next BD still needs to be cleaned up, then the bds
3415 are full. We need to tell the kernel to stop sending us stuff. */
3416 if (bd == ugeth->confBd[txQ]) {
3417 if (!netif_queue_stopped(dev))
3418 netif_stop_queue(dev);
3419 }
3420
3421 ugeth->txBd[txQ] = bd;
3422
3423 if (ugeth->p_scheduler) {
3424 ugeth->cpucount[txQ]++;
3425 /* Indicate to QE that there are more Tx bds ready for
3426 transmission */
3427 /* This is done by writing a running counter of the bd
3428 count to the scheduler PRAM. */
3429 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3430 }
3431
3432 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3433 uccf = ugeth->uccf;
3434 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3435 #endif
3436 spin_unlock_irq(&ugeth->lock);
3437
3438 return 0;
3439 }
3440
3441 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3442 {
3443 struct sk_buff *skb;
3444 u8 *bd;
3445 u16 length, howmany = 0;
3446 u32 bd_status;
3447 u8 *bdBuffer;
3448 struct net_device *dev;
3449
3450 ugeth_vdbg("%s: IN", __FUNCTION__);
3451
3452 dev = ugeth->dev;
3453
3454 /* collect received buffers */
3455 bd = ugeth->rxBd[rxQ];
3456
3457 bd_status = in_be32((u32 *)bd);
3458
3459 /* while there are received buffers and BD is full (~R_E) */
3460 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3461 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3462 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3463 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3464
3465 /* determine whether buffer is first, last, first and last
3466 (single buffer frame) or middle (not first and not last) */
3467 if (!skb ||
3468 (!(bd_status & (R_F | R_L))) ||
3469 (bd_status & R_ERRORS_FATAL)) {
3470 if (netif_msg_rx_err(ugeth))
3471 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3472 __FUNCTION__, __LINE__, (u32) skb);
3473 if (skb)
3474 dev_kfree_skb_any(skb);
3475
3476 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3477 dev->stats.rx_dropped++;
3478 } else {
3479 dev->stats.rx_packets++;
3480 howmany++;
3481
3482 /* Prep the skb for the packet */
3483 skb_put(skb, length);
3484
3485 /* Tell the skb what kind of packet this is */
3486 skb->protocol = eth_type_trans(skb, ugeth->dev);
3487
3488 dev->stats.rx_bytes += length;
3489 /* Send the packet up the stack */
3490 #ifdef CONFIG_UGETH_NAPI
3491 netif_receive_skb(skb);
3492 #else
3493 netif_rx(skb);
3494 #endif /* CONFIG_UGETH_NAPI */
3495 }
3496
3497 ugeth->dev->last_rx = jiffies;
3498
3499 skb = get_new_skb(ugeth, bd);
3500 if (!skb) {
3501 if (netif_msg_rx_err(ugeth))
3502 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
3503 dev->stats.rx_dropped++;
3504 break;
3505 }
3506
3507 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3508
3509 /* update to point at the next skb */
3510 ugeth->skb_currx[rxQ] =
3511 (ugeth->skb_currx[rxQ] +
3512 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3513
3514 if (bd_status & R_W)
3515 bd = ugeth->p_rx_bd_ring[rxQ];
3516 else
3517 bd += sizeof(struct qe_bd);
3518
3519 bd_status = in_be32((u32 *)bd);
3520 }
3521
3522 ugeth->rxBd[rxQ] = bd;
3523 return howmany;
3524 }
3525
3526 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3527 {
3528 /* Start from the next BD that should be filled */
3529 struct ucc_geth_private *ugeth = netdev_priv(dev);
3530 u8 *bd; /* BD pointer */
3531 u32 bd_status;
3532
3533 bd = ugeth->confBd[txQ];
3534 bd_status = in_be32((u32 *)bd);
3535
3536 /* Normal processing. */
3537 while ((bd_status & T_R) == 0) {
3538 /* BD contains already transmitted buffer. */
3539 /* Handle the transmitted buffer and release */
3540 /* the BD to be used with the current frame */
3541
3542 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3543 break;
3544
3545 dev->stats.tx_packets++;
3546
3547 /* Free the sk buffer associated with this TxBD */
3548 dev_kfree_skb_irq(ugeth->
3549 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3550 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3551 ugeth->skb_dirtytx[txQ] =
3552 (ugeth->skb_dirtytx[txQ] +
3553 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3554
3555 /* We freed a buffer, so now we can restart transmission */
3556 if (netif_queue_stopped(dev))
3557 netif_wake_queue(dev);
3558
3559 /* Advance the confirmation BD pointer */
3560 if (!(bd_status & T_W))
3561 bd += sizeof(struct qe_bd);
3562 else
3563 bd = ugeth->p_tx_bd_ring[txQ];
3564 bd_status = in_be32((u32 *)bd);
3565 }
3566 ugeth->confBd[txQ] = bd;
3567 return 0;
3568 }
3569
3570 #ifdef CONFIG_UGETH_NAPI
3571 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3572 {
3573 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3574 struct net_device *dev = ugeth->dev;
3575 struct ucc_geth_info *ug_info;
3576 int howmany, i;
3577
3578 ug_info = ugeth->ug_info;
3579
3580 howmany = 0;
3581 for (i = 0; i < ug_info->numQueuesRx; i++)
3582 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3583
3584 if (howmany < budget) {
3585 struct ucc_fast_private *uccf;
3586 u32 uccm;
3587
3588 netif_rx_complete(dev, napi);
3589 uccf = ugeth->uccf;
3590 uccm = in_be32(uccf->p_uccm);
3591 uccm |= UCCE_RX_EVENTS;
3592 out_be32(uccf->p_uccm, uccm);
3593 }
3594
3595 return howmany;
3596 }
3597 #endif /* CONFIG_UGETH_NAPI */
3598
3599 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3600 {
3601 struct net_device *dev = info;
3602 struct ucc_geth_private *ugeth = netdev_priv(dev);
3603 struct ucc_fast_private *uccf;
3604 struct ucc_geth_info *ug_info;
3605 register u32 ucce;
3606 register u32 uccm;
3607 #ifndef CONFIG_UGETH_NAPI
3608 register u32 rx_mask;
3609 #endif
3610 register u32 tx_mask;
3611 u8 i;
3612
3613 ugeth_vdbg("%s: IN", __FUNCTION__);
3614
3615 uccf = ugeth->uccf;
3616 ug_info = ugeth->ug_info;
3617
3618 /* read and clear events */
3619 ucce = (u32) in_be32(uccf->p_ucce);
3620 uccm = (u32) in_be32(uccf->p_uccm);
3621 ucce &= uccm;
3622 out_be32(uccf->p_ucce, ucce);
3623
3624 /* check for receive events that require processing */
3625 if (ucce & UCCE_RX_EVENTS) {
3626 #ifdef CONFIG_UGETH_NAPI
3627 if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
3628 uccm &= ~UCCE_RX_EVENTS;
3629 out_be32(uccf->p_uccm, uccm);
3630 __netif_rx_schedule(dev, &ugeth->napi);
3631 }
3632 #else
3633 rx_mask = UCCE_RXBF_SINGLE_MASK;
3634 for (i = 0; i < ug_info->numQueuesRx; i++) {
3635 if (ucce & rx_mask)
3636 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3637 ucce &= ~rx_mask;
3638 rx_mask <<= 1;
3639 }
3640 #endif /* CONFIG_UGETH_NAPI */
3641 }
3642
3643 /* Tx event processing */
3644 if (ucce & UCCE_TX_EVENTS) {
3645 spin_lock(&ugeth->lock);
3646 tx_mask = UCCE_TXBF_SINGLE_MASK;
3647 for (i = 0; i < ug_info->numQueuesTx; i++) {
3648 if (ucce & tx_mask)
3649 ucc_geth_tx(dev, i);
3650 ucce &= ~tx_mask;
3651 tx_mask <<= 1;
3652 }
3653 spin_unlock(&ugeth->lock);
3654 }
3655
3656 /* Errors and other events */
3657 if (ucce & UCCE_OTHER) {
3658 if (ucce & UCCE_BSY) {
3659 dev->stats.rx_errors++;
3660 }
3661 if (ucce & UCCE_TXE) {
3662 dev->stats.tx_errors++;
3663 }
3664 }
3665
3666 return IRQ_HANDLED;
3667 }
3668
3669 #ifdef CONFIG_NET_POLL_CONTROLLER
3670 /*
3671 * Polling 'interrupt' - used by things like netconsole to send skbs
3672 * without having to re-enable interrupts. It's not called while
3673 * the interrupt routine is executing.
3674 */
3675 static void ucc_netpoll(struct net_device *dev)
3676 {
3677 struct ucc_geth_private *ugeth = netdev_priv(dev);
3678 int irq = ugeth->ug_info->uf_info.irq;
3679
3680 disable_irq(irq);
3681 ucc_geth_irq_handler(irq, dev);
3682 enable_irq(irq);
3683 }
3684 #endif /* CONFIG_NET_POLL_CONTROLLER */
3685
3686 /* Called when something needs to use the ethernet device */
3687 /* Returns 0 for success. */
3688 static int ucc_geth_open(struct net_device *dev)
3689 {
3690 struct ucc_geth_private *ugeth = netdev_priv(dev);
3691 int err;
3692
3693 ugeth_vdbg("%s: IN", __FUNCTION__);
3694
3695 /* Test station address */
3696 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3697 if (netif_msg_ifup(ugeth))
3698 ugeth_err("%s: Multicast address used for station address"
3699 " - is this what you wanted?", __FUNCTION__);
3700 return -EINVAL;
3701 }
3702
3703 err = ucc_struct_init(ugeth);
3704 if (err) {
3705 if (netif_msg_ifup(ugeth))
3706 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3707 return err;
3708 }
3709
3710 #ifdef CONFIG_UGETH_NAPI
3711 napi_enable(&ugeth->napi);
3712 #endif
3713 err = ucc_geth_startup(ugeth);
3714 if (err) {
3715 if (netif_msg_ifup(ugeth))
3716 ugeth_err("%s: Cannot configure net device, aborting.",
3717 dev->name);
3718 goto out_err;
3719 }
3720
3721 err = adjust_enet_interface(ugeth);
3722 if (err) {
3723 if (netif_msg_ifup(ugeth))
3724 ugeth_err("%s: Cannot configure net device, aborting.",
3725 dev->name);
3726 goto out_err;
3727 }
3728
3729 /* Set MACSTNADDR1, MACSTNADDR2 */
3730 /* For more details see the hardware spec. */
3731 init_mac_station_addr_regs(dev->dev_addr[0],
3732 dev->dev_addr[1],
3733 dev->dev_addr[2],
3734 dev->dev_addr[3],
3735 dev->dev_addr[4],
3736 dev->dev_addr[5],
3737 &ugeth->ug_regs->macstnaddr1,
3738 &ugeth->ug_regs->macstnaddr2);
3739
3740 err = init_phy(dev);
3741 if (err) {
3742 if (netif_msg_ifup(ugeth))
3743 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
3744 goto out_err;
3745 }
3746
3747 phy_start(ugeth->phydev);
3748
3749 err =
3750 request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3751 "UCC Geth", dev);
3752 if (err) {
3753 if (netif_msg_ifup(ugeth))
3754 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3755 dev->name);
3756 ucc_geth_stop(ugeth);
3757 goto out_err;
3758 }
3759
3760 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3761 if (err) {
3762 if (netif_msg_ifup(ugeth))
3763 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3764 ucc_geth_stop(ugeth);
3765 goto out_err;
3766 }
3767
3768 netif_start_queue(dev);
3769
3770 return err;
3771
3772 out_err:
3773 #ifdef CONFIG_UGETH_NAPI
3774 napi_disable(&ugeth->napi);
3775 #endif
3776 return err;
3777 }
3778
3779 /* Stops the kernel queue, and halts the controller */
3780 static int ucc_geth_close(struct net_device *dev)
3781 {
3782 struct ucc_geth_private *ugeth = netdev_priv(dev);
3783
3784 ugeth_vdbg("%s: IN", __FUNCTION__);
3785
3786 #ifdef CONFIG_UGETH_NAPI
3787 napi_disable(&ugeth->napi);
3788 #endif
3789
3790 ucc_geth_stop(ugeth);
3791
3792 phy_disconnect(ugeth->phydev);
3793 ugeth->phydev = NULL;
3794
3795 netif_stop_queue(dev);
3796
3797 return 0;
3798 }
3799
3800 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3801 {
3802 if (strcasecmp(phy_connection_type, "mii") == 0)
3803 return PHY_INTERFACE_MODE_MII;
3804 if (strcasecmp(phy_connection_type, "gmii") == 0)
3805 return PHY_INTERFACE_MODE_GMII;
3806 if (strcasecmp(phy_connection_type, "tbi") == 0)
3807 return PHY_INTERFACE_MODE_TBI;
3808 if (strcasecmp(phy_connection_type, "rmii") == 0)
3809 return PHY_INTERFACE_MODE_RMII;
3810 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3811 return PHY_INTERFACE_MODE_RGMII;
3812 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3813 return PHY_INTERFACE_MODE_RGMII_ID;
3814 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3815 return PHY_INTERFACE_MODE_RGMII_TXID;
3816 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3817 return PHY_INTERFACE_MODE_RGMII_RXID;
3818 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3819 return PHY_INTERFACE_MODE_RTBI;
3820
3821 return PHY_INTERFACE_MODE_MII;
3822 }
3823
3824 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3825 {
3826 struct device *device = &ofdev->dev;
3827 struct device_node *np = ofdev->node;
3828 struct device_node *mdio;
3829 struct net_device *dev = NULL;
3830 struct ucc_geth_private *ugeth = NULL;
3831 struct ucc_geth_info *ug_info;
3832 struct resource res;
3833 struct device_node *phy;
3834 int err, ucc_num, max_speed = 0;
3835 const phandle *ph;
3836 const u32 *fixed_link;
3837 const unsigned int *prop;
3838 const char *sprop;
3839 const void *mac_addr;
3840 phy_interface_t phy_interface;
3841 static const int enet_to_speed[] = {
3842 SPEED_10, SPEED_10, SPEED_10,
3843 SPEED_100, SPEED_100, SPEED_100,
3844 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3845 };
3846 static const phy_interface_t enet_to_phy_interface[] = {
3847 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3848 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3849 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3850 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3851 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3852 };
3853
3854 ugeth_vdbg("%s: IN", __FUNCTION__);
3855
3856 prop = of_get_property(np, "cell-index", NULL);
3857 if (!prop) {
3858 prop = of_get_property(np, "device-id", NULL);
3859 if (!prop)
3860 return -ENODEV;
3861 }
3862
3863 ucc_num = *prop - 1;
3864 if ((ucc_num < 0) || (ucc_num > 7))
3865 return -ENODEV;
3866
3867 ug_info = &ugeth_info[ucc_num];
3868 if (ug_info == NULL) {
3869 if (netif_msg_probe(&debug))
3870 ugeth_err("%s: [%d] Missing additional data!",
3871 __FUNCTION__, ucc_num);
3872 return -ENODEV;
3873 }
3874
3875 ug_info->uf_info.ucc_num = ucc_num;
3876
3877 sprop = of_get_property(np, "rx-clock-name", NULL);
3878 if (sprop) {
3879 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3880 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3881 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3882 printk(KERN_ERR
3883 "ucc_geth: invalid rx-clock-name property\n");
3884 return -EINVAL;
3885 }
3886 } else {
3887 prop = of_get_property(np, "rx-clock", NULL);
3888 if (!prop) {
3889 /* If both rx-clock-name and rx-clock are missing,
3890 we want to tell people to use rx-clock-name. */
3891 printk(KERN_ERR
3892 "ucc_geth: missing rx-clock-name property\n");
3893 return -EINVAL;
3894 }
3895 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3896 printk(KERN_ERR
3897 "ucc_geth: invalid rx-clock propperty\n");
3898 return -EINVAL;
3899 }
3900 ug_info->uf_info.rx_clock = *prop;
3901 }
3902
3903 sprop = of_get_property(np, "tx-clock-name", NULL);
3904 if (sprop) {
3905 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3906 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3907 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3908 printk(KERN_ERR
3909 "ucc_geth: invalid tx-clock-name property\n");
3910 return -EINVAL;
3911 }
3912 } else {
3913 prop = of_get_property(np, "rx-clock", NULL);
3914 if (!prop) {
3915 printk(KERN_ERR
3916 "ucc_geth: mising tx-clock-name property\n");
3917 return -EINVAL;
3918 }
3919 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3920 printk(KERN_ERR
3921 "ucc_geth: invalid tx-clock property\n");
3922 return -EINVAL;
3923 }
3924 ug_info->uf_info.tx_clock = *prop;
3925 }
3926
3927 err = of_address_to_resource(np, 0, &res);
3928 if (err)
3929 return -EINVAL;
3930
3931 ug_info->uf_info.regs = res.start;
3932 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3933 fixed_link = of_get_property(np, "fixed-link", NULL);
3934 if (fixed_link) {
3935 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "0");
3936 ug_info->phy_address = fixed_link[0];
3937 phy = NULL;
3938 } else {
3939 ph = of_get_property(np, "phy-handle", NULL);
3940 phy = of_find_node_by_phandle(*ph);
3941
3942 if (phy == NULL)
3943 return -ENODEV;
3944
3945 /* set the PHY address */
3946 prop = of_get_property(phy, "reg", NULL);
3947 if (prop == NULL)
3948 return -1;
3949 ug_info->phy_address = *prop;
3950
3951 /* Set the bus id */
3952 mdio = of_get_parent(phy);
3953
3954 if (mdio == NULL)
3955 return -1;
3956
3957 err = of_address_to_resource(mdio, 0, &res);
3958 of_node_put(mdio);
3959
3960 if (err)
3961 return -1;
3962
3963 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
3964 }
3965
3966 /* get the phy interface type, or default to MII */
3967 prop = of_get_property(np, "phy-connection-type", NULL);
3968 if (!prop) {
3969 /* handle interface property present in old trees */
3970 prop = of_get_property(phy, "interface", NULL);
3971 if (prop != NULL) {
3972 phy_interface = enet_to_phy_interface[*prop];
3973 max_speed = enet_to_speed[*prop];
3974 } else
3975 phy_interface = PHY_INTERFACE_MODE_MII;
3976 } else {
3977 phy_interface = to_phy_interface((const char *)prop);
3978 }
3979
3980 /* get speed, or derive from PHY interface */
3981 if (max_speed == 0)
3982 switch (phy_interface) {
3983 case PHY_INTERFACE_MODE_GMII:
3984 case PHY_INTERFACE_MODE_RGMII:
3985 case PHY_INTERFACE_MODE_RGMII_ID:
3986 case PHY_INTERFACE_MODE_RGMII_RXID:
3987 case PHY_INTERFACE_MODE_RGMII_TXID:
3988 case PHY_INTERFACE_MODE_TBI:
3989 case PHY_INTERFACE_MODE_RTBI:
3990 max_speed = SPEED_1000;
3991 break;
3992 default:
3993 max_speed = SPEED_100;
3994 break;
3995 }
3996
3997 if (max_speed == SPEED_1000) {
3998 /* configure muram FIFOs for gigabit operation */
3999 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
4000 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
4001 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
4002 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
4003 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
4004 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
4005 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
4006 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
4007 }
4008
4009 if (netif_msg_probe(&debug))
4010 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
4011 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
4012 ug_info->uf_info.irq);
4013
4014 /* Create an ethernet device instance */
4015 dev = alloc_etherdev(sizeof(*ugeth));
4016
4017 if (dev == NULL)
4018 return -ENOMEM;
4019
4020 ugeth = netdev_priv(dev);
4021 spin_lock_init(&ugeth->lock);
4022
4023 /* Create CQs for hash tables */
4024 INIT_LIST_HEAD(&ugeth->group_hash_q);
4025 INIT_LIST_HEAD(&ugeth->ind_hash_q);
4026
4027 dev_set_drvdata(device, dev);
4028
4029 /* Set the dev->base_addr to the gfar reg region */
4030 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
4031
4032 SET_NETDEV_DEV(dev, device);
4033
4034 /* Fill in the dev structure */
4035 uec_set_ethtool_ops(dev);
4036 dev->open = ucc_geth_open;
4037 dev->hard_start_xmit = ucc_geth_start_xmit;
4038 dev->tx_timeout = ucc_geth_timeout;
4039 dev->watchdog_timeo = TX_TIMEOUT;
4040 #ifdef CONFIG_UGETH_NAPI
4041 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
4042 #endif /* CONFIG_UGETH_NAPI */
4043 #ifdef CONFIG_NET_POLL_CONTROLLER
4044 dev->poll_controller = ucc_netpoll;
4045 #endif
4046 dev->stop = ucc_geth_close;
4047 // dev->change_mtu = ucc_geth_change_mtu;
4048 dev->mtu = 1500;
4049 dev->set_multicast_list = ucc_geth_set_multi;
4050
4051 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
4052 ugeth->phy_interface = phy_interface;
4053 ugeth->max_speed = max_speed;
4054
4055 err = register_netdev(dev);
4056 if (err) {
4057 if (netif_msg_probe(ugeth))
4058 ugeth_err("%s: Cannot register net device, aborting.",
4059 dev->name);
4060 free_netdev(dev);
4061 return err;
4062 }
4063
4064 mac_addr = of_get_mac_address(np);
4065 if (mac_addr)
4066 memcpy(dev->dev_addr, mac_addr, 6);
4067
4068 ugeth->ug_info = ug_info;
4069 ugeth->dev = dev;
4070
4071 return 0;
4072 }
4073
4074 static int ucc_geth_remove(struct of_device* ofdev)
4075 {
4076 struct device *device = &ofdev->dev;
4077 struct net_device *dev = dev_get_drvdata(device);
4078 struct ucc_geth_private *ugeth = netdev_priv(dev);
4079
4080 unregister_netdev(dev);
4081 free_netdev(dev);
4082 ucc_geth_memclean(ugeth);
4083 dev_set_drvdata(device, NULL);
4084
4085 return 0;
4086 }
4087
4088 static struct of_device_id ucc_geth_match[] = {
4089 {
4090 .type = "network",
4091 .compatible = "ucc_geth",
4092 },
4093 {},
4094 };
4095
4096 MODULE_DEVICE_TABLE(of, ucc_geth_match);
4097
4098 static struct of_platform_driver ucc_geth_driver = {
4099 .name = DRV_NAME,
4100 .match_table = ucc_geth_match,
4101 .probe = ucc_geth_probe,
4102 .remove = ucc_geth_remove,
4103 };
4104
4105 static int __init ucc_geth_init(void)
4106 {
4107 int i, ret;
4108
4109 ret = uec_mdio_init();
4110
4111 if (ret)
4112 return ret;
4113
4114 if (netif_msg_drv(&debug))
4115 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
4116 for (i = 0; i < 8; i++)
4117 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4118 sizeof(ugeth_primary_info));
4119
4120 ret = of_register_platform_driver(&ucc_geth_driver);
4121
4122 if (ret)
4123 uec_mdio_exit();
4124
4125 return ret;
4126 }
4127
4128 static void __exit ucc_geth_exit(void)
4129 {
4130 of_unregister_platform_driver(&ucc_geth_driver);
4131 uec_mdio_exit();
4132 }
4133
4134 module_init(ucc_geth_init);
4135 module_exit(ucc_geth_exit);
4136
4137 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4138 MODULE_DESCRIPTION(DRV_DESC);
4139 MODULE_VERSION(DRV_VERSION);
4140 MODULE_LICENSE("GPL");
A Kernel for the Dreambox dm7025.