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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6/linux-mips/linux-dm7025.git] / drivers / serial / cpm_uart / cpm_uart_cpm2.c
blobbb862e2f54cfdbdd98d0243dbaebc33df4bcb4e1
1 /*
2 * linux/drivers/serial/cpm_uart_cpm2.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/tty.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/serial.h>
35 #include <linux/console.h>
36 #include <linux/sysrq.h>
37 #include <linux/device.h>
38 #include <linux/bootmem.h>
39 #include <linux/dma-mapping.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/fs_pd.h>
44 #ifdef CONFIG_PPC_CPM_NEW_BINDING
45 #include <asm/prom.h>
46 #endif
47
48 #include <linux/serial_core.h>
49 #include <linux/kernel.h>
50
51 #include "cpm_uart.h"
52
53 /**************************************************************/
54
55 #ifdef CONFIG_PPC_CPM_NEW_BINDING
56 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
57 {
58 cpm_command(port->command, cmd);
59 }
60
61 void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
62 struct device_node *np)
63 {
64 void __iomem *pram;
65 unsigned long offset;
66 struct resource res;
67 unsigned long len;
68
69 /* Don't remap parameter RAM if it has already been initialized
70 * during console setup.
71 */
72 if (IS_SMC(port) && port->smcup)
73 return port->smcup;
74 else if (!IS_SMC(port) && port->sccup)
75 return port->sccup;
76
77 if (of_address_to_resource(np, 1, &res))
78 return NULL;
79
80 len = 1 + res.end - res.start;
81 pram = ioremap(res.start, len);
82 if (!pram)
83 return NULL;
84
85 if (!IS_SMC(port))
86 return pram;
87
88 if (len != 2) {
89 printk(KERN_WARNING "cpm_uart[%d]: device tree references "
90 "SMC pram, using boot loader/wrapper pram mapping. "
91 "Please fix your device tree to reference the pram "
92 "base register instead.\n",
93 port->port.line);
94 return pram;
95 }
96
97 offset = cpm_dpalloc(PROFF_SMC_SIZE, 64);
98 out_be16(pram, offset);
99 iounmap(pram);
100 return cpm_muram_addr(offset);
101 }
102
103 void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
104 {
105 if (!IS_SMC(port))
106 iounmap(pram);
107 }
108
109 #else
110 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
111 {
112 ulong val;
113 int line = port - cpm_uart_ports;
114 volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
115
116
117 switch (line) {
118 case UART_SMC1:
119 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
120 cmd) | CPM_CR_FLG;
121 break;
122 case UART_SMC2:
123 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
124 cmd) | CPM_CR_FLG;
125 break;
126 case UART_SCC1:
127 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
128 cmd) | CPM_CR_FLG;
129 break;
130 case UART_SCC2:
131 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
132 cmd) | CPM_CR_FLG;
133 break;
134 case UART_SCC3:
135 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
136 cmd) | CPM_CR_FLG;
137 break;
138 case UART_SCC4:
139 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
140 cmd) | CPM_CR_FLG;
141 break;
142 default:
143 return;
144
145 }
146 cp->cp_cpcr = val;
147 while (cp->cp_cpcr & CPM_CR_FLG) ;
148
149 cpm2_unmap(cp);
150 }
151
152 void smc1_lineif(struct uart_cpm_port *pinfo)
153 {
154 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
155 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
156
157 /* SMC1 is only on port D */
158 io->iop_ppard |= 0x00c00000;
159 io->iop_pdird |= 0x00400000;
160 io->iop_pdird &= ~0x00800000;
161 io->iop_psord &= ~0x00c00000;
162
163 /* Wire BRG1 to SMC1 */
164 cpmux->cmx_smr &= 0x0f;
165 pinfo->brg = 1;
166
167 cpm2_unmap(cpmux);
168 cpm2_unmap(io);
169 }
170
171 void smc2_lineif(struct uart_cpm_port *pinfo)
172 {
173 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
174 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
175
176 /* SMC2 is only on port A */
177 io->iop_ppara |= 0x00c00000;
178 io->iop_pdira |= 0x00400000;
179 io->iop_pdira &= ~0x00800000;
180 io->iop_psora &= ~0x00c00000;
181
182 /* Wire BRG2 to SMC2 */
183 cpmux->cmx_smr &= 0xf0;
184 pinfo->brg = 2;
185
186 cpm2_unmap(cpmux);
187 cpm2_unmap(io);
188 }
189
190 void scc1_lineif(struct uart_cpm_port *pinfo)
191 {
192 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
193 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
194
195 /* Use Port D for SCC1 instead of other functions. */
196 io->iop_ppard |= 0x00000003;
197 io->iop_psord &= ~0x00000001; /* Rx */
198 io->iop_psord |= 0x00000002; /* Tx */
199 io->iop_pdird &= ~0x00000001; /* Rx */
200 io->iop_pdird |= 0x00000002; /* Tx */
201
202 /* Wire BRG1 to SCC1 */
203 cpmux->cmx_scr &= 0x00ffffff;
204 cpmux->cmx_scr |= 0x00000000;
205 pinfo->brg = 1;
206
207 cpm2_unmap(cpmux);
208 cpm2_unmap(io);
209 }
210
211 void scc2_lineif(struct uart_cpm_port *pinfo)
212 {
213 /*
214 * STx GP3 uses the SCC2 secondary option pin assignment
215 * which this driver doesn't account for in the static
216 * pin assignments. This kind of board specific info
217 * really has to get out of the driver so boards can
218 * be supported in a sane fashion.
219 */
220 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
221 #ifndef CONFIG_STX_GP3
222 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
223
224 io->iop_pparb |= 0x008b0000;
225 io->iop_pdirb |= 0x00880000;
226 io->iop_psorb |= 0x00880000;
227 io->iop_pdirb &= ~0x00030000;
228 io->iop_psorb &= ~0x00030000;
229 #endif
230 cpmux->cmx_scr &= 0xff00ffff;
231 cpmux->cmx_scr |= 0x00090000;
232 pinfo->brg = 2;
233
234 cpm2_unmap(cpmux);
235 cpm2_unmap(io);
236 }
237
238 void scc3_lineif(struct uart_cpm_port *pinfo)
239 {
240 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
241 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
242
243 io->iop_pparb |= 0x008b0000;
244 io->iop_pdirb |= 0x00880000;
245 io->iop_psorb |= 0x00880000;
246 io->iop_pdirb &= ~0x00030000;
247 io->iop_psorb &= ~0x00030000;
248 cpmux->cmx_scr &= 0xffff00ff;
249 cpmux->cmx_scr |= 0x00001200;
250 pinfo->brg = 3;
251
252 cpm2_unmap(cpmux);
253 cpm2_unmap(io);
254 }
255
256 void scc4_lineif(struct uart_cpm_port *pinfo)
257 {
258 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
259 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
260
261 io->iop_ppard |= 0x00000600;
262 io->iop_psord &= ~0x00000600; /* Tx/Rx */
263 io->iop_pdird &= ~0x00000200; /* Rx */
264 io->iop_pdird |= 0x00000400; /* Tx */
265
266 cpmux->cmx_scr &= 0xffffff00;
267 cpmux->cmx_scr |= 0x0000001b;
268 pinfo->brg = 4;
269
270 cpm2_unmap(cpmux);
271 cpm2_unmap(io);
272 }
273 #endif
274
275 /*
276 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
277 * receive buffer descriptors from dual port ram, and a character
278 * buffer area from host mem. If we are allocating for the console we need
279 * to do it from bootmem
280 */
281 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
282 {
283 int dpmemsz, memsz;
284 u8 __iomem *dp_mem;
285 unsigned long dp_offset;
286 u8 *mem_addr;
287 dma_addr_t dma_addr = 0;
288
289 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
290
291 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
292 dp_offset = cpm_dpalloc(dpmemsz, 8);
293 if (IS_ERR_VALUE(dp_offset)) {
294 printk(KERN_ERR
295 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
296 return -ENOMEM;
297 }
298
299 dp_mem = cpm_dpram_addr(dp_offset);
300
301 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
302 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
303 if (is_con) {
304 mem_addr = alloc_bootmem(memsz);
305 dma_addr = virt_to_bus(mem_addr);
306 }
307 else
308 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
309 GFP_KERNEL);
310
311 if (mem_addr == NULL) {
312 cpm_dpfree(dp_offset);
313 printk(KERN_ERR
314 "cpm_uart_cpm.c: could not allocate coherent memory\n");
315 return -ENOMEM;
316 }
317
318 pinfo->dp_addr = dp_offset;
319 pinfo->mem_addr = mem_addr;
320 pinfo->dma_addr = dma_addr;
321 pinfo->mem_size = memsz;
322
323 pinfo->rx_buf = mem_addr;
324 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
325 * pinfo->rx_fifosize);
326
327 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem;
328 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
329
330 return 0;
331 }
332
333 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
334 {
335 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
336 pinfo->rx_fifosize) +
337 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
338 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
339 pinfo->dma_addr);
340
341 cpm_dpfree(pinfo->dp_addr);
342 }
343
344 #ifndef CONFIG_PPC_CPM_NEW_BINDING
345 /* Setup any dynamic params in the uart desc */
346 int cpm_uart_init_portdesc(void)
347 {
348 #if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
349 u16 *addr;
350 #endif
351 pr_debug("CPM uart[-]:init portdesc\n");
352
353 cpm_uart_nr = 0;
354 #ifdef CONFIG_SERIAL_CPM_SMC1
355 cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
356 cpm_uart_ports[UART_SMC1].port.mapbase =
357 (unsigned long)cpm_uart_ports[UART_SMC1].smcp;
358
359 cpm_uart_ports[UART_SMC1].smcup =
360 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
361 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
362 *addr = PROFF_SMC1;
363 cpm2_unmap(addr);
364
365 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
366 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
367 cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
368 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
369 #endif
370
371 #ifdef CONFIG_SERIAL_CPM_SMC2
372 cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
373 cpm_uart_ports[UART_SMC2].port.mapbase =
374 (unsigned long)cpm_uart_ports[UART_SMC2].smcp;
375
376 cpm_uart_ports[UART_SMC2].smcup =
377 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
378 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
379 *addr = PROFF_SMC2;
380 cpm2_unmap(addr);
381
382 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
383 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
384 cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
385 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
386 #endif
387
388 #ifdef CONFIG_SERIAL_CPM_SCC1
389 cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
390 cpm_uart_ports[UART_SCC1].port.mapbase =
391 (unsigned long)cpm_uart_ports[UART_SCC1].sccp;
392 cpm_uart_ports[UART_SCC1].sccup =
393 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
394
395 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
396 ~(UART_SCCM_TX | UART_SCCM_RX);
397 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
398 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
399 cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
400 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
401 #endif
402
403 #ifdef CONFIG_SERIAL_CPM_SCC2
404 cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
405 cpm_uart_ports[UART_SCC2].port.mapbase =
406 (unsigned long)cpm_uart_ports[UART_SCC2].sccp;
407 cpm_uart_ports[UART_SCC2].sccup =
408 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
409
410 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
411 ~(UART_SCCM_TX | UART_SCCM_RX);
412 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
413 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
414 cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
415 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
416 #endif
417
418 #ifdef CONFIG_SERIAL_CPM_SCC3
419 cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
420 cpm_uart_ports[UART_SCC3].port.mapbase =
421 (unsigned long)cpm_uart_ports[UART_SCC3].sccp;
422 cpm_uart_ports[UART_SCC3].sccup =
423 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
424
425 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
426 ~(UART_SCCM_TX | UART_SCCM_RX);
427 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
428 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
429 cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
430 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
431 #endif
432
433 #ifdef CONFIG_SERIAL_CPM_SCC4
434 cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
435 cpm_uart_ports[UART_SCC4].port.mapbase =
436 (unsigned long)cpm_uart_ports[UART_SCC4].sccp;
437 cpm_uart_ports[UART_SCC4].sccup =
438 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
439
440 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
441 ~(UART_SCCM_TX | UART_SCCM_RX);
442 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
443 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
444 cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
445 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
446 #endif
447
448 return 0;
449 }
450 #endif
A Kernel for the Dreambox dm7025.