drivers/video/geode/lxfb_ops.c

   1 /* Geode LX framebuffer driver
   2  *
   3  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/fb.h>
  14 #include <linux/uaccess.h>
  15 #include <linux/delay.h>
  16 #include <asm/geode.h>
  17
  18 #include "lxfb.h"
  19
  20 /* TODO
  21  * Support panel scaling
  22  * Add acceleration
  23  * Add support for interlacing (TV out)
  24  * Support compression
  25  */
  26
  27 /* This is the complete list of PLL frequencies that we can set -
  28  * we will choose the closest match to the incoming clock.
  29  * freq is the frequency of the dotclock * 1000 (for example,
  30  * 24823 = 24.983 Mhz).
  31  * pllval is the corresponding PLL value
  32 */
  33
  34 static const struct {
  35   unsigned int pllval;
  36   unsigned int freq;
  37 } pll_table[] = {
  38   { 0x000131AC,   6231 },
  39   { 0x0001215D,   6294 },
  40   { 0x00011087,   6750 },
  41   { 0x0001216C,   7081 },
  42   { 0x0001218D,   7140 },
  43   { 0x000110C9,   7800 },
  44   { 0x00013147,   7875 },
  45   { 0x000110A7,   8258 },
  46   { 0x00012159,   8778 },
  47   { 0x00014249,   8875 },
  48   { 0x00010057,   9000 },
  49   { 0x0001219A,   9472 },
  50   { 0x00012158,   9792 },
  51   { 0x00010045,  10000 },
  52   { 0x00010089,  10791 },
  53   { 0x000110E7,  11225 },
  54   { 0x00012136,  11430 },
  55   { 0x00013207,  12375 },
  56   { 0x00012187,  12500 },
  57   { 0x00014286,  14063 },
  58   { 0x000110E5,  15016 },
  59   { 0x00014214,  16250 },
  60   { 0x00011105,  17045 },
  61   { 0x000131E4,  18563 },
  62   { 0x00013183,  18750 },
  63   { 0x00014284,  19688 },
  64   { 0x00011104,  20400 },
  65   { 0x00016363,  23625 },
  66   { 0x00015303,  24380 },
  67   { 0x000031AC,  24923 },
  68   { 0x0000215D,  25175 },
  69   { 0x00001087,  27000 },
  70   { 0x0000216C,  28322 },
  71   { 0x0000218D,  28560 },
  72   { 0x00010041,  29913 },
  73   { 0x000010C9,  31200 },
  74   { 0x00003147,  31500 },
  75   { 0x000141A1,  32400 },
  76   { 0x000010A7,  33032 },
  77   { 0x00012182,  33375 },
  78   { 0x000141B1,  33750 },
  79   { 0x00002159,  35112 },
  80   { 0x00004249,  35500 },
  81   { 0x00000057,  36000 },
  82   { 0x000141E1,  37125 },
  83   { 0x0000219A,  37889 },
  84   { 0x00002158,  39168 },
  85   { 0x00000045,  40000 },
  86   { 0x000131A1,  40500 },
  87   { 0x00010061,  42301 },
  88   { 0x00000089,  43163 },
  89   { 0x00012151,  43875 },
  90   { 0x000010E7,  44900 },
  91   { 0x00002136,  45720 },
  92   { 0x000152E1,  47250 },
  93   { 0x00010071,  48000 },
  94   { 0x00003207,  49500 },
  95   { 0x00002187,  50000 },
  96   { 0x00014291,  50625 },
  97   { 0x00011101,  51188 },
  98   { 0x00017481,  54563 },
  99   { 0x00004286,  56250 },
 100   { 0x00014170,  57375 },
 101   { 0x00016210,  58500 },
 102   { 0x000010E5,  60065 },
 103   { 0x00013140,  62796 },
 104   { 0x00004214,  65000 },
 105   { 0x00016250,  65250 },
 106   { 0x00001105,  68179 },
 107   { 0x000141C0,  69600 },
 108   { 0x00015220,  70160 },
 109   { 0x00010050,  72000 },
 110   { 0x000031E4,  74250 },
 111   { 0x00003183,  75000 },
 112   { 0x00004284,  78750 },
 113   { 0x00012130,  80052 },
 114   { 0x00001104,  81600 },
 115   { 0x00006363,  94500 },
 116   { 0x00005303,  97520 },
 117   { 0x00002183, 100187 },
 118   { 0x00002122, 101420 },
 119   { 0x00001081, 108000 },
 120   { 0x00006201, 113310 },
 121   { 0x00000041, 119650 },
 122   { 0x000041A1, 129600 },
 123   { 0x00002182, 133500 },
 124   { 0x000041B1, 135000 },
 125   { 0x00000051, 144000 },
 126   { 0x000041E1, 148500 },
 127   { 0x000062D1, 157500 },
 128   { 0x000031A1, 162000 },
 129   { 0x00000061, 169203 },
 130   { 0x00004231, 172800 },
 131   { 0x00002151, 175500 },
 132   { 0x000052E1, 189000 },
 133   { 0x00000071, 192000 },
 134   { 0x00003201, 198000 },
 135   { 0x00004291, 202500 },
 136   { 0x00001101, 204750 },
 137   { 0x00007481, 218250 },
 138   { 0x00004170, 229500 },
 139   { 0x00006210, 234000 },
 140   { 0x00003140, 251182 },
 141   { 0x00006250, 261000 },
 142   { 0x000041C0, 278400 },
 143   { 0x00005220, 280640 },
 144   { 0x00000050, 288000 },
 145   { 0x000041E0, 297000 },
 146   { 0x00002130, 320207 }
 147 };
 148
 149
 150 static void lx_set_dotpll(u32 pllval)
 151 {
 152         u32 dotpll_lo, dotpll_hi;
 153         int i;
 154
 155         rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 156
 157         if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
 158                 return;
 159
 160         dotpll_hi = pllval;
 161         dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
 162         dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
 163
 164         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 165
 166         /* Wait 100us for the PLL to lock */
 167
 168         udelay(100);
 169
 170         /* Now, loop for the lock bit */
 171
 172         for (i = 0; i < 1000; i++) {
 173                 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 174                 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
 175                         break;
 176         }
 177
 178         /* Clear the reset bit */
 179
 180         dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
 181         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 182 }
 183
 184 /* Set the clock based on the frequency specified by the current mode */
 185
 186 static void lx_set_clock(struct fb_info *info)
 187 {
 188         unsigned int diff, min, best = 0;
 189         unsigned int freq, i;
 190
 191         freq = (unsigned int) (1000000000 / info->var.pixclock);
 192
 193         min = abs(pll_table[0].freq - freq);
 194
 195         for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
 196                 diff = abs(pll_table[i].freq - freq);
 197                 if (diff < min) {
 198                         min = diff;
 199                         best = i;
 200                 }
 201         }
 202
 203         lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
 204 }
 205
 206 static void lx_graphics_disable(struct fb_info *info)
 207 {
 208         struct lxfb_par *par = info->par;
 209         unsigned int val, gcfg;
 210
 211         /* Note:  This assumes that the video is in a quitet state */
 212
 213         write_vp(par, VP_A1T, 0);
 214         write_vp(par, VP_A2T, 0);
 215         write_vp(par, VP_A3T, 0);
 216
 217         /* Turn off the VGA and video enable */
 218         val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
 219                         DC_GENERAL_CFG_VIDE);
 220
 221         write_dc(par, DC_GENERAL_CFG, val);
 222
 223         val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
 224         write_vp(par, VP_VCFG, val);
 225
 226         write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
 227                         DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
 228
 229         val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
 230         write_dc(par, DC_GENLK_CTL, val);
 231
 232         val = read_dc(par, DC_CLR_KEY);
 233         write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
 234
 235         /* turn off the panel */
 236         write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
 237
 238         val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
 239         write_vp(par, VP_MISC, val);
 240
 241         /* Turn off the display */
 242
 243         val = read_vp(par, VP_DCFG);
 244         write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 245                         VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
 246
 247         gcfg = read_dc(par, DC_GENERAL_CFG);
 248         gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
 249         write_dc(par, DC_GENERAL_CFG, gcfg);
 250
 251         /* Turn off the TGEN */
 252         val = read_dc(par, DC_DISPLAY_CFG);
 253         val &= ~DC_DISPLAY_CFG_TGEN;
 254         write_dc(par, DC_DISPLAY_CFG, val);
 255
 256         /* Wait 1000 usecs to ensure that the TGEN is clear */
 257         udelay(1000);
 258
 259         /* Turn off the FIFO loader */
 260
 261         gcfg &= ~DC_GENERAL_CFG_DFLE;
 262         write_dc(par, DC_GENERAL_CFG, gcfg);
 263
 264         /* Lastly, wait for the GP to go idle */
 265
 266         do {
 267                 val = read_gp(par, GP_BLT_STATUS);
 268         } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
 269 }
 270
 271 static void lx_graphics_enable(struct fb_info *info)
 272 {
 273         struct lxfb_par *par = info->par;
 274         u32 temp, config;
 275
 276         /* Set the video request register */
 277         write_vp(par, VP_VRR, 0);
 278
 279         /* Set up the polarities */
 280
 281         config = read_vp(par, VP_DCFG);
 282
 283         config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
 284                         VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
 285
 286         config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
 287                         | VP_DCFG_GV_GAM);
 288
 289         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 290                 config |= VP_DCFG_CRT_HSYNC_POL;
 291
 292         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 293                 config |= VP_DCFG_CRT_VSYNC_POL;
 294
 295         if (par->output & OUTPUT_PANEL) {
 296                 u32 msrlo, msrhi;
 297
 298                 write_fp(par, FP_PT1, 0);
 299                 write_fp(par, FP_PT2, FP_PT2_SCRC);
 300                 write_fp(par, FP_DFC, FP_DFC_BC);
 301
 302                 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
 303                 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
 304
 305                 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
 306         }
 307
 308         if (par->output & OUTPUT_CRT) {
 309                 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 310                                 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
 311         }
 312
 313         write_vp(par, VP_DCFG, config);
 314
 315         /* Turn the CRT dacs back on */
 316
 317         if (par->output & OUTPUT_CRT) {
 318                 temp = read_vp(par, VP_MISC);
 319                 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
 320                 write_vp(par, VP_MISC, temp);
 321         }
 322
 323         /* Turn the panel on (if it isn't already) */
 324         if (par->output & OUTPUT_PANEL)
 325                 write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
 326 }
 327
 328 unsigned int lx_framebuffer_size(void)
 329 {
 330         unsigned int val;
 331
 332         if (!geode_has_vsa2()) {
 333                 uint32_t hi, lo;
 334
 335                 /* The number of pages is (PMAX - PMIN)+1 */
 336                 rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
 337
 338                 /* PMAX */
 339                 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
 340                 /* PMIN */
 341                 val -= (lo & 0x000fffff);
 342                 val += 1;
 343
 344                 /* The page size is 4k */
 345                 return (val << 12);
 346         }
 347
 348         /* The frame buffer size is reported by a VSM in VSA II */
 349         /* Virtual Register Class    = 0x02                     */
 350         /* VG_MEM_SIZE (1MB units)   = 0x00                     */
 351
 352         outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
 353         outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
 354
 355         val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
 356         return (val << 20);
 357 }
 358
 359 void lx_set_mode(struct fb_info *info)
 360 {
 361         struct lxfb_par *par = info->par;
 362         u64 msrval;
 363
 364         unsigned int max, dv, val, size;
 365
 366         unsigned int gcfg, dcfg;
 367         int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
 368         int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
 369
 370         /* Unlock the DC registers */
 371         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 372
 373         lx_graphics_disable(info);
 374
 375         lx_set_clock(info);
 376
 377         /* Set output mode */
 378
 379         rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 380         msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
 381
 382         if (par->output & OUTPUT_PANEL) {
 383                 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
 384
 385                 if (par->output & OUTPUT_CRT)
 386                         msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
 387                 else
 388                         msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
 389         } else
 390                 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
 391
 392         wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 393
 394         /* Clear the various buffers */
 395         /* FIXME:  Adjust for panning here */
 396
 397         write_dc(par, DC_FB_ST_OFFSET, 0);
 398         write_dc(par, DC_CB_ST_OFFSET, 0);
 399         write_dc(par, DC_CURS_ST_OFFSET, 0);
 400
 401         /* FIXME: Add support for interlacing */
 402         /* FIXME: Add support for scaling */
 403
 404         val = read_dc(par, DC_GENLK_CTL);
 405         val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
 406                         DC_GENLK_CTL_FLICK_SEL_MASK);
 407
 408         /* Default scaling params */
 409
 410         write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
 411         write_dc(par, DC_IRQ_FILT_CTL, 0);
 412         write_dc(par, DC_GENLK_CTL, val);
 413
 414         /* FIXME:  Support compression */
 415
 416         if (info->fix.line_length > 4096)
 417                 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
 418         else if (info->fix.line_length > 2048)
 419                 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
 420         else if (info->fix.line_length > 1024)
 421                 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
 422         else
 423                 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
 424
 425         max = info->fix.line_length * info->var.yres;
 426         max = (max + 0x3FF) & 0xFFFFFC00;
 427
 428         write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
 429
 430         val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
 431         write_dc(par, DC_DV_CTL, val | dv);
 432
 433         size = info->var.xres * (info->var.bits_per_pixel >> 3);
 434
 435         write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
 436         write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
 437
 438         /* Set default watermark values */
 439
 440         rdmsrl(MSR_LX_SPARE_MSR, msrval);
 441
 442         msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
 443                         | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
 444                         | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
 445                         | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
 446         msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
 447                         MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
 448         wrmsrl(MSR_LX_SPARE_MSR, msrval);
 449
 450         gcfg = DC_GENERAL_CFG_DFLE;   /* Display fifo enable */
 451         gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
 452                         (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
 453         gcfg |= DC_GENERAL_CFG_FDTY;  /* Set the frame dirty mode */
 454
 455         dcfg  = DC_DISPLAY_CFG_VDEN;  /* Enable video data */
 456         dcfg |= DC_DISPLAY_CFG_GDEN;  /* Enable graphics */
 457         dcfg |= DC_DISPLAY_CFG_TGEN;  /* Turn on the timing generator */
 458         dcfg |= DC_DISPLAY_CFG_TRUP;  /* Update timings immediately */
 459         dcfg |= DC_DISPLAY_CFG_PALB;  /* Palette bypass in > 8 bpp modes */
 460         dcfg |= DC_DISPLAY_CFG_VISL;
 461         dcfg |= DC_DISPLAY_CFG_DCEN;  /* Always center the display */
 462
 463         /* Set the current BPP mode */
 464
 465         switch (info->var.bits_per_pixel) {
 466         case 8:
 467                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
 468                 break;
 469
 470         case 16:
 471                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
 472                 break;
 473
 474         case 32:
 475         case 24:
 476                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
 477                 break;
 478         }
 479
 480         /* Now - set up the timings */
 481
 482         hactive = info->var.xres;
 483         hblankstart = hactive;
 484         hsyncstart = hblankstart + info->var.right_margin;
 485         hsyncend =  hsyncstart + info->var.hsync_len;
 486         hblankend = hsyncend + info->var.left_margin;
 487         htotal = hblankend;
 488
 489         vactive = info->var.yres;
 490         vblankstart = vactive;
 491         vsyncstart = vblankstart + info->var.lower_margin;
 492         vsyncend =  vsyncstart + info->var.vsync_len;
 493         vblankend = vsyncend + info->var.upper_margin;
 494         vtotal = vblankend;
 495
 496         write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
 497         write_dc(par, DC_H_BLANK_TIMING,
 498                         (hblankstart - 1) | ((hblankend - 1) << 16));
 499         write_dc(par, DC_H_SYNC_TIMING,
 500                         (hsyncstart - 1) | ((hsyncend - 1) << 16));
 501
 502         write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
 503         write_dc(par, DC_V_BLANK_TIMING,
 504                         (vblankstart - 1) | ((vblankend - 1) << 16));
 505         write_dc(par, DC_V_SYNC_TIMING,
 506                         (vsyncstart - 1) | ((vsyncend - 1) << 16));
 507
 508         write_dc(par, DC_FB_ACTIVE,
 509                         (info->var.xres - 1) << 16 | (info->var.yres - 1));
 510
 511         /* And re-enable the graphics output */
 512         lx_graphics_enable(info);
 513
 514         /* Write the two main configuration registers */
 515         write_dc(par, DC_DISPLAY_CFG, dcfg);
 516         write_dc(par, DC_ARB_CFG, 0);
 517         write_dc(par, DC_GENERAL_CFG, gcfg);
 518
 519         /* Lock the DC registers */
 520         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 521 }
 522
 523 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
 524                         unsigned red, unsigned green, unsigned blue)
 525 {
 526         struct lxfb_par *par = info->par;
 527         int val;
 528
 529         /* Hardware palette is in RGB 8-8-8 format. */
 530
 531         val  = (red   << 8) & 0xff0000;
 532         val |= (green)      & 0x00ff00;
 533         val |= (blue  >> 8) & 0x0000ff;
 534
 535         write_dc(par, DC_PAL_ADDRESS, regno);
 536         write_dc(par, DC_PAL_DATA, val);
 537 }
 538
 539 int lx_blank_display(struct fb_info *info, int blank_mode)
 540 {
 541         struct lxfb_par *par = info->par;
 542         u32 dcfg, fp_pm;
 543         int blank, hsync, vsync, crt;
 544
 545         /* CRT power saving modes. */
 546         switch (blank_mode) {
 547         case FB_BLANK_UNBLANK:
 548                 blank = 0; hsync = 1; vsync = 1; crt = 1;
 549                 break;
 550         case FB_BLANK_NORMAL:
 551                 blank = 1; hsync = 1; vsync = 1; crt = 1;
 552                 break;
 553         case FB_BLANK_VSYNC_SUSPEND:
 554                 blank = 1; hsync = 1; vsync = 0; crt = 1;
 555                 break;
 556         case FB_BLANK_HSYNC_SUSPEND:
 557                 blank = 1; hsync = 0; vsync = 1; crt = 1;
 558                 break;
 559         case FB_BLANK_POWERDOWN:
 560                 blank = 1; hsync = 0; vsync = 0; crt = 0;
 561                 break;
 562         default:
 563                 return -EINVAL;
 564         }
 565
 566         dcfg = read_vp(par, VP_DCFG);
 567         dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
 568                         VP_DCFG_CRT_EN);
 569         if (!blank)
 570                 dcfg |= VP_DCFG_DAC_BL_EN;
 571         if (hsync)
 572                 dcfg |= VP_DCFG_HSYNC_EN;
 573         if (vsync)
 574                 dcfg |= VP_DCFG_VSYNC_EN;
 575         if (crt)
 576                 dcfg |= VP_DCFG_CRT_EN;
 577         write_vp(par, VP_DCFG, dcfg);
 578
 579         /* Power on/off flat panel */
 580
 581         if (par->output & OUTPUT_PANEL) {
 582                 fp_pm = read_fp(par, FP_PM);
 583                 if (blank_mode == FB_BLANK_POWERDOWN)
 584                         fp_pm &= ~FP_PM_P;
 585                 else
 586                         fp_pm |= FP_PM_P;
 587                 write_fp(par, FP_PM, fp_pm);
 588         }
 589
 590         return 0;
 591 }
 592
 593 #ifdef CONFIG_PM
 594
 595 static void lx_save_regs(struct lxfb_par *par)
 596 {
 597         uint32_t filt;
 598         int i;
 599
 600         /* wait for the BLT engine to stop being busy */
 601         do {
 602                 i = read_gp(par, GP_BLT_STATUS);
 603         } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
 604
 605         /* save MSRs */
 606         rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
 607         rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
 608         rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
 609         rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
 610
 611         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 612
 613         /* save registers */
 614         memcpy(par->gp, par->gp_regs, sizeof(par->gp));
 615         memcpy(par->dc, par->dc_regs, sizeof(par->dc));
 616         memcpy(par->vp, par->vp_regs, sizeof(par->vp));
 617         memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
 618
 619         /* save the palette */
 620         write_dc(par, DC_PAL_ADDRESS, 0);
 621         for (i = 0; i < ARRAY_SIZE(par->pal); i++)
 622                 par->pal[i] = read_dc(par, DC_PAL_DATA);
 623
 624         /* save the horizontal filter coefficients */
 625         filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
 626         for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
 627                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 628                 par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
 629                 par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
 630         }
 631
 632         /* save the vertical filter coefficients */
 633         filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
 634         for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
 635                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 636                 par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
 637         }
 638
 639         /* save video coeff ram */
 640         memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
 641 }
 642
 643 static void lx_restore_gfx_proc(struct lxfb_par *par)
 644 {
 645         int i;
 646
 647         /* a bunch of registers require GP_RASTER_MODE to be set first */
 648         write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
 649
 650         for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
 651                 switch (i) {
 652                 case GP_RASTER_MODE:
 653                 case GP_VECTOR_MODE:
 654                 case GP_BLT_MODE:
 655                 case GP_BLT_STATUS:
 656                 case GP_HST_SRC:
 657                         /* FIXME: restore LUT data */
 658                 case GP_LUT_INDEX:
 659                 case GP_LUT_DATA:
 660                         /* don't restore these registers */
 661                         break;
 662
 663                 default:
 664                         write_gp(par, i, par->gp[i]);
 665                 }
 666         }
 667 }
 668
 669 static void lx_restore_display_ctlr(struct lxfb_par *par)
 670 {
 671         uint32_t filt;
 672         int i;
 673
 674         wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
 675
 676         for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
 677                 switch (i) {
 678                 case DC_UNLOCK:
 679                         /* unlock the DC; runs first */
 680                         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 681                         break;
 682
 683                 case DC_GENERAL_CFG:
 684                 case DC_DISPLAY_CFG:
 685                         /* disable all while restoring */
 686                         write_dc(par, i, 0);
 687                         break;
 688
 689                 case DC_DV_CTL:
 690                         /* set all ram to dirty */
 691                         write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
 692
 693                 case DC_RSVD_1:
 694                 case DC_RSVD_2:
 695                 case DC_RSVD_3:
 696                 case DC_LINE_CNT:
 697                 case DC_PAL_ADDRESS:
 698                 case DC_PAL_DATA:
 699                 case DC_DFIFO_DIAG:
 700                 case DC_CFIFO_DIAG:
 701                 case DC_FILT_COEFF1:
 702                 case DC_FILT_COEFF2:
 703                 case DC_RSVD_4:
 704                 case DC_RSVD_5:
 705                         /* don't restore these registers */
 706                         break;
 707
 708                 default:
 709                         write_dc(par, i, par->dc[i]);
 710                 }
 711         }
 712
 713         /* restore the palette */
 714         write_dc(par, DC_PAL_ADDRESS, 0);
 715         for (i = 0; i < ARRAY_SIZE(par->pal); i++)
 716                 write_dc(par, DC_PAL_DATA, par->pal[i]);
 717
 718         /* restore the horizontal filter coefficients */
 719         filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
 720         for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
 721                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 722                 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
 723                 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
 724         }
 725
 726         /* restore the vertical filter coefficients */
 727         filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
 728         for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
 729                 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
 730                 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
 731         }
 732 }
 733
 734 static void lx_restore_video_proc(struct lxfb_par *par)
 735 {
 736         int i;
 737
 738         wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
 739         wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
 740
 741         for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
 742                 switch (i) {
 743                 case VP_VCFG:
 744                 case VP_DCFG:
 745                 case VP_PAR:
 746                 case VP_PDR:
 747                 case VP_CCS:
 748                 case VP_RSVD_0:
 749                 /* case VP_VDC: */ /* why should this not be restored? */
 750                 case VP_RSVD_1:
 751                 case VP_CRC32:
 752                         /* don't restore these registers */
 753                         break;
 754
 755                 default:
 756                         write_vp(par, i, par->vp[i]);
 757                 }
 758         }
 759
 760         /* restore video coeff ram */
 761         memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
 762 }
 763
 764 static void lx_restore_regs(struct lxfb_par *par)
 765 {
 766         int i;
 767
 768         lx_set_dotpll((u32) (par->msr.dotpll >> 32));
 769         lx_restore_gfx_proc(par);
 770         lx_restore_display_ctlr(par);
 771         lx_restore_video_proc(par);
 772
 773         /* Flat Panel */
 774         for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
 775                 switch (i) {
 776                 case FP_PM:
 777                 case FP_RSVD_0:
 778                 case FP_RSVD_1:
 779                 case FP_RSVD_2:
 780                 case FP_RSVD_3:
 781                 case FP_RSVD_4:
 782                         /* don't restore these registers */
 783                         break;
 784
 785                 default:
 786                         write_fp(par, i, par->fp[i]);
 787                 }
 788         }
 789
 790         /* control the panel */
 791         if (par->fp[FP_PM] & FP_PM_P) {
 792                 /* power on the panel if not already power{ed,ing} on */
 793                 if (!(read_fp(par, FP_PM) &
 794                                 (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
 795                         write_fp(par, FP_PM, par->fp[FP_PM]);
 796         } else {
 797                 /* power down the panel if not already power{ed,ing} down */
 798                 if (!(read_fp(par, FP_PM) &
 799                                 (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
 800                         write_fp(par, FP_PM, par->fp[FP_PM]);
 801         }
 802
 803         /* turn everything on */
 804         write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
 805         write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
 806         write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
 807         /* do this last; it will enable the FIFO load */
 808         write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
 809
 810         /* lock the door behind us */
 811         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 812 }
 813
 814 int lx_powerdown(struct fb_info *info)
 815 {
 816         struct lxfb_par *par = info->par;
 817
 818         if (par->powered_down)
 819                 return 0;
 820
 821         lx_save_regs(par);
 822         lx_graphics_disable(info);
 823
 824         par->powered_down = 1;
 825         return 0;
 826 }
 827
 828 int lx_powerup(struct fb_info *info)
 829 {
 830         struct lxfb_par *par = info->par;
 831
 832         if (!par->powered_down)
 833                 return 0;
 834
 835         lx_restore_regs(par);
 836
 837         par->powered_down = 0;
 838         return 0;
 839 }
 840
 841 #endif