drivers/scsi/eata_generic.h

   1 /********************************************************
   2 * Header file for eata_dma.c and eata_pio.c             *
   3 * Linux EATA SCSI drivers                               *
   4 * (c) 1993-96 Michael Neuffer                           *
   5 *             mike@i-Connect.Net                        *
   6 *             neuffer@mail.uni-mainz.de                 *
   7 *********************************************************
   8 * last change: 96/08/14                                 *
   9 ********************************************************/
  10
  11
  12 #ifndef _EATA_GENERIC_H
  13 #define _EATA_GENERIC_H
  14
  15
  16
  17 /*********************************************
  18  * Misc. definitions                         *
  19  *********************************************/
  20
  21 #ifndef TRUE
  22 #define TRUE 1
  23 #endif
  24 #ifndef FALSE
  25 #define FALSE 0
  26 #endif
  27
  28 #define R_LIMIT 0x20000
  29
  30 #define MAXISA     4
  31 #define MAXEISA   16
  32 #define MAXPCI    16
  33 #define MAXIRQ    16
  34 #define MAXTARGET 16
  35 #define MAXCHANNEL 3
  36
  37 #define IS_ISA     'I'
  38 #define IS_EISA    'E'
  39 #define IS_PCI     'P'
  40
  41 #define BROKEN_INQUIRY  1
  42
  43 #define BUSMASTER       0xff
  44 #define PIO             0xfe
  45
  46 #define EATA_SIGNATURE  0x45415441     /* BIG ENDIAN coded "EATA" sig.   */
  47
  48 #define DPT_ID1         0x12
  49 #define DPT_ID2         0x14
  50
  51 #define ATT_ID1         0x06
  52 #define ATT_ID2         0x94
  53 #define ATT_ID3         0x0
  54
  55 #define NEC_ID1         0x38
  56 #define NEC_ID2         0xa3
  57 #define NEC_ID3         0x82
  58
  59
  60 #define EATA_CP_SIZE     44
  61
  62 #define MAX_PCI_DEVICES  32            /* Maximum # Of Devices Per Bus   */
  63 #define MAX_METHOD_2     16            /* Max Devices For Method 2       */
  64 #define MAX_PCI_BUS      16            /* Maximum # Of Busses Allowed    */
  65
  66 #define SG_SIZE          64
  67 #define SG_SIZE_BIG      252           /* max. 8096 elements, 64k */
  68
  69 #define UPPER_DEVICE_QUEUE_LIMIT 64    /* The limit we have to set for the
  70                                         * device queue to keep the broken
  71                                         * midlevel SCSI code from producing
  72                                         * bogus timeouts
  73                                         */
  74
  75 #define TYPE_DISK_QUEUE  16
  76 #define TYPE_TAPE_QUEUE  4
  77 #define TYPE_ROM_QUEUE   4
  78 #define TYPE_OTHER_QUEUE 2
  79
  80 #define FREE             0
  81 #define OK               0
  82 #define NO_TIMEOUT       0
  83 #define USED             1
  84 #define TIMEOUT          2
  85 #define RESET            4
  86 #define LOCKED           8
  87 #define ABORTED          16
  88
  89 #define READ             0
  90 #define WRITE            1
  91 #define OTHER            2
  92
  93 #define HD(cmd)  ((hostdata *)&(cmd->device->host->hostdata))
  94 #define CD(cmd)  ((struct eata_ccb *)(cmd->host_scribble))
  95 #define SD(host) ((hostdata *)&(host->hostdata))
  96
  97 /***********************************************
  98  *    EATA Command & Register definitions      *
  99  ***********************************************/
 100 #define PCI_REG_DPTconfig        0x40
 101 #define PCI_REG_PumpModeAddress  0x44
 102 #define PCI_REG_PumpModeData     0x48
 103 #define PCI_REG_ConfigParam1     0x50
 104 #define PCI_REG_ConfigParam2     0x54
 105
 106
 107 #define EATA_CMD_PIO_SETUPTEST   0xc6
 108 #define EATA_CMD_PIO_READ_CONFIG 0xf0
 109 #define EATA_CMD_PIO_SET_CONFIG  0xf1
 110 #define EATA_CMD_PIO_SEND_CP     0xf2
 111 #define EATA_CMD_PIO_RECEIVE_SP  0xf3
 112 #define EATA_CMD_PIO_TRUNC       0xf4
 113
 114 #define EATA_CMD_RESET           0xf9
 115 #define EATA_CMD_IMMEDIATE       0xfa
 116
 117 #define EATA_CMD_DMA_READ_CONFIG 0xfd
 118 #define EATA_CMD_DMA_SET_CONFIG  0xfe
 119 #define EATA_CMD_DMA_SEND_CP     0xff
 120
 121 #define ECS_EMULATE_SENSE        0xd4
 122
 123 #define EATA_GENERIC_ABORT       0x00
 124 #define EATA_SPECIFIC_RESET      0x01
 125 #define EATA_BUS_RESET           0x02
 126 #define EATA_SPECIFIC_ABORT      0x03
 127 #define EATA_QUIET_INTR          0x04
 128 #define EATA_COLD_BOOT_HBA       0x06      /* Only as a last resort     */
 129 #define EATA_FORCE_IO            0x07
 130
 131 #define HA_CTRLREG     0x206       /* control register for HBA    */
 132 #define HA_CTRL_DISINT 0x02        /* CTRLREG: disable interrupts */
 133 #define HA_CTRL_RESCPU 0x04        /* CTRLREG: reset processor    */
 134 #define HA_CTRL_8HEADS 0x08        /* CTRLREG: set for drives with*
 135                                     * >=8 heads (WD1003 rudimentary :-) */
 136
 137 #define HA_WCOMMAND    0x07        /* command register offset   */
 138 #define HA_WIFC        0x06        /* immediate command offset  */
 139 #define HA_WCODE       0x05
 140 #define HA_WCODE2      0x04
 141 #define HA_WDMAADDR    0x02        /* DMA address LSB offset    */
 142 #define HA_RAUXSTAT    0x08        /* aux status register offset*/
 143 #define HA_RSTATUS     0x07        /* status register offset    */
 144 #define HA_RDATA       0x00        /* data register (16bit)     */
 145 #define HA_WDATA       0x00        /* data register (16bit)     */
 146
 147 #define HA_ABUSY       0x01        /* aux busy bit              */
 148 #define HA_AIRQ        0x02        /* aux IRQ pending bit       */
 149 #define HA_SERROR      0x01        /* pr. command ended in error*/
 150 #define HA_SMORE       0x02        /* more data soon to come    */
 151 #define HA_SCORR       0x04        /* data corrected            */
 152 #define HA_SDRQ        0x08        /* data request active       */
 153 #define HA_SSC         0x10        /* seek complete             */
 154 #define HA_SFAULT      0x20        /* write fault               */
 155 #define HA_SREADY      0x40        /* drive ready               */
 156 #define HA_SBUSY       0x80        /* drive busy                */
 157 #define HA_SDRDY       HA_SSC+HA_SREADY+HA_SDRQ
 158
 159 /**********************************************
 160  * Message definitions                        *
 161  **********************************************/
 162
 163 #define HA_NO_ERROR      0x00   /* No Error                             */
 164 #define HA_ERR_SEL_TO    0x01   /* Selection Timeout                    */
 165 #define HA_ERR_CMD_TO    0x02   /* Command Timeout                      */
 166 #define HA_BUS_RESET     0x03   /* SCSI Bus Reset Received              */
 167 #define HA_INIT_POWERUP  0x04   /* Initial Controller Power-up          */
 168 #define HA_UNX_BUSPHASE  0x05   /* Unexpected Bus Phase                 */
 169 #define HA_UNX_BUS_FREE  0x06   /* Unexpected Bus Free                  */
 170 #define HA_BUS_PARITY    0x07   /* Bus Parity Error                     */
 171 #define HA_SCSI_HUNG     0x08   /* SCSI Hung                            */
 172 #define HA_UNX_MSGRJCT   0x09   /* Unexpected Message Rejected          */
 173 #define HA_RESET_STUCK   0x0a   /* SCSI Bus Reset Stuck                 */
 174 #define HA_RSENSE_FAIL   0x0b   /* Auto Request-Sense Failed            */
 175 #define HA_PARITY_ERR    0x0c   /* Controller Ram Parity Error          */
 176 #define HA_CP_ABORT_NA   0x0d   /* Abort Message sent to non-active cmd */
 177 #define HA_CP_ABORTED    0x0e   /* Abort Message sent to active cmd     */
 178 #define HA_CP_RESET_NA   0x0f   /* Reset Message sent to non-active cmd */
 179 #define HA_CP_RESET      0x10   /* Reset Message sent to active cmd     */
 180 #define HA_ECC_ERR       0x11   /* Controller Ram ECC Error             */
 181 #define HA_PCI_PARITY    0x12   /* PCI Parity Error                     */
 182 #define HA_PCI_MABORT    0x13   /* PCI Master Abort                     */
 183 #define HA_PCI_TABORT    0x14   /* PCI Target Abort                     */
 184 #define HA_PCI_STABORT   0x15   /* PCI Signaled Target Abort            */
 185
 186 /**********************************************
 187  *  Other  definitions                        *
 188  **********************************************/
 189
 190 struct reg_bit {      /* reading this one will clear the interrupt    */
 191     __u8 error:1;     /* previous command ended in an error           */
 192     __u8 more:1;      /* more DATA coming soon, poll BSY & DRQ (PIO)  */
 193     __u8 corr:1;      /* data read was successfully corrected with ECC*/
 194     __u8 drq:1;       /* data request active  */
 195     __u8 sc:1;        /* seek complete        */
 196     __u8 fault:1;     /* write fault          */
 197     __u8 ready:1;     /* drive ready          */
 198     __u8 busy:1;      /* controller busy      */
 199 };
 200
 201 struct reg_abit {     /* reading this won't clear the interrupt */
 202     __u8 abusy:1;     /* auxiliary busy                         */
 203     __u8 irq:1;       /* set when drive interrupt is asserted   */
 204     __u8 dummy:6;
 205 };
 206
 207 struct eata_register {      /* EATA register set */
 208     __u8 data_reg[2];       /* R, couldn't figure this one out          */
 209     __u8 cp_addr[4];        /* W, CP address register                   */
 210     union {
 211         __u8 command;       /* W, command code: [read|set] conf, send CP*/
 212         struct reg_bit status;  /* R, see register_bit1                 */
 213         __u8 statusbyte;
 214     } ovr;
 215     struct reg_abit aux_stat; /* R, see register_bit2                   */
 216 };
 217
 218 struct get_conf {             /* Read Configuration Array               */
 219     __u32  len;               /* Should return 0x22, 0x24, etc          */
 220     __u32 signature;          /* Signature MUST be "EATA"               */
 221     __u8    version2:4,
 222              version:4;       /* EATA Version level                     */
 223     __u8 OCS_enabled:1,       /* Overlap Command Support enabled        */
 224          TAR_support:1,       /* SCSI Target Mode supported             */
 225               TRNXFR:1,       /* Truncate Transfer Cmd not necessary    *
 226                                * Only used in PIO Mode                  */
 227         MORE_support:1,       /* MORE supported (only PIO Mode)         */
 228          DMA_support:1,       /* DMA supported Driver uses only         *
 229                                * this mode                              */
 230            DMA_valid:1,       /* DRQ value in Byte 30 is valid          */
 231                  ATA:1,       /* ATA device connected (not supported)   */
 232            HAA_valid:1;       /* Hostadapter Address is valid           */
 233
 234     __u16 cppadlen;           /* Number of pad bytes send after CD data *
 235                                * set to zero for DMA commands           */
 236     __u8 scsi_id[4];          /* SCSI ID of controller 2-0 Byte 0 res.  *
 237                                * if not, zero is returned               */
 238     __u32  cplen;             /* CP length: number of valid cp bytes    */
 239     __u32  splen;             /* Number of bytes returned after         *
 240                                * Receive SP command                     */
 241     __u16 queuesiz;           /* max number of queueable CPs            */
 242     __u16 dummy;
 243     __u16 SGsiz;              /* max number of SG table entries         */
 244     __u8    IRQ:4,            /* IRQ used this HA                       */
 245          IRQ_TR:1,            /* IRQ Trigger: 0=edge, 1=level           */
 246          SECOND:1,            /* This is a secondary controller         */
 247     DMA_channel:2;            /* DRQ index, DRQ is 2comp of DRQX        */
 248     __u8 sync;                /* device at ID 7 tru 0 is running in     *
 249                                * synchronous mode, this will disappear  */
 250     __u8   DSBLE:1,           /* ISA i/o addressing is disabled         */
 251          FORCADR:1,           /* i/o address has been forced            */
 252           SG_64K:1,
 253           SG_UAE:1,
 254                 :4;
 255     __u8  MAX_ID:5,           /* Max number of SCSI target IDs          */
 256         MAX_CHAN:3;           /* Number of SCSI busses on HBA           */
 257     __u8 MAX_LUN;             /* Max number of LUNs                     */
 258     __u8        :3,
 259          AUTOTRM:1,
 260          M1_inst:1,
 261          ID_qest:1,           /* Raidnum ID is questionable             */
 262           is_PCI:1,           /* HBA is PCI                             */
 263          is_EISA:1;           /* HBA is EISA                            */
 264     __u8 RAIDNUM;             /* unique HBA identifier                  */
 265     __u8 unused[474];
 266 };
 267
 268 struct eata_sg_list
 269 {
 270     __u32 data;
 271     __u32 len;
 272 };
 273
 274 struct eata_ccb {             /* Send Command Packet structure      */
 275
 276     __u8 SCSI_Reset:1,        /* Cause a SCSI Bus reset on the cmd      */
 277            HBA_Init:1,        /* Cause Controller to reinitialize       */
 278        Auto_Req_Sen:1,        /* Do Auto Request Sense on errors        */
 279             scatter:1,        /* Data Ptr points to a SG Packet         */
 280              Resrvd:1,        /* RFU                                    */
 281           Interpret:1,        /* Interpret the SCSI cdb of own use      */
 282             DataOut:1,        /* Data Out phase with command            */
 283              DataIn:1;        /* Data In phase with command             */
 284     __u8 reqlen;              /* Request Sense Length                   *
 285                                * Valid if Auto_Req_Sen=1                */
 286     __u8 unused[3];
 287     __u8  FWNEST:1,           /* send cmd to phys RAID component        */
 288          unused2:7;
 289     __u8 Phsunit:1,           /* physical unit on mirrored pair         */
 290             I_AT:1,           /* inhibit address translation            */
 291          I_HBA_C:1,           /* HBA inhibit caching                    */
 292          unused3:5;
 293
 294     __u8     cp_id:5,         /* SCSI Device ID of target               */
 295         cp_channel:3;         /* SCSI Channel # of HBA                  */
 296     __u8    cp_lun:3,
 297                   :2,
 298          cp_luntar:1,         /* CP is for target ROUTINE               */
 299          cp_dispri:1,         /* Grant disconnect privilege             */
 300        cp_identify:1;         /* Always TRUE                            */
 301     __u8 cp_msg1;             /* Message bytes 0-3                      */
 302     __u8 cp_msg2;
 303     __u8 cp_msg3;
 304     __u8 cp_cdb[12];          /* Command Descriptor Block               */
 305     __u32 cp_datalen;         /* Data Transfer Length                   *
 306                                * If scatter=1 len of sg package         */
 307     void *cp_viraddr;         /* address of this ccb                    */
 308     __u32 cp_dataDMA;         /* Data Address, if scatter=1             *
 309                                * address of scatter packet              */
 310     __u32 cp_statDMA;         /* address for Status Packet              */
 311     __u32 cp_reqDMA;          /* Request Sense Address, used if         *
 312                                * CP command ends with error             */
 313     /* Additional CP info begins here */
 314     __u32 timestamp;          /* Needed to measure command latency      */
 315     __u32 timeout;
 316     __u8 sizeindex;
 317     __u8 rw_latency;
 318     __u8 retries;
 319     __u8 status;              /* status of this queueslot               */
 320     struct scsi_cmnd *cmd;    /* address of cmd                         */
 321     struct eata_sg_list *sg_list;
 322 };
 323
 324
 325 struct eata_sp {
 326     __u8 hba_stat:7,          /* HBA status                             */
 327               EOC:1;          /* True if command finished               */
 328     __u8 scsi_stat;           /* Target SCSI status                     */
 329     __u8 reserved[2];
 330     __u32  residue_len;       /* Number of bytes not transferred        */
 331     struct eata_ccb *ccb;     /* Address set in COMMAND PACKET          */
 332     __u8 msg[12];
 333 };
 334
 335 typedef struct hstd {
 336     __u8   vendor[9];
 337     __u8   name[18];
 338     __u8   revision[6];
 339     __u8   EATA_revision;
 340     __u32  firmware_revision;
 341     __u8   HBA_number;
 342     __u8   bustype;              /* bustype of HBA             */
 343     __u8   channel;              /* # of avail. scsi channels  */
 344     __u8   state;                /* state of HBA               */
 345     __u8   primary;              /* true if primary            */
 346     __u8        more_support:1,  /* HBA supports MORE flag     */
 347            immediate_support:1,  /* HBA supports IMMEDIATE CMDs*/
 348               broken_INQUIRY:1;  /* This is an EISA HBA with   *
 349                                   * broken INQUIRY             */
 350     __u8   do_latency;           /* Latency measurement flag   */
 351     __u32  reads[13];
 352     __u32  writes[13];
 353     __u32  reads_lat[12][4];
 354     __u32  writes_lat[12][4];
 355     __u32  all_lat[4];
 356     __u8   resetlevel[MAXCHANNEL];
 357     __u32  last_ccb;             /* Last used ccb              */
 358     __u32  cplen;                /* size of CP in words        */
 359     __u16  cppadlen;             /* pad length of cp in words  */
 360     __u16  queuesize;
 361     __u16  sgsize;               /* # of entries in the SG list*/
 362     __u16  devflags;             /* bits set for detected devices */
 363     __u8   hostid;               /* SCSI ID of HBA             */
 364     __u8   moresupport;          /* HBA supports MORE flag     */
 365     struct Scsi_Host *next;
 366     struct Scsi_Host *prev;
 367     struct pci_dev *pdev;       /* PCI device or NULL for non PCI */
 368     struct eata_sp sp;           /* status packet              */
 369     struct eata_ccb ccb[0];      /* ccb array begins here      */
 370 }hostdata;
 371
 372 /* structure for max. 2 emulated drives */
 373 struct drive_geom_emul {
 374     __u8  trans;                 /* translation flag 1=transl */
 375     __u8  channel;               /* SCSI channel number       */
 376     __u8  HBA;                   /* HBA number (prim/sec)     */
 377     __u8  id;                    /* drive id                  */
 378     __u8  lun;                   /* drive lun                 */
 379     __u32 heads;                 /* number of heads           */
 380     __u32 sectors;               /* number of sectors         */
 381     __u32 cylinder;              /* number of cylinders       */
 382 };
 383
 384 struct geom_emul {
 385     __u8 bios_drives;            /* number of emulated drives */
 386     struct drive_geom_emul drv[2]; /* drive structures        */
 387 };
 388
 389 #endif /* _EATA_GENERIC_H */
 390
 391 /*
 392  * Overrides for Emacs so that we almost follow Linus's tabbing style.
 393  * Emacs will notice this stuff at the end of the file and automatically
 394  * adjust the settings for this buffer only.  This must remain at the end
 395  * of the file.
 396  * ---------------------------------------------------------------------------
 397  * Local variables:
 398  * c-indent-level: 4
 399  * c-brace-imaginary-offset: 0
 400  * c-brace-offset: -4
 401  * c-argdecl-indent: 4
 402  * c-label-offset: -4
 403  * c-continued-statement-offset: 4
 404  * c-continued-brace-offset: 0
 405  * tab-width: 8
 406  * End:
 407  */