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jiffies_round-jiffies_round_relative-conversion-rt2x00-checkpatch-fixes
[linux-2.6/linux-trees-mm.git] / drivers / net / e100.c
blob9189affec1dad552a3a497a57f4d2617c7ec75a8
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * senario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 */
147
148 #include <linux/module.h>
149 #include <linux/moduleparam.h>
150 #include <linux/kernel.h>
151 #include <linux/types.h>
152 #include <linux/slab.h>
153 #include <linux/delay.h>
154 #include <linux/init.h>
155 #include <linux/pci.h>
156 #include <linux/dma-mapping.h>
157 #include <linux/netdevice.h>
158 #include <linux/etherdevice.h>
159 #include <linux/mii.h>
160 #include <linux/if_vlan.h>
161 #include <linux/skbuff.h>
162 #include <linux/ethtool.h>
163 #include <linux/string.h>
164 #include <asm/unaligned.h>
165
166
167 #define DRV_NAME "e100"
168 #define DRV_EXT "-NAPI"
169 #define DRV_VERSION "3.5.23-k4"DRV_EXT
170 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
171 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
172 #define PFX DRV_NAME ": "
173
174 #define E100_WATCHDOG_PERIOD (2 * HZ)
175 #define E100_NAPI_WEIGHT 16
176
177 MODULE_DESCRIPTION(DRV_DESCRIPTION);
178 MODULE_AUTHOR(DRV_COPYRIGHT);
179 MODULE_LICENSE("GPL");
180 MODULE_VERSION(DRV_VERSION);
181
182 static int debug = 3;
183 static int eeprom_bad_csum_allow = 0;
184 static int use_io = 0;
185 module_param(debug, int, 0);
186 module_param(eeprom_bad_csum_allow, int, 0);
187 module_param(use_io, int, 0);
188 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
189 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
190 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
191 #define DPRINTK(nlevel, klevel, fmt, args...) \
192 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
193 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
194 __FUNCTION__ , ## args))
195
196 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
197 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
198 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
199 static struct pci_device_id e100_id_table[] = {
200 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
201 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
202 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
203 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
204 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
205 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
206 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
207 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
208 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
209 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
210 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
211 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
212 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
213 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
214 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
215 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
216 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
217 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
218 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
219 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
220 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
221 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
222 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
223 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
224 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
225 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
226 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
227 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
228 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
229 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
230 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
231 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
232 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
233 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
234 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
235 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
236 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
237 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
238 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
239 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
240 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
241 { 0, }
242 };
243 MODULE_DEVICE_TABLE(pci, e100_id_table);
244
245 enum mac {
246 mac_82557_D100_A = 0,
247 mac_82557_D100_B = 1,
248 mac_82557_D100_C = 2,
249 mac_82558_D101_A4 = 4,
250 mac_82558_D101_B0 = 5,
251 mac_82559_D101M = 8,
252 mac_82559_D101S = 9,
253 mac_82550_D102 = 12,
254 mac_82550_D102_C = 13,
255 mac_82551_E = 14,
256 mac_82551_F = 15,
257 mac_82551_10 = 16,
258 mac_unknown = 0xFF,
259 };
260
261 enum phy {
262 phy_100a = 0x000003E0,
263 phy_100c = 0x035002A8,
264 phy_82555_tx = 0x015002A8,
265 phy_nsc_tx = 0x5C002000,
266 phy_82562_et = 0x033002A8,
267 phy_82562_em = 0x032002A8,
268 phy_82562_ek = 0x031002A8,
269 phy_82562_eh = 0x017002A8,
270 phy_unknown = 0xFFFFFFFF,
271 };
272
273 /* CSR (Control/Status Registers) */
274 struct csr {
275 struct {
276 u8 status;
277 u8 stat_ack;
278 u8 cmd_lo;
279 u8 cmd_hi;
280 u32 gen_ptr;
281 } scb;
282 u32 port;
283 u16 flash_ctrl;
284 u8 eeprom_ctrl_lo;
285 u8 eeprom_ctrl_hi;
286 u32 mdi_ctrl;
287 u32 rx_dma_count;
288 };
289
290 enum scb_status {
291 rus_no_res = 0x08,
292 rus_ready = 0x10,
293 rus_mask = 0x3C,
294 };
295
296 enum ru_state {
297 RU_SUSPENDED = 0,
298 RU_RUNNING = 1,
299 RU_UNINITIALIZED = -1,
300 };
301
302 enum scb_stat_ack {
303 stat_ack_not_ours = 0x00,
304 stat_ack_sw_gen = 0x04,
305 stat_ack_rnr = 0x10,
306 stat_ack_cu_idle = 0x20,
307 stat_ack_frame_rx = 0x40,
308 stat_ack_cu_cmd_done = 0x80,
309 stat_ack_not_present = 0xFF,
310 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
311 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
312 };
313
314 enum scb_cmd_hi {
315 irq_mask_none = 0x00,
316 irq_mask_all = 0x01,
317 irq_sw_gen = 0x02,
318 };
319
320 enum scb_cmd_lo {
321 cuc_nop = 0x00,
322 ruc_start = 0x01,
323 ruc_load_base = 0x06,
324 cuc_start = 0x10,
325 cuc_resume = 0x20,
326 cuc_dump_addr = 0x40,
327 cuc_dump_stats = 0x50,
328 cuc_load_base = 0x60,
329 cuc_dump_reset = 0x70,
330 };
331
332 enum cuc_dump {
333 cuc_dump_complete = 0x0000A005,
334 cuc_dump_reset_complete = 0x0000A007,
335 };
336
337 enum port {
338 software_reset = 0x0000,
339 selftest = 0x0001,
340 selective_reset = 0x0002,
341 };
342
343 enum eeprom_ctrl_lo {
344 eesk = 0x01,
345 eecs = 0x02,
346 eedi = 0x04,
347 eedo = 0x08,
348 };
349
350 enum mdi_ctrl {
351 mdi_write = 0x04000000,
352 mdi_read = 0x08000000,
353 mdi_ready = 0x10000000,
354 };
355
356 enum eeprom_op {
357 op_write = 0x05,
358 op_read = 0x06,
359 op_ewds = 0x10,
360 op_ewen = 0x13,
361 };
362
363 enum eeprom_offsets {
364 eeprom_cnfg_mdix = 0x03,
365 eeprom_id = 0x0A,
366 eeprom_config_asf = 0x0D,
367 eeprom_smbus_addr = 0x90,
368 };
369
370 enum eeprom_cnfg_mdix {
371 eeprom_mdix_enabled = 0x0080,
372 };
373
374 enum eeprom_id {
375 eeprom_id_wol = 0x0020,
376 };
377
378 enum eeprom_config_asf {
379 eeprom_asf = 0x8000,
380 eeprom_gcl = 0x4000,
381 };
382
383 enum cb_status {
384 cb_complete = 0x8000,
385 cb_ok = 0x2000,
386 };
387
388 enum cb_command {
389 cb_nop = 0x0000,
390 cb_iaaddr = 0x0001,
391 cb_config = 0x0002,
392 cb_multi = 0x0003,
393 cb_tx = 0x0004,
394 cb_ucode = 0x0005,
395 cb_dump = 0x0006,
396 cb_tx_sf = 0x0008,
397 cb_cid = 0x1f00,
398 cb_i = 0x2000,
399 cb_s = 0x4000,
400 cb_el = 0x8000,
401 };
402
403 struct rfd {
404 u16 status;
405 u16 command;
406 u32 link;
407 u32 rbd;
408 u16 actual_size;
409 u16 size;
410 };
411
412 struct rx {
413 struct rx *next, *prev;
414 struct sk_buff *skb;
415 dma_addr_t dma_addr;
416 };
417
418 #if defined(__BIG_ENDIAN_BITFIELD)
419 #define X(a,b) b,a
420 #else
421 #define X(a,b) a,b
422 #endif
423 struct config {
424 /*0*/ u8 X(byte_count:6, pad0:2);
425 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
426 /*2*/ u8 adaptive_ifs;
427 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
428 term_write_cache_line:1), pad3:4);
429 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
430 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
431 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
432 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
433 rx_discard_overruns:1), rx_save_bad_frames:1);
434 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
435 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
436 tx_dynamic_tbd:1);
437 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
438 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
439 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
440 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
441 loopback:2);
442 /*11*/ u8 X(linear_priority:3, pad11:5);
443 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
444 /*13*/ u8 ip_addr_lo;
445 /*14*/ u8 ip_addr_hi;
446 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
447 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
448 pad15_2:1), crs_or_cdt:1);
449 /*16*/ u8 fc_delay_lo;
450 /*17*/ u8 fc_delay_hi;
451 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
452 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
453 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
454 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
455 full_duplex_force:1), full_duplex_pin:1);
456 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
457 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
458 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
459 u8 pad_d102[9];
460 };
461
462 #define E100_MAX_MULTICAST_ADDRS 64
463 struct multi {
464 u16 count;
465 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
466 };
467
468 /* Important: keep total struct u32-aligned */
469 #define UCODE_SIZE 134
470 struct cb {
471 u16 status;
472 u16 command;
473 u32 link;
474 union {
475 u8 iaaddr[ETH_ALEN];
476 u32 ucode[UCODE_SIZE];
477 struct config config;
478 struct multi multi;
479 struct {
480 u32 tbd_array;
481 u16 tcb_byte_count;
482 u8 threshold;
483 u8 tbd_count;
484 struct {
485 u32 buf_addr;
486 u16 size;
487 u16 eol;
488 } tbd;
489 } tcb;
490 u32 dump_buffer_addr;
491 } u;
492 struct cb *next, *prev;
493 dma_addr_t dma_addr;
494 struct sk_buff *skb;
495 };
496
497 enum loopback {
498 lb_none = 0, lb_mac = 1, lb_phy = 3,
499 };
500
501 struct stats {
502 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
503 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
504 tx_multiple_collisions, tx_total_collisions;
505 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
506 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
507 rx_short_frame_errors;
508 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
509 u16 xmt_tco_frames, rcv_tco_frames;
510 u32 complete;
511 };
512
513 struct mem {
514 struct {
515 u32 signature;
516 u32 result;
517 } selftest;
518 struct stats stats;
519 u8 dump_buf[596];
520 };
521
522 struct param_range {
523 u32 min;
524 u32 max;
525 u32 count;
526 };
527
528 struct params {
529 struct param_range rfds;
530 struct param_range cbs;
531 };
532
533 struct nic {
534 /* Begin: frequently used values: keep adjacent for cache effect */
535 u32 msg_enable ____cacheline_aligned;
536 struct net_device *netdev;
537 struct pci_dev *pdev;
538
539 struct rx *rxs ____cacheline_aligned;
540 struct rx *rx_to_use;
541 struct rx *rx_to_clean;
542 struct rfd blank_rfd;
543 enum ru_state ru_running;
544
545 spinlock_t cb_lock ____cacheline_aligned;
546 spinlock_t cmd_lock;
547 struct csr __iomem *csr;
548 enum scb_cmd_lo cuc_cmd;
549 unsigned int cbs_avail;
550 struct napi_struct napi;
551 struct cb *cbs;
552 struct cb *cb_to_use;
553 struct cb *cb_to_send;
554 struct cb *cb_to_clean;
555 u16 tx_command;
556 /* End: frequently used values: keep adjacent for cache effect */
557
558 enum {
559 ich = (1 << 0),
560 promiscuous = (1 << 1),
561 multicast_all = (1 << 2),
562 wol_magic = (1 << 3),
563 ich_10h_workaround = (1 << 4),
564 } flags ____cacheline_aligned;
565
566 enum mac mac;
567 enum phy phy;
568 struct params params;
569 struct timer_list watchdog;
570 struct timer_list blink_timer;
571 struct mii_if_info mii;
572 struct work_struct tx_timeout_task;
573 enum loopback loopback;
574
575 struct mem *mem;
576 dma_addr_t dma_addr;
577
578 dma_addr_t cbs_dma_addr;
579 u8 adaptive_ifs;
580 u8 tx_threshold;
581 u32 tx_frames;
582 u32 tx_collisions;
583 u32 tx_deferred;
584 u32 tx_single_collisions;
585 u32 tx_multiple_collisions;
586 u32 tx_fc_pause;
587 u32 tx_tco_frames;
588
589 u32 rx_fc_pause;
590 u32 rx_fc_unsupported;
591 u32 rx_tco_frames;
592 u32 rx_over_length_errors;
593
594 u16 leds;
595 u16 eeprom_wc;
596 u16 eeprom[256];
597 spinlock_t mdio_lock;
598 };
599
600 static inline void e100_write_flush(struct nic *nic)
601 {
602 /* Flush previous PCI writes through intermediate bridges
603 * by doing a benign read */
604 (void)ioread8(&nic->csr->scb.status);
605 }
606
607 static void e100_enable_irq(struct nic *nic)
608 {
609 unsigned long flags;
610
611 spin_lock_irqsave(&nic->cmd_lock, flags);
612 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
613 e100_write_flush(nic);
614 spin_unlock_irqrestore(&nic->cmd_lock, flags);
615 }
616
617 static void e100_disable_irq(struct nic *nic)
618 {
619 unsigned long flags;
620
621 spin_lock_irqsave(&nic->cmd_lock, flags);
622 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
623 e100_write_flush(nic);
624 spin_unlock_irqrestore(&nic->cmd_lock, flags);
625 }
626
627 static void e100_hw_reset(struct nic *nic)
628 {
629 /* Put CU and RU into idle with a selective reset to get
630 * device off of PCI bus */
631 iowrite32(selective_reset, &nic->csr->port);
632 e100_write_flush(nic); udelay(20);
633
634 /* Now fully reset device */
635 iowrite32(software_reset, &nic->csr->port);
636 e100_write_flush(nic); udelay(20);
637
638 /* Mask off our interrupt line - it's unmasked after reset */
639 e100_disable_irq(nic);
640 }
641
642 static int e100_self_test(struct nic *nic)
643 {
644 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
645
646 /* Passing the self-test is a pretty good indication
647 * that the device can DMA to/from host memory */
648
649 nic->mem->selftest.signature = 0;
650 nic->mem->selftest.result = 0xFFFFFFFF;
651
652 iowrite32(selftest | dma_addr, &nic->csr->port);
653 e100_write_flush(nic);
654 /* Wait 10 msec for self-test to complete */
655 msleep(10);
656
657 /* Interrupts are enabled after self-test */
658 e100_disable_irq(nic);
659
660 /* Check results of self-test */
661 if(nic->mem->selftest.result != 0) {
662 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
663 nic->mem->selftest.result);
664 return -ETIMEDOUT;
665 }
666 if(nic->mem->selftest.signature == 0) {
667 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
668 return -ETIMEDOUT;
669 }
670
671 return 0;
672 }
673
674 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
675 {
676 u32 cmd_addr_data[3];
677 u8 ctrl;
678 int i, j;
679
680 /* Three cmds: write/erase enable, write data, write/erase disable */
681 cmd_addr_data[0] = op_ewen << (addr_len - 2);
682 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
683 cpu_to_le16(data);
684 cmd_addr_data[2] = op_ewds << (addr_len - 2);
685
686 /* Bit-bang cmds to write word to eeprom */
687 for(j = 0; j < 3; j++) {
688
689 /* Chip select */
690 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
691 e100_write_flush(nic); udelay(4);
692
693 for(i = 31; i >= 0; i--) {
694 ctrl = (cmd_addr_data[j] & (1 << i)) ?
695 eecs | eedi : eecs;
696 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
697 e100_write_flush(nic); udelay(4);
698
699 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
700 e100_write_flush(nic); udelay(4);
701 }
702 /* Wait 10 msec for cmd to complete */
703 msleep(10);
704
705 /* Chip deselect */
706 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708 }
709 };
710
711 /* General technique stolen from the eepro100 driver - very clever */
712 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
713 {
714 u32 cmd_addr_data;
715 u16 data = 0;
716 u8 ctrl;
717 int i;
718
719 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
720
721 /* Chip select */
722 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
723 e100_write_flush(nic); udelay(4);
724
725 /* Bit-bang to read word from eeprom */
726 for(i = 31; i >= 0; i--) {
727 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
728 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
729 e100_write_flush(nic); udelay(4);
730
731 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
732 e100_write_flush(nic); udelay(4);
733
734 /* Eeprom drives a dummy zero to EEDO after receiving
735 * complete address. Use this to adjust addr_len. */
736 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
737 if(!(ctrl & eedo) && i > 16) {
738 *addr_len -= (i - 16);
739 i = 17;
740 }
741
742 data = (data << 1) | (ctrl & eedo ? 1 : 0);
743 }
744
745 /* Chip deselect */
746 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
747 e100_write_flush(nic); udelay(4);
748
749 return le16_to_cpu(data);
750 };
751
752 /* Load entire EEPROM image into driver cache and validate checksum */
753 static int e100_eeprom_load(struct nic *nic)
754 {
755 u16 addr, addr_len = 8, checksum = 0;
756
757 /* Try reading with an 8-bit addr len to discover actual addr len */
758 e100_eeprom_read(nic, &addr_len, 0);
759 nic->eeprom_wc = 1 << addr_len;
760
761 for(addr = 0; addr < nic->eeprom_wc; addr++) {
762 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
763 if(addr < nic->eeprom_wc - 1)
764 checksum += cpu_to_le16(nic->eeprom[addr]);
765 }
766
767 /* The checksum, stored in the last word, is calculated such that
768 * the sum of words should be 0xBABA */
769 checksum = le16_to_cpu(0xBABA - checksum);
770 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
771 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
772 if (!eeprom_bad_csum_allow)
773 return -EAGAIN;
774 }
775
776 return 0;
777 }
778
779 /* Save (portion of) driver EEPROM cache to device and update checksum */
780 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
781 {
782 u16 addr, addr_len = 8, checksum = 0;
783
784 /* Try reading with an 8-bit addr len to discover actual addr len */
785 e100_eeprom_read(nic, &addr_len, 0);
786 nic->eeprom_wc = 1 << addr_len;
787
788 if(start + count >= nic->eeprom_wc)
789 return -EINVAL;
790
791 for(addr = start; addr < start + count; addr++)
792 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
793
794 /* The checksum, stored in the last word, is calculated such that
795 * the sum of words should be 0xBABA */
796 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
797 checksum += cpu_to_le16(nic->eeprom[addr]);
798 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
799 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
800 nic->eeprom[nic->eeprom_wc - 1]);
801
802 return 0;
803 }
804
805 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
806 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
807 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
808 {
809 unsigned long flags;
810 unsigned int i;
811 int err = 0;
812
813 spin_lock_irqsave(&nic->cmd_lock, flags);
814
815 /* Previous command is accepted when SCB clears */
816 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
817 if(likely(!ioread8(&nic->csr->scb.cmd_lo)))
818 break;
819 cpu_relax();
820 if(unlikely(i > E100_WAIT_SCB_FAST))
821 udelay(5);
822 }
823 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
824 err = -EAGAIN;
825 goto err_unlock;
826 }
827
828 if(unlikely(cmd != cuc_resume))
829 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
830 iowrite8(cmd, &nic->csr->scb.cmd_lo);
831
832 err_unlock:
833 spin_unlock_irqrestore(&nic->cmd_lock, flags);
834
835 return err;
836 }
837
838 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
839 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
840 {
841 struct cb *cb;
842 unsigned long flags;
843 int err = 0;
844
845 spin_lock_irqsave(&nic->cb_lock, flags);
846
847 if(unlikely(!nic->cbs_avail)) {
848 err = -ENOMEM;
849 goto err_unlock;
850 }
851
852 cb = nic->cb_to_use;
853 nic->cb_to_use = cb->next;
854 nic->cbs_avail--;
855 cb->skb = skb;
856
857 if(unlikely(!nic->cbs_avail))
858 err = -ENOSPC;
859
860 cb_prepare(nic, cb, skb);
861
862 /* Order is important otherwise we'll be in a race with h/w:
863 * set S-bit in current first, then clear S-bit in previous. */
864 cb->command |= cpu_to_le16(cb_s);
865 wmb();
866 cb->prev->command &= cpu_to_le16(~cb_s);
867
868 while(nic->cb_to_send != nic->cb_to_use) {
869 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
870 nic->cb_to_send->dma_addr))) {
871 /* Ok, here's where things get sticky. It's
872 * possible that we can't schedule the command
873 * because the controller is too busy, so
874 * let's just queue the command and try again
875 * when another command is scheduled. */
876 if(err == -ENOSPC) {
877 //request a reset
878 schedule_work(&nic->tx_timeout_task);
879 }
880 break;
881 } else {
882 nic->cuc_cmd = cuc_resume;
883 nic->cb_to_send = nic->cb_to_send->next;
884 }
885 }
886
887 err_unlock:
888 spin_unlock_irqrestore(&nic->cb_lock, flags);
889
890 return err;
891 }
892
893 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
894 {
895 u32 data_out = 0;
896 unsigned int i;
897 unsigned long flags;
898
899
900 /*
901 * Stratus87247: we shouldn't be writing the MDI control
902 * register until the Ready bit shows True. Also, since
903 * manipulation of the MDI control registers is a multi-step
904 * procedure it should be done under lock.
905 */
906 spin_lock_irqsave(&nic->mdio_lock, flags);
907 for (i = 100; i; --i) {
908 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
909 break;
910 udelay(20);
911 }
912 if (unlikely(!i)) {
913 printk("e100.mdio_ctrl(%s) won't go Ready\n",
914 nic->netdev->name );
915 spin_unlock_irqrestore(&nic->mdio_lock, flags);
916 return 0; /* No way to indicate timeout error */
917 }
918 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
919
920 for (i = 0; i < 100; i++) {
921 udelay(20);
922 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
923 break;
924 }
925 spin_unlock_irqrestore(&nic->mdio_lock, flags);
926 DPRINTK(HW, DEBUG,
927 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
928 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
929 return (u16)data_out;
930 }
931
932 static int mdio_read(struct net_device *netdev, int addr, int reg)
933 {
934 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
935 }
936
937 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
938 {
939 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
940 }
941
942 static void e100_get_defaults(struct nic *nic)
943 {
944 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
945 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
946
947 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
948 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
949 if(nic->mac == mac_unknown)
950 nic->mac = mac_82557_D100_A;
951
952 nic->params.rfds = rfds;
953 nic->params.cbs = cbs;
954
955 /* Quadwords to DMA into FIFO before starting frame transmit */
956 nic->tx_threshold = 0xE0;
957
958 /* no interrupt for every tx completion, delay = 256us if not 557*/
959 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
960 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
961
962 /* Template for a freshly allocated RFD */
963 nic->blank_rfd.command = 0;
964 nic->blank_rfd.rbd = 0xFFFFFFFF;
965 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
966
967 /* MII setup */
968 nic->mii.phy_id_mask = 0x1F;
969 nic->mii.reg_num_mask = 0x1F;
970 nic->mii.dev = nic->netdev;
971 nic->mii.mdio_read = mdio_read;
972 nic->mii.mdio_write = mdio_write;
973 }
974
975 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
976 {
977 struct config *config = &cb->u.config;
978 u8 *c = (u8 *)config;
979
980 cb->command = cpu_to_le16(cb_config);
981
982 memset(config, 0, sizeof(struct config));
983
984 config->byte_count = 0x16; /* bytes in this struct */
985 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
986 config->direct_rx_dma = 0x1; /* reserved */
987 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
988 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
989 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
990 config->tx_underrun_retry = 0x3; /* # of underrun retries */
991 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
992 config->pad10 = 0x6;
993 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
994 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
995 config->ifs = 0x6; /* x16 = inter frame spacing */
996 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
997 config->pad15_1 = 0x1;
998 config->pad15_2 = 0x1;
999 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1000 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1001 config->tx_padding = 0x1; /* 1=pad short frames */
1002 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1003 config->pad18 = 0x1;
1004 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1005 config->pad20_1 = 0x1F;
1006 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1007 config->pad21_1 = 0x5;
1008
1009 config->adaptive_ifs = nic->adaptive_ifs;
1010 config->loopback = nic->loopback;
1011
1012 if(nic->mii.force_media && nic->mii.full_duplex)
1013 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1014
1015 if(nic->flags & promiscuous || nic->loopback) {
1016 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1017 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1018 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1019 }
1020
1021 if(nic->flags & multicast_all)
1022 config->multicast_all = 0x1; /* 1=accept, 0=no */
1023
1024 /* disable WoL when up */
1025 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
1026 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1027
1028 if(nic->mac >= mac_82558_D101_A4) {
1029 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1030 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1031 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1032 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1033 if (nic->mac >= mac_82559_D101M) {
1034 config->tno_intr = 0x1; /* TCO stats enable */
1035 /* Enable TCO in extended config */
1036 if (nic->mac >= mac_82551_10) {
1037 config->byte_count = 0x20; /* extended bytes */
1038 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1039 }
1040 } else {
1041 config->standard_stat_counter = 0x0;
1042 }
1043 }
1044
1045 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1046 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1047 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1048 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1049 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1050 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1051 }
1052
1053 /********************************************************/
1054 /* Micro code for 8086:1229 Rev 8 */
1055 /********************************************************/
1056
1057 /* Parameter values for the D101M B-step */
1058 #define D101M_CPUSAVER_TIMER_DWORD 78
1059 #define D101M_CPUSAVER_BUNDLE_DWORD 65
1060 #define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1061
1062 #define D101M_B_RCVBUNDLE_UCODE \
1063 {\
1064 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
1065 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
1066 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
1067 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
1068 0x00380438, 0x00000000, 0x00140000, 0x00380555, \
1069 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
1070 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1071 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1072 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
1073 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
1074 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1075 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
1076 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
1077 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
1078 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
1079 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
1080 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
1081 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1082 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1083 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1084 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
1085 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
1086 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
1087 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
1088 0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
1089 0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
1090 0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
1091 0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
1092 0x00380559, 0x00000000, 0x00000000, 0x00000000, \
1093 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1094 0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
1095 0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
1096 0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1097 }
1098
1099 /********************************************************/
1100 /* Micro code for 8086:1229 Rev 9 */
1101 /********************************************************/
1102
1103 /* Parameter values for the D101S */
1104 #define D101S_CPUSAVER_TIMER_DWORD 78
1105 #define D101S_CPUSAVER_BUNDLE_DWORD 67
1106 #define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1107
1108 #define D101S_RCVBUNDLE_UCODE \
1109 {\
1110 0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
1111 0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
1112 0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
1113 0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
1114 0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
1115 0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
1116 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1117 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1118 0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
1119 0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
1120 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1121 0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
1122 0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
1123 0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
1124 0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
1125 0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
1126 0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
1127 0x00101313, 0x00380700, 0x00000000, 0x00000000, \
1128 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1129 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1130 0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
1131 0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
1132 0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
1133 0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
1134 0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
1135 0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
1136 0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
1137 0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
1138 0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
1139 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1140 0x00000000, 0x00000000, 0x00000000, 0x00130831, \
1141 0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
1142 0x00041000, 0x00010004, 0x00380700 \
1143 }
1144
1145 /********************************************************/
1146 /* Micro code for the 8086:1229 Rev F/10 */
1147 /********************************************************/
1148
1149 /* Parameter values for the D102 E-step */
1150 #define D102_E_CPUSAVER_TIMER_DWORD 42
1151 #define D102_E_CPUSAVER_BUNDLE_DWORD 54
1152 #define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1153
1154 #define D102_E_RCVBUNDLE_UCODE \
1155 {\
1156 0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
1157 0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
1158 0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
1159 0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
1160 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1161 0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
1162 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1163 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1164 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1165 0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
1166 0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
1167 0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
1168 0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
1169 0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
1170 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1171 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1172 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1173 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
1174 0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
1175 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1176 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1177 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1178 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1179 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1180 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1181 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1182 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1183 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1184 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1185 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1186 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1187 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1188 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1189 }
1190
1191 static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1192 {
1193 /* *INDENT-OFF* */
1194 static struct {
1195 u32 ucode[UCODE_SIZE + 1];
1196 u8 mac;
1197 u8 timer_dword;
1198 u8 bundle_dword;
1199 u8 min_size_dword;
1200 } ucode_opts[] = {
1201 { D101M_B_RCVBUNDLE_UCODE,
1202 mac_82559_D101M,
1203 D101M_CPUSAVER_TIMER_DWORD,
1204 D101M_CPUSAVER_BUNDLE_DWORD,
1205 D101M_CPUSAVER_MIN_SIZE_DWORD },
1206 { D101S_RCVBUNDLE_UCODE,
1207 mac_82559_D101S,
1208 D101S_CPUSAVER_TIMER_DWORD,
1209 D101S_CPUSAVER_BUNDLE_DWORD,
1210 D101S_CPUSAVER_MIN_SIZE_DWORD },
1211 { D102_E_RCVBUNDLE_UCODE,
1212 mac_82551_F,
1213 D102_E_CPUSAVER_TIMER_DWORD,
1214 D102_E_CPUSAVER_BUNDLE_DWORD,
1215 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1216 { D102_E_RCVBUNDLE_UCODE,
1217 mac_82551_10,
1218 D102_E_CPUSAVER_TIMER_DWORD,
1219 D102_E_CPUSAVER_BUNDLE_DWORD,
1220 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1221 { {0}, 0, 0, 0, 0}
1222 }, *opts;
1223 /* *INDENT-ON* */
1224
1225 /*************************************************************************
1226 * CPUSaver parameters
1227 *
1228 * All CPUSaver parameters are 16-bit literals that are part of a
1229 * "move immediate value" instruction. By changing the value of
1230 * the literal in the instruction before the code is loaded, the
1231 * driver can change the algorithm.
1232 *
1233 * INTDELAY - This loads the dead-man timer with its initial value.
1234 * When this timer expires the interrupt is asserted, and the
1235 * timer is reset each time a new packet is received. (see
1236 * BUNDLEMAX below to set the limit on number of chained packets)
1237 * The current default is 0x600 or 1536. Experiments show that
1238 * the value should probably stay within the 0x200 - 0x1000.
1239 *
1240 * BUNDLEMAX -
1241 * This sets the maximum number of frames that will be bundled. In
1242 * some situations, such as the TCP windowing algorithm, it may be
1243 * better to limit the growth of the bundle size than let it go as
1244 * high as it can, because that could cause too much added latency.
1245 * The default is six, because this is the number of packets in the
1246 * default TCP window size. A value of 1 would make CPUSaver indicate
1247 * an interrupt for every frame received. If you do not want to put
1248 * a limit on the bundle size, set this value to xFFFF.
1249 *
1250 * BUNDLESMALL -
1251 * This contains a bit-mask describing the minimum size frame that
1252 * will be bundled. The default masks the lower 7 bits, which means
1253 * that any frame less than 128 bytes in length will not be bundled,
1254 * but will instead immediately generate an interrupt. This does
1255 * not affect the current bundle in any way. Any frame that is 128
1256 * bytes or large will be bundled normally. This feature is meant
1257 * to provide immediate indication of ACK frames in a TCP environment.
1258 * Customers were seeing poor performance when a machine with CPUSaver
1259 * enabled was sending but not receiving. The delay introduced when
1260 * the ACKs were received was enough to reduce total throughput, because
1261 * the sender would sit idle until the ACK was finally seen.
1262 *
1263 * The current default is 0xFF80, which masks out the lower 7 bits.
1264 * This means that any frame which is x7F (127) bytes or smaller
1265 * will cause an immediate interrupt. Because this value must be a
1266 * bit mask, there are only a few valid values that can be used. To
1267 * turn this feature off, the driver can write the value xFFFF to the
1268 * lower word of this instruction (in the same way that the other
1269 * parameters are used). Likewise, a value of 0xF800 (2047) would
1270 * cause an interrupt to be generated for every frame, because all
1271 * standard Ethernet frames are <= 2047 bytes in length.
1272 *************************************************************************/
1273
1274 /* if you wish to disable the ucode functionality, while maintaining the
1275 * workarounds it provides, set the following defines to:
1276 * BUNDLESMALL 0
1277 * BUNDLEMAX 1
1278 * INTDELAY 1
1279 */
1280 #define BUNDLESMALL 1
1281 #define BUNDLEMAX (u16)6
1282 #define INTDELAY (u16)1536 /* 0x600 */
1283
1284 /* do not load u-code for ICH devices */
1285 if (nic->flags & ich)
1286 goto noloaducode;
1287
1288 /* Search for ucode match against h/w revision */
1289 for (opts = ucode_opts; opts->mac; opts++) {
1290 int i;
1291 u32 *ucode = opts->ucode;
1292 if (nic->mac != opts->mac)
1293 continue;
1294
1295 /* Insert user-tunable settings */
1296 ucode[opts->timer_dword] &= 0xFFFF0000;
1297 ucode[opts->timer_dword] |= INTDELAY;
1298 ucode[opts->bundle_dword] &= 0xFFFF0000;
1299 ucode[opts->bundle_dword] |= BUNDLEMAX;
1300 ucode[opts->min_size_dword] &= 0xFFFF0000;
1301 ucode[opts->min_size_dword] |= (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1302
1303 for (i = 0; i < UCODE_SIZE; i++)
1304 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1305 cb->command = cpu_to_le16(cb_ucode | cb_el);
1306 return;
1307 }
1308
1309 noloaducode:
1310 cb->command = cpu_to_le16(cb_nop | cb_el);
1311 }
1312
1313 static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb,
1314 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
1315 {
1316 int err = 0, counter = 50;
1317 struct cb *cb = nic->cb_to_clean;
1318
1319 if ((err = e100_exec_cb(nic, NULL, e100_setup_ucode)))
1320 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1321
1322 /* must restart cuc */
1323 nic->cuc_cmd = cuc_start;
1324
1325 /* wait for completion */
1326 e100_write_flush(nic);
1327 udelay(10);
1328
1329 /* wait for possibly (ouch) 500ms */
1330 while (!(cb->status & cpu_to_le16(cb_complete))) {
1331 msleep(10);
1332 if (!--counter) break;
1333 }
1334
1335 /* ack any interrupts, something could have been set */
1336 iowrite8(~0, &nic->csr->scb.stat_ack);
1337
1338 /* if the command failed, or is not OK, notify and return */
1339 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1340 DPRINTK(PROBE,ERR, "ucode load failed\n");
1341 err = -EPERM;
1342 }
1343
1344 return err;
1345 }
1346
1347 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1348 struct sk_buff *skb)
1349 {
1350 cb->command = cpu_to_le16(cb_iaaddr);
1351 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1352 }
1353
1354 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1355 {
1356 cb->command = cpu_to_le16(cb_dump);
1357 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1358 offsetof(struct mem, dump_buf));
1359 }
1360
1361 #define NCONFIG_AUTO_SWITCH 0x0080
1362 #define MII_NSC_CONG MII_RESV1
1363 #define NSC_CONG_ENABLE 0x0100
1364 #define NSC_CONG_TXREADY 0x0400
1365 #define ADVERTISE_FC_SUPPORTED 0x0400
1366 static int e100_phy_init(struct nic *nic)
1367 {
1368 struct net_device *netdev = nic->netdev;
1369 u32 addr;
1370 u16 bmcr, stat, id_lo, id_hi, cong;
1371
1372 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1373 for(addr = 0; addr < 32; addr++) {
1374 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1375 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1376 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1377 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1378 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1379 break;
1380 }
1381 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1382 if(addr == 32)
1383 return -EAGAIN;
1384
1385 /* Selected the phy and isolate the rest */
1386 for(addr = 0; addr < 32; addr++) {
1387 if(addr != nic->mii.phy_id) {
1388 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1389 } else {
1390 bmcr = mdio_read(netdev, addr, MII_BMCR);
1391 mdio_write(netdev, addr, MII_BMCR,
1392 bmcr & ~BMCR_ISOLATE);
1393 }
1394 }
1395
1396 /* Get phy ID */
1397 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1398 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1399 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1400 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1401
1402 /* Handle National tx phys */
1403 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1404 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1405 /* Disable congestion control */
1406 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1407 cong |= NSC_CONG_TXREADY;
1408 cong &= ~NSC_CONG_ENABLE;
1409 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1410 }
1411
1412 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1413 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1414 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1415 /* enable/disable MDI/MDI-X auto-switching. */
1416 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1417 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1418 }
1419
1420 return 0;
1421 }
1422
1423 static int e100_hw_init(struct nic *nic)
1424 {
1425 int err;
1426
1427 e100_hw_reset(nic);
1428
1429 DPRINTK(HW, ERR, "e100_hw_init\n");
1430 if(!in_interrupt() && (err = e100_self_test(nic)))
1431 return err;
1432
1433 if((err = e100_phy_init(nic)))
1434 return err;
1435 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1436 return err;
1437 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1438 return err;
1439 if ((err = e100_exec_cb_wait(nic, NULL, e100_setup_ucode)))
1440 return err;
1441 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1442 return err;
1443 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1444 return err;
1445 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1446 nic->dma_addr + offsetof(struct mem, stats))))
1447 return err;
1448 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1449 return err;
1450
1451 e100_disable_irq(nic);
1452
1453 return 0;
1454 }
1455
1456 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1457 {
1458 struct net_device *netdev = nic->netdev;
1459 struct dev_mc_list *list = netdev->mc_list;
1460 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1461
1462 cb->command = cpu_to_le16(cb_multi);
1463 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1464 for(i = 0; list && i < count; i++, list = list->next)
1465 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1466 ETH_ALEN);
1467 }
1468
1469 static void e100_set_multicast_list(struct net_device *netdev)
1470 {
1471 struct nic *nic = netdev_priv(netdev);
1472
1473 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1474 netdev->mc_count, netdev->flags);
1475
1476 if(netdev->flags & IFF_PROMISC)
1477 nic->flags |= promiscuous;
1478 else
1479 nic->flags &= ~promiscuous;
1480
1481 if(netdev->flags & IFF_ALLMULTI ||
1482 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1483 nic->flags |= multicast_all;
1484 else
1485 nic->flags &= ~multicast_all;
1486
1487 e100_exec_cb(nic, NULL, e100_configure);
1488 e100_exec_cb(nic, NULL, e100_multi);
1489 }
1490
1491 static void e100_update_stats(struct nic *nic)
1492 {
1493 struct net_device *dev = nic->netdev;
1494 struct net_device_stats *ns = &dev->stats;
1495 struct stats *s = &nic->mem->stats;
1496 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1497 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1498 &s->complete;
1499
1500 /* Device's stats reporting may take several microseconds to
1501 * complete, so where always waiting for results of the
1502 * previous command. */
1503
1504 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1505 *complete = 0;
1506 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1507 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1508 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1509 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1510 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1511 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1512 ns->collisions += nic->tx_collisions;
1513 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1514 le32_to_cpu(s->tx_lost_crs);
1515 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1516 nic->rx_over_length_errors;
1517 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1518 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1519 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1520 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1521 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1522 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1523 le32_to_cpu(s->rx_alignment_errors) +
1524 le32_to_cpu(s->rx_short_frame_errors) +
1525 le32_to_cpu(s->rx_cdt_errors);
1526 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1527 nic->tx_single_collisions +=
1528 le32_to_cpu(s->tx_single_collisions);
1529 nic->tx_multiple_collisions +=
1530 le32_to_cpu(s->tx_multiple_collisions);
1531 if(nic->mac >= mac_82558_D101_A4) {
1532 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1533 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1534 nic->rx_fc_unsupported +=
1535 le32_to_cpu(s->fc_rcv_unsupported);
1536 if(nic->mac >= mac_82559_D101M) {
1537 nic->tx_tco_frames +=
1538 le16_to_cpu(s->xmt_tco_frames);
1539 nic->rx_tco_frames +=
1540 le16_to_cpu(s->rcv_tco_frames);
1541 }
1542 }
1543 }
1544
1545
1546 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1547 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1548 }
1549
1550 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1551 {
1552 /* Adjust inter-frame-spacing (IFS) between two transmits if
1553 * we're getting collisions on a half-duplex connection. */
1554
1555 if(duplex == DUPLEX_HALF) {
1556 u32 prev = nic->adaptive_ifs;
1557 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1558
1559 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1560 (nic->tx_frames > min_frames)) {
1561 if(nic->adaptive_ifs < 60)
1562 nic->adaptive_ifs += 5;
1563 } else if (nic->tx_frames < min_frames) {
1564 if(nic->adaptive_ifs >= 5)
1565 nic->adaptive_ifs -= 5;
1566 }
1567 if(nic->adaptive_ifs != prev)
1568 e100_exec_cb(nic, NULL, e100_configure);
1569 }
1570 }
1571
1572 static void e100_watchdog(unsigned long data)
1573 {
1574 struct nic *nic = (struct nic *)data;
1575 struct ethtool_cmd cmd;
1576
1577 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1578
1579 /* mii library handles link maintenance tasks */
1580
1581 mii_ethtool_gset(&nic->mii, &cmd);
1582
1583 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1584 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1585 cmd.speed == SPEED_100 ? "100" : "10",
1586 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1587 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1588 DPRINTK(LINK, INFO, "link down\n");
1589 }
1590
1591 mii_check_link(&nic->mii);
1592
1593 /* Software generated interrupt to recover from (rare) Rx
1594 * allocation failure.
1595 * Unfortunately have to use a spinlock to not re-enable interrupts
1596 * accidentally, due to hardware that shares a register between the
1597 * interrupt mask bit and the SW Interrupt generation bit */
1598 spin_lock_irq(&nic->cmd_lock);
1599 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1600 e100_write_flush(nic);
1601 spin_unlock_irq(&nic->cmd_lock);
1602
1603 e100_update_stats(nic);
1604 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1605
1606 if(nic->mac <= mac_82557_D100_C)
1607 /* Issue a multicast command to workaround a 557 lock up */
1608 e100_set_multicast_list(nic->netdev);
1609
1610 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1611 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1612 nic->flags |= ich_10h_workaround;
1613 else
1614 nic->flags &= ~ich_10h_workaround;
1615
1616 mod_timer(&nic->watchdog,
1617 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1618 }
1619
1620 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1621 struct sk_buff *skb)
1622 {
1623 cb->command = nic->tx_command;
1624 /* interrupt every 16 packets regardless of delay */
1625 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1626 cb->command |= cpu_to_le16(cb_i);
1627 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1628 cb->u.tcb.tcb_byte_count = 0;
1629 cb->u.tcb.threshold = nic->tx_threshold;
1630 cb->u.tcb.tbd_count = 1;
1631 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1632 skb->data, skb->len, PCI_DMA_TODEVICE));
1633 /* check for mapping failure? */
1634 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1635 }
1636
1637 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1638 {
1639 struct nic *nic = netdev_priv(netdev);
1640 int err;
1641
1642 if(nic->flags & ich_10h_workaround) {
1643 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1644 Issue a NOP command followed by a 1us delay before
1645 issuing the Tx command. */
1646 if(e100_exec_cmd(nic, cuc_nop, 0))
1647 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1648 udelay(1);
1649 }
1650
1651 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1652
1653 switch(err) {
1654 case -ENOSPC:
1655 /* We queued the skb, but now we're out of space. */
1656 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1657 netif_stop_queue(netdev);
1658 break;
1659 case -ENOMEM:
1660 /* This is a hard error - log it. */
1661 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1662 netif_stop_queue(netdev);
1663 return 1;
1664 }
1665
1666 netdev->trans_start = jiffies;
1667 return 0;
1668 }
1669
1670 static int e100_tx_clean(struct nic *nic)
1671 {
1672 struct net_device *dev = nic->netdev;
1673 struct cb *cb;
1674 int tx_cleaned = 0;
1675
1676 spin_lock(&nic->cb_lock);
1677
1678 /* Clean CBs marked complete */
1679 for(cb = nic->cb_to_clean;
1680 cb->status & cpu_to_le16(cb_complete);
1681 cb = nic->cb_to_clean = cb->next) {
1682 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1683 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1684 cb->status);
1685
1686 if(likely(cb->skb != NULL)) {
1687 dev->stats.tx_packets++;
1688 dev->stats.tx_bytes += cb->skb->len;
1689
1690 pci_unmap_single(nic->pdev,
1691 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1692 le16_to_cpu(cb->u.tcb.tbd.size),
1693 PCI_DMA_TODEVICE);
1694 dev_kfree_skb_any(cb->skb);
1695 cb->skb = NULL;
1696 tx_cleaned = 1;
1697 }
1698 cb->status = 0;
1699 nic->cbs_avail++;
1700 }
1701
1702 spin_unlock(&nic->cb_lock);
1703
1704 /* Recover from running out of Tx resources in xmit_frame */
1705 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1706 netif_wake_queue(nic->netdev);
1707
1708 return tx_cleaned;
1709 }
1710
1711 static void e100_clean_cbs(struct nic *nic)
1712 {
1713 if(nic->cbs) {
1714 while(nic->cbs_avail != nic->params.cbs.count) {
1715 struct cb *cb = nic->cb_to_clean;
1716 if(cb->skb) {
1717 pci_unmap_single(nic->pdev,
1718 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1719 le16_to_cpu(cb->u.tcb.tbd.size),
1720 PCI_DMA_TODEVICE);
1721 dev_kfree_skb(cb->skb);
1722 }
1723 nic->cb_to_clean = nic->cb_to_clean->next;
1724 nic->cbs_avail++;
1725 }
1726 pci_free_consistent(nic->pdev,
1727 sizeof(struct cb) * nic->params.cbs.count,
1728 nic->cbs, nic->cbs_dma_addr);
1729 nic->cbs = NULL;
1730 nic->cbs_avail = 0;
1731 }
1732 nic->cuc_cmd = cuc_start;
1733 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1734 nic->cbs;
1735 }
1736
1737 static int e100_alloc_cbs(struct nic *nic)
1738 {
1739 struct cb *cb;
1740 unsigned int i, count = nic->params.cbs.count;
1741
1742 nic->cuc_cmd = cuc_start;
1743 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1744 nic->cbs_avail = 0;
1745
1746 nic->cbs = pci_alloc_consistent(nic->pdev,
1747 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1748 if(!nic->cbs)
1749 return -ENOMEM;
1750
1751 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1752 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1753 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1754
1755 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1756 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1757 ((i+1) % count) * sizeof(struct cb));
1758 cb->skb = NULL;
1759 }
1760
1761 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1762 nic->cbs_avail = count;
1763
1764 return 0;
1765 }
1766
1767 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1768 {
1769 if(!nic->rxs) return;
1770 if(RU_SUSPENDED != nic->ru_running) return;
1771
1772 /* handle init time starts */
1773 if(!rx) rx = nic->rxs;
1774
1775 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1776 if(rx->skb) {
1777 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1778 nic->ru_running = RU_RUNNING;
1779 }
1780 }
1781
1782 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1783 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1784 {
1785 if(!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1786 return -ENOMEM;
1787
1788 /* Align, init, and map the RFD. */
1789 skb_reserve(rx->skb, NET_IP_ALIGN);
1790 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1791 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1792 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1793
1794 if(pci_dma_mapping_error(rx->dma_addr)) {
1795 dev_kfree_skb_any(rx->skb);
1796 rx->skb = NULL;
1797 rx->dma_addr = 0;
1798 return -ENOMEM;
1799 }
1800
1801 /* Link the RFD to end of RFA by linking previous RFD to
1802 * this one. We are safe to touch the previous RFD because
1803 * it is protected by the before last buffer's el bit being set */
1804 if(rx->prev->skb) {
1805 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1806 put_unaligned(cpu_to_le32(rx->dma_addr),
1807 (u32 *)&prev_rfd->link);
1808 }
1809
1810 return 0;
1811 }
1812
1813 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1814 unsigned int *work_done, unsigned int work_to_do)
1815 {
1816 struct net_device *dev = nic->netdev;
1817 struct sk_buff *skb = rx->skb;
1818 struct rfd *rfd = (struct rfd *)skb->data;
1819 u16 rfd_status, actual_size;
1820
1821 if(unlikely(work_done && *work_done >= work_to_do))
1822 return -EAGAIN;
1823
1824 /* Need to sync before taking a peek at cb_complete bit */
1825 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1826 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1827 rfd_status = le16_to_cpu(rfd->status);
1828
1829 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1830
1831 /* If data isn't ready, nothing to indicate */
1832 if (unlikely(!(rfd_status & cb_complete))) {
1833 /* If the next buffer has the el bit, but we think the receiver
1834 * is still running, check to see if it really stopped while
1835 * we had interrupts off.
1836 * This allows for a fast restart without re-enabling
1837 * interrupts */
1838 if ((le16_to_cpu(rfd->command) & cb_el) &&
1839 (RU_RUNNING == nic->ru_running))
1840
1841 if (readb(&nic->csr->scb.status) & rus_no_res)
1842 nic->ru_running = RU_SUSPENDED;
1843 return -ENODATA;
1844 }
1845
1846 /* Get actual data size */
1847 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1848 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1849 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1850
1851 /* Get data */
1852 pci_unmap_single(nic->pdev, rx->dma_addr,
1853 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1854
1855 /* If this buffer has the el bit, but we think the receiver
1856 * is still running, check to see if it really stopped while
1857 * we had interrupts off.
1858 * This allows for a fast restart without re-enabling interrupts.
1859 * This can happen when the RU sees the size change but also sees
1860 * the el bit set. */
1861 if ((le16_to_cpu(rfd->command) & cb_el) &&
1862 (RU_RUNNING == nic->ru_running)) {
1863
1864 if (readb(&nic->csr->scb.status) & rus_no_res)
1865 nic->ru_running = RU_SUSPENDED;
1866 }
1867
1868 /* Pull off the RFD and put the actual data (minus eth hdr) */
1869 skb_reserve(skb, sizeof(struct rfd));
1870 skb_put(skb, actual_size);
1871 skb->protocol = eth_type_trans(skb, nic->netdev);
1872
1873 if(unlikely(!(rfd_status & cb_ok))) {
1874 /* Don't indicate if hardware indicates errors */
1875 dev_kfree_skb_any(skb);
1876 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1877 /* Don't indicate oversized frames */
1878 nic->rx_over_length_errors++;
1879 dev_kfree_skb_any(skb);
1880 } else {
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += actual_size;
1883 nic->netdev->last_rx = jiffies;
1884 netif_receive_skb(skb);
1885 if(work_done)
1886 (*work_done)++;
1887 }
1888
1889 rx->skb = NULL;
1890
1891 return 0;
1892 }
1893
1894 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1895 unsigned int work_to_do)
1896 {
1897 struct rx *rx;
1898 int restart_required = 0, err = 0;
1899 struct rx *old_before_last_rx, *new_before_last_rx;
1900 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1901
1902 /* Indicate newly arrived packets */
1903 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1904 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1905 /* Hit quota or no more to clean */
1906 if (-EAGAIN == err || -ENODATA == err)
1907 break;
1908 }
1909
1910
1911 /* On EAGAIN, hit quota so have more work to do, restart once
1912 * cleanup is complete.
1913 * Else, are we already rnr? then pay attention!!! this ensures that
1914 * the state machine progression never allows a start with a
1915 * partially cleaned list, avoiding a race between hardware
1916 * and rx_to_clean when in NAPI mode */
1917 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1918 restart_required = 1;
1919
1920 old_before_last_rx = nic->rx_to_use->prev->prev;
1921 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1922
1923 /* Alloc new skbs to refill list */
1924 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1925 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1926 break; /* Better luck next time (see watchdog) */
1927 }
1928
1929 new_before_last_rx = nic->rx_to_use->prev->prev;
1930 if (new_before_last_rx != old_before_last_rx) {
1931 /* Set the el-bit on the buffer that is before the last buffer.
1932 * This lets us update the next pointer on the last buffer
1933 * without worrying about hardware touching it.
1934 * We set the size to 0 to prevent hardware from touching this
1935 * buffer.
1936 * When the hardware hits the before last buffer with el-bit
1937 * and size of 0, it will RNR interrupt, the RUS will go into
1938 * the No Resources state. It will not complete nor write to
1939 * this buffer. */
1940 new_before_last_rfd =
1941 (struct rfd *)new_before_last_rx->skb->data;
1942 new_before_last_rfd->size = 0;
1943 new_before_last_rfd->command |= cpu_to_le16(cb_el);
1944 pci_dma_sync_single_for_device(nic->pdev,
1945 new_before_last_rx->dma_addr, sizeof(struct rfd),
1946 PCI_DMA_TODEVICE);
1947
1948 /* Now that we have a new stopping point, we can clear the old
1949 * stopping point. We must sync twice to get the proper
1950 * ordering on the hardware side of things. */
1951 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
1952 pci_dma_sync_single_for_device(nic->pdev,
1953 old_before_last_rx->dma_addr, sizeof(struct rfd),
1954 PCI_DMA_TODEVICE);
1955 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1956 pci_dma_sync_single_for_device(nic->pdev,
1957 old_before_last_rx->dma_addr, sizeof(struct rfd),
1958 PCI_DMA_TODEVICE);
1959 }
1960
1961 if(restart_required) {
1962 // ack the rnr?
1963 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1964 e100_start_receiver(nic, nic->rx_to_clean);
1965 if(work_done)
1966 (*work_done)++;
1967 }
1968 }
1969
1970 static void e100_rx_clean_list(struct nic *nic)
1971 {
1972 struct rx *rx;
1973 unsigned int i, count = nic->params.rfds.count;
1974
1975 nic->ru_running = RU_UNINITIALIZED;
1976
1977 if(nic->rxs) {
1978 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1979 if(rx->skb) {
1980 pci_unmap_single(nic->pdev, rx->dma_addr,
1981 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1982 dev_kfree_skb(rx->skb);
1983 }
1984 }
1985 kfree(nic->rxs);
1986 nic->rxs = NULL;
1987 }
1988
1989 nic->rx_to_use = nic->rx_to_clean = NULL;
1990 }
1991
1992 static int e100_rx_alloc_list(struct nic *nic)
1993 {
1994 struct rx *rx;
1995 unsigned int i, count = nic->params.rfds.count;
1996 struct rfd *before_last;
1997
1998 nic->rx_to_use = nic->rx_to_clean = NULL;
1999 nic->ru_running = RU_UNINITIALIZED;
2000
2001 if(!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2002 return -ENOMEM;
2003
2004 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
2005 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2006 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2007 if(e100_rx_alloc_skb(nic, rx)) {
2008 e100_rx_clean_list(nic);
2009 return -ENOMEM;
2010 }
2011 }
2012 /* Set the el-bit on the buffer that is before the last buffer.
2013 * This lets us update the next pointer on the last buffer without
2014 * worrying about hardware touching it.
2015 * We set the size to 0 to prevent hardware from touching this buffer.
2016 * When the hardware hits the before last buffer with el-bit and size
2017 * of 0, it will RNR interrupt, the RU will go into the No Resources
2018 * state. It will not complete nor write to this buffer. */
2019 rx = nic->rxs->prev->prev;
2020 before_last = (struct rfd *)rx->skb->data;
2021 before_last->command |= cpu_to_le16(cb_el);
2022 before_last->size = 0;
2023 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2024 sizeof(struct rfd), PCI_DMA_TODEVICE);
2025
2026 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2027 nic->ru_running = RU_SUSPENDED;
2028
2029 return 0;
2030 }
2031
2032 static irqreturn_t e100_intr(int irq, void *dev_id)
2033 {
2034 struct net_device *netdev = dev_id;
2035 struct nic *nic = netdev_priv(netdev);
2036 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2037
2038 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2039
2040 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
2041 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2042 return IRQ_NONE;
2043
2044 /* Ack interrupt(s) */
2045 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2046
2047 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2048 if(stat_ack & stat_ack_rnr)
2049 nic->ru_running = RU_SUSPENDED;
2050
2051 if(likely(netif_rx_schedule_prep(netdev, &nic->napi))) {
2052 e100_disable_irq(nic);
2053 __netif_rx_schedule(netdev, &nic->napi);
2054 }
2055
2056 return IRQ_HANDLED;
2057 }
2058
2059 static int e100_poll(struct napi_struct *napi, int budget)
2060 {
2061 struct nic *nic = container_of(napi, struct nic, napi);
2062 struct net_device *netdev = nic->netdev;
2063 unsigned int work_done = 0;
2064 int tx_cleaned;
2065
2066 e100_rx_clean(nic, &work_done, budget);
2067 tx_cleaned = e100_tx_clean(nic);
2068
2069 /* If no Rx and Tx cleanup work was done, exit polling mode. */
2070 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
2071 netif_rx_complete(netdev, napi);
2072 e100_enable_irq(nic);
2073 }
2074
2075 return work_done;
2076 }
2077
2078 #ifdef CONFIG_NET_POLL_CONTROLLER
2079 static void e100_netpoll(struct net_device *netdev)
2080 {
2081 struct nic *nic = netdev_priv(netdev);
2082
2083 e100_disable_irq(nic);
2084 e100_intr(nic->pdev->irq, netdev);
2085 e100_tx_clean(nic);
2086 e100_enable_irq(nic);
2087 }
2088 #endif
2089
2090 static int e100_set_mac_address(struct net_device *netdev, void *p)
2091 {
2092 struct nic *nic = netdev_priv(netdev);
2093 struct sockaddr *addr = p;
2094
2095 if (!is_valid_ether_addr(addr->sa_data))
2096 return -EADDRNOTAVAIL;
2097
2098 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2099 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2100
2101 return 0;
2102 }
2103
2104 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2105 {
2106 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2107 return -EINVAL;
2108 netdev->mtu = new_mtu;
2109 return 0;
2110 }
2111
2112 static int e100_asf(struct nic *nic)
2113 {
2114 /* ASF can be enabled from eeprom */
2115 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2116 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2117 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2118 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2119 }
2120
2121 static int e100_up(struct nic *nic)
2122 {
2123 int err;
2124
2125 if((err = e100_rx_alloc_list(nic)))
2126 return err;
2127 if((err = e100_alloc_cbs(nic)))
2128 goto err_rx_clean_list;
2129 if((err = e100_hw_init(nic)))
2130 goto err_clean_cbs;
2131 e100_set_multicast_list(nic->netdev);
2132 e100_start_receiver(nic, NULL);
2133 mod_timer(&nic->watchdog, jiffies);
2134 if((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2135 nic->netdev->name, nic->netdev)))
2136 goto err_no_irq;
2137 netif_wake_queue(nic->netdev);
2138 napi_enable(&nic->napi);
2139 /* enable ints _after_ enabling poll, preventing a race between
2140 * disable ints+schedule */
2141 e100_enable_irq(nic);
2142 return 0;
2143
2144 err_no_irq:
2145 del_timer_sync(&nic->watchdog);
2146 err_clean_cbs:
2147 e100_clean_cbs(nic);
2148 err_rx_clean_list:
2149 e100_rx_clean_list(nic);
2150 return err;
2151 }
2152
2153 static void e100_down(struct nic *nic)
2154 {
2155 /* wait here for poll to complete */
2156 napi_disable(&nic->napi);
2157 netif_stop_queue(nic->netdev);
2158 e100_hw_reset(nic);
2159 free_irq(nic->pdev->irq, nic->netdev);
2160 del_timer_sync(&nic->watchdog);
2161 netif_carrier_off(nic->netdev);
2162 e100_clean_cbs(nic);
2163 e100_rx_clean_list(nic);
2164 }
2165
2166 static void e100_tx_timeout(struct net_device *netdev)
2167 {
2168 struct nic *nic = netdev_priv(netdev);
2169
2170 /* Reset outside of interrupt context, to avoid request_irq
2171 * in interrupt context */
2172 schedule_work(&nic->tx_timeout_task);
2173 }
2174
2175 static void e100_tx_timeout_task(struct work_struct *work)
2176 {
2177 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2178 struct net_device *netdev = nic->netdev;
2179
2180 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2181 ioread8(&nic->csr->scb.status));
2182 e100_down(netdev_priv(netdev));
2183 e100_up(netdev_priv(netdev));
2184 }
2185
2186 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2187 {
2188 int err;
2189 struct sk_buff *skb;
2190
2191 /* Use driver resources to perform internal MAC or PHY
2192 * loopback test. A single packet is prepared and transmitted
2193 * in loopback mode, and the test passes if the received
2194 * packet compares byte-for-byte to the transmitted packet. */
2195
2196 if((err = e100_rx_alloc_list(nic)))
2197 return err;
2198 if((err = e100_alloc_cbs(nic)))
2199 goto err_clean_rx;
2200
2201 /* ICH PHY loopback is broken so do MAC loopback instead */
2202 if(nic->flags & ich && loopback_mode == lb_phy)
2203 loopback_mode = lb_mac;
2204
2205 nic->loopback = loopback_mode;
2206 if((err = e100_hw_init(nic)))
2207 goto err_loopback_none;
2208
2209 if(loopback_mode == lb_phy)
2210 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2211 BMCR_LOOPBACK);
2212
2213 e100_start_receiver(nic, NULL);
2214
2215 if(!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2216 err = -ENOMEM;
2217 goto err_loopback_none;
2218 }
2219 skb_put(skb, ETH_DATA_LEN);
2220 memset(skb->data, 0xFF, ETH_DATA_LEN);
2221 e100_xmit_frame(skb, nic->netdev);
2222
2223 msleep(10);
2224
2225 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2226 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
2227
2228 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2229 skb->data, ETH_DATA_LEN))
2230 err = -EAGAIN;
2231
2232 err_loopback_none:
2233 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2234 nic->loopback = lb_none;
2235 e100_clean_cbs(nic);
2236 e100_hw_reset(nic);
2237 err_clean_rx:
2238 e100_rx_clean_list(nic);
2239 return err;
2240 }
2241
2242 #define MII_LED_CONTROL 0x1B
2243 static void e100_blink_led(unsigned long data)
2244 {
2245 struct nic *nic = (struct nic *)data;
2246 enum led_state {
2247 led_on = 0x01,
2248 led_off = 0x04,
2249 led_on_559 = 0x05,
2250 led_on_557 = 0x07,
2251 };
2252
2253 nic->leds = (nic->leds & led_on) ? led_off :
2254 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2255 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2256 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2257 }
2258
2259 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2260 {
2261 struct nic *nic = netdev_priv(netdev);
2262 return mii_ethtool_gset(&nic->mii, cmd);
2263 }
2264
2265 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2266 {
2267 struct nic *nic = netdev_priv(netdev);
2268 int err;
2269
2270 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2271 err = mii_ethtool_sset(&nic->mii, cmd);
2272 e100_exec_cb(nic, NULL, e100_configure);
2273
2274 return err;
2275 }
2276
2277 static void e100_get_drvinfo(struct net_device *netdev,
2278 struct ethtool_drvinfo *info)
2279 {
2280 struct nic *nic = netdev_priv(netdev);
2281 strcpy(info->driver, DRV_NAME);
2282 strcpy(info->version, DRV_VERSION);
2283 strcpy(info->fw_version, "N/A");
2284 strcpy(info->bus_info, pci_name(nic->pdev));
2285 }
2286
2287 static int e100_get_regs_len(struct net_device *netdev)
2288 {
2289 struct nic *nic = netdev_priv(netdev);
2290 #define E100_PHY_REGS 0x1C
2291 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
2292 sizeof(nic->mem->dump_buf) / sizeof(u32)
2293 return E100_REGS_LEN * sizeof(u32);
2294 }
2295
2296 static void e100_get_regs(struct net_device *netdev,
2297 struct ethtool_regs *regs, void *p)
2298 {
2299 struct nic *nic = netdev_priv(netdev);
2300 u32 *buff = p;
2301 int i;
2302
2303 regs->version = (1 << 24) | nic->pdev->revision;
2304 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2305 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2306 ioread16(&nic->csr->scb.status);
2307 for(i = E100_PHY_REGS; i >= 0; i--)
2308 buff[1 + E100_PHY_REGS - i] =
2309 mdio_read(netdev, nic->mii.phy_id, i);
2310 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2311 e100_exec_cb(nic, NULL, e100_dump);
2312 msleep(10);
2313 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2314 sizeof(nic->mem->dump_buf));
2315 }
2316
2317 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2318 {
2319 struct nic *nic = netdev_priv(netdev);
2320 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2321 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2322 }
2323
2324 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2325 {
2326 struct nic *nic = netdev_priv(netdev);
2327
2328 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2329 return -EOPNOTSUPP;
2330
2331 if(wol->wolopts)
2332 nic->flags |= wol_magic;
2333 else
2334 nic->flags &= ~wol_magic;
2335
2336 e100_exec_cb(nic, NULL, e100_configure);
2337
2338 return 0;
2339 }
2340
2341 static u32 e100_get_msglevel(struct net_device *netdev)
2342 {
2343 struct nic *nic = netdev_priv(netdev);
2344 return nic->msg_enable;
2345 }
2346
2347 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2348 {
2349 struct nic *nic = netdev_priv(netdev);
2350 nic->msg_enable = value;
2351 }
2352
2353 static int e100_nway_reset(struct net_device *netdev)
2354 {
2355 struct nic *nic = netdev_priv(netdev);
2356 return mii_nway_restart(&nic->mii);
2357 }
2358
2359 static u32 e100_get_link(struct net_device *netdev)
2360 {
2361 struct nic *nic = netdev_priv(netdev);
2362 return mii_link_ok(&nic->mii);
2363 }
2364
2365 static int e100_get_eeprom_len(struct net_device *netdev)
2366 {
2367 struct nic *nic = netdev_priv(netdev);
2368 return nic->eeprom_wc << 1;
2369 }
2370
2371 #define E100_EEPROM_MAGIC 0x1234
2372 static int e100_get_eeprom(struct net_device *netdev,
2373 struct ethtool_eeprom *eeprom, u8 *bytes)
2374 {
2375 struct nic *nic = netdev_priv(netdev);
2376
2377 eeprom->magic = E100_EEPROM_MAGIC;
2378 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2379
2380 return 0;
2381 }
2382
2383 static int e100_set_eeprom(struct net_device *netdev,
2384 struct ethtool_eeprom *eeprom, u8 *bytes)
2385 {
2386 struct nic *nic = netdev_priv(netdev);
2387
2388 if(eeprom->magic != E100_EEPROM_MAGIC)
2389 return -EINVAL;
2390
2391 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2392
2393 return e100_eeprom_save(nic, eeprom->offset >> 1,
2394 (eeprom->len >> 1) + 1);
2395 }
2396
2397 static void e100_get_ringparam(struct net_device *netdev,
2398 struct ethtool_ringparam *ring)
2399 {
2400 struct nic *nic = netdev_priv(netdev);
2401 struct param_range *rfds = &nic->params.rfds;
2402 struct param_range *cbs = &nic->params.cbs;
2403
2404 ring->rx_max_pending = rfds->max;
2405 ring->tx_max_pending = cbs->max;
2406 ring->rx_mini_max_pending = 0;
2407 ring->rx_jumbo_max_pending = 0;
2408 ring->rx_pending = rfds->count;
2409 ring->tx_pending = cbs->count;
2410 ring->rx_mini_pending = 0;
2411 ring->rx_jumbo_pending = 0;
2412 }
2413
2414 static int e100_set_ringparam(struct net_device *netdev,
2415 struct ethtool_ringparam *ring)
2416 {
2417 struct nic *nic = netdev_priv(netdev);
2418 struct param_range *rfds = &nic->params.rfds;
2419 struct param_range *cbs = &nic->params.cbs;
2420
2421 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2422 return -EINVAL;
2423
2424 if(netif_running(netdev))
2425 e100_down(nic);
2426 rfds->count = max(ring->rx_pending, rfds->min);
2427 rfds->count = min(rfds->count, rfds->max);
2428 cbs->count = max(ring->tx_pending, cbs->min);
2429 cbs->count = min(cbs->count, cbs->max);
2430 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2431 rfds->count, cbs->count);
2432 if(netif_running(netdev))
2433 e100_up(nic);
2434
2435 return 0;
2436 }
2437
2438 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2439 "Link test (on/offline)",
2440 "Eeprom test (on/offline)",
2441 "Self test (offline)",
2442 "Mac loopback (offline)",
2443 "Phy loopback (offline)",
2444 };
2445 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2446
2447 static void e100_diag_test(struct net_device *netdev,
2448 struct ethtool_test *test, u64 *data)
2449 {
2450 struct ethtool_cmd cmd;
2451 struct nic *nic = netdev_priv(netdev);
2452 int i, err;
2453
2454 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2455 data[0] = !mii_link_ok(&nic->mii);
2456 data[1] = e100_eeprom_load(nic);
2457 if(test->flags & ETH_TEST_FL_OFFLINE) {
2458
2459 /* save speed, duplex & autoneg settings */
2460 err = mii_ethtool_gset(&nic->mii, &cmd);
2461
2462 if(netif_running(netdev))
2463 e100_down(nic);
2464 data[2] = e100_self_test(nic);
2465 data[3] = e100_loopback_test(nic, lb_mac);
2466 data[4] = e100_loopback_test(nic, lb_phy);
2467
2468 /* restore speed, duplex & autoneg settings */
2469 err = mii_ethtool_sset(&nic->mii, &cmd);
2470
2471 if(netif_running(netdev))
2472 e100_up(nic);
2473 }
2474 for(i = 0; i < E100_TEST_LEN; i++)
2475 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2476
2477 msleep_interruptible(4 * 1000);
2478 }
2479
2480 static int e100_phys_id(struct net_device *netdev, u32 data)
2481 {
2482 struct nic *nic = netdev_priv(netdev);
2483
2484 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2485 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2486 mod_timer(&nic->blink_timer, jiffies);
2487 msleep_interruptible(data * 1000);
2488 del_timer_sync(&nic->blink_timer);
2489 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2490
2491 return 0;
2492 }
2493
2494 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2495 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2496 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2497 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2498 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2499 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2500 "tx_heartbeat_errors", "tx_window_errors",
2501 /* device-specific stats */
2502 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2503 "tx_flow_control_pause", "rx_flow_control_pause",
2504 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2505 };
2506 #define E100_NET_STATS_LEN 21
2507 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2508
2509 static int e100_get_sset_count(struct net_device *netdev, int sset)
2510 {
2511 switch (sset) {
2512 case ETH_SS_TEST:
2513 return E100_TEST_LEN;
2514 case ETH_SS_STATS:
2515 return E100_STATS_LEN;
2516 default:
2517 return -EOPNOTSUPP;
2518 }
2519 }
2520
2521 static void e100_get_ethtool_stats(struct net_device *netdev,
2522 struct ethtool_stats *stats, u64 *data)
2523 {
2524 struct nic *nic = netdev_priv(netdev);
2525 int i;
2526
2527 for(i = 0; i < E100_NET_STATS_LEN; i++)
2528 data[i] = ((unsigned long *)&netdev->stats)[i];
2529
2530 data[i++] = nic->tx_deferred;
2531 data[i++] = nic->tx_single_collisions;
2532 data[i++] = nic->tx_multiple_collisions;
2533 data[i++] = nic->tx_fc_pause;
2534 data[i++] = nic->rx_fc_pause;
2535 data[i++] = nic->rx_fc_unsupported;
2536 data[i++] = nic->tx_tco_frames;
2537 data[i++] = nic->rx_tco_frames;
2538 }
2539
2540 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2541 {
2542 switch(stringset) {
2543 case ETH_SS_TEST:
2544 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2545 break;
2546 case ETH_SS_STATS:
2547 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2548 break;
2549 }
2550 }
2551
2552 static const struct ethtool_ops e100_ethtool_ops = {
2553 .get_settings = e100_get_settings,
2554 .set_settings = e100_set_settings,
2555 .get_drvinfo = e100_get_drvinfo,
2556 .get_regs_len = e100_get_regs_len,
2557 .get_regs = e100_get_regs,
2558 .get_wol = e100_get_wol,
2559 .set_wol = e100_set_wol,
2560 .get_msglevel = e100_get_msglevel,
2561 .set_msglevel = e100_set_msglevel,
2562 .nway_reset = e100_nway_reset,
2563 .get_link = e100_get_link,
2564 .get_eeprom_len = e100_get_eeprom_len,
2565 .get_eeprom = e100_get_eeprom,
2566 .set_eeprom = e100_set_eeprom,
2567 .get_ringparam = e100_get_ringparam,
2568 .set_ringparam = e100_set_ringparam,
2569 .self_test = e100_diag_test,
2570 .get_strings = e100_get_strings,
2571 .phys_id = e100_phys_id,
2572 .get_ethtool_stats = e100_get_ethtool_stats,
2573 .get_sset_count = e100_get_sset_count,
2574 };
2575
2576 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2577 {
2578 struct nic *nic = netdev_priv(netdev);
2579
2580 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2581 }
2582
2583 static int e100_alloc(struct nic *nic)
2584 {
2585 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2586 &nic->dma_addr);
2587 return nic->mem ? 0 : -ENOMEM;
2588 }
2589
2590 static void e100_free(struct nic *nic)
2591 {
2592 if(nic->mem) {
2593 pci_free_consistent(nic->pdev, sizeof(struct mem),
2594 nic->mem, nic->dma_addr);
2595 nic->mem = NULL;
2596 }
2597 }
2598
2599 static int e100_open(struct net_device *netdev)
2600 {
2601 struct nic *nic = netdev_priv(netdev);
2602 int err = 0;
2603
2604 netif_carrier_off(netdev);
2605 if((err = e100_up(nic)))
2606 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2607 return err;
2608 }
2609
2610 static int e100_close(struct net_device *netdev)
2611 {
2612 e100_down(netdev_priv(netdev));
2613 return 0;
2614 }
2615
2616 static int __devinit e100_probe(struct pci_dev *pdev,
2617 const struct pci_device_id *ent)
2618 {
2619 struct net_device *netdev;
2620 struct nic *nic;
2621 int err;
2622 DECLARE_MAC_BUF(mac);
2623
2624 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2625 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2626 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2627 return -ENOMEM;
2628 }
2629
2630 netdev->open = e100_open;
2631 netdev->stop = e100_close;
2632 netdev->hard_start_xmit = e100_xmit_frame;
2633 netdev->set_multicast_list = e100_set_multicast_list;
2634 netdev->set_mac_address = e100_set_mac_address;
2635 netdev->change_mtu = e100_change_mtu;
2636 netdev->do_ioctl = e100_do_ioctl;
2637 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2638 netdev->tx_timeout = e100_tx_timeout;
2639 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2640 #ifdef CONFIG_NET_POLL_CONTROLLER
2641 netdev->poll_controller = e100_netpoll;
2642 #endif
2643 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2644
2645 nic = netdev_priv(netdev);
2646 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2647 nic->netdev = netdev;
2648 nic->pdev = pdev;
2649 nic->msg_enable = (1 << debug) - 1;
2650 pci_set_drvdata(pdev, netdev);
2651
2652 if((err = pci_enable_device(pdev))) {
2653 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2654 goto err_out_free_dev;
2655 }
2656
2657 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2658 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2659 "base address, aborting.\n");
2660 err = -ENODEV;
2661 goto err_out_disable_pdev;
2662 }
2663
2664 if((err = pci_request_regions(pdev, DRV_NAME))) {
2665 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2666 goto err_out_disable_pdev;
2667 }
2668
2669 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
2670 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2671 goto err_out_free_res;
2672 }
2673
2674 SET_NETDEV_DEV(netdev, &pdev->dev);
2675
2676 if (use_io)
2677 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2678
2679 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2680 if(!nic->csr) {
2681 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2682 err = -ENOMEM;
2683 goto err_out_free_res;
2684 }
2685
2686 if(ent->driver_data)
2687 nic->flags |= ich;
2688 else
2689 nic->flags &= ~ich;
2690
2691 e100_get_defaults(nic);
2692
2693 /* locks must be initialized before calling hw_reset */
2694 spin_lock_init(&nic->cb_lock);
2695 spin_lock_init(&nic->cmd_lock);
2696 spin_lock_init(&nic->mdio_lock);
2697
2698 /* Reset the device before pci_set_master() in case device is in some
2699 * funky state and has an interrupt pending - hint: we don't have the
2700 * interrupt handler registered yet. */
2701 e100_hw_reset(nic);
2702
2703 pci_set_master(pdev);
2704
2705 init_timer(&nic->watchdog);
2706 nic->watchdog.function = e100_watchdog;
2707 nic->watchdog.data = (unsigned long)nic;
2708 init_timer(&nic->blink_timer);
2709 nic->blink_timer.function = e100_blink_led;
2710 nic->blink_timer.data = (unsigned long)nic;
2711
2712 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2713
2714 if((err = e100_alloc(nic))) {
2715 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2716 goto err_out_iounmap;
2717 }
2718
2719 if((err = e100_eeprom_load(nic)))
2720 goto err_out_free;
2721
2722 e100_phy_init(nic);
2723
2724 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2725 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2726 if (!is_valid_ether_addr(netdev->perm_addr)) {
2727 if (!eeprom_bad_csum_allow) {
2728 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2729 "EEPROM, aborting.\n");
2730 err = -EAGAIN;
2731 goto err_out_free;
2732 } else {
2733 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2734 "you MUST configure one.\n");
2735 }
2736 }
2737
2738 /* Wol magic packet can be enabled from eeprom */
2739 if((nic->mac >= mac_82558_D101_A4) &&
2740 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2741 nic->flags |= wol_magic;
2742
2743 /* ack any pending wake events, disable PME */
2744 err = pci_enable_wake(pdev, 0, 0);
2745 if (err)
2746 DPRINTK(PROBE, ERR, "Error clearing wake event\n");
2747
2748 strcpy(netdev->name, "eth%d");
2749 if((err = register_netdev(netdev))) {
2750 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2751 goto err_out_free;
2752 }
2753
2754 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %s\n",
2755 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2756 pdev->irq, print_mac(mac, netdev->dev_addr));
2757
2758 return 0;
2759
2760 err_out_free:
2761 e100_free(nic);
2762 err_out_iounmap:
2763 pci_iounmap(pdev, nic->csr);
2764 err_out_free_res:
2765 pci_release_regions(pdev);
2766 err_out_disable_pdev:
2767 pci_disable_device(pdev);
2768 err_out_free_dev:
2769 pci_set_drvdata(pdev, NULL);
2770 free_netdev(netdev);
2771 return err;
2772 }
2773
2774 static void __devexit e100_remove(struct pci_dev *pdev)
2775 {
2776 struct net_device *netdev = pci_get_drvdata(pdev);
2777
2778 if(netdev) {
2779 struct nic *nic = netdev_priv(netdev);
2780 unregister_netdev(netdev);
2781 e100_free(nic);
2782 iounmap(nic->csr);
2783 free_netdev(netdev);
2784 pci_release_regions(pdev);
2785 pci_disable_device(pdev);
2786 pci_set_drvdata(pdev, NULL);
2787 }
2788 }
2789
2790 #ifdef CONFIG_PM
2791 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2792 {
2793 struct net_device *netdev = pci_get_drvdata(pdev);
2794 struct nic *nic = netdev_priv(netdev);
2795
2796 if (netif_running(netdev))
2797 napi_disable(&nic->napi);
2798 del_timer_sync(&nic->watchdog);
2799 netif_carrier_off(nic->netdev);
2800 netif_device_detach(netdev);
2801
2802 pci_save_state(pdev);
2803
2804 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2805 pci_enable_wake(pdev, PCI_D3hot, 1);
2806 pci_enable_wake(pdev, PCI_D3cold, 1);
2807 } else {
2808 pci_enable_wake(pdev, PCI_D3hot, 0);
2809 pci_enable_wake(pdev, PCI_D3cold, 0);
2810 }
2811
2812 pci_disable_device(pdev);
2813 free_irq(pdev->irq, netdev);
2814 pci_set_power_state(pdev, PCI_D3hot);
2815
2816 return 0;
2817 }
2818
2819 static int e100_resume(struct pci_dev *pdev)
2820 {
2821 struct net_device *netdev = pci_get_drvdata(pdev);
2822 struct nic *nic = netdev_priv(netdev);
2823
2824 pci_set_power_state(pdev, PCI_D0);
2825 pci_restore_state(pdev);
2826 /* ack any pending wake events, disable PME */
2827 pci_enable_wake(pdev, 0, 0);
2828
2829 netif_device_attach(netdev);
2830 if (netif_running(netdev))
2831 e100_up(nic);
2832
2833 return 0;
2834 }
2835 #endif /* CONFIG_PM */
2836
2837 static void e100_shutdown(struct pci_dev *pdev)
2838 {
2839 struct net_device *netdev = pci_get_drvdata(pdev);
2840 struct nic *nic = netdev_priv(netdev);
2841
2842 if (netif_running(netdev))
2843 napi_disable(&nic->napi);
2844 del_timer_sync(&nic->watchdog);
2845 netif_carrier_off(nic->netdev);
2846
2847 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2848 pci_enable_wake(pdev, PCI_D3hot, 1);
2849 pci_enable_wake(pdev, PCI_D3cold, 1);
2850 } else {
2851 pci_enable_wake(pdev, PCI_D3hot, 0);
2852 pci_enable_wake(pdev, PCI_D3cold, 0);
2853 }
2854
2855 pci_disable_device(pdev);
2856 pci_set_power_state(pdev, PCI_D3hot);
2857 }
2858
2859 /* ------------------ PCI Error Recovery infrastructure -------------- */
2860 /**
2861 * e100_io_error_detected - called when PCI error is detected.
2862 * @pdev: Pointer to PCI device
2863 * @state: The current pci conneection state
2864 */
2865 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2866 {
2867 struct net_device *netdev = pci_get_drvdata(pdev);
2868 struct nic *nic = netdev_priv(netdev);
2869
2870 /* Similar to calling e100_down(), but avoids adpater I/O. */
2871 netdev->stop(netdev);
2872
2873 /* Detach; put netif into state similar to hotplug unplug. */
2874 napi_enable(&nic->napi);
2875 netif_device_detach(netdev);
2876 pci_disable_device(pdev);
2877
2878 /* Request a slot reset. */
2879 return PCI_ERS_RESULT_NEED_RESET;
2880 }
2881
2882 /**
2883 * e100_io_slot_reset - called after the pci bus has been reset.
2884 * @pdev: Pointer to PCI device
2885 *
2886 * Restart the card from scratch.
2887 */
2888 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2889 {
2890 struct net_device *netdev = pci_get_drvdata(pdev);
2891 struct nic *nic = netdev_priv(netdev);
2892
2893 if (pci_enable_device(pdev)) {
2894 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2895 return PCI_ERS_RESULT_DISCONNECT;
2896 }
2897 pci_set_master(pdev);
2898
2899 /* Only one device per card can do a reset */
2900 if (0 != PCI_FUNC(pdev->devfn))
2901 return PCI_ERS_RESULT_RECOVERED;
2902 e100_hw_reset(nic);
2903 e100_phy_init(nic);
2904
2905 return PCI_ERS_RESULT_RECOVERED;
2906 }
2907
2908 /**
2909 * e100_io_resume - resume normal operations
2910 * @pdev: Pointer to PCI device
2911 *
2912 * Resume normal operations after an error recovery
2913 * sequence has been completed.
2914 */
2915 static void e100_io_resume(struct pci_dev *pdev)
2916 {
2917 struct net_device *netdev = pci_get_drvdata(pdev);
2918 struct nic *nic = netdev_priv(netdev);
2919
2920 /* ack any pending wake events, disable PME */
2921 pci_enable_wake(pdev, 0, 0);
2922
2923 netif_device_attach(netdev);
2924 if (netif_running(netdev)) {
2925 e100_open(netdev);
2926 mod_timer(&nic->watchdog, jiffies);
2927 }
2928 }
2929
2930 static struct pci_error_handlers e100_err_handler = {
2931 .error_detected = e100_io_error_detected,
2932 .slot_reset = e100_io_slot_reset,
2933 .resume = e100_io_resume,
2934 };
2935
2936 static struct pci_driver e100_driver = {
2937 .name = DRV_NAME,
2938 .id_table = e100_id_table,
2939 .probe = e100_probe,
2940 .remove = __devexit_p(e100_remove),
2941 #ifdef CONFIG_PM
2942 /* Power Management hooks */
2943 .suspend = e100_suspend,
2944 .resume = e100_resume,
2945 #endif
2946 .shutdown = e100_shutdown,
2947 .err_handler = &e100_err_handler,
2948 };
2949
2950 static int __init e100_init_module(void)
2951 {
2952 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2953 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2954 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2955 }
2956 return pci_register_driver(&e100_driver);
2957 }
2958
2959 static void __exit e100_cleanup_module(void)
2960 {
2961 pci_unregister_driver(&e100_driver);
2962 }
2963
2964 module_init(e100_init_module);
2965 module_exit(e100_cleanup_module);
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