drivers/serial/cpm_uart/cpm_uart_cpm1.c

   1 /*
   2  *  linux/drivers/serial/cpm_uart.c
   3  *
   4  *  Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
   5  *
   6  *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
   7  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
   8  *
   9  *  Copyright (C) 2004 Freescale Semiconductor, Inc.
  10  *            (C) 2004 Intracom, S.A.
  11  *            (C) 2006 MontaVista Software, Inc.
  12  *              Vitaly Bordug <vbordug@ru.mvista.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27  *
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/tty.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/serial.h>
  35 #include <linux/console.h>
  36 #include <linux/sysrq.h>
  37 #include <linux/device.h>
  38 #include <linux/bootmem.h>
  39 #include <linux/dma-mapping.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/fs_pd.h>
  44
  45 #include <linux/serial_core.h>
  46 #include <linux/kernel.h>
  47
  48 #include "cpm_uart.h"
  49
  50 /**************************************************************/
  51
  52 #ifdef CONFIG_PPC_CPM_NEW_BINDING
  53 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
  54 {
  55         u16 __iomem *cpcr = &cpmp->cp_cpcr;
  56
  57         out_be16(cpcr, port->command | (cmd << 8) | CPM_CR_FLG);
  58         while (in_be16(cpcr) & CPM_CR_FLG)
  59                 ;
  60 }
  61 #else
  62 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
  63 {
  64         ushort val;
  65         int line = port - cpm_uart_ports;
  66         volatile cpm8xx_t *cp = cpmp;
  67
  68         switch (line) {
  69         case UART_SMC1:
  70                 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
  71                 break;
  72         case UART_SMC2:
  73                 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
  74                 break;
  75         case UART_SCC1:
  76                 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
  77                 break;
  78         case UART_SCC2:
  79                 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
  80                 break;
  81         case UART_SCC3:
  82                 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
  83                 break;
  84         case UART_SCC4:
  85                 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
  86                 break;
  87         default:
  88                 return;
  89
  90         }
  91         cp->cp_cpcr = val;
  92         while (cp->cp_cpcr & CPM_CR_FLG) ;
  93 }
  94
  95 void smc1_lineif(struct uart_cpm_port *pinfo)
  96 {
  97         pinfo->brg = 1;
  98 }
  99
 100 void smc2_lineif(struct uart_cpm_port *pinfo)
 101 {
 102         pinfo->brg = 2;
 103 }
 104
 105 void scc1_lineif(struct uart_cpm_port *pinfo)
 106 {
 107         /* XXX SCC1: insert port configuration here */
 108         pinfo->brg = 1;
 109 }
 110
 111 void scc2_lineif(struct uart_cpm_port *pinfo)
 112 {
 113         /* XXX SCC2: insert port configuration here */
 114         pinfo->brg = 2;
 115 }
 116
 117 void scc3_lineif(struct uart_cpm_port *pinfo)
 118 {
 119         /* XXX SCC3: insert port configuration here */
 120         pinfo->brg = 3;
 121 }
 122
 123 void scc4_lineif(struct uart_cpm_port *pinfo)
 124 {
 125         /* XXX SCC4: insert port configuration here */
 126         pinfo->brg = 4;
 127 }
 128 #endif
 129
 130 /*
 131  * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
 132  * receive buffer descriptors from dual port ram, and a character
 133  * buffer area from host mem. If we are allocating for the console we need
 134  * to do it from bootmem
 135  */
 136 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 137 {
 138         int dpmemsz, memsz;
 139         u8 *dp_mem;
 140         unsigned long dp_offset;
 141         u8 *mem_addr;
 142         dma_addr_t dma_addr = 0;
 143
 144         pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
 145
 146         dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
 147         dp_offset = cpm_dpalloc(dpmemsz, 8);
 148         if (IS_ERR_VALUE(dp_offset)) {
 149                 printk(KERN_ERR
 150                        "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
 151                 return -ENOMEM;
 152         }
 153         dp_mem = cpm_dpram_addr(dp_offset);
 154
 155         memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 156             L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 157         if (is_con) {
 158                 /* was hostalloc but changed cause it blows away the */
 159                 /* large tlb mapping when pinning the kernel area    */
 160                 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
 161                 dma_addr = (u32)cpm_dpram_phys(mem_addr);
 162         } else
 163                 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
 164                                               GFP_KERNEL);
 165
 166         if (mem_addr == NULL) {
 167                 cpm_dpfree(dp_offset);
 168                 printk(KERN_ERR
 169                        "cpm_uart_cpm1.c: could not allocate coherent memory\n");
 170                 return -ENOMEM;
 171         }
 172
 173         pinfo->dp_addr = dp_offset;
 174         pinfo->mem_addr = mem_addr;             /*  virtual address*/
 175         pinfo->dma_addr = dma_addr;             /*  physical address*/
 176         pinfo->mem_size = memsz;
 177
 178         pinfo->rx_buf = mem_addr;
 179         pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
 180                                                        * pinfo->rx_fifosize);
 181
 182         pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
 183         pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
 184
 185         return 0;
 186 }
 187
 188 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
 189 {
 190         dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
 191                                                pinfo->rx_fifosize) +
 192                           L1_CACHE_ALIGN(pinfo->tx_nrfifos *
 193                                          pinfo->tx_fifosize), pinfo->mem_addr,
 194                           pinfo->dma_addr);
 195
 196         cpm_dpfree(pinfo->dp_addr);
 197 }
 198
 199 #ifndef CONFIG_PPC_CPM_NEW_BINDING
 200 /* Setup any dynamic params in the uart desc */
 201 int cpm_uart_init_portdesc(void)
 202 {
 203         pr_debug("CPM uart[-]:init portdesc\n");
 204
 205         cpm_uart_nr = 0;
 206 #ifdef CONFIG_SERIAL_CPM_SMC1
 207         cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
 208 /*
 209  *  Is SMC1 being relocated?
 210  */
 211 # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
 212         cpm_uart_ports[UART_SMC1].smcup =
 213             (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
 214 # else
 215         cpm_uart_ports[UART_SMC1].smcup =
 216             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
 217 # endif
 218         cpm_uart_ports[UART_SMC1].port.mapbase =
 219             (unsigned long)&cpmp->cp_smc[0];
 220         cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 221         cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 222         cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
 223         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
 224 #endif
 225
 226 #ifdef CONFIG_SERIAL_CPM_SMC2
 227         cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
 228         cpm_uart_ports[UART_SMC2].smcup =
 229             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
 230         cpm_uart_ports[UART_SMC2].port.mapbase =
 231             (unsigned long)&cpmp->cp_smc[1];
 232         cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 233         cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 234         cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
 235         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
 236 #endif
 237
 238 #ifdef CONFIG_SERIAL_CPM_SCC1
 239         cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
 240         cpm_uart_ports[UART_SCC1].sccup =
 241             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
 242         cpm_uart_ports[UART_SCC1].port.mapbase =
 243             (unsigned long)&cpmp->cp_scc[0];
 244         cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
 245             ~(UART_SCCM_TX | UART_SCCM_RX);
 246         cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
 247             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 248         cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
 249         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
 250 #endif
 251
 252 #ifdef CONFIG_SERIAL_CPM_SCC2
 253         cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
 254         cpm_uart_ports[UART_SCC2].sccup =
 255             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
 256         cpm_uart_ports[UART_SCC2].port.mapbase =
 257             (unsigned long)&cpmp->cp_scc[1];
 258         cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
 259             ~(UART_SCCM_TX | UART_SCCM_RX);
 260         cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
 261             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 262         cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
 263         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
 264 #endif
 265
 266 #ifdef CONFIG_SERIAL_CPM_SCC3
 267         cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
 268         cpm_uart_ports[UART_SCC3].sccup =
 269             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
 270         cpm_uart_ports[UART_SCC3].port.mapbase =
 271             (unsigned long)&cpmp->cp_scc[2];
 272         cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
 273             ~(UART_SCCM_TX | UART_SCCM_RX);
 274         cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
 275             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 276         cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
 277         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
 278 #endif
 279
 280 #ifdef CONFIG_SERIAL_CPM_SCC4
 281         cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
 282         cpm_uart_ports[UART_SCC4].sccup =
 283             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
 284         cpm_uart_ports[UART_SCC4].port.mapbase =
 285             (unsigned long)&cpmp->cp_scc[3];
 286         cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
 287             ~(UART_SCCM_TX | UART_SCCM_RX);
 288         cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
 289             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 290         cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
 291         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
 292 #endif
 293         return 0;
 294 }
 295 #endif