arch/mips/philips/pnx8550/common/time.c

   1 /*
   2  * Copyright 2001, 2002, 2003 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
   5  *
   6  * Common time service routines for MIPS machines. See
   7  * Documents/MIPS/README.txt.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/param.h>
  19 #include <linux/time.h>
  20 #include <linux/timer.h>
  21 #include <linux/smp.h>
  22 #include <linux/kernel_stat.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/module.h>
  26
  27 #include <asm/bootinfo.h>
  28 #include <asm/cpu.h>
  29 #include <asm/time.h>
  30 #include <asm/hardirq.h>
  31 #include <asm/div64.h>
  32 #include <asm/debug.h>
  33
  34 #include <int.h>
  35 #include <cm.h>
  36
  37 static unsigned long cpj;
  38
  39 static cycle_t hpt_read(void)
  40 {
  41         return read_c0_count2();
  42 }
  43
  44 static void timer_ack(void)
  45 {
  46         write_c0_compare(cpj);
  47 }
  48
  49 /*
  50  * plat_time_init() - it does the following things:
  51  *
  52  * 1) plat_time_init() -
  53  *      a) (optional) set up RTC routines,
  54  *      b) (optional) calibrate and set the mips_hpt_frequency
  55  *          (only needed if you intended to use cpu counter as timer interrupt
  56  *           source)
  57  */
  58
  59 __init void plat_time_init(void)
  60 {
  61         unsigned int             n;
  62         unsigned int             m;
  63         unsigned int             p;
  64         unsigned int             pow2p;
  65
  66         /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
  67         /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1:  FIXME) */
  68
  69         n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
  70         m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
  71         p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
  72         pow2p = (1 << p);
  73
  74         db_assert(m != 0 && pow2p != 0);
  75
  76         /*
  77          * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
  78          * (a.k.a. 8-10).  Divide by HZ for a timer offset that results in
  79          * HZ timer interrupts per second.
  80          */
  81         mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
  82         cpj = (mips_hpt_frequency + HZ / 2) / HZ;
  83         write_c0_count(0);
  84         timer_ack();
  85
  86         /* Setup Timer 2 */
  87         write_c0_count2(0);
  88         write_c0_compare2(0xffffffff);
  89
  90         clocksource_mips.read = hpt_read;
  91         mips_timer_ack = timer_ack;
  92 }
  93
  94 static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
  95 {
  96         /* Timer 2 clear interrupt */
  97         write_c0_compare2(-1);
  98         return IRQ_HANDLED;
  99 }
 100
 101 static struct irqaction monotonic_irqaction = {
 102         .handler = monotonic_interrupt,
 103         .flags = IRQF_DISABLED,
 104         .name = "Monotonic timer",
 105 };
 106
 107 void __init plat_timer_setup(struct irqaction *irq)
 108 {
 109         int configPR;
 110
 111         setup_irq(PNX8550_INT_TIMER1, irq);
 112         setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
 113
 114         /* Timer 1 start */
 115         configPR = read_c0_config7();
 116         configPR &= ~0x00000008;
 117         write_c0_config7(configPR);
 118
 119         /* Timer 2 start */
 120         configPR = read_c0_config7();
 121         configPR &= ~0x00000010;
 122         write_c0_config7(configPR);
 123
 124         /* Timer 3 stop */
 125         configPR = read_c0_config7();
 126         configPR |= 0x00000020;
 127         write_c0_config7(configPR);
 128 }