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revert-mm-fix-blkdev-size-calculation-in-generic_write_checks
[linux-2.6/linux-trees-mm.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blobd13af99c6cac3ea48e66dbd45361d3b90d1bcfb6
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/console.h>
20 #include <linux/pci.h>
21 #include <linux/pm.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
27 #include <asm/time.h>
28 #include <asm/txx9tmr.h>
29 #include <asm/io.h>
30 #include <asm/bootinfo.h>
31 #include <asm/tx4938/rbtx4938.h>
32 #ifdef CONFIG_SERIAL_TXX9
33 #include <linux/serial_core.h>
34 #endif
35 #include <linux/spi/spi.h>
36 #include <asm/tx4938/spi.h>
37 #include <asm/gpio.h>
38
39 extern char * __init prom_getcmdline(void);
40 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
41
42 /* These functions are used for rebooting or halting the machine*/
43 extern void rbtx4938_machine_restart(char *command);
44 extern void rbtx4938_machine_halt(void);
45 extern void rbtx4938_machine_power_off(void);
46
47 /* clocks */
48 unsigned int txx9_master_clock;
49 unsigned int txx9_cpu_clock;
50 unsigned int txx9_gbus_clock;
51
52 unsigned long rbtx4938_ce_base[8];
53 unsigned long rbtx4938_ce_size[8];
54 int txboard_pci66_mode;
55 static int tx4938_pcic_trdyto; /* default: disabled */
56 static int tx4938_pcic_retryto; /* default: disabled */
57 static int tx4938_ccfg_toeon = 1;
58
59 struct tx4938_pcic_reg *pcicptrs[4] = {
60 tx4938_pcicptr /* default setting for TX4938 */
61 };
62
63 static struct {
64 unsigned long base;
65 unsigned long size;
66 } phys_regions[16] __initdata;
67 static int num_phys_regions __initdata;
68
69 #define PHYS_REGION_MINSIZE 0x10000
70
71 void rbtx4938_machine_halt(void)
72 {
73 printk(KERN_NOTICE "System Halted\n");
74 local_irq_disable();
75
76 while (1)
77 __asm__(".set\tmips3\n\t"
78 "wait\n\t"
79 ".set\tmips0");
80 }
81
82 void rbtx4938_machine_power_off(void)
83 {
84 rbtx4938_machine_halt();
85 /* no return */
86 }
87
88 void rbtx4938_machine_restart(char *command)
89 {
90 local_irq_disable();
91
92 printk("Rebooting...");
93 *rbtx4938_softresetlock_ptr = 1;
94 *rbtx4938_sfvol_ptr = 1;
95 *rbtx4938_softreset_ptr = 1;
96 wbflush();
97
98 while(1);
99 }
100
101 void __init
102 txboard_add_phys_region(unsigned long base, unsigned long size)
103 {
104 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
105 printk("phys_region overflow\n");
106 return;
107 }
108 phys_regions[num_phys_regions].base = base;
109 phys_regions[num_phys_regions].size = size;
110 num_phys_regions++;
111 }
112 unsigned long __init
113 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
114 unsigned long size)
115 {
116 unsigned long base;
117 int i;
118
119 for (base = begin / size * size; base < end; base += size) {
120 for (i = 0; i < num_phys_regions; i++) {
121 if (phys_regions[i].size &&
122 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
123 base + (size - 1) >= phys_regions[i].base)
124 break;
125 }
126 if (i == num_phys_regions)
127 return base;
128 }
129 return 0;
130 }
131 unsigned long __init
132 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
133 unsigned long *size)
134 {
135 unsigned long sz, base;
136 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
137 base = txboard_find_free_phys_region(begin, end, sz);
138 if (base) {
139 *size = sz;
140 return base;
141 }
142 }
143 return 0;
144 }
145 unsigned long __init
146 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
147 unsigned long size)
148 {
149 unsigned long base;
150 base = txboard_find_free_phys_region(begin, end, size);
151 if (base)
152 txboard_add_phys_region(base, size);
153 return base;
154 }
155 unsigned long __init
156 txboard_request_phys_region(unsigned long size)
157 {
158 unsigned long base;
159 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
160 base = txboard_find_free_phys_region(begin, end, size);
161 if (base)
162 txboard_add_phys_region(base, size);
163 return base;
164 }
165 unsigned long __init
166 txboard_request_phys_region_shrink(unsigned long *size)
167 {
168 unsigned long base;
169 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
170 base = txboard_find_free_phys_region_shrink(begin, end, size);
171 if (base)
172 txboard_add_phys_region(base, *size);
173 return base;
174 }
175
176 #ifdef CONFIG_PCI
177 void __init
178 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
179 struct pci_controller *channel,
180 unsigned long pci_io_base,
181 int extarb)
182 {
183 int i;
184
185 /* Disable All Initiator Space */
186 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
187 TX4938_PCIC_PCICCFG_G2PMEN(1)|
188 TX4938_PCIC_PCICCFG_G2PMEN(2)|
189 TX4938_PCIC_PCICCFG_G2PIOEN);
190
191 /* GB->PCI mappings */
192 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
193 pcicptr->g2piogbase = pci_io_base |
194 #ifdef __BIG_ENDIAN
195 TX4938_PCIC_G2PIOGBASE_ECHG
196 #else
197 TX4938_PCIC_G2PIOGBASE_BSDIS
198 #endif
199 ;
200 pcicptr->g2piopbase = 0;
201 for (i = 0; i < 3; i++) {
202 pcicptr->g2pmmask[i] = 0;
203 pcicptr->g2pmgbase[i] = 0;
204 pcicptr->g2pmpbase[i] = 0;
205 }
206 if (channel->mem_resource->end) {
207 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
208 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
209 #ifdef __BIG_ENDIAN
210 TX4938_PCIC_G2PMnGBASE_ECHG
211 #else
212 TX4938_PCIC_G2PMnGBASE_BSDIS
213 #endif
214 ;
215 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
216 }
217 /* PCI->GB mappings (I/O 256B) */
218 pcicptr->p2giopbase = 0; /* 256B */
219 pcicptr->p2giogbase = 0;
220 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
221 pcicptr->p2gm0plbase = 0;
222 pcicptr->p2gm0pubase = 0;
223 pcicptr->p2gmgbase[0] = 0 |
224 TX4938_PCIC_P2GMnGBASE_TMEMEN |
225 #ifdef __BIG_ENDIAN
226 TX4938_PCIC_P2GMnGBASE_TECHG
227 #else
228 TX4938_PCIC_P2GMnGBASE_TBSDIS
229 #endif
230 ;
231 /* PCI->GB mappings (MEM 16MB) */
232 pcicptr->p2gm1plbase = 0xffffffff;
233 pcicptr->p2gm1pubase = 0xffffffff;
234 pcicptr->p2gmgbase[1] = 0;
235 /* PCI->GB mappings (MEM 1MB) */
236 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
237 pcicptr->p2gmgbase[2] = 0;
238
239 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
240 /* Enable Initiator Memory Space */
241 if (channel->mem_resource->end)
242 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
243 /* Enable Initiator I/O Space */
244 if (channel->io_resource->end)
245 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
246 /* Enable Initiator Config */
247 pcicptr->pciccfg |=
248 TX4938_PCIC_PCICCFG_ICAEN |
249 TX4938_PCIC_PCICCFG_TCAR;
250
251 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
252 pcicptr->pcicfg1 = 0;
253
254 pcicptr->g2ptocnt &= ~0xffff;
255
256 if (tx4938_pcic_trdyto >= 0) {
257 pcicptr->g2ptocnt &= ~0xff;
258 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
259 }
260
261 if (tx4938_pcic_retryto >= 0) {
262 pcicptr->g2ptocnt &= ~0xff00;
263 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
264 }
265
266 /* Clear All Local Bus Status */
267 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
268 /* Enable All Local Bus Interrupts */
269 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
270 /* Clear All Initiator Status */
271 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
272 /* Enable All Initiator Interrupts */
273 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
274 /* Clear All PCI Status Error */
275 pcicptr->pcistatus =
276 (pcicptr->pcistatus & 0x0000ffff) |
277 (TX4938_PCIC_PCISTATUS_ALL << 16);
278 /* Enable All PCI Status Error Interrupts */
279 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
280
281 if (!extarb) {
282 /* Reset Bus Arbiter */
283 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
284 pcicptr->pbabm = 0;
285 /* Enable Bus Arbiter */
286 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
287 }
288
289 /* PCIC Int => IRC IRQ16 */
290 pcicptr->pcicfg2 =
291 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
292
293 pcicptr->pcistatus = PCI_COMMAND_MASTER |
294 PCI_COMMAND_MEMORY |
295 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
296 }
297
298 int __init
299 tx4938_report_pciclk(void)
300 {
301 unsigned long pcode = TX4938_REV_PCODE();
302 int pciclk = 0;
303 printk("TX%lx PCIC --%s PCICLK:",
304 pcode,
305 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
306 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
307
308 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
309 case TX4938_CCFG_PCIDIVMODE_4:
310 pciclk = txx9_cpu_clock / 4; break;
311 case TX4938_CCFG_PCIDIVMODE_4_5:
312 pciclk = txx9_cpu_clock * 2 / 9; break;
313 case TX4938_CCFG_PCIDIVMODE_5:
314 pciclk = txx9_cpu_clock / 5; break;
315 case TX4938_CCFG_PCIDIVMODE_5_5:
316 pciclk = txx9_cpu_clock * 2 / 11; break;
317 case TX4938_CCFG_PCIDIVMODE_8:
318 pciclk = txx9_cpu_clock / 8; break;
319 case TX4938_CCFG_PCIDIVMODE_9:
320 pciclk = txx9_cpu_clock / 9; break;
321 case TX4938_CCFG_PCIDIVMODE_10:
322 pciclk = txx9_cpu_clock / 10; break;
323 case TX4938_CCFG_PCIDIVMODE_11:
324 pciclk = txx9_cpu_clock / 11; break;
325 }
326 printk("Internal(%dMHz)", pciclk / 1000000);
327 } else {
328 printk("External");
329 pciclk = -1;
330 }
331 printk("\n");
332 return pciclk;
333 }
334
335 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
336 {
337 pcicptrs[ch] = pcicptr;
338 }
339
340 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
341 {
342 return pcicptrs[ch];
343 }
344
345 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
346 int top_bus, int busnr, int devfn)
347 {
348 static struct pci_dev dev;
349 static struct pci_bus bus;
350
351 dev.sysdata = bus.sysdata = hose;
352 dev.devfn = devfn;
353 bus.number = busnr;
354 bus.ops = hose->pci_ops;
355 bus.parent = NULL;
356 dev.bus = &bus;
357
358 return &dev;
359 }
360
361 #define EARLY_PCI_OP(rw, size, type) \
362 static int early_##rw##_config_##size(struct pci_controller *hose, \
363 int top_bus, int bus, int devfn, int offset, type value) \
364 { \
365 return pci_##rw##_config_##size( \
366 fake_pci_dev(hose, top_bus, bus, devfn), \
367 offset, value); \
368 }
369
370 EARLY_PCI_OP(read, word, u16 *)
371
372 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
373 {
374 u32 pci_devfn;
375 unsigned short vid;
376 int devfn_start = 0;
377 int devfn_stop = 0xff;
378 int cap66 = -1;
379 u16 stat;
380
381 printk("PCI: Checking 66MHz capabilities...\n");
382
383 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
384 if (early_read_config_word(hose, top_bus, current_bus,
385 pci_devfn, PCI_VENDOR_ID,
386 &vid) != PCIBIOS_SUCCESSFUL)
387 continue;
388
389 if (vid == 0xffff) continue;
390
391 /* check 66MHz capability */
392 if (cap66 < 0)
393 cap66 = 1;
394 if (cap66) {
395 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
396 PCI_STATUS, &stat);
397 if (!(stat & PCI_STATUS_66MHZ)) {
398 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
399 current_bus, pci_devfn);
400 cap66 = 0;
401 break;
402 }
403 }
404 }
405 return cap66 > 0;
406 }
407
408 int __init
409 tx4938_pciclk66_setup(void)
410 {
411 int pciclk;
412
413 /* Assert M66EN */
414 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
415 /* Double PCICLK (if possible) */
416 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
417 unsigned int pcidivmode =
418 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
419 switch (pcidivmode) {
420 case TX4938_CCFG_PCIDIVMODE_8:
421 case TX4938_CCFG_PCIDIVMODE_4:
422 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
423 pciclk = txx9_cpu_clock / 4;
424 break;
425 case TX4938_CCFG_PCIDIVMODE_9:
426 case TX4938_CCFG_PCIDIVMODE_4_5:
427 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
428 pciclk = txx9_cpu_clock * 2 / 9;
429 break;
430 case TX4938_CCFG_PCIDIVMODE_10:
431 case TX4938_CCFG_PCIDIVMODE_5:
432 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
433 pciclk = txx9_cpu_clock / 5;
434 break;
435 case TX4938_CCFG_PCIDIVMODE_11:
436 case TX4938_CCFG_PCIDIVMODE_5_5:
437 default:
438 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
439 pciclk = txx9_cpu_clock * 2 / 11;
440 break;
441 }
442 tx4938_ccfgptr->ccfg =
443 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
444 | pcidivmode;
445 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
446 (unsigned long)tx4938_ccfgptr->ccfg);
447 } else {
448 pciclk = -1;
449 }
450 return pciclk;
451 }
452
453 extern struct pci_controller tx4938_pci_controller[];
454 static int __init tx4938_pcibios_init(void)
455 {
456 unsigned long mem_base[2];
457 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
458 unsigned long io_base[2];
459 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
460 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
461 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
462
463 PCIBIOS_MIN_IO = 0x00001000UL;
464
465 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
466 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
467
468 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
469 (unsigned short)(tx4938_pcicptr->pciid >> 16),
470 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
471 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
472 extarb ? "External" : "Internal");
473
474 /* setup PCI area */
475 tx4938_pci_controller[0].io_resource->start = io_base[0];
476 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
477 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
478 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
479
480 set_tx4938_pcicptr(0, tx4938_pcicptr);
481
482 register_pci_controller(&tx4938_pci_controller[0]);
483
484 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
485 printk("TX4938_CCFG_PCI66 already configured\n");
486 txboard_pci66_mode = -1; /* already configured */
487 }
488
489 /* Reset PCI Bus */
490 *rbtx4938_pcireset_ptr = 0;
491 /* Reset PCIC */
492 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
493 if (txboard_pci66_mode > 0)
494 tx4938_pciclk66_setup();
495 mdelay(10);
496 /* clear PCIC reset */
497 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
498 *rbtx4938_pcireset_ptr = 1;
499 wbflush();
500 tx4938_report_pcic_status1(tx4938_pcicptr);
501
502 tx4938_report_pciclk();
503 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
504 if (txboard_pci66_mode == 0 &&
505 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
506 /* Reset PCI Bus */
507 *rbtx4938_pcireset_ptr = 0;
508 /* Reset PCIC */
509 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
510 tx4938_pciclk66_setup();
511 mdelay(10);
512 /* clear PCIC reset */
513 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
514 *rbtx4938_pcireset_ptr = 1;
515 wbflush();
516 /* Reinitialize PCIC */
517 tx4938_report_pciclk();
518 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
519 }
520
521 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
522 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
523 /* Reset PCIC1 */
524 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
525 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
526 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
527 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
528 else
529 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
530 mdelay(10);
531 /* clear PCIC1 reset */
532 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
533 tx4938_report_pcic_status1(tx4938_pcic1ptr);
534
535 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
536 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
537 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
538 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
539 printk("%s PCICLK:%dMHz\n",
540 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
541 txx9_gbus_clock /
542 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
543 1000000);
544
545 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
546 tx4938_pci_controller[1].io_resource->start =
547 io_base[1] - io_base[0];
548 tx4938_pci_controller[1].io_resource->end =
549 io_base[1] - io_base[0] + io_size[1] - 1;
550 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
551 tx4938_pci_controller[1].mem_resource->end =
552 mem_base[1] + mem_size[1] - 1;
553 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
554
555 register_pci_controller(&tx4938_pci_controller[1]);
556
557 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
558
559 /* map ioport 0 to PCI I/O space address 0 */
560 set_io_port_base(KSEG1 + io_base[0]);
561
562 return 0;
563 }
564
565 arch_initcall(tx4938_pcibios_init);
566
567 #endif /* CONFIG_PCI */
568
569 /* SPI support */
570
571 /* chip select for SPI devices */
572 #define SEEPROM1_CS 7 /* PIO7 */
573 #define SEEPROM2_CS 0 /* IOC */
574 #define SEEPROM3_CS 1 /* IOC */
575 #define SRTC_CS 2 /* IOC */
576
577 #ifdef CONFIG_PCI
578 static int __init rbtx4938_ethaddr_init(void)
579 {
580 unsigned char dat[17];
581 unsigned char sum;
582 int i;
583
584 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
585 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
586 printk(KERN_ERR "seeprom: read error.\n");
587 return -ENODEV;
588 } else {
589 if (strcmp(dat, "MAC") != 0)
590 printk(KERN_WARNING "seeprom: bad signature.\n");
591 for (i = 0, sum = 0; i < sizeof(dat); i++)
592 sum += dat[i];
593 if (sum)
594 printk(KERN_WARNING "seeprom: bad checksum.\n");
595 }
596 for (i = 0; i < 2; i++) {
597 unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
598 unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
599 struct platform_device *pdev;
600 if (!(tx4938_ccfgptr->pcfg &
601 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
602 continue;
603 pdev = platform_device_alloc("tc35815-mac", id);
604 if (!pdev ||
605 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
606 platform_device_add(pdev))
607 platform_device_put(pdev);
608 }
609 return 0;
610 }
611 device_initcall(rbtx4938_ethaddr_init);
612 #endif /* CONFIG_PCI */
613
614 static void __init rbtx4938_spi_setup(void)
615 {
616 /* set SPI_SEL */
617 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
618 /* chip selects for SPI devices */
619 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
620 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
621 }
622
623 static struct resource rbtx4938_fpga_resource;
624
625 static char pcode_str[8];
626 static struct resource tx4938_reg_resource = {
627 .start = TX4938_REG_BASE,
628 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
629 .name = pcode_str,
630 .flags = IORESOURCE_MEM
631 };
632
633 void __init tx4938_board_setup(void)
634 {
635 int i;
636 unsigned long divmode;
637 int cpuclk = 0;
638 unsigned long pcode = TX4938_REV_PCODE();
639
640 ioport_resource.start = 0x1000;
641 ioport_resource.end = 0xffffffff;
642 iomem_resource.start = 0x1000;
643 iomem_resource.end = 0xffffffff; /* expand to 4GB */
644
645 sprintf(pcode_str, "TX%lx", pcode);
646 /* SDRAMC,EBUSC are configured by PROM */
647 for (i = 0; i < 8; i++) {
648 if (!(tx4938_ebuscptr->cr[i] & 0x8))
649 continue; /* disabled */
650 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
651 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
652 }
653
654 /* clocks */
655 if (txx9_master_clock) {
656 /* calculate gbus_clock and cpu_clock_freq from master_clock */
657 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
658 switch (divmode) {
659 case TX4938_CCFG_DIVMODE_8:
660 case TX4938_CCFG_DIVMODE_10:
661 case TX4938_CCFG_DIVMODE_12:
662 case TX4938_CCFG_DIVMODE_16:
663 case TX4938_CCFG_DIVMODE_18:
664 txx9_gbus_clock = txx9_master_clock * 4; break;
665 default:
666 txx9_gbus_clock = txx9_master_clock;
667 }
668 switch (divmode) {
669 case TX4938_CCFG_DIVMODE_2:
670 case TX4938_CCFG_DIVMODE_8:
671 cpuclk = txx9_gbus_clock * 2; break;
672 case TX4938_CCFG_DIVMODE_2_5:
673 case TX4938_CCFG_DIVMODE_10:
674 cpuclk = txx9_gbus_clock * 5 / 2; break;
675 case TX4938_CCFG_DIVMODE_3:
676 case TX4938_CCFG_DIVMODE_12:
677 cpuclk = txx9_gbus_clock * 3; break;
678 case TX4938_CCFG_DIVMODE_4:
679 case TX4938_CCFG_DIVMODE_16:
680 cpuclk = txx9_gbus_clock * 4; break;
681 case TX4938_CCFG_DIVMODE_4_5:
682 case TX4938_CCFG_DIVMODE_18:
683 cpuclk = txx9_gbus_clock * 9 / 2; break;
684 }
685 txx9_cpu_clock = cpuclk;
686 } else {
687 if (txx9_cpu_clock == 0) {
688 txx9_cpu_clock = 300000000; /* 300MHz */
689 }
690 /* calculate gbus_clock and master_clock from cpu_clock_freq */
691 cpuclk = txx9_cpu_clock;
692 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
693 switch (divmode) {
694 case TX4938_CCFG_DIVMODE_2:
695 case TX4938_CCFG_DIVMODE_8:
696 txx9_gbus_clock = cpuclk / 2; break;
697 case TX4938_CCFG_DIVMODE_2_5:
698 case TX4938_CCFG_DIVMODE_10:
699 txx9_gbus_clock = cpuclk * 2 / 5; break;
700 case TX4938_CCFG_DIVMODE_3:
701 case TX4938_CCFG_DIVMODE_12:
702 txx9_gbus_clock = cpuclk / 3; break;
703 case TX4938_CCFG_DIVMODE_4:
704 case TX4938_CCFG_DIVMODE_16:
705 txx9_gbus_clock = cpuclk / 4; break;
706 case TX4938_CCFG_DIVMODE_4_5:
707 case TX4938_CCFG_DIVMODE_18:
708 txx9_gbus_clock = cpuclk * 2 / 9; break;
709 }
710 switch (divmode) {
711 case TX4938_CCFG_DIVMODE_8:
712 case TX4938_CCFG_DIVMODE_10:
713 case TX4938_CCFG_DIVMODE_12:
714 case TX4938_CCFG_DIVMODE_16:
715 case TX4938_CCFG_DIVMODE_18:
716 txx9_master_clock = txx9_gbus_clock / 4; break;
717 default:
718 txx9_master_clock = txx9_gbus_clock;
719 }
720 }
721 /* change default value to udelay/mdelay take reasonable time */
722 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
723
724 /* CCFG */
725 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
726 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
727 /* clear PCIC1 reset */
728 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
729 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
730
731 /* enable Timeout BusError */
732 if (tx4938_ccfg_toeon)
733 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
734
735 /* DMA selection */
736 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
737
738 /* Use external clock for external arbiter */
739 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
740 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
741
742 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
743 pcode_str,
744 cpuclk / 1000000, txx9_master_clock / 1000000,
745 (unsigned long)tx4938_ccfgptr->crir,
746 tx4938_ccfgptr->ccfg,
747 tx4938_ccfgptr->pcfg);
748
749 printk("%s SDRAMC --", pcode_str);
750 for (i = 0; i < 4; i++) {
751 unsigned long long cr = tx4938_sdramcptr->cr[i];
752 unsigned long ram_base, ram_size;
753 if (!((unsigned long)cr & 0x00000400))
754 continue; /* disabled */
755 ram_base = (unsigned long)(cr >> 49) << 21;
756 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
757 if (ram_base >= 0x20000000)
758 continue; /* high memory (ignore) */
759 printk(" CR%d:%016Lx", i, cr);
760 txboard_add_phys_region(ram_base, ram_size);
761 }
762 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
763
764 /* SRAM */
765 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
766 unsigned int size = 0x800;
767 unsigned long base =
768 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
769 txboard_add_phys_region(base, size);
770 }
771
772 /* TMR */
773 for (i = 0; i < TX4938_NR_TMR; i++)
774 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
775
776 /* enable DMA */
777 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
778 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
779
780 /* PIO */
781 tx4938_pioptr->maskcpu = 0;
782 tx4938_pioptr->maskext = 0;
783
784 /* TX4938 internal registers */
785 if (request_resource(&iomem_resource, &tx4938_reg_resource))
786 printk("request resource for internal registers failed\n");
787 }
788
789 #ifdef CONFIG_PCI
790 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
791 {
792 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
793 unsigned long g2pstatus = pcicptr->g2pstatus;
794 unsigned long pcicstatus = pcicptr->pcicstatus;
795 static struct {
796 unsigned long flag;
797 const char *str;
798 } pcistat_tbl[] = {
799 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
800 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
801 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
802 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
803 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
804 { PCI_STATUS_PARITY, "MasterParityError" },
805 }, g2pstat_tbl[] = {
806 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
807 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
808 }, pcicstat_tbl[] = {
809 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
810 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
811 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
812 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
813 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
814 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
815 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
816 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
817 };
818 int i;
819
820 printk("pcistat:%04x(", pcistatus);
821 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
822 if (pcistatus & pcistat_tbl[i].flag)
823 printk("%s ", pcistat_tbl[i].str);
824 printk("), g2pstatus:%08lx(", g2pstatus);
825 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
826 if (g2pstatus & g2pstat_tbl[i].flag)
827 printk("%s ", g2pstat_tbl[i].str);
828 printk("), pcicstatus:%08lx(", pcicstatus);
829 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
830 if (pcicstatus & pcicstat_tbl[i].flag)
831 printk("%s ", pcicstat_tbl[i].str);
832 printk(")\n");
833 }
834
835 void tx4938_report_pcic_status(void)
836 {
837 int i;
838 struct tx4938_pcic_reg *pcicptr;
839 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
840 tx4938_report_pcic_status1(pcicptr);
841 }
842
843 #endif /* CONFIG_PCI */
844
845 void __init plat_time_init(void)
846 {
847 mips_hpt_frequency = txx9_cpu_clock / 2;
848 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
849 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
850 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
851 txx9_gbus_clock / 2);
852 }
853
854 void __init plat_mem_setup(void)
855 {
856 unsigned long long pcfg;
857 char *argptr;
858
859 iomem_resource.end = 0xffffffff; /* 4GB */
860
861 if (txx9_master_clock == 0)
862 txx9_master_clock = 25000000; /* 25MHz */
863 tx4938_board_setup();
864 /* setup serial stuff */
865 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
866 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
867
868 #ifndef CONFIG_PCI
869 set_io_port_base(RBTX4938_ETHER_BASE);
870 #endif
871
872 #ifdef CONFIG_SERIAL_TXX9
873 {
874 extern int early_serial_txx9_setup(struct uart_port *port);
875 int i;
876 struct uart_port req;
877 for(i = 0; i < 2; i++) {
878 memset(&req, 0, sizeof(req));
879 req.line = i;
880 req.iotype = UPIO_MEM;
881 req.membase = (char *)(0xff1ff300 + i * 0x100);
882 req.mapbase = 0xff1ff300 + i * 0x100;
883 req.irq = RBTX4938_IRQ_IRC_SIO(i);
884 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
885 req.uartclk = 50000000;
886 early_serial_txx9_setup(&req);
887 }
888 }
889 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
890 argptr = prom_getcmdline();
891 if (strstr(argptr, "console=") == NULL) {
892 strcat(argptr, " console=ttyS0,38400");
893 }
894 #endif
895 #endif
896
897 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
898 printk("PIOSEL: disabling both ata and nand selection\n");
899 local_irq_disable();
900 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
901 #endif
902
903 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
904 printk("PIOSEL: enabling nand selection\n");
905 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
906 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
907 #endif
908
909 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
910 printk("PIOSEL: enabling ata selection\n");
911 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
912 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
913 #endif
914
915 #ifdef CONFIG_IP_PNP
916 argptr = prom_getcmdline();
917 if (strstr(argptr, "ip=") == NULL) {
918 strcat(argptr, " ip=any");
919 }
920 #endif
921
922
923 #ifdef CONFIG_FB
924 {
925 conswitchp = &dummy_con;
926 }
927 #endif
928
929 rbtx4938_spi_setup();
930 pcfg = tx4938_ccfgptr->pcfg; /* updated */
931 /* fixup piosel */
932 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
933 TX4938_PCFG_ATA_SEL) {
934 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
935 }
936 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
937 TX4938_PCFG_NDF_SEL) {
938 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
939 }
940 else {
941 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
942 }
943
944 rbtx4938_fpga_resource.name = "FPGA Registers";
945 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
946 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
947 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
948 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
949 printk("request resource for fpga failed\n");
950
951 /* disable all OnBoard I/O interrupts */
952 *rbtx4938_imask_ptr = 0;
953
954 _machine_restart = rbtx4938_machine_restart;
955 _machine_halt = rbtx4938_machine_halt;
956 pm_power_off = rbtx4938_machine_power_off;
957
958 *rbtx4938_led_ptr = 0xff;
959 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
960 printk(" DIPSW:%02x,%02x\n",
961 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
962 }
963
964 static int __init rbtx4938_ne_init(void)
965 {
966 struct resource res[] = {
967 {
968 .start = RBTX4938_RTL_8019_BASE,
969 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
970 .flags = IORESOURCE_IO,
971 }, {
972 .start = RBTX4938_RTL_8019_IRQ,
973 .flags = IORESOURCE_IRQ,
974 }
975 };
976 struct platform_device *dev =
977 platform_device_register_simple("ne", -1,
978 res, ARRAY_SIZE(res));
979 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
980 }
981 device_initcall(rbtx4938_ne_init);
982
983 /* GPIO support */
984
985 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
986
987 static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
988 {
989 u8 val;
990 unsigned long flags;
991 gpio -= 16;
992 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
993 val = *rbtx4938_spics_ptr;
994 if (value)
995 val |= 1 << gpio;
996 else
997 val &= ~(1 << gpio);
998 *rbtx4938_spics_ptr = val;
999 mmiowb();
1000 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1001 }
1002
1003 static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1004 {
1005 rbtx4938_spi_gpio_set(gpio, value);
1006 return 0;
1007 }
1008
1009 static DEFINE_SPINLOCK(tx4938_gpio_lock);
1010
1011 static int tx4938_gpio_get(unsigned gpio)
1012 {
1013 return tx4938_pioptr->din & (1 << gpio);
1014 }
1015
1016 static void tx4938_gpio_set_raw(unsigned gpio, int value)
1017 {
1018 u32 val;
1019 val = tx4938_pioptr->dout;
1020 if (value)
1021 val |= 1 << gpio;
1022 else
1023 val &= ~(1 << gpio);
1024 tx4938_pioptr->dout = val;
1025 }
1026
1027 static void tx4938_gpio_set(unsigned gpio, int value)
1028 {
1029 unsigned long flags;
1030 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1031 tx4938_gpio_set_raw(gpio, value);
1032 mmiowb();
1033 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1034 }
1035
1036 static int tx4938_gpio_dir_in(unsigned gpio)
1037 {
1038 spin_lock_irq(&tx4938_gpio_lock);
1039 tx4938_pioptr->dir &= ~(1 << gpio);
1040 mmiowb();
1041 spin_unlock_irq(&tx4938_gpio_lock);
1042 return 0;
1043 }
1044
1045 static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1046 {
1047 spin_lock_irq(&tx4938_gpio_lock);
1048 tx4938_gpio_set_raw(gpio, value);
1049 tx4938_pioptr->dir |= 1 << gpio;
1050 mmiowb();
1051 spin_unlock_irq(&tx4938_gpio_lock);
1052 return 0;
1053 }
1054
1055 int gpio_direction_input(unsigned gpio)
1056 {
1057 if (gpio < 16)
1058 return tx4938_gpio_dir_in(gpio);
1059 return -EINVAL;
1060 }
1061
1062 int gpio_direction_output(unsigned gpio, int value)
1063 {
1064 if (gpio < 16)
1065 return tx4938_gpio_dir_out(gpio, value);
1066 if (gpio < 16 + 3)
1067 return rbtx4938_spi_gpio_dir_out(gpio, value);
1068 return -EINVAL;
1069 }
1070
1071 int gpio_get_value(unsigned gpio)
1072 {
1073 if (gpio < 16)
1074 return tx4938_gpio_get(gpio);
1075 return 0;
1076 }
1077
1078 void gpio_set_value(unsigned gpio, int value)
1079 {
1080 if (gpio < 16)
1081 tx4938_gpio_set(gpio, value);
1082 else
1083 rbtx4938_spi_gpio_set(gpio, value);
1084 }
1085
1086 /* SPI support */
1087
1088 static void __init txx9_spi_init(unsigned long base, int irq)
1089 {
1090 struct resource res[] = {
1091 {
1092 .start = base,
1093 .end = base + 0x20 - 1,
1094 .flags = IORESOURCE_MEM,
1095 .parent = &tx4938_reg_resource,
1096 }, {
1097 .start = irq,
1098 .flags = IORESOURCE_IRQ,
1099 },
1100 };
1101 platform_device_register_simple("spi_txx9", 0,
1102 res, ARRAY_SIZE(res));
1103 }
1104
1105 static int __init rbtx4938_spi_init(void)
1106 {
1107 struct spi_board_info srtc_info = {
1108 .modalias = "rtc-rs5c348",
1109 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1110 .bus_num = 0,
1111 .chip_select = 16 + SRTC_CS,
1112 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1113 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1114 };
1115 spi_register_board_info(&srtc_info, 1);
1116 spi_eeprom_register(SEEPROM1_CS);
1117 spi_eeprom_register(16 + SEEPROM2_CS);
1118 spi_eeprom_register(16 + SEEPROM3_CS);
1119 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1120 return 0;
1121 }
1122 arch_initcall(rbtx4938_spi_init);
1123
1124 /* Minimum CLK support */
1125
1126 struct clk *clk_get(struct device *dev, const char *id)
1127 {
1128 if (!strcmp(id, "spi-baseclk"))
1129 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1130 return ERR_PTR(-ENOENT);
1131 }
1132 EXPORT_SYMBOL(clk_get);
1133
1134 int clk_enable(struct clk *clk)
1135 {
1136 return 0;
1137 }
1138 EXPORT_SYMBOL(clk_enable);
1139
1140 void clk_disable(struct clk *clk)
1141 {
1142 }
1143 EXPORT_SYMBOL(clk_disable);
1144
1145 unsigned long clk_get_rate(struct clk *clk)
1146 {
1147 return (unsigned long)clk;
1148 }
1149 EXPORT_SYMBOL(clk_get_rate);
1150
1151 void clk_put(struct clk *clk)
1152 {
1153 }
1154 EXPORT_SYMBOL(clk_put);
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