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revert-mm-fix-blkdev-size-calculation-in-generic_write_checks
[linux-2.6/linux-trees-mm.git] / drivers / i2c / busses / i2c-amd8111.c
blob985d2d67cd720669609a8d33b06c445dbf7cbda0
1 /*
2 * SMBus 2.0 driver for AMD-8111 IO-Hub.
3 *
4 * Copyright (c) 2002 Vojtech Pavlik
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation version 2.
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/stddef.h>
15 #include <linux/ioport.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <linux/acpi.h>
20 #include <asm/io.h>
21
22 MODULE_LICENSE("GPL");
23 MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
24 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
25
26 struct amd_smbus {
27 struct pci_dev *dev;
28 struct i2c_adapter adapter;
29 int base;
30 int size;
31 };
32
33 static struct pci_driver amd8111_driver;
34
35 /*
36 * AMD PCI control registers definitions.
37 */
38
39 #define AMD_PCI_MISC 0x48
40
41 #define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */
42 #define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */
43 #define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */
44
45 /*
46 * ACPI 2.0 chapter 13 PCI interface definitions.
47 */
48
49 #define AMD_EC_DATA 0x00 /* data register */
50 #define AMD_EC_SC 0x04 /* status of controller */
51 #define AMD_EC_CMD 0x04 /* command register */
52 #define AMD_EC_ICR 0x08 /* interrupt control register */
53
54 #define AMD_EC_SC_SMI 0x04 /* smi event pending */
55 #define AMD_EC_SC_SCI 0x02 /* sci event pending */
56 #define AMD_EC_SC_BURST 0x01 /* burst mode enabled */
57 #define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */
58 #define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */
59 #define AMD_EC_SC_OBF 0x01 /* data ready for host */
60
61 #define AMD_EC_CMD_RD 0x80 /* read EC */
62 #define AMD_EC_CMD_WR 0x81 /* write EC */
63 #define AMD_EC_CMD_BE 0x82 /* enable burst mode */
64 #define AMD_EC_CMD_BD 0x83 /* disable burst mode */
65 #define AMD_EC_CMD_QR 0x84 /* query EC */
66
67 /*
68 * ACPI 2.0 chapter 13 access of registers of the EC
69 */
70
71 static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
72 {
73 int timeout = 500;
74
75 while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
76 udelay(1);
77
78 if (!timeout) {
79 dev_warn(&smbus->dev->dev,
80 "Timeout while waiting for IBF to clear\n");
81 return -1;
82 }
83
84 return 0;
85 }
86
87 static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
88 {
89 int timeout = 500;
90
91 while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
92 udelay(1);
93
94 if (!timeout) {
95 dev_warn(&smbus->dev->dev,
96 "Timeout while waiting for OBF to set\n");
97 return -1;
98 }
99
100 return 0;
101 }
102
103 static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
104 unsigned char *data)
105 {
106 if (amd_ec_wait_write(smbus))
107 return -1;
108 outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
109
110 if (amd_ec_wait_write(smbus))
111 return -1;
112 outb(address, smbus->base + AMD_EC_DATA);
113
114 if (amd_ec_wait_read(smbus))
115 return -1;
116 *data = inb(smbus->base + AMD_EC_DATA);
117
118 return 0;
119 }
120
121 static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
122 unsigned char data)
123 {
124 if (amd_ec_wait_write(smbus))
125 return -1;
126 outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
127
128 if (amd_ec_wait_write(smbus))
129 return -1;
130 outb(address, smbus->base + AMD_EC_DATA);
131
132 if (amd_ec_wait_write(smbus))
133 return -1;
134 outb(data, smbus->base + AMD_EC_DATA);
135
136 return 0;
137 }
138
139 /*
140 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
141 */
142
143 #define AMD_SMB_PRTCL 0x00 /* protocol, PEC */
144 #define AMD_SMB_STS 0x01 /* status */
145 #define AMD_SMB_ADDR 0x02 /* address */
146 #define AMD_SMB_CMD 0x03 /* command */
147 #define AMD_SMB_DATA 0x04 /* 32 data registers */
148 #define AMD_SMB_BCNT 0x24 /* number of data bytes */
149 #define AMD_SMB_ALRM_A 0x25 /* alarm address */
150 #define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */
151
152 #define AMD_SMB_STS_DONE 0x80
153 #define AMD_SMB_STS_ALRM 0x40
154 #define AMD_SMB_STS_RES 0x20
155 #define AMD_SMB_STS_STATUS 0x1f
156
157 #define AMD_SMB_STATUS_OK 0x00
158 #define AMD_SMB_STATUS_FAIL 0x07
159 #define AMD_SMB_STATUS_DNAK 0x10
160 #define AMD_SMB_STATUS_DERR 0x11
161 #define AMD_SMB_STATUS_CMD_DENY 0x12
162 #define AMD_SMB_STATUS_UNKNOWN 0x13
163 #define AMD_SMB_STATUS_ACC_DENY 0x17
164 #define AMD_SMB_STATUS_TIMEOUT 0x18
165 #define AMD_SMB_STATUS_NOTSUP 0x19
166 #define AMD_SMB_STATUS_BUSY 0x1A
167 #define AMD_SMB_STATUS_PEC 0x1F
168
169 #define AMD_SMB_PRTCL_WRITE 0x00
170 #define AMD_SMB_PRTCL_READ 0x01
171 #define AMD_SMB_PRTCL_QUICK 0x02
172 #define AMD_SMB_PRTCL_BYTE 0x04
173 #define AMD_SMB_PRTCL_BYTE_DATA 0x06
174 #define AMD_SMB_PRTCL_WORD_DATA 0x08
175 #define AMD_SMB_PRTCL_BLOCK_DATA 0x0a
176 #define AMD_SMB_PRTCL_PROC_CALL 0x0c
177 #define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
178 #define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a
179 #define AMD_SMB_PRTCL_PEC 0x80
180
181
182 static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
183 unsigned short flags, char read_write, u8 command, int size,
184 union i2c_smbus_data * data)
185 {
186 struct amd_smbus *smbus = adap->algo_data;
187 unsigned char protocol, len, pec, temp[2];
188 int i;
189
190 protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
191 : AMD_SMB_PRTCL_WRITE;
192 pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
193
194 switch (size) {
195 case I2C_SMBUS_QUICK:
196 protocol |= AMD_SMB_PRTCL_QUICK;
197 read_write = I2C_SMBUS_WRITE;
198 break;
199
200 case I2C_SMBUS_BYTE:
201 if (read_write == I2C_SMBUS_WRITE)
202 amd_ec_write(smbus, AMD_SMB_CMD, command);
203 protocol |= AMD_SMB_PRTCL_BYTE;
204 break;
205
206 case I2C_SMBUS_BYTE_DATA:
207 amd_ec_write(smbus, AMD_SMB_CMD, command);
208 if (read_write == I2C_SMBUS_WRITE)
209 amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
210 protocol |= AMD_SMB_PRTCL_BYTE_DATA;
211 break;
212
213 case I2C_SMBUS_WORD_DATA:
214 amd_ec_write(smbus, AMD_SMB_CMD, command);
215 if (read_write == I2C_SMBUS_WRITE) {
216 amd_ec_write(smbus, AMD_SMB_DATA,
217 data->word & 0xff);
218 amd_ec_write(smbus, AMD_SMB_DATA + 1,
219 data->word >> 8);
220 }
221 protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
222 break;
223
224 case I2C_SMBUS_BLOCK_DATA:
225 amd_ec_write(smbus, AMD_SMB_CMD, command);
226 if (read_write == I2C_SMBUS_WRITE) {
227 len = min_t(u8, data->block[0],
228 I2C_SMBUS_BLOCK_MAX);
229 amd_ec_write(smbus, AMD_SMB_BCNT, len);
230 for (i = 0; i < len; i++)
231 amd_ec_write(smbus, AMD_SMB_DATA + i,
232 data->block[i + 1]);
233 }
234 protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
235 break;
236
237 case I2C_SMBUS_I2C_BLOCK_DATA:
238 len = min_t(u8, data->block[0],
239 I2C_SMBUS_BLOCK_MAX);
240 amd_ec_write(smbus, AMD_SMB_CMD, command);
241 amd_ec_write(smbus, AMD_SMB_BCNT, len);
242 if (read_write == I2C_SMBUS_WRITE)
243 for (i = 0; i < len; i++)
244 amd_ec_write(smbus, AMD_SMB_DATA + i,
245 data->block[i + 1]);
246 protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
247 break;
248
249 case I2C_SMBUS_PROC_CALL:
250 amd_ec_write(smbus, AMD_SMB_CMD, command);
251 amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
252 amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
253 protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
254 read_write = I2C_SMBUS_READ;
255 break;
256
257 case I2C_SMBUS_BLOCK_PROC_CALL:
258 len = min_t(u8, data->block[0],
259 I2C_SMBUS_BLOCK_MAX - 1);
260 amd_ec_write(smbus, AMD_SMB_CMD, command);
261 amd_ec_write(smbus, AMD_SMB_BCNT, len);
262 for (i = 0; i < len; i++)
263 amd_ec_write(smbus, AMD_SMB_DATA + i,
264 data->block[i + 1]);
265 protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
266 read_write = I2C_SMBUS_READ;
267 break;
268
269 default:
270 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
271 return -1;
272 }
273
274 amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
275 amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
276
277 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
278
279 if (~temp[0] & AMD_SMB_STS_DONE) {
280 udelay(500);
281 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
282 }
283
284 if (~temp[0] & AMD_SMB_STS_DONE) {
285 msleep(1);
286 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
287 }
288
289 if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
290 return -1;
291
292 if (read_write == I2C_SMBUS_WRITE)
293 return 0;
294
295 switch (size) {
296 case I2C_SMBUS_BYTE:
297 case I2C_SMBUS_BYTE_DATA:
298 amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
299 break;
300
301 case I2C_SMBUS_WORD_DATA:
302 case I2C_SMBUS_PROC_CALL:
303 amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
304 amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
305 data->word = (temp[1] << 8) | temp[0];
306 break;
307
308 case I2C_SMBUS_BLOCK_DATA:
309 case I2C_SMBUS_BLOCK_PROC_CALL:
310 amd_ec_read(smbus, AMD_SMB_BCNT, &len);
311 len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
312 case I2C_SMBUS_I2C_BLOCK_DATA:
313 for (i = 0; i < len; i++)
314 amd_ec_read(smbus, AMD_SMB_DATA + i,
315 data->block + i + 1);
316 data->block[0] = len;
317 break;
318 }
319
320 return 0;
321 }
322
323
324 static u32 amd8111_func(struct i2c_adapter *adapter)
325 {
326 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
327 I2C_FUNC_SMBUS_BYTE_DATA |
328 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
329 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
330 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
331 }
332
333 static const struct i2c_algorithm smbus_algorithm = {
334 .smbus_xfer = amd8111_access,
335 .functionality = amd8111_func,
336 };
337
338
339 static struct pci_device_id amd8111_ids[] = {
340 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
341 { 0, }
342 };
343
344 MODULE_DEVICE_TABLE (pci, amd8111_ids);
345
346 static int __devinit amd8111_probe(struct pci_dev *dev,
347 const struct pci_device_id *id)
348 {
349 struct amd_smbus *smbus;
350 int error;
351
352 if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
353 return -ENODEV;
354
355 smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
356 if (!smbus)
357 return -ENOMEM;
358
359 smbus->dev = dev;
360 smbus->base = pci_resource_start(dev, 0);
361 smbus->size = pci_resource_len(dev, 0);
362
363 error = acpi_check_resource_conflict(&dev->resource[0]);
364 if (error)
365 goto out_kfree;
366
367 if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
368 error = -EBUSY;
369 goto out_kfree;
370 }
371
372 smbus->adapter.owner = THIS_MODULE;
373 snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
374 "SMBus2 AMD8111 adapter at %04x", smbus->base);
375 smbus->adapter.id = I2C_HW_SMBUS_AMD8111;
376 smbus->adapter.class = I2C_CLASS_HWMON;
377 smbus->adapter.algo = &smbus_algorithm;
378 smbus->adapter.algo_data = smbus;
379
380 /* set up the sysfs linkage to our parent device */
381 smbus->adapter.dev.parent = &dev->dev;
382
383 pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
384 error = i2c_add_adapter(&smbus->adapter);
385 if (error)
386 goto out_release_region;
387
388 pci_set_drvdata(dev, smbus);
389 return 0;
390
391 out_release_region:
392 release_region(smbus->base, smbus->size);
393 out_kfree:
394 kfree(smbus);
395 return error;
396 }
397
398 static void __devexit amd8111_remove(struct pci_dev *dev)
399 {
400 struct amd_smbus *smbus = pci_get_drvdata(dev);
401
402 i2c_del_adapter(&smbus->adapter);
403 release_region(smbus->base, smbus->size);
404 kfree(smbus);
405 }
406
407 static struct pci_driver amd8111_driver = {
408 .name = "amd8111_smbus2",
409 .id_table = amd8111_ids,
410 .probe = amd8111_probe,
411 .remove = __devexit_p(amd8111_remove),
412 };
413
414 static int __init i2c_amd8111_init(void)
415 {
416 return pci_register_driver(&amd8111_driver);
417 }
418
419 static void __exit i2c_amd8111_exit(void)
420 {
421 pci_unregister_driver(&amd8111_driver);
422 }
423
424 module_init(i2c_amd8111_init);
425 module_exit(i2c_amd8111_exit);
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