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agk-dm-dm-crypt-tidy-crypt_endio
[linux-2.6/linux-trees-mm.git] / drivers / i2c / busses / i2c-mv64xxx.c
blobbb7bf68a7fb66eb4fb648ba0d770d2bcbda38333
1 /*
2 * Driver for the i2c controller on the Marvell line of host bridges for MIPS
3 * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/mv643xx.h>
18 #include <linux/platform_device.h>
19
20 #include <asm/io.h>
21
22 /* Register defines */
23 #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
24 #define MV64XXX_I2C_REG_DATA 0x04
25 #define MV64XXX_I2C_REG_CONTROL 0x08
26 #define MV64XXX_I2C_REG_STATUS 0x0c
27 #define MV64XXX_I2C_REG_BAUD 0x0c
28 #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
29 #define MV64XXX_I2C_REG_SOFT_RESET 0x1c
30
31 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
32 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
33 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
34 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020
35 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
36 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
37
38 /* Ctlr status values */
39 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
40 #define MV64XXX_I2C_STATUS_MAST_START 0x08
41 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
42 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
43 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
44 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
45 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
46 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
47 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
48 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
49 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
50 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
51 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
52 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
53 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
54 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
55 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
56
57 /* Driver states */
58 enum {
59 MV64XXX_I2C_STATE_INVALID,
60 MV64XXX_I2C_STATE_IDLE,
61 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
62 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
63 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
64 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
65 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
66 };
67
68 /* Driver actions */
69 enum {
70 MV64XXX_I2C_ACTION_INVALID,
71 MV64XXX_I2C_ACTION_CONTINUE,
72 MV64XXX_I2C_ACTION_SEND_START,
73 MV64XXX_I2C_ACTION_SEND_ADDR_1,
74 MV64XXX_I2C_ACTION_SEND_ADDR_2,
75 MV64XXX_I2C_ACTION_SEND_DATA,
76 MV64XXX_I2C_ACTION_RCV_DATA,
77 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
78 MV64XXX_I2C_ACTION_SEND_STOP,
79 };
80
81 struct mv64xxx_i2c_data {
82 int irq;
83 u32 state;
84 u32 action;
85 u32 aborting;
86 u32 cntl_bits;
87 void __iomem *reg_base;
88 u32 reg_base_p;
89 u32 addr1;
90 u32 addr2;
91 u32 bytes_left;
92 u32 byte_posn;
93 u32 block;
94 int rc;
95 u32 freq_m;
96 u32 freq_n;
97 wait_queue_head_t waitq;
98 spinlock_t lock;
99 struct i2c_msg *msg;
100 struct i2c_adapter adapter;
101 };
102
103 /*
104 *****************************************************************************
105 *
106 * Finite State Machine & Interrupt Routines
107 *
108 *****************************************************************************
109 */
110
111 /* Reset hardware and initialize FSM */
112 static void
113 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
114 {
115 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
116 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
117 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
118 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
119 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
120 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
121 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
122 drv_data->state = MV64XXX_I2C_STATE_IDLE;
123 }
124
125 static void
126 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
127 {
128 /*
129 * If state is idle, then this is likely the remnants of an old
130 * operation that driver has given up on or the user has killed.
131 * If so, issue the stop condition and go to idle.
132 */
133 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
134 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
135 return;
136 }
137
138 /* The status from the ctlr [mostly] tells us what to do next */
139 switch (status) {
140 /* Start condition interrupt */
141 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
142 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
143 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
144 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
145 break;
146
147 /* Performing a write */
148 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
149 if (drv_data->msg->flags & I2C_M_TEN) {
150 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
151 drv_data->state =
152 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
153 break;
154 }
155 /* FALLTHRU */
156 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
157 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
158 if ((drv_data->bytes_left == 0)
159 || (drv_data->aborting
160 && (drv_data->byte_posn != 0))) {
161 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
162 drv_data->state = MV64XXX_I2C_STATE_IDLE;
163 } else {
164 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
165 drv_data->state =
166 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
167 drv_data->bytes_left--;
168 }
169 break;
170
171 /* Performing a read */
172 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
173 if (drv_data->msg->flags & I2C_M_TEN) {
174 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
175 drv_data->state =
176 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
177 break;
178 }
179 /* FALLTHRU */
180 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
181 if (drv_data->bytes_left == 0) {
182 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
183 drv_data->state = MV64XXX_I2C_STATE_IDLE;
184 break;
185 }
186 /* FALLTHRU */
187 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
188 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
189 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
190 else {
191 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
192 drv_data->bytes_left--;
193 }
194 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
195
196 if ((drv_data->bytes_left == 1) || drv_data->aborting)
197 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
198 break;
199
200 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
201 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
202 drv_data->state = MV64XXX_I2C_STATE_IDLE;
203 break;
204
205 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
206 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
207 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
208 /* Doesn't seem to be a device at other end */
209 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
210 drv_data->state = MV64XXX_I2C_STATE_IDLE;
211 drv_data->rc = -ENODEV;
212 break;
213
214 default:
215 dev_err(&drv_data->adapter.dev,
216 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
217 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
218 drv_data->state, status, drv_data->msg->addr,
219 drv_data->msg->flags);
220 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
221 mv64xxx_i2c_hw_init(drv_data);
222 drv_data->rc = -EIO;
223 }
224 }
225
226 static void
227 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
228 {
229 switch(drv_data->action) {
230 case MV64XXX_I2C_ACTION_CONTINUE:
231 writel(drv_data->cntl_bits,
232 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
233 break;
234
235 case MV64XXX_I2C_ACTION_SEND_START:
236 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
237 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
238 break;
239
240 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
241 writel(drv_data->addr1,
242 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
243 writel(drv_data->cntl_bits,
244 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
245 break;
246
247 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
248 writel(drv_data->addr2,
249 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
250 writel(drv_data->cntl_bits,
251 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
252 break;
253
254 case MV64XXX_I2C_ACTION_SEND_DATA:
255 writel(drv_data->msg->buf[drv_data->byte_posn++],
256 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
257 writel(drv_data->cntl_bits,
258 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
259 break;
260
261 case MV64XXX_I2C_ACTION_RCV_DATA:
262 drv_data->msg->buf[drv_data->byte_posn++] =
263 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
264 writel(drv_data->cntl_bits,
265 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
266 break;
267
268 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
269 drv_data->msg->buf[drv_data->byte_posn++] =
270 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
271 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
272 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
273 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
274 drv_data->block = 0;
275 wake_up_interruptible(&drv_data->waitq);
276 break;
277
278 case MV64XXX_I2C_ACTION_INVALID:
279 default:
280 dev_err(&drv_data->adapter.dev,
281 "mv64xxx_i2c_do_action: Invalid action: %d\n",
282 drv_data->action);
283 drv_data->rc = -EIO;
284 /* FALLTHRU */
285 case MV64XXX_I2C_ACTION_SEND_STOP:
286 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
287 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
288 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
289 drv_data->block = 0;
290 wake_up_interruptible(&drv_data->waitq);
291 break;
292 }
293 }
294
295 static int
296 mv64xxx_i2c_intr(int irq, void *dev_id)
297 {
298 struct mv64xxx_i2c_data *drv_data = dev_id;
299 unsigned long flags;
300 u32 status;
301 int rc = IRQ_NONE;
302
303 spin_lock_irqsave(&drv_data->lock, flags);
304 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
305 MV64XXX_I2C_REG_CONTROL_IFLG) {
306 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
307 mv64xxx_i2c_fsm(drv_data, status);
308 mv64xxx_i2c_do_action(drv_data);
309 rc = IRQ_HANDLED;
310 }
311 spin_unlock_irqrestore(&drv_data->lock, flags);
312
313 return rc;
314 }
315
316 /*
317 *****************************************************************************
318 *
319 * I2C Msg Execution Routines
320 *
321 *****************************************************************************
322 */
323 static void
324 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
325 struct i2c_msg *msg)
326 {
327 u32 dir = 0;
328
329 drv_data->msg = msg;
330 drv_data->byte_posn = 0;
331 drv_data->bytes_left = msg->len;
332 drv_data->aborting = 0;
333 drv_data->rc = 0;
334 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
335 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
336
337 if (msg->flags & I2C_M_RD)
338 dir = 1;
339
340 if (msg->flags & I2C_M_REV_DIR_ADDR)
341 dir ^= 1;
342
343 if (msg->flags & I2C_M_TEN) {
344 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
345 drv_data->addr2 = (u32)msg->addr & 0xff;
346 } else {
347 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
348 drv_data->addr2 = 0;
349 }
350 }
351
352 static void
353 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
354 {
355 long time_left;
356 unsigned long flags;
357 char abort = 0;
358
359 time_left = wait_event_interruptible_timeout(drv_data->waitq,
360 !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
361
362 spin_lock_irqsave(&drv_data->lock, flags);
363 if (!time_left) { /* Timed out */
364 drv_data->rc = -ETIMEDOUT;
365 abort = 1;
366 } else if (time_left < 0) { /* Interrupted/Error */
367 drv_data->rc = time_left; /* errno value */
368 abort = 1;
369 }
370
371 if (abort && drv_data->block) {
372 drv_data->aborting = 1;
373 spin_unlock_irqrestore(&drv_data->lock, flags);
374
375 time_left = wait_event_timeout(drv_data->waitq,
376 !drv_data->block,
377 msecs_to_jiffies(drv_data->adapter.timeout));
378
379 if ((time_left <= 0) && drv_data->block) {
380 drv_data->state = MV64XXX_I2C_STATE_IDLE;
381 dev_err(&drv_data->adapter.dev,
382 "mv64xxx: I2C bus locked, block: %d, "
383 "time_left: %d\n", drv_data->block,
384 (int)time_left);
385 mv64xxx_i2c_hw_init(drv_data);
386 }
387 } else
388 spin_unlock_irqrestore(&drv_data->lock, flags);
389 }
390
391 static int
392 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
393 {
394 unsigned long flags;
395
396 spin_lock_irqsave(&drv_data->lock, flags);
397 mv64xxx_i2c_prepare_for_io(drv_data, msg);
398
399 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
400 if (drv_data->msg->flags & I2C_M_RD) {
401 /* No action to do, wait for slave to send a byte */
402 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
403 drv_data->state =
404 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
405 } else {
406 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
407 drv_data->state =
408 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
409 drv_data->bytes_left--;
410 }
411 } else {
412 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
413 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
414 }
415
416 drv_data->block = 1;
417 mv64xxx_i2c_do_action(drv_data);
418 spin_unlock_irqrestore(&drv_data->lock, flags);
419
420 mv64xxx_i2c_wait_for_completion(drv_data);
421 return drv_data->rc;
422 }
423
424 /*
425 *****************************************************************************
426 *
427 * I2C Core Support Routines (Interface to higher level I2C code)
428 *
429 *****************************************************************************
430 */
431 static u32
432 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
433 {
434 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
435 }
436
437 static int
438 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
439 {
440 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
441 int i, rc;
442
443 for (i=0; i<num; i++)
444 if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
445 return rc;
446
447 return num;
448 }
449
450 static const struct i2c_algorithm mv64xxx_i2c_algo = {
451 .master_xfer = mv64xxx_i2c_xfer,
452 .functionality = mv64xxx_i2c_functionality,
453 };
454
455 /*
456 *****************************************************************************
457 *
458 * Driver Interface & Early Init Routines
459 *
460 *****************************************************************************
461 */
462 static int __devinit
463 mv64xxx_i2c_map_regs(struct platform_device *pd,
464 struct mv64xxx_i2c_data *drv_data)
465 {
466 struct resource *r;
467
468 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
469 request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
470 drv_data->adapter.name)) {
471
472 drv_data->reg_base = ioremap(r->start,
473 MV64XXX_I2C_REG_BLOCK_SIZE);
474 drv_data->reg_base_p = r->start;
475 } else
476 return -ENOMEM;
477
478 return 0;
479 }
480
481 static void __devexit
482 mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
483 {
484 if (drv_data->reg_base) {
485 iounmap(drv_data->reg_base);
486 release_mem_region(drv_data->reg_base_p,
487 MV64XXX_I2C_REG_BLOCK_SIZE);
488 }
489
490 drv_data->reg_base = NULL;
491 drv_data->reg_base_p = 0;
492 }
493
494 static int __devinit
495 mv64xxx_i2c_probe(struct platform_device *pd)
496 {
497 struct mv64xxx_i2c_data *drv_data;
498 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
499 int rc;
500
501 if ((pd->id != 0) || !pdata)
502 return -ENODEV;
503
504 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
505 if (!drv_data)
506 return -ENOMEM;
507
508 if (mv64xxx_i2c_map_regs(pd, drv_data)) {
509 rc = -ENODEV;
510 goto exit_kfree;
511 }
512
513 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
514 sizeof(drv_data->adapter.name));
515
516 init_waitqueue_head(&drv_data->waitq);
517 spin_lock_init(&drv_data->lock);
518
519 drv_data->freq_m = pdata->freq_m;
520 drv_data->freq_n = pdata->freq_n;
521 drv_data->irq = platform_get_irq(pd, 0);
522 if (drv_data->irq < 0) {
523 rc = -ENXIO;
524 goto exit_unmap_regs;
525 }
526 drv_data->adapter.dev.parent = &pd->dev;
527 drv_data->adapter.id = I2C_HW_MV64XXX;
528 drv_data->adapter.algo = &mv64xxx_i2c_algo;
529 drv_data->adapter.owner = THIS_MODULE;
530 drv_data->adapter.class = I2C_CLASS_HWMON;
531 drv_data->adapter.timeout = pdata->timeout;
532 drv_data->adapter.retries = pdata->retries;
533 drv_data->adapter.nr = pd->id;
534 platform_set_drvdata(pd, drv_data);
535 i2c_set_adapdata(&drv_data->adapter, drv_data);
536
537 mv64xxx_i2c_hw_init(drv_data);
538
539 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
540 MV64XXX_I2C_CTLR_NAME, drv_data)) {
541 dev_err(&drv_data->adapter.dev,
542 "mv64xxx: Can't register intr handler irq: %d\n",
543 drv_data->irq);
544 rc = -EINVAL;
545 goto exit_unmap_regs;
546 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
547 dev_err(&drv_data->adapter.dev,
548 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
549 goto exit_free_irq;
550 }
551
552 return 0;
553
554 exit_free_irq:
555 free_irq(drv_data->irq, drv_data);
556 exit_unmap_regs:
557 mv64xxx_i2c_unmap_regs(drv_data);
558 exit_kfree:
559 kfree(drv_data);
560 return rc;
561 }
562
563 static int __devexit
564 mv64xxx_i2c_remove(struct platform_device *dev)
565 {
566 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
567 int rc;
568
569 rc = i2c_del_adapter(&drv_data->adapter);
570 free_irq(drv_data->irq, drv_data);
571 mv64xxx_i2c_unmap_regs(drv_data);
572 kfree(drv_data);
573
574 return rc;
575 }
576
577 static struct platform_driver mv64xxx_i2c_driver = {
578 .probe = mv64xxx_i2c_probe,
579 .remove = mv64xxx_i2c_remove,
580 .driver = {
581 .owner = THIS_MODULE,
582 .name = MV64XXX_I2C_CTLR_NAME,
583 },
584 };
585
586 static int __init
587 mv64xxx_i2c_init(void)
588 {
589 return platform_driver_register(&mv64xxx_i2c_driver);
590 }
591
592 static void __exit
593 mv64xxx_i2c_exit(void)
594 {
595 platform_driver_unregister(&mv64xxx_i2c_driver);
596 }
597
598 module_init(mv64xxx_i2c_init);
599 module_exit(mv64xxx_i2c_exit);
600
601 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
602 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
603 MODULE_LICENSE("GPL");
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