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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / cassini.c
blob646c86bcc545e08835cc07b07ca913b1ba64dbcc
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2 *
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19 * 02111-1307, USA.
20 *
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
23 *
24 * The cassini chip has a number of features that distinguish it from
25 * the gem chip:
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
33 *
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
37 * on them.
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
40 * to make them happy.
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
46 * the page.
47 *
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
50 *
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targeted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl.
57 *
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
64 * instead.
65 *
66 * by default, the selective clear mask is set up to process rx packets.
67 */
68
69 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/interrupt.h>
79 #include <linux/vmalloc.h>
80 #include <linux/ioport.h>
81 #include <linux/pci.h>
82 #include <linux/mm.h>
83 #include <linux/highmem.h>
84 #include <linux/list.h>
85 #include <linux/dma-mapping.h>
86
87 #include <linux/netdevice.h>
88 #include <linux/etherdevice.h>
89 #include <linux/skbuff.h>
90 #include <linux/ethtool.h>
91 #include <linux/crc32.h>
92 #include <linux/random.h>
93 #include <linux/mii.h>
94 #include <linux/ip.h>
95 #include <linux/tcp.h>
96 #include <linux/mutex.h>
97 #include <linux/firmware.h>
98
99 #include <net/checksum.h>
100
101 #include <linux/atomic.h>
102 #include <asm/system.h>
103 #include <asm/io.h>
104 #include <asm/byteorder.h>
105 #include <asm/uaccess.h>
106
107 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
108 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
109 #define CAS_NCPUS num_online_cpus()
110
111 #define cas_skb_release(x) netif_rx(x)
112
113 /* select which firmware to use */
114 #define USE_HP_WORKAROUND
115 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
116 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
117
118 #include "cassini.h"
119
120 #define USE_TX_COMPWB /* use completion writeback registers */
121 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
122 #define USE_RX_BLANK /* hw interrupt mitigation */
123 #undef USE_ENTROPY_DEV /* don't test for entropy device */
124
125 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
126 * also, we need to make cp->lock finer-grained.
127 */
128 #undef USE_PCI_INTB
129 #undef USE_PCI_INTC
130 #undef USE_PCI_INTD
131 #undef USE_QOS
132
133 #undef USE_VPD_DEBUG /* debug vpd information if defined */
134
135 /* rx processing options */
136 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
137 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
138 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
139 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
140 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
141
142 #define DRV_MODULE_NAME "cassini"
143 #define DRV_MODULE_VERSION "1.6"
144 #define DRV_MODULE_RELDATE "21 May 2008"
145
146 #define CAS_DEF_MSG_ENABLE \
147 (NETIF_MSG_DRV | \
148 NETIF_MSG_PROBE | \
149 NETIF_MSG_LINK | \
150 NETIF_MSG_TIMER | \
151 NETIF_MSG_IFDOWN | \
152 NETIF_MSG_IFUP | \
153 NETIF_MSG_RX_ERR | \
154 NETIF_MSG_TX_ERR)
155
156 /* length of time before we decide the hardware is borked,
157 * and dev->tx_timeout() should be called to fix the problem
158 */
159 #define CAS_TX_TIMEOUT (HZ)
160 #define CAS_LINK_TIMEOUT (22*HZ/10)
161 #define CAS_LINK_FAST_TIMEOUT (1)
162
163 /* timeout values for state changing. these specify the number
164 * of 10us delays to be used before giving up.
165 */
166 #define STOP_TRIES_PHY 1000
167 #define STOP_TRIES 5000
168
169 /* specify a minimum frame size to deal with some fifo issues
170 * max mtu == 2 * page size - ethernet header - 64 - swivel =
171 * 2 * page_size - 0x50
172 */
173 #define CAS_MIN_FRAME 97
174 #define CAS_1000MB_MIN_FRAME 255
175 #define CAS_MIN_MTU 60
176 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
177
178 #if 1
179 /*
180 * Eliminate these and use separate atomic counters for each, to
181 * avoid a race condition.
182 */
183 #else
184 #define CAS_RESET_MTU 1
185 #define CAS_RESET_ALL 2
186 #define CAS_RESET_SPARE 3
187 #endif
188
189 static char version[] __devinitdata =
190 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
191
192 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
193 static int link_mode;
194
195 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
196 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
197 MODULE_LICENSE("GPL");
198 MODULE_FIRMWARE("sun/cassini.bin");
199 module_param(cassini_debug, int, 0);
200 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
201 module_param(link_mode, int, 0);
202 MODULE_PARM_DESC(link_mode, "default link mode");
203
204 /*
205 * Work around for a PCS bug in which the link goes down due to the chip
206 * being confused and never showing a link status of "up."
207 */
208 #define DEFAULT_LINKDOWN_TIMEOUT 5
209 /*
210 * Value in seconds, for user input.
211 */
212 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
213 module_param(linkdown_timeout, int, 0);
214 MODULE_PARM_DESC(linkdown_timeout,
215 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
216
217 /*
218 * value in 'ticks' (units used by jiffies). Set when we init the
219 * module because 'HZ' in actually a function call on some flavors of
220 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
221 */
222 static int link_transition_timeout;
223
224
225
226 static u16 link_modes[] __devinitdata = {
227 BMCR_ANENABLE, /* 0 : autoneg */
228 0, /* 1 : 10bt half duplex */
229 BMCR_SPEED100, /* 2 : 100bt half duplex */
230 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
231 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
232 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
233 };
234
235 static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
236 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { 0, }
241 };
242
243 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
244
245 static void cas_set_link_modes(struct cas *cp);
246
247 static inline void cas_lock_tx(struct cas *cp)
248 {
249 int i;
250
251 for (i = 0; i < N_TX_RINGS; i++)
252 spin_lock(&cp->tx_lock[i]);
253 }
254
255 static inline void cas_lock_all(struct cas *cp)
256 {
257 spin_lock_irq(&cp->lock);
258 cas_lock_tx(cp);
259 }
260
261 /* WTZ: QA was finding deadlock problems with the previous
262 * versions after long test runs with multiple cards per machine.
263 * See if replacing cas_lock_all with safer versions helps. The
264 * symptoms QA is reporting match those we'd expect if interrupts
265 * aren't being properly restored, and we fixed a previous deadlock
266 * with similar symptoms by using save/restore versions in other
267 * places.
268 */
269 #define cas_lock_all_save(cp, flags) \
270 do { \
271 struct cas *xxxcp = (cp); \
272 spin_lock_irqsave(&xxxcp->lock, flags); \
273 cas_lock_tx(xxxcp); \
274 } while (0)
275
276 static inline void cas_unlock_tx(struct cas *cp)
277 {
278 int i;
279
280 for (i = N_TX_RINGS; i > 0; i--)
281 spin_unlock(&cp->tx_lock[i - 1]);
282 }
283
284 static inline void cas_unlock_all(struct cas *cp)
285 {
286 cas_unlock_tx(cp);
287 spin_unlock_irq(&cp->lock);
288 }
289
290 #define cas_unlock_all_restore(cp, flags) \
291 do { \
292 struct cas *xxxcp = (cp); \
293 cas_unlock_tx(xxxcp); \
294 spin_unlock_irqrestore(&xxxcp->lock, flags); \
295 } while (0)
296
297 static void cas_disable_irq(struct cas *cp, const int ring)
298 {
299 /* Make sure we won't get any more interrupts */
300 if (ring == 0) {
301 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
302 return;
303 }
304
305 /* disable completion interrupts and selectively mask */
306 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
307 switch (ring) {
308 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
309 #ifdef USE_PCI_INTB
310 case 1:
311 #endif
312 #ifdef USE_PCI_INTC
313 case 2:
314 #endif
315 #ifdef USE_PCI_INTD
316 case 3:
317 #endif
318 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
319 cp->regs + REG_PLUS_INTRN_MASK(ring));
320 break;
321 #endif
322 default:
323 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
324 REG_PLUS_INTRN_MASK(ring));
325 break;
326 }
327 }
328 }
329
330 static inline void cas_mask_intr(struct cas *cp)
331 {
332 int i;
333
334 for (i = 0; i < N_RX_COMP_RINGS; i++)
335 cas_disable_irq(cp, i);
336 }
337
338 static void cas_enable_irq(struct cas *cp, const int ring)
339 {
340 if (ring == 0) { /* all but TX_DONE */
341 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
342 return;
343 }
344
345 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
346 switch (ring) {
347 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
348 #ifdef USE_PCI_INTB
349 case 1:
350 #endif
351 #ifdef USE_PCI_INTC
352 case 2:
353 #endif
354 #ifdef USE_PCI_INTD
355 case 3:
356 #endif
357 writel(INTRN_MASK_RX_EN, cp->regs +
358 REG_PLUS_INTRN_MASK(ring));
359 break;
360 #endif
361 default:
362 break;
363 }
364 }
365 }
366
367 static inline void cas_unmask_intr(struct cas *cp)
368 {
369 int i;
370
371 for (i = 0; i < N_RX_COMP_RINGS; i++)
372 cas_enable_irq(cp, i);
373 }
374
375 static inline void cas_entropy_gather(struct cas *cp)
376 {
377 #ifdef USE_ENTROPY_DEV
378 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
379 return;
380
381 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
382 readl(cp->regs + REG_ENTROPY_IV),
383 sizeof(uint64_t)*8);
384 #endif
385 }
386
387 static inline void cas_entropy_reset(struct cas *cp)
388 {
389 #ifdef USE_ENTROPY_DEV
390 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
391 return;
392
393 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
394 cp->regs + REG_BIM_LOCAL_DEV_EN);
395 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
396 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
397
398 /* if we read back 0x0, we don't have an entropy device */
399 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
400 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
401 #endif
402 }
403
404 /* access to the phy. the following assumes that we've initialized the MIF to
405 * be in frame rather than bit-bang mode
406 */
407 static u16 cas_phy_read(struct cas *cp, int reg)
408 {
409 u32 cmd;
410 int limit = STOP_TRIES_PHY;
411
412 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
413 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
414 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
415 cmd |= MIF_FRAME_TURN_AROUND_MSB;
416 writel(cmd, cp->regs + REG_MIF_FRAME);
417
418 /* poll for completion */
419 while (limit-- > 0) {
420 udelay(10);
421 cmd = readl(cp->regs + REG_MIF_FRAME);
422 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
423 return cmd & MIF_FRAME_DATA_MASK;
424 }
425 return 0xFFFF; /* -1 */
426 }
427
428 static int cas_phy_write(struct cas *cp, int reg, u16 val)
429 {
430 int limit = STOP_TRIES_PHY;
431 u32 cmd;
432
433 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
434 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
435 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
436 cmd |= MIF_FRAME_TURN_AROUND_MSB;
437 cmd |= val & MIF_FRAME_DATA_MASK;
438 writel(cmd, cp->regs + REG_MIF_FRAME);
439
440 /* poll for completion */
441 while (limit-- > 0) {
442 udelay(10);
443 cmd = readl(cp->regs + REG_MIF_FRAME);
444 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
445 return 0;
446 }
447 return -1;
448 }
449
450 static void cas_phy_powerup(struct cas *cp)
451 {
452 u16 ctl = cas_phy_read(cp, MII_BMCR);
453
454 if ((ctl & BMCR_PDOWN) == 0)
455 return;
456 ctl &= ~BMCR_PDOWN;
457 cas_phy_write(cp, MII_BMCR, ctl);
458 }
459
460 static void cas_phy_powerdown(struct cas *cp)
461 {
462 u16 ctl = cas_phy_read(cp, MII_BMCR);
463
464 if (ctl & BMCR_PDOWN)
465 return;
466 ctl |= BMCR_PDOWN;
467 cas_phy_write(cp, MII_BMCR, ctl);
468 }
469
470 /* cp->lock held. note: the last put_page will free the buffer */
471 static int cas_page_free(struct cas *cp, cas_page_t *page)
472 {
473 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
474 PCI_DMA_FROMDEVICE);
475 __free_pages(page->buffer, cp->page_order);
476 kfree(page);
477 return 0;
478 }
479
480 #ifdef RX_COUNT_BUFFERS
481 #define RX_USED_ADD(x, y) ((x)->used += (y))
482 #define RX_USED_SET(x, y) ((x)->used = (y))
483 #else
484 #define RX_USED_ADD(x, y)
485 #define RX_USED_SET(x, y)
486 #endif
487
488 /* local page allocation routines for the receive buffers. jumbo pages
489 * require at least 8K contiguous and 8K aligned buffers.
490 */
491 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
492 {
493 cas_page_t *page;
494
495 page = kmalloc(sizeof(cas_page_t), flags);
496 if (!page)
497 return NULL;
498
499 INIT_LIST_HEAD(&page->list);
500 RX_USED_SET(page, 0);
501 page->buffer = alloc_pages(flags, cp->page_order);
502 if (!page->buffer)
503 goto page_err;
504 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
505 cp->page_size, PCI_DMA_FROMDEVICE);
506 return page;
507
508 page_err:
509 kfree(page);
510 return NULL;
511 }
512
513 /* initialize spare pool of rx buffers, but allocate during the open */
514 static void cas_spare_init(struct cas *cp)
515 {
516 spin_lock(&cp->rx_inuse_lock);
517 INIT_LIST_HEAD(&cp->rx_inuse_list);
518 spin_unlock(&cp->rx_inuse_lock);
519
520 spin_lock(&cp->rx_spare_lock);
521 INIT_LIST_HEAD(&cp->rx_spare_list);
522 cp->rx_spares_needed = RX_SPARE_COUNT;
523 spin_unlock(&cp->rx_spare_lock);
524 }
525
526 /* used on close. free all the spare buffers. */
527 static void cas_spare_free(struct cas *cp)
528 {
529 struct list_head list, *elem, *tmp;
530
531 /* free spare buffers */
532 INIT_LIST_HEAD(&list);
533 spin_lock(&cp->rx_spare_lock);
534 list_splice_init(&cp->rx_spare_list, &list);
535 spin_unlock(&cp->rx_spare_lock);
536 list_for_each_safe(elem, tmp, &list) {
537 cas_page_free(cp, list_entry(elem, cas_page_t, list));
538 }
539
540 INIT_LIST_HEAD(&list);
541 #if 1
542 /*
543 * Looks like Adrian had protected this with a different
544 * lock than used everywhere else to manipulate this list.
545 */
546 spin_lock(&cp->rx_inuse_lock);
547 list_splice_init(&cp->rx_inuse_list, &list);
548 spin_unlock(&cp->rx_inuse_lock);
549 #else
550 spin_lock(&cp->rx_spare_lock);
551 list_splice_init(&cp->rx_inuse_list, &list);
552 spin_unlock(&cp->rx_spare_lock);
553 #endif
554 list_for_each_safe(elem, tmp, &list) {
555 cas_page_free(cp, list_entry(elem, cas_page_t, list));
556 }
557 }
558
559 /* replenish spares if needed */
560 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
561 {
562 struct list_head list, *elem, *tmp;
563 int needed, i;
564
565 /* check inuse list. if we don't need any more free buffers,
566 * just free it
567 */
568
569 /* make a local copy of the list */
570 INIT_LIST_HEAD(&list);
571 spin_lock(&cp->rx_inuse_lock);
572 list_splice_init(&cp->rx_inuse_list, &list);
573 spin_unlock(&cp->rx_inuse_lock);
574
575 list_for_each_safe(elem, tmp, &list) {
576 cas_page_t *page = list_entry(elem, cas_page_t, list);
577
578 /*
579 * With the lockless pagecache, cassini buffering scheme gets
580 * slightly less accurate: we might find that a page has an
581 * elevated reference count here, due to a speculative ref,
582 * and skip it as in-use. Ideally we would be able to reclaim
583 * it. However this would be such a rare case, it doesn't
584 * matter too much as we should pick it up the next time round.
585 *
586 * Importantly, if we find that the page has a refcount of 1
587 * here (our refcount), then we know it is definitely not inuse
588 * so we can reuse it.
589 */
590 if (page_count(page->buffer) > 1)
591 continue;
592
593 list_del(elem);
594 spin_lock(&cp->rx_spare_lock);
595 if (cp->rx_spares_needed > 0) {
596 list_add(elem, &cp->rx_spare_list);
597 cp->rx_spares_needed--;
598 spin_unlock(&cp->rx_spare_lock);
599 } else {
600 spin_unlock(&cp->rx_spare_lock);
601 cas_page_free(cp, page);
602 }
603 }
604
605 /* put any inuse buffers back on the list */
606 if (!list_empty(&list)) {
607 spin_lock(&cp->rx_inuse_lock);
608 list_splice(&list, &cp->rx_inuse_list);
609 spin_unlock(&cp->rx_inuse_lock);
610 }
611
612 spin_lock(&cp->rx_spare_lock);
613 needed = cp->rx_spares_needed;
614 spin_unlock(&cp->rx_spare_lock);
615 if (!needed)
616 return;
617
618 /* we still need spares, so try to allocate some */
619 INIT_LIST_HEAD(&list);
620 i = 0;
621 while (i < needed) {
622 cas_page_t *spare = cas_page_alloc(cp, flags);
623 if (!spare)
624 break;
625 list_add(&spare->list, &list);
626 i++;
627 }
628
629 spin_lock(&cp->rx_spare_lock);
630 list_splice(&list, &cp->rx_spare_list);
631 cp->rx_spares_needed -= i;
632 spin_unlock(&cp->rx_spare_lock);
633 }
634
635 /* pull a page from the list. */
636 static cas_page_t *cas_page_dequeue(struct cas *cp)
637 {
638 struct list_head *entry;
639 int recover;
640
641 spin_lock(&cp->rx_spare_lock);
642 if (list_empty(&cp->rx_spare_list)) {
643 /* try to do a quick recovery */
644 spin_unlock(&cp->rx_spare_lock);
645 cas_spare_recover(cp, GFP_ATOMIC);
646 spin_lock(&cp->rx_spare_lock);
647 if (list_empty(&cp->rx_spare_list)) {
648 netif_err(cp, rx_err, cp->dev,
649 "no spare buffers available\n");
650 spin_unlock(&cp->rx_spare_lock);
651 return NULL;
652 }
653 }
654
655 entry = cp->rx_spare_list.next;
656 list_del(entry);
657 recover = ++cp->rx_spares_needed;
658 spin_unlock(&cp->rx_spare_lock);
659
660 /* trigger the timer to do the recovery */
661 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
662 #if 1
663 atomic_inc(&cp->reset_task_pending);
664 atomic_inc(&cp->reset_task_pending_spare);
665 schedule_work(&cp->reset_task);
666 #else
667 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
668 schedule_work(&cp->reset_task);
669 #endif
670 }
671 return list_entry(entry, cas_page_t, list);
672 }
673
674
675 static void cas_mif_poll(struct cas *cp, const int enable)
676 {
677 u32 cfg;
678
679 cfg = readl(cp->regs + REG_MIF_CFG);
680 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
681
682 if (cp->phy_type & CAS_PHY_MII_MDIO1)
683 cfg |= MIF_CFG_PHY_SELECT;
684
685 /* poll and interrupt on link status change. */
686 if (enable) {
687 cfg |= MIF_CFG_POLL_EN;
688 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
689 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
690 }
691 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
692 cp->regs + REG_MIF_MASK);
693 writel(cfg, cp->regs + REG_MIF_CFG);
694 }
695
696 /* Must be invoked under cp->lock */
697 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
698 {
699 u16 ctl;
700 #if 1
701 int lcntl;
702 int changed = 0;
703 int oldstate = cp->lstate;
704 int link_was_not_down = !(oldstate == link_down);
705 #endif
706 /* Setup link parameters */
707 if (!ep)
708 goto start_aneg;
709 lcntl = cp->link_cntl;
710 if (ep->autoneg == AUTONEG_ENABLE)
711 cp->link_cntl = BMCR_ANENABLE;
712 else {
713 u32 speed = ethtool_cmd_speed(ep);
714 cp->link_cntl = 0;
715 if (speed == SPEED_100)
716 cp->link_cntl |= BMCR_SPEED100;
717 else if (speed == SPEED_1000)
718 cp->link_cntl |= CAS_BMCR_SPEED1000;
719 if (ep->duplex == DUPLEX_FULL)
720 cp->link_cntl |= BMCR_FULLDPLX;
721 }
722 #if 1
723 changed = (lcntl != cp->link_cntl);
724 #endif
725 start_aneg:
726 if (cp->lstate == link_up) {
727 netdev_info(cp->dev, "PCS link down\n");
728 } else {
729 if (changed) {
730 netdev_info(cp->dev, "link configuration changed\n");
731 }
732 }
733 cp->lstate = link_down;
734 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
735 if (!cp->hw_running)
736 return;
737 #if 1
738 /*
739 * WTZ: If the old state was link_up, we turn off the carrier
740 * to replicate everything we do elsewhere on a link-down
741 * event when we were already in a link-up state..
742 */
743 if (oldstate == link_up)
744 netif_carrier_off(cp->dev);
745 if (changed && link_was_not_down) {
746 /*
747 * WTZ: This branch will simply schedule a full reset after
748 * we explicitly changed link modes in an ioctl. See if this
749 * fixes the link-problems we were having for forced mode.
750 */
751 atomic_inc(&cp->reset_task_pending);
752 atomic_inc(&cp->reset_task_pending_all);
753 schedule_work(&cp->reset_task);
754 cp->timer_ticks = 0;
755 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
756 return;
757 }
758 #endif
759 if (cp->phy_type & CAS_PHY_SERDES) {
760 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
761
762 if (cp->link_cntl & BMCR_ANENABLE) {
763 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
764 cp->lstate = link_aneg;
765 } else {
766 if (cp->link_cntl & BMCR_FULLDPLX)
767 val |= PCS_MII_CTRL_DUPLEX;
768 val &= ~PCS_MII_AUTONEG_EN;
769 cp->lstate = link_force_ok;
770 }
771 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
772 writel(val, cp->regs + REG_PCS_MII_CTRL);
773
774 } else {
775 cas_mif_poll(cp, 0);
776 ctl = cas_phy_read(cp, MII_BMCR);
777 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
778 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
779 ctl |= cp->link_cntl;
780 if (ctl & BMCR_ANENABLE) {
781 ctl |= BMCR_ANRESTART;
782 cp->lstate = link_aneg;
783 } else {
784 cp->lstate = link_force_ok;
785 }
786 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
787 cas_phy_write(cp, MII_BMCR, ctl);
788 cas_mif_poll(cp, 1);
789 }
790
791 cp->timer_ticks = 0;
792 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
793 }
794
795 /* Must be invoked under cp->lock. */
796 static int cas_reset_mii_phy(struct cas *cp)
797 {
798 int limit = STOP_TRIES_PHY;
799 u16 val;
800
801 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
802 udelay(100);
803 while (--limit) {
804 val = cas_phy_read(cp, MII_BMCR);
805 if ((val & BMCR_RESET) == 0)
806 break;
807 udelay(10);
808 }
809 return limit <= 0;
810 }
811
812 static int cas_saturn_firmware_init(struct cas *cp)
813 {
814 const struct firmware *fw;
815 const char fw_name[] = "sun/cassini.bin";
816 int err;
817
818 if (PHY_NS_DP83065 != cp->phy_id)
819 return 0;
820
821 err = request_firmware(&fw, fw_name, &cp->pdev->dev);
822 if (err) {
823 pr_err("Failed to load firmware \"%s\"\n",
824 fw_name);
825 return err;
826 }
827 if (fw->size < 2) {
828 pr_err("bogus length %zu in \"%s\"\n",
829 fw->size, fw_name);
830 err = -EINVAL;
831 goto out;
832 }
833 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
834 cp->fw_size = fw->size - 2;
835 cp->fw_data = vmalloc(cp->fw_size);
836 if (!cp->fw_data) {
837 err = -ENOMEM;
838 pr_err("\"%s\" Failed %d\n", fw_name, err);
839 goto out;
840 }
841 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
842 out:
843 release_firmware(fw);
844 return err;
845 }
846
847 static void cas_saturn_firmware_load(struct cas *cp)
848 {
849 int i;
850
851 cas_phy_powerdown(cp);
852
853 /* expanded memory access mode */
854 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
855
856 /* pointer configuration for new firmware */
857 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
858 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
859 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
860 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
861 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
862 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
863 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
864 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
865
866 /* download new firmware */
867 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
868 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
869 for (i = 0; i < cp->fw_size; i++)
870 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
871
872 /* enable firmware */
873 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
874 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
875 }
876
877
878 /* phy initialization */
879 static void cas_phy_init(struct cas *cp)
880 {
881 u16 val;
882
883 /* if we're in MII/GMII mode, set up phy */
884 if (CAS_PHY_MII(cp->phy_type)) {
885 writel(PCS_DATAPATH_MODE_MII,
886 cp->regs + REG_PCS_DATAPATH_MODE);
887
888 cas_mif_poll(cp, 0);
889 cas_reset_mii_phy(cp); /* take out of isolate mode */
890
891 if (PHY_LUCENT_B0 == cp->phy_id) {
892 /* workaround link up/down issue with lucent */
893 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
894 cas_phy_write(cp, MII_BMCR, 0x00f1);
895 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
896
897 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
898 /* workarounds for broadcom phy */
899 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
900 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
901 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
902 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
903 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
904 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
905 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
906 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
907 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
908 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
909 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
910
911 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
912 val = cas_phy_read(cp, BROADCOM_MII_REG4);
913 val = cas_phy_read(cp, BROADCOM_MII_REG4);
914 if (val & 0x0080) {
915 /* link workaround */
916 cas_phy_write(cp, BROADCOM_MII_REG4,
917 val & ~0x0080);
918 }
919
920 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
921 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
922 SATURN_PCFG_FSI : 0x0,
923 cp->regs + REG_SATURN_PCFG);
924
925 /* load firmware to address 10Mbps auto-negotiation
926 * issue. NOTE: this will need to be changed if the
927 * default firmware gets fixed.
928 */
929 if (PHY_NS_DP83065 == cp->phy_id) {
930 cas_saturn_firmware_load(cp);
931 }
932 cas_phy_powerup(cp);
933 }
934
935 /* advertise capabilities */
936 val = cas_phy_read(cp, MII_BMCR);
937 val &= ~BMCR_ANENABLE;
938 cas_phy_write(cp, MII_BMCR, val);
939 udelay(10);
940
941 cas_phy_write(cp, MII_ADVERTISE,
942 cas_phy_read(cp, MII_ADVERTISE) |
943 (ADVERTISE_10HALF | ADVERTISE_10FULL |
944 ADVERTISE_100HALF | ADVERTISE_100FULL |
945 CAS_ADVERTISE_PAUSE |
946 CAS_ADVERTISE_ASYM_PAUSE));
947
948 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
949 /* make sure that we don't advertise half
950 * duplex to avoid a chip issue
951 */
952 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
953 val &= ~CAS_ADVERTISE_1000HALF;
954 val |= CAS_ADVERTISE_1000FULL;
955 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
956 }
957
958 } else {
959 /* reset pcs for serdes */
960 u32 val;
961 int limit;
962
963 writel(PCS_DATAPATH_MODE_SERDES,
964 cp->regs + REG_PCS_DATAPATH_MODE);
965
966 /* enable serdes pins on saturn */
967 if (cp->cas_flags & CAS_FLAG_SATURN)
968 writel(0, cp->regs + REG_SATURN_PCFG);
969
970 /* Reset PCS unit. */
971 val = readl(cp->regs + REG_PCS_MII_CTRL);
972 val |= PCS_MII_RESET;
973 writel(val, cp->regs + REG_PCS_MII_CTRL);
974
975 limit = STOP_TRIES;
976 while (--limit > 0) {
977 udelay(10);
978 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
979 PCS_MII_RESET) == 0)
980 break;
981 }
982 if (limit <= 0)
983 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
984 readl(cp->regs + REG_PCS_STATE_MACHINE));
985
986 /* Make sure PCS is disabled while changing advertisement
987 * configuration.
988 */
989 writel(0x0, cp->regs + REG_PCS_CFG);
990
991 /* Advertise all capabilities except half-duplex. */
992 val = readl(cp->regs + REG_PCS_MII_ADVERT);
993 val &= ~PCS_MII_ADVERT_HD;
994 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
995 PCS_MII_ADVERT_ASYM_PAUSE);
996 writel(val, cp->regs + REG_PCS_MII_ADVERT);
997
998 /* enable PCS */
999 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
1000
1001 /* pcs workaround: enable sync detect */
1002 writel(PCS_SERDES_CTRL_SYNCD_EN,
1003 cp->regs + REG_PCS_SERDES_CTRL);
1004 }
1005 }
1006
1007
1008 static int cas_pcs_link_check(struct cas *cp)
1009 {
1010 u32 stat, state_machine;
1011 int retval = 0;
1012
1013 /* The link status bit latches on zero, so you must
1014 * read it twice in such a case to see a transition
1015 * to the link being up.
1016 */
1017 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1018 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1019 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1020
1021 /* The remote-fault indication is only valid
1022 * when autoneg has completed.
1023 */
1024 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1025 PCS_MII_STATUS_REMOTE_FAULT)) ==
1026 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1027 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1028
1029 /* work around link detection issue by querying the PCS state
1030 * machine directly.
1031 */
1032 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1033 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1034 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1035 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1036 stat |= PCS_MII_STATUS_LINK_STATUS;
1037 }
1038
1039 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1040 if (cp->lstate != link_up) {
1041 if (cp->opened) {
1042 cp->lstate = link_up;
1043 cp->link_transition = LINK_TRANSITION_LINK_UP;
1044
1045 cas_set_link_modes(cp);
1046 netif_carrier_on(cp->dev);
1047 }
1048 }
1049 } else if (cp->lstate == link_up) {
1050 cp->lstate = link_down;
1051 if (link_transition_timeout != 0 &&
1052 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1053 !cp->link_transition_jiffies_valid) {
1054 /*
1055 * force a reset, as a workaround for the
1056 * link-failure problem. May want to move this to a
1057 * point a bit earlier in the sequence. If we had
1058 * generated a reset a short time ago, we'll wait for
1059 * the link timer to check the status until a
1060 * timer expires (link_transistion_jiffies_valid is
1061 * true when the timer is running.) Instead of using
1062 * a system timer, we just do a check whenever the
1063 * link timer is running - this clears the flag after
1064 * a suitable delay.
1065 */
1066 retval = 1;
1067 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1068 cp->link_transition_jiffies = jiffies;
1069 cp->link_transition_jiffies_valid = 1;
1070 } else {
1071 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1072 }
1073 netif_carrier_off(cp->dev);
1074 if (cp->opened)
1075 netif_info(cp, link, cp->dev, "PCS link down\n");
1076
1077 /* Cassini only: if you force a mode, there can be
1078 * sync problems on link down. to fix that, the following
1079 * things need to be checked:
1080 * 1) read serialink state register
1081 * 2) read pcs status register to verify link down.
1082 * 3) if link down and serial link == 0x03, then you need
1083 * to global reset the chip.
1084 */
1085 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1086 /* should check to see if we're in a forced mode */
1087 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1088 if (stat == 0x03)
1089 return 1;
1090 }
1091 } else if (cp->lstate == link_down) {
1092 if (link_transition_timeout != 0 &&
1093 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1094 !cp->link_transition_jiffies_valid) {
1095 /* force a reset, as a workaround for the
1096 * link-failure problem. May want to move
1097 * this to a point a bit earlier in the
1098 * sequence.
1099 */
1100 retval = 1;
1101 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1102 cp->link_transition_jiffies = jiffies;
1103 cp->link_transition_jiffies_valid = 1;
1104 } else {
1105 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1106 }
1107 }
1108
1109 return retval;
1110 }
1111
1112 static int cas_pcs_interrupt(struct net_device *dev,
1113 struct cas *cp, u32 status)
1114 {
1115 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1116
1117 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1118 return 0;
1119 return cas_pcs_link_check(cp);
1120 }
1121
1122 static int cas_txmac_interrupt(struct net_device *dev,
1123 struct cas *cp, u32 status)
1124 {
1125 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1126
1127 if (!txmac_stat)
1128 return 0;
1129
1130 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1131 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1132
1133 /* Defer timer expiration is quite normal,
1134 * don't even log the event.
1135 */
1136 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1137 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1138 return 0;
1139
1140 spin_lock(&cp->stat_lock[0]);
1141 if (txmac_stat & MAC_TX_UNDERRUN) {
1142 netdev_err(dev, "TX MAC xmit underrun\n");
1143 cp->net_stats[0].tx_fifo_errors++;
1144 }
1145
1146 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1147 netdev_err(dev, "TX MAC max packet size error\n");
1148 cp->net_stats[0].tx_errors++;
1149 }
1150
1151 /* The rest are all cases of one of the 16-bit TX
1152 * counters expiring.
1153 */
1154 if (txmac_stat & MAC_TX_COLL_NORMAL)
1155 cp->net_stats[0].collisions += 0x10000;
1156
1157 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1158 cp->net_stats[0].tx_aborted_errors += 0x10000;
1159 cp->net_stats[0].collisions += 0x10000;
1160 }
1161
1162 if (txmac_stat & MAC_TX_COLL_LATE) {
1163 cp->net_stats[0].tx_aborted_errors += 0x10000;
1164 cp->net_stats[0].collisions += 0x10000;
1165 }
1166 spin_unlock(&cp->stat_lock[0]);
1167
1168 /* We do not keep track of MAC_TX_COLL_FIRST and
1169 * MAC_TX_PEAK_ATTEMPTS events.
1170 */
1171 return 0;
1172 }
1173
1174 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1175 {
1176 cas_hp_inst_t *inst;
1177 u32 val;
1178 int i;
1179
1180 i = 0;
1181 while ((inst = firmware) && inst->note) {
1182 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1183
1184 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1185 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1186 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1187
1188 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1189 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1190 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1191 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1192 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1193 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1194 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1195 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1196
1197 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1198 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1199 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1200 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1201 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1202 ++firmware;
1203 ++i;
1204 }
1205 }
1206
1207 static void cas_init_rx_dma(struct cas *cp)
1208 {
1209 u64 desc_dma = cp->block_dvma;
1210 u32 val;
1211 int i, size;
1212
1213 /* rx free descriptors */
1214 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1215 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1216 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1217 if ((N_RX_DESC_RINGS > 1) &&
1218 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1219 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1220 writel(val, cp->regs + REG_RX_CFG);
1221
1222 val = (unsigned long) cp->init_rxds[0] -
1223 (unsigned long) cp->init_block;
1224 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1225 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1226 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1227
1228 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1229 /* rx desc 2 is for IPSEC packets. however,
1230 * we don't it that for that purpose.
1231 */
1232 val = (unsigned long) cp->init_rxds[1] -
1233 (unsigned long) cp->init_block;
1234 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1235 writel((desc_dma + val) & 0xffffffff, cp->regs +
1236 REG_PLUS_RX_DB1_LOW);
1237 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1238 REG_PLUS_RX_KICK1);
1239 }
1240
1241 /* rx completion registers */
1242 val = (unsigned long) cp->init_rxcs[0] -
1243 (unsigned long) cp->init_block;
1244 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1245 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1246
1247 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1248 /* rx comp 2-4 */
1249 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1250 val = (unsigned long) cp->init_rxcs[i] -
1251 (unsigned long) cp->init_block;
1252 writel((desc_dma + val) >> 32, cp->regs +
1253 REG_PLUS_RX_CBN_HI(i));
1254 writel((desc_dma + val) & 0xffffffff, cp->regs +
1255 REG_PLUS_RX_CBN_LOW(i));
1256 }
1257 }
1258
1259 /* read selective clear regs to prevent spurious interrupts
1260 * on reset because complete == kick.
1261 * selective clear set up to prevent interrupts on resets
1262 */
1263 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1264 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1265 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1266 for (i = 1; i < N_RX_COMP_RINGS; i++)
1267 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1268
1269 /* 2 is different from 3 and 4 */
1270 if (N_RX_COMP_RINGS > 1)
1271 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1272 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1273
1274 for (i = 2; i < N_RX_COMP_RINGS; i++)
1275 writel(INTR_RX_DONE_ALT,
1276 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1277 }
1278
1279 /* set up pause thresholds */
1280 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1281 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1282 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1283 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1284 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1285
1286 /* zero out dma reassembly buffers */
1287 for (i = 0; i < 64; i++) {
1288 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1289 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1290 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1291 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1292 }
1293
1294 /* make sure address register is 0 for normal operation */
1295 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1296 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1297
1298 /* interrupt mitigation */
1299 #ifdef USE_RX_BLANK
1300 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1301 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1302 writel(val, cp->regs + REG_RX_BLANK);
1303 #else
1304 writel(0x0, cp->regs + REG_RX_BLANK);
1305 #endif
1306
1307 /* interrupt generation as a function of low water marks for
1308 * free desc and completion entries. these are used to trigger
1309 * housekeeping for rx descs. we don't use the free interrupt
1310 * as it's not very useful
1311 */
1312 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1313 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1314 writel(val, cp->regs + REG_RX_AE_THRESH);
1315 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1316 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1317 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1318 }
1319
1320 /* Random early detect registers. useful for congestion avoidance.
1321 * this should be tunable.
1322 */
1323 writel(0x0, cp->regs + REG_RX_RED);
1324
1325 /* receive page sizes. default == 2K (0x800) */
1326 val = 0;
1327 if (cp->page_size == 0x1000)
1328 val = 0x1;
1329 else if (cp->page_size == 0x2000)
1330 val = 0x2;
1331 else if (cp->page_size == 0x4000)
1332 val = 0x3;
1333
1334 /* round mtu + offset. constrain to page size. */
1335 size = cp->dev->mtu + 64;
1336 if (size > cp->page_size)
1337 size = cp->page_size;
1338
1339 if (size <= 0x400)
1340 i = 0x0;
1341 else if (size <= 0x800)
1342 i = 0x1;
1343 else if (size <= 0x1000)
1344 i = 0x2;
1345 else
1346 i = 0x3;
1347
1348 cp->mtu_stride = 1 << (i + 10);
1349 val = CAS_BASE(RX_PAGE_SIZE, val);
1350 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1351 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1352 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1353 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1354
1355 /* enable the header parser if desired */
1356 if (CAS_HP_FIRMWARE == cas_prog_null)
1357 return;
1358
1359 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1360 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1361 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1362 writel(val, cp->regs + REG_HP_CFG);
1363 }
1364
1365 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1366 {
1367 memset(rxc, 0, sizeof(*rxc));
1368 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1369 }
1370
1371 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1372 * flipping is protected by the fact that the chip will not
1373 * hand back the same page index while it's being processed.
1374 */
1375 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1376 {
1377 cas_page_t *page = cp->rx_pages[1][index];
1378 cas_page_t *new;
1379
1380 if (page_count(page->buffer) == 1)
1381 return page;
1382
1383 new = cas_page_dequeue(cp);
1384 if (new) {
1385 spin_lock(&cp->rx_inuse_lock);
1386 list_add(&page->list, &cp->rx_inuse_list);
1387 spin_unlock(&cp->rx_inuse_lock);
1388 }
1389 return new;
1390 }
1391
1392 /* this needs to be changed if we actually use the ENC RX DESC ring */
1393 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1394 const int index)
1395 {
1396 cas_page_t **page0 = cp->rx_pages[0];
1397 cas_page_t **page1 = cp->rx_pages[1];
1398
1399 /* swap if buffer is in use */
1400 if (page_count(page0[index]->buffer) > 1) {
1401 cas_page_t *new = cas_page_spare(cp, index);
1402 if (new) {
1403 page1[index] = page0[index];
1404 page0[index] = new;
1405 }
1406 }
1407 RX_USED_SET(page0[index], 0);
1408 return page0[index];
1409 }
1410
1411 static void cas_clean_rxds(struct cas *cp)
1412 {
1413 /* only clean ring 0 as ring 1 is used for spare buffers */
1414 struct cas_rx_desc *rxd = cp->init_rxds[0];
1415 int i, size;
1416
1417 /* release all rx flows */
1418 for (i = 0; i < N_RX_FLOWS; i++) {
1419 struct sk_buff *skb;
1420 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1421 cas_skb_release(skb);
1422 }
1423 }
1424
1425 /* initialize descriptors */
1426 size = RX_DESC_RINGN_SIZE(0);
1427 for (i = 0; i < size; i++) {
1428 cas_page_t *page = cas_page_swap(cp, 0, i);
1429 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1430 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1431 CAS_BASE(RX_INDEX_RING, 0));
1432 }
1433
1434 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1435 cp->rx_last[0] = 0;
1436 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1437 }
1438
1439 static void cas_clean_rxcs(struct cas *cp)
1440 {
1441 int i, j;
1442
1443 /* take ownership of rx comp descriptors */
1444 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1445 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1446 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1447 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1448 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1449 cas_rxc_init(rxc + j);
1450 }
1451 }
1452 }
1453
1454 #if 0
1455 /* When we get a RX fifo overflow, the RX unit is probably hung
1456 * so we do the following.
1457 *
1458 * If any part of the reset goes wrong, we return 1 and that causes the
1459 * whole chip to be reset.
1460 */
1461 static int cas_rxmac_reset(struct cas *cp)
1462 {
1463 struct net_device *dev = cp->dev;
1464 int limit;
1465 u32 val;
1466
1467 /* First, reset MAC RX. */
1468 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1469 for (limit = 0; limit < STOP_TRIES; limit++) {
1470 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1471 break;
1472 udelay(10);
1473 }
1474 if (limit == STOP_TRIES) {
1475 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1476 return 1;
1477 }
1478
1479 /* Second, disable RX DMA. */
1480 writel(0, cp->regs + REG_RX_CFG);
1481 for (limit = 0; limit < STOP_TRIES; limit++) {
1482 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1483 break;
1484 udelay(10);
1485 }
1486 if (limit == STOP_TRIES) {
1487 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1488 return 1;
1489 }
1490
1491 mdelay(5);
1492
1493 /* Execute RX reset command. */
1494 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1495 for (limit = 0; limit < STOP_TRIES; limit++) {
1496 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1497 break;
1498 udelay(10);
1499 }
1500 if (limit == STOP_TRIES) {
1501 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1502 return 1;
1503 }
1504
1505 /* reset driver rx state */
1506 cas_clean_rxds(cp);
1507 cas_clean_rxcs(cp);
1508
1509 /* Now, reprogram the rest of RX unit. */
1510 cas_init_rx_dma(cp);
1511
1512 /* re-enable */
1513 val = readl(cp->regs + REG_RX_CFG);
1514 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1515 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1516 val = readl(cp->regs + REG_MAC_RX_CFG);
1517 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1518 return 0;
1519 }
1520 #endif
1521
1522 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1523 u32 status)
1524 {
1525 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1526
1527 if (!stat)
1528 return 0;
1529
1530 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1531
1532 /* these are all rollovers */
1533 spin_lock(&cp->stat_lock[0]);
1534 if (stat & MAC_RX_ALIGN_ERR)
1535 cp->net_stats[0].rx_frame_errors += 0x10000;
1536
1537 if (stat & MAC_RX_CRC_ERR)
1538 cp->net_stats[0].rx_crc_errors += 0x10000;
1539
1540 if (stat & MAC_RX_LEN_ERR)
1541 cp->net_stats[0].rx_length_errors += 0x10000;
1542
1543 if (stat & MAC_RX_OVERFLOW) {
1544 cp->net_stats[0].rx_over_errors++;
1545 cp->net_stats[0].rx_fifo_errors++;
1546 }
1547
1548 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1549 * events.
1550 */
1551 spin_unlock(&cp->stat_lock[0]);
1552 return 0;
1553 }
1554
1555 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1556 u32 status)
1557 {
1558 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1559
1560 if (!stat)
1561 return 0;
1562
1563 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1564 "mac interrupt, stat: 0x%x\n", stat);
1565
1566 /* This interrupt is just for pause frame and pause
1567 * tracking. It is useful for diagnostics and debug
1568 * but probably by default we will mask these events.
1569 */
1570 if (stat & MAC_CTRL_PAUSE_STATE)
1571 cp->pause_entered++;
1572
1573 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1574 cp->pause_last_time_recvd = (stat >> 16);
1575
1576 return 0;
1577 }
1578
1579
1580 /* Must be invoked under cp->lock. */
1581 static inline int cas_mdio_link_not_up(struct cas *cp)
1582 {
1583 u16 val;
1584
1585 switch (cp->lstate) {
1586 case link_force_ret:
1587 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1588 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1589 cp->timer_ticks = 5;
1590 cp->lstate = link_force_ok;
1591 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1592 break;
1593
1594 case link_aneg:
1595 val = cas_phy_read(cp, MII_BMCR);
1596
1597 /* Try forced modes. we try things in the following order:
1598 * 1000 full -> 100 full/half -> 10 half
1599 */
1600 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1601 val |= BMCR_FULLDPLX;
1602 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1603 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1604 cas_phy_write(cp, MII_BMCR, val);
1605 cp->timer_ticks = 5;
1606 cp->lstate = link_force_try;
1607 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1608 break;
1609
1610 case link_force_try:
1611 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1612 val = cas_phy_read(cp, MII_BMCR);
1613 cp->timer_ticks = 5;
1614 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1615 val &= ~CAS_BMCR_SPEED1000;
1616 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1617 cas_phy_write(cp, MII_BMCR, val);
1618 break;
1619 }
1620
1621 if (val & BMCR_SPEED100) {
1622 if (val & BMCR_FULLDPLX) /* fd failed */
1623 val &= ~BMCR_FULLDPLX;
1624 else { /* 100Mbps failed */
1625 val &= ~BMCR_SPEED100;
1626 }
1627 cas_phy_write(cp, MII_BMCR, val);
1628 break;
1629 }
1630 default:
1631 break;
1632 }
1633 return 0;
1634 }
1635
1636
1637 /* must be invoked with cp->lock held */
1638 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1639 {
1640 int restart;
1641
1642 if (bmsr & BMSR_LSTATUS) {
1643 /* Ok, here we got a link. If we had it due to a forced
1644 * fallback, and we were configured for autoneg, we
1645 * retry a short autoneg pass. If you know your hub is
1646 * broken, use ethtool ;)
1647 */
1648 if ((cp->lstate == link_force_try) &&
1649 (cp->link_cntl & BMCR_ANENABLE)) {
1650 cp->lstate = link_force_ret;
1651 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1652 cas_mif_poll(cp, 0);
1653 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1654 cp->timer_ticks = 5;
1655 if (cp->opened)
1656 netif_info(cp, link, cp->dev,
1657 "Got link after fallback, retrying autoneg once...\n");
1658 cas_phy_write(cp, MII_BMCR,
1659 cp->link_fcntl | BMCR_ANENABLE |
1660 BMCR_ANRESTART);
1661 cas_mif_poll(cp, 1);
1662
1663 } else if (cp->lstate != link_up) {
1664 cp->lstate = link_up;
1665 cp->link_transition = LINK_TRANSITION_LINK_UP;
1666
1667 if (cp->opened) {
1668 cas_set_link_modes(cp);
1669 netif_carrier_on(cp->dev);
1670 }
1671 }
1672 return 0;
1673 }
1674
1675 /* link not up. if the link was previously up, we restart the
1676 * whole process
1677 */
1678 restart = 0;
1679 if (cp->lstate == link_up) {
1680 cp->lstate = link_down;
1681 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1682
1683 netif_carrier_off(cp->dev);
1684 if (cp->opened)
1685 netif_info(cp, link, cp->dev, "Link down\n");
1686 restart = 1;
1687
1688 } else if (++cp->timer_ticks > 10)
1689 cas_mdio_link_not_up(cp);
1690
1691 return restart;
1692 }
1693
1694 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1695 u32 status)
1696 {
1697 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1698 u16 bmsr;
1699
1700 /* check for a link change */
1701 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1702 return 0;
1703
1704 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1705 return cas_mii_link_check(cp, bmsr);
1706 }
1707
1708 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1709 u32 status)
1710 {
1711 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1712
1713 if (!stat)
1714 return 0;
1715
1716 netdev_err(dev, "PCI error [%04x:%04x]",
1717 stat, readl(cp->regs + REG_BIM_DIAG));
1718
1719 /* cassini+ has this reserved */
1720 if ((stat & PCI_ERR_BADACK) &&
1721 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1722 pr_cont(" <No ACK64# during ABS64 cycle>");
1723
1724 if (stat & PCI_ERR_DTRTO)
1725 pr_cont(" <Delayed transaction timeout>");
1726 if (stat & PCI_ERR_OTHER)
1727 pr_cont(" <other>");
1728 if (stat & PCI_ERR_BIM_DMA_WRITE)
1729 pr_cont(" <BIM DMA 0 write req>");
1730 if (stat & PCI_ERR_BIM_DMA_READ)
1731 pr_cont(" <BIM DMA 0 read req>");
1732 pr_cont("\n");
1733
1734 if (stat & PCI_ERR_OTHER) {
1735 u16 cfg;
1736
1737 /* Interrogate PCI config space for the
1738 * true cause.
1739 */
1740 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1741 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1742 if (cfg & PCI_STATUS_PARITY)
1743 netdev_err(dev, "PCI parity error detected\n");
1744 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1745 netdev_err(dev, "PCI target abort\n");
1746 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1747 netdev_err(dev, "PCI master acks target abort\n");
1748 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1749 netdev_err(dev, "PCI master abort\n");
1750 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1751 netdev_err(dev, "PCI system error SERR#\n");
1752 if (cfg & PCI_STATUS_DETECTED_PARITY)
1753 netdev_err(dev, "PCI parity error\n");
1754
1755 /* Write the error bits back to clear them. */
1756 cfg &= (PCI_STATUS_PARITY |
1757 PCI_STATUS_SIG_TARGET_ABORT |
1758 PCI_STATUS_REC_TARGET_ABORT |
1759 PCI_STATUS_REC_MASTER_ABORT |
1760 PCI_STATUS_SIG_SYSTEM_ERROR |
1761 PCI_STATUS_DETECTED_PARITY);
1762 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1763 }
1764
1765 /* For all PCI errors, we should reset the chip. */
1766 return 1;
1767 }
1768
1769 /* All non-normal interrupt conditions get serviced here.
1770 * Returns non-zero if we should just exit the interrupt
1771 * handler right now (ie. if we reset the card which invalidates
1772 * all of the other original irq status bits).
1773 */
1774 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1775 u32 status)
1776 {
1777 if (status & INTR_RX_TAG_ERROR) {
1778 /* corrupt RX tag framing */
1779 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1780 "corrupt rx tag framing\n");
1781 spin_lock(&cp->stat_lock[0]);
1782 cp->net_stats[0].rx_errors++;
1783 spin_unlock(&cp->stat_lock[0]);
1784 goto do_reset;
1785 }
1786
1787 if (status & INTR_RX_LEN_MISMATCH) {
1788 /* length mismatch. */
1789 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1790 "length mismatch for rx frame\n");
1791 spin_lock(&cp->stat_lock[0]);
1792 cp->net_stats[0].rx_errors++;
1793 spin_unlock(&cp->stat_lock[0]);
1794 goto do_reset;
1795 }
1796
1797 if (status & INTR_PCS_STATUS) {
1798 if (cas_pcs_interrupt(dev, cp, status))
1799 goto do_reset;
1800 }
1801
1802 if (status & INTR_TX_MAC_STATUS) {
1803 if (cas_txmac_interrupt(dev, cp, status))
1804 goto do_reset;
1805 }
1806
1807 if (status & INTR_RX_MAC_STATUS) {
1808 if (cas_rxmac_interrupt(dev, cp, status))
1809 goto do_reset;
1810 }
1811
1812 if (status & INTR_MAC_CTRL_STATUS) {
1813 if (cas_mac_interrupt(dev, cp, status))
1814 goto do_reset;
1815 }
1816
1817 if (status & INTR_MIF_STATUS) {
1818 if (cas_mif_interrupt(dev, cp, status))
1819 goto do_reset;
1820 }
1821
1822 if (status & INTR_PCI_ERROR_STATUS) {
1823 if (cas_pci_interrupt(dev, cp, status))
1824 goto do_reset;
1825 }
1826 return 0;
1827
1828 do_reset:
1829 #if 1
1830 atomic_inc(&cp->reset_task_pending);
1831 atomic_inc(&cp->reset_task_pending_all);
1832 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1833 schedule_work(&cp->reset_task);
1834 #else
1835 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1836 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1837 schedule_work(&cp->reset_task);
1838 #endif
1839 return 1;
1840 }
1841
1842 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1843 * determining whether to do a netif_stop/wakeup
1844 */
1845 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1846 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1847 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1848 const int len)
1849 {
1850 unsigned long off = addr + len;
1851
1852 if (CAS_TABORT(cp) == 1)
1853 return 0;
1854 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1855 return 0;
1856 return TX_TARGET_ABORT_LEN;
1857 }
1858
1859 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1860 {
1861 struct cas_tx_desc *txds;
1862 struct sk_buff **skbs;
1863 struct net_device *dev = cp->dev;
1864 int entry, count;
1865
1866 spin_lock(&cp->tx_lock[ring]);
1867 txds = cp->init_txds[ring];
1868 skbs = cp->tx_skbs[ring];
1869 entry = cp->tx_old[ring];
1870
1871 count = TX_BUFF_COUNT(ring, entry, limit);
1872 while (entry != limit) {
1873 struct sk_buff *skb = skbs[entry];
1874 dma_addr_t daddr;
1875 u32 dlen;
1876 int frag;
1877
1878 if (!skb) {
1879 /* this should never occur */
1880 entry = TX_DESC_NEXT(ring, entry);
1881 continue;
1882 }
1883
1884 /* however, we might get only a partial skb release. */
1885 count -= skb_shinfo(skb)->nr_frags +
1886 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1887 if (count < 0)
1888 break;
1889
1890 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1891 "tx[%d] done, slot %d\n", ring, entry);
1892
1893 skbs[entry] = NULL;
1894 cp->tx_tiny_use[ring][entry].nbufs = 0;
1895
1896 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1897 struct cas_tx_desc *txd = txds + entry;
1898
1899 daddr = le64_to_cpu(txd->buffer);
1900 dlen = CAS_VAL(TX_DESC_BUFLEN,
1901 le64_to_cpu(txd->control));
1902 pci_unmap_page(cp->pdev, daddr, dlen,
1903 PCI_DMA_TODEVICE);
1904 entry = TX_DESC_NEXT(ring, entry);
1905
1906 /* tiny buffer may follow */
1907 if (cp->tx_tiny_use[ring][entry].used) {
1908 cp->tx_tiny_use[ring][entry].used = 0;
1909 entry = TX_DESC_NEXT(ring, entry);
1910 }
1911 }
1912
1913 spin_lock(&cp->stat_lock[ring]);
1914 cp->net_stats[ring].tx_packets++;
1915 cp->net_stats[ring].tx_bytes += skb->len;
1916 spin_unlock(&cp->stat_lock[ring]);
1917 dev_kfree_skb_irq(skb);
1918 }
1919 cp->tx_old[ring] = entry;
1920
1921 /* this is wrong for multiple tx rings. the net device needs
1922 * multiple queues for this to do the right thing. we wait
1923 * for 2*packets to be available when using tiny buffers
1924 */
1925 if (netif_queue_stopped(dev) &&
1926 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1927 netif_wake_queue(dev);
1928 spin_unlock(&cp->tx_lock[ring]);
1929 }
1930
1931 static void cas_tx(struct net_device *dev, struct cas *cp,
1932 u32 status)
1933 {
1934 int limit, ring;
1935 #ifdef USE_TX_COMPWB
1936 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1937 #endif
1938 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1939 "tx interrupt, status: 0x%x, %llx\n",
1940 status, (unsigned long long)compwb);
1941 /* process all the rings */
1942 for (ring = 0; ring < N_TX_RINGS; ring++) {
1943 #ifdef USE_TX_COMPWB
1944 /* use the completion writeback registers */
1945 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1946 CAS_VAL(TX_COMPWB_LSB, compwb);
1947 compwb = TX_COMPWB_NEXT(compwb);
1948 #else
1949 limit = readl(cp->regs + REG_TX_COMPN(ring));
1950 #endif
1951 if (cp->tx_old[ring] != limit)
1952 cas_tx_ringN(cp, ring, limit);
1953 }
1954 }
1955
1956
1957 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1958 int entry, const u64 *words,
1959 struct sk_buff **skbref)
1960 {
1961 int dlen, hlen, len, i, alloclen;
1962 int off, swivel = RX_SWIVEL_OFF_VAL;
1963 struct cas_page *page;
1964 struct sk_buff *skb;
1965 void *addr, *crcaddr;
1966 __sum16 csum;
1967 char *p;
1968
1969 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1970 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1971 len = hlen + dlen;
1972
1973 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1974 alloclen = len;
1975 else
1976 alloclen = max(hlen, RX_COPY_MIN);
1977
1978 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1979 if (skb == NULL)
1980 return -1;
1981
1982 *skbref = skb;
1983 skb_reserve(skb, swivel);
1984
1985 p = skb->data;
1986 addr = crcaddr = NULL;
1987 if (hlen) { /* always copy header pages */
1988 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1989 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1990 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1991 swivel;
1992
1993 i = hlen;
1994 if (!dlen) /* attach FCS */
1995 i += cp->crc_size;
1996 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1997 PCI_DMA_FROMDEVICE);
1998 addr = cas_page_map(page->buffer);
1999 memcpy(p, addr + off, i);
2000 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2001 PCI_DMA_FROMDEVICE);
2002 cas_page_unmap(addr);
2003 RX_USED_ADD(page, 0x100);
2004 p += hlen;
2005 swivel = 0;
2006 }
2007
2008
2009 if (alloclen < (hlen + dlen)) {
2010 skb_frag_t *frag = skb_shinfo(skb)->frags;
2011
2012 /* normal or jumbo packets. we use frags */
2013 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2014 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2015 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2016
2017 hlen = min(cp->page_size - off, dlen);
2018 if (hlen < 0) {
2019 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2020 "rx page overflow: %d\n", hlen);
2021 dev_kfree_skb_irq(skb);
2022 return -1;
2023 }
2024 i = hlen;
2025 if (i == dlen) /* attach FCS */
2026 i += cp->crc_size;
2027 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2028 PCI_DMA_FROMDEVICE);
2029
2030 /* make sure we always copy a header */
2031 swivel = 0;
2032 if (p == (char *) skb->data) { /* not split */
2033 addr = cas_page_map(page->buffer);
2034 memcpy(p, addr + off, RX_COPY_MIN);
2035 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2036 PCI_DMA_FROMDEVICE);
2037 cas_page_unmap(addr);
2038 off += RX_COPY_MIN;
2039 swivel = RX_COPY_MIN;
2040 RX_USED_ADD(page, cp->mtu_stride);
2041 } else {
2042 RX_USED_ADD(page, hlen);
2043 }
2044 skb_put(skb, alloclen);
2045
2046 skb_shinfo(skb)->nr_frags++;
2047 skb->data_len += hlen - swivel;
2048 skb->truesize += hlen - swivel;
2049 skb->len += hlen - swivel;
2050
2051 get_page(page->buffer);
2052 frag->page = page->buffer;
2053 frag->page_offset = off;
2054 frag->size = hlen - swivel;
2055
2056 /* any more data? */
2057 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2058 hlen = dlen;
2059 off = 0;
2060
2061 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2062 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2063 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2064 hlen + cp->crc_size,
2065 PCI_DMA_FROMDEVICE);
2066 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2067 hlen + cp->crc_size,
2068 PCI_DMA_FROMDEVICE);
2069
2070 skb_shinfo(skb)->nr_frags++;
2071 skb->data_len += hlen;
2072 skb->len += hlen;
2073 frag++;
2074
2075 get_page(page->buffer);
2076 frag->page = page->buffer;
2077 frag->page_offset = 0;
2078 frag->size = hlen;
2079 RX_USED_ADD(page, hlen + cp->crc_size);
2080 }
2081
2082 if (cp->crc_size) {
2083 addr = cas_page_map(page->buffer);
2084 crcaddr = addr + off + hlen;
2085 }
2086
2087 } else {
2088 /* copying packet */
2089 if (!dlen)
2090 goto end_copy_pkt;
2091
2092 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2093 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2094 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2095 hlen = min(cp->page_size - off, dlen);
2096 if (hlen < 0) {
2097 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2098 "rx page overflow: %d\n", hlen);
2099 dev_kfree_skb_irq(skb);
2100 return -1;
2101 }
2102 i = hlen;
2103 if (i == dlen) /* attach FCS */
2104 i += cp->crc_size;
2105 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2106 PCI_DMA_FROMDEVICE);
2107 addr = cas_page_map(page->buffer);
2108 memcpy(p, addr + off, i);
2109 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2110 PCI_DMA_FROMDEVICE);
2111 cas_page_unmap(addr);
2112 if (p == (char *) skb->data) /* not split */
2113 RX_USED_ADD(page, cp->mtu_stride);
2114 else
2115 RX_USED_ADD(page, i);
2116
2117 /* any more data? */
2118 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2119 p += hlen;
2120 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2121 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2122 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2123 dlen + cp->crc_size,
2124 PCI_DMA_FROMDEVICE);
2125 addr = cas_page_map(page->buffer);
2126 memcpy(p, addr, dlen + cp->crc_size);
2127 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2128 dlen + cp->crc_size,
2129 PCI_DMA_FROMDEVICE);
2130 cas_page_unmap(addr);
2131 RX_USED_ADD(page, dlen + cp->crc_size);
2132 }
2133 end_copy_pkt:
2134 if (cp->crc_size) {
2135 addr = NULL;
2136 crcaddr = skb->data + alloclen;
2137 }
2138 skb_put(skb, alloclen);
2139 }
2140
2141 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2142 if (cp->crc_size) {
2143 /* checksum includes FCS. strip it out. */
2144 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2145 csum_unfold(csum)));
2146 if (addr)
2147 cas_page_unmap(addr);
2148 }
2149 skb->protocol = eth_type_trans(skb, cp->dev);
2150 if (skb->protocol == htons(ETH_P_IP)) {
2151 skb->csum = csum_unfold(~csum);
2152 skb->ip_summed = CHECKSUM_COMPLETE;
2153 } else
2154 skb_checksum_none_assert(skb);
2155 return len;
2156 }
2157
2158
2159 /* we can handle up to 64 rx flows at a time. we do the same thing
2160 * as nonreassm except that we batch up the buffers.
2161 * NOTE: we currently just treat each flow as a bunch of packets that
2162 * we pass up. a better way would be to coalesce the packets
2163 * into a jumbo packet. to do that, we need to do the following:
2164 * 1) the first packet will have a clean split between header and
2165 * data. save both.
2166 * 2) each time the next flow packet comes in, extend the
2167 * data length and merge the checksums.
2168 * 3) on flow release, fix up the header.
2169 * 4) make sure the higher layer doesn't care.
2170 * because packets get coalesced, we shouldn't run into fragment count
2171 * issues.
2172 */
2173 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2174 struct sk_buff *skb)
2175 {
2176 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2177 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2178
2179 /* this is protected at a higher layer, so no need to
2180 * do any additional locking here. stick the buffer
2181 * at the end.
2182 */
2183 __skb_queue_tail(flow, skb);
2184 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2185 while ((skb = __skb_dequeue(flow))) {
2186 cas_skb_release(skb);
2187 }
2188 }
2189 }
2190
2191 /* put rx descriptor back on ring. if a buffer is in use by a higher
2192 * layer, this will need to put in a replacement.
2193 */
2194 static void cas_post_page(struct cas *cp, const int ring, const int index)
2195 {
2196 cas_page_t *new;
2197 int entry;
2198
2199 entry = cp->rx_old[ring];
2200
2201 new = cas_page_swap(cp, ring, index);
2202 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2203 cp->init_rxds[ring][entry].index =
2204 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2205 CAS_BASE(RX_INDEX_RING, ring));
2206
2207 entry = RX_DESC_ENTRY(ring, entry + 1);
2208 cp->rx_old[ring] = entry;
2209
2210 if (entry % 4)
2211 return;
2212
2213 if (ring == 0)
2214 writel(entry, cp->regs + REG_RX_KICK);
2215 else if ((N_RX_DESC_RINGS > 1) &&
2216 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2217 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2218 }
2219
2220
2221 /* only when things are bad */
2222 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2223 {
2224 unsigned int entry, last, count, released;
2225 int cluster;
2226 cas_page_t **page = cp->rx_pages[ring];
2227
2228 entry = cp->rx_old[ring];
2229
2230 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2231 "rxd[%d] interrupt, done: %d\n", ring, entry);
2232
2233 cluster = -1;
2234 count = entry & 0x3;
2235 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2236 released = 0;
2237 while (entry != last) {
2238 /* make a new buffer if it's still in use */
2239 if (page_count(page[entry]->buffer) > 1) {
2240 cas_page_t *new = cas_page_dequeue(cp);
2241 if (!new) {
2242 /* let the timer know that we need to
2243 * do this again
2244 */
2245 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2246 if (!timer_pending(&cp->link_timer))
2247 mod_timer(&cp->link_timer, jiffies +
2248 CAS_LINK_FAST_TIMEOUT);
2249 cp->rx_old[ring] = entry;
2250 cp->rx_last[ring] = num ? num - released : 0;
2251 return -ENOMEM;
2252 }
2253 spin_lock(&cp->rx_inuse_lock);
2254 list_add(&page[entry]->list, &cp->rx_inuse_list);
2255 spin_unlock(&cp->rx_inuse_lock);
2256 cp->init_rxds[ring][entry].buffer =
2257 cpu_to_le64(new->dma_addr);
2258 page[entry] = new;
2259
2260 }
2261
2262 if (++count == 4) {
2263 cluster = entry;
2264 count = 0;
2265 }
2266 released++;
2267 entry = RX_DESC_ENTRY(ring, entry + 1);
2268 }
2269 cp->rx_old[ring] = entry;
2270
2271 if (cluster < 0)
2272 return 0;
2273
2274 if (ring == 0)
2275 writel(cluster, cp->regs + REG_RX_KICK);
2276 else if ((N_RX_DESC_RINGS > 1) &&
2277 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2278 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2279 return 0;
2280 }
2281
2282
2283 /* process a completion ring. packets are set up in three basic ways:
2284 * small packets: should be copied header + data in single buffer.
2285 * large packets: header and data in a single buffer.
2286 * split packets: header in a separate buffer from data.
2287 * data may be in multiple pages. data may be > 256
2288 * bytes but in a single page.
2289 *
2290 * NOTE: RX page posting is done in this routine as well. while there's
2291 * the capability of using multiple RX completion rings, it isn't
2292 * really worthwhile due to the fact that the page posting will
2293 * force serialization on the single descriptor ring.
2294 */
2295 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2296 {
2297 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2298 int entry, drops;
2299 int npackets = 0;
2300
2301 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2302 "rx[%d] interrupt, done: %d/%d\n",
2303 ring,
2304 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2305
2306 entry = cp->rx_new[ring];
2307 drops = 0;
2308 while (1) {
2309 struct cas_rx_comp *rxc = rxcs + entry;
2310 struct sk_buff *uninitialized_var(skb);
2311 int type, len;
2312 u64 words[4];
2313 int i, dring;
2314
2315 words[0] = le64_to_cpu(rxc->word1);
2316 words[1] = le64_to_cpu(rxc->word2);
2317 words[2] = le64_to_cpu(rxc->word3);
2318 words[3] = le64_to_cpu(rxc->word4);
2319
2320 /* don't touch if still owned by hw */
2321 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2322 if (type == 0)
2323 break;
2324
2325 /* hw hasn't cleared the zero bit yet */
2326 if (words[3] & RX_COMP4_ZERO) {
2327 break;
2328 }
2329
2330 /* get info on the packet */
2331 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2332 spin_lock(&cp->stat_lock[ring]);
2333 cp->net_stats[ring].rx_errors++;
2334 if (words[3] & RX_COMP4_LEN_MISMATCH)
2335 cp->net_stats[ring].rx_length_errors++;
2336 if (words[3] & RX_COMP4_BAD)
2337 cp->net_stats[ring].rx_crc_errors++;
2338 spin_unlock(&cp->stat_lock[ring]);
2339
2340 /* We'll just return it to Cassini. */
2341 drop_it:
2342 spin_lock(&cp->stat_lock[ring]);
2343 ++cp->net_stats[ring].rx_dropped;
2344 spin_unlock(&cp->stat_lock[ring]);
2345 goto next;
2346 }
2347
2348 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2349 if (len < 0) {
2350 ++drops;
2351 goto drop_it;
2352 }
2353
2354 /* see if it's a flow re-assembly or not. the driver
2355 * itself handles release back up.
2356 */
2357 if (RX_DONT_BATCH || (type == 0x2)) {
2358 /* non-reassm: these always get released */
2359 cas_skb_release(skb);
2360 } else {
2361 cas_rx_flow_pkt(cp, words, skb);
2362 }
2363
2364 spin_lock(&cp->stat_lock[ring]);
2365 cp->net_stats[ring].rx_packets++;
2366 cp->net_stats[ring].rx_bytes += len;
2367 spin_unlock(&cp->stat_lock[ring]);
2368
2369 next:
2370 npackets++;
2371
2372 /* should it be released? */
2373 if (words[0] & RX_COMP1_RELEASE_HDR) {
2374 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2375 dring = CAS_VAL(RX_INDEX_RING, i);
2376 i = CAS_VAL(RX_INDEX_NUM, i);
2377 cas_post_page(cp, dring, i);
2378 }
2379
2380 if (words[0] & RX_COMP1_RELEASE_DATA) {
2381 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2382 dring = CAS_VAL(RX_INDEX_RING, i);
2383 i = CAS_VAL(RX_INDEX_NUM, i);
2384 cas_post_page(cp, dring, i);
2385 }
2386
2387 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2388 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2389 dring = CAS_VAL(RX_INDEX_RING, i);
2390 i = CAS_VAL(RX_INDEX_NUM, i);
2391 cas_post_page(cp, dring, i);
2392 }
2393
2394 /* skip to the next entry */
2395 entry = RX_COMP_ENTRY(ring, entry + 1 +
2396 CAS_VAL(RX_COMP1_SKIP, words[0]));
2397 #ifdef USE_NAPI
2398 if (budget && (npackets >= budget))
2399 break;
2400 #endif
2401 }
2402 cp->rx_new[ring] = entry;
2403
2404 if (drops)
2405 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2406 return npackets;
2407 }
2408
2409
2410 /* put completion entries back on the ring */
2411 static void cas_post_rxcs_ringN(struct net_device *dev,
2412 struct cas *cp, int ring)
2413 {
2414 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2415 int last, entry;
2416
2417 last = cp->rx_cur[ring];
2418 entry = cp->rx_new[ring];
2419 netif_printk(cp, intr, KERN_DEBUG, dev,
2420 "rxc[%d] interrupt, done: %d/%d\n",
2421 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2422
2423 /* zero and re-mark descriptors */
2424 while (last != entry) {
2425 cas_rxc_init(rxc + last);
2426 last = RX_COMP_ENTRY(ring, last + 1);
2427 }
2428 cp->rx_cur[ring] = last;
2429
2430 if (ring == 0)
2431 writel(last, cp->regs + REG_RX_COMP_TAIL);
2432 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2433 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2434 }
2435
2436
2437
2438 /* cassini can use all four PCI interrupts for the completion ring.
2439 * rings 3 and 4 are identical
2440 */
2441 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2442 static inline void cas_handle_irqN(struct net_device *dev,
2443 struct cas *cp, const u32 status,
2444 const int ring)
2445 {
2446 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2447 cas_post_rxcs_ringN(dev, cp, ring);
2448 }
2449
2450 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2451 {
2452 struct net_device *dev = dev_id;
2453 struct cas *cp = netdev_priv(dev);
2454 unsigned long flags;
2455 int ring;
2456 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2457
2458 /* check for shared irq */
2459 if (status == 0)
2460 return IRQ_NONE;
2461
2462 ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2463 spin_lock_irqsave(&cp->lock, flags);
2464 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2465 #ifdef USE_NAPI
2466 cas_mask_intr(cp);
2467 napi_schedule(&cp->napi);
2468 #else
2469 cas_rx_ringN(cp, ring, 0);
2470 #endif
2471 status &= ~INTR_RX_DONE_ALT;
2472 }
2473
2474 if (status)
2475 cas_handle_irqN(dev, cp, status, ring);
2476 spin_unlock_irqrestore(&cp->lock, flags);
2477 return IRQ_HANDLED;
2478 }
2479 #endif
2480
2481 #ifdef USE_PCI_INTB
2482 /* everything but rx packets */
2483 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2484 {
2485 if (status & INTR_RX_BUF_UNAVAIL_1) {
2486 /* Frame arrived, no free RX buffers available.
2487 * NOTE: we can get this on a link transition. */
2488 cas_post_rxds_ringN(cp, 1, 0);
2489 spin_lock(&cp->stat_lock[1]);
2490 cp->net_stats[1].rx_dropped++;
2491 spin_unlock(&cp->stat_lock[1]);
2492 }
2493
2494 if (status & INTR_RX_BUF_AE_1)
2495 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2496 RX_AE_FREEN_VAL(1));
2497
2498 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2499 cas_post_rxcs_ringN(cp, 1);
2500 }
2501
2502 /* ring 2 handles a few more events than 3 and 4 */
2503 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2504 {
2505 struct net_device *dev = dev_id;
2506 struct cas *cp = netdev_priv(dev);
2507 unsigned long flags;
2508 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2509
2510 /* check for shared interrupt */
2511 if (status == 0)
2512 return IRQ_NONE;
2513
2514 spin_lock_irqsave(&cp->lock, flags);
2515 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2516 #ifdef USE_NAPI
2517 cas_mask_intr(cp);
2518 napi_schedule(&cp->napi);
2519 #else
2520 cas_rx_ringN(cp, 1, 0);
2521 #endif
2522 status &= ~INTR_RX_DONE_ALT;
2523 }
2524 if (status)
2525 cas_handle_irq1(cp, status);
2526 spin_unlock_irqrestore(&cp->lock, flags);
2527 return IRQ_HANDLED;
2528 }
2529 #endif
2530
2531 static inline void cas_handle_irq(struct net_device *dev,
2532 struct cas *cp, const u32 status)
2533 {
2534 /* housekeeping interrupts */
2535 if (status & INTR_ERROR_MASK)
2536 cas_abnormal_irq(dev, cp, status);
2537
2538 if (status & INTR_RX_BUF_UNAVAIL) {
2539 /* Frame arrived, no free RX buffers available.
2540 * NOTE: we can get this on a link transition.
2541 */
2542 cas_post_rxds_ringN(cp, 0, 0);
2543 spin_lock(&cp->stat_lock[0]);
2544 cp->net_stats[0].rx_dropped++;
2545 spin_unlock(&cp->stat_lock[0]);
2546 } else if (status & INTR_RX_BUF_AE) {
2547 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2548 RX_AE_FREEN_VAL(0));
2549 }
2550
2551 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2552 cas_post_rxcs_ringN(dev, cp, 0);
2553 }
2554
2555 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2556 {
2557 struct net_device *dev = dev_id;
2558 struct cas *cp = netdev_priv(dev);
2559 unsigned long flags;
2560 u32 status = readl(cp->regs + REG_INTR_STATUS);
2561
2562 if (status == 0)
2563 return IRQ_NONE;
2564
2565 spin_lock_irqsave(&cp->lock, flags);
2566 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2567 cas_tx(dev, cp, status);
2568 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2569 }
2570
2571 if (status & INTR_RX_DONE) {
2572 #ifdef USE_NAPI
2573 cas_mask_intr(cp);
2574 napi_schedule(&cp->napi);
2575 #else
2576 cas_rx_ringN(cp, 0, 0);
2577 #endif
2578 status &= ~INTR_RX_DONE;
2579 }
2580
2581 if (status)
2582 cas_handle_irq(dev, cp, status);
2583 spin_unlock_irqrestore(&cp->lock, flags);
2584 return IRQ_HANDLED;
2585 }
2586
2587
2588 #ifdef USE_NAPI
2589 static int cas_poll(struct napi_struct *napi, int budget)
2590 {
2591 struct cas *cp = container_of(napi, struct cas, napi);
2592 struct net_device *dev = cp->dev;
2593 int i, enable_intr, credits;
2594 u32 status = readl(cp->regs + REG_INTR_STATUS);
2595 unsigned long flags;
2596
2597 spin_lock_irqsave(&cp->lock, flags);
2598 cas_tx(dev, cp, status);
2599 spin_unlock_irqrestore(&cp->lock, flags);
2600
2601 /* NAPI rx packets. we spread the credits across all of the
2602 * rxc rings
2603 *
2604 * to make sure we're fair with the work we loop through each
2605 * ring N_RX_COMP_RING times with a request of
2606 * budget / N_RX_COMP_RINGS
2607 */
2608 enable_intr = 1;
2609 credits = 0;
2610 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2611 int j;
2612 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2613 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2614 if (credits >= budget) {
2615 enable_intr = 0;
2616 goto rx_comp;
2617 }
2618 }
2619 }
2620
2621 rx_comp:
2622 /* final rx completion */
2623 spin_lock_irqsave(&cp->lock, flags);
2624 if (status)
2625 cas_handle_irq(dev, cp, status);
2626
2627 #ifdef USE_PCI_INTB
2628 if (N_RX_COMP_RINGS > 1) {
2629 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2630 if (status)
2631 cas_handle_irq1(dev, cp, status);
2632 }
2633 #endif
2634
2635 #ifdef USE_PCI_INTC
2636 if (N_RX_COMP_RINGS > 2) {
2637 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2638 if (status)
2639 cas_handle_irqN(dev, cp, status, 2);
2640 }
2641 #endif
2642
2643 #ifdef USE_PCI_INTD
2644 if (N_RX_COMP_RINGS > 3) {
2645 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2646 if (status)
2647 cas_handle_irqN(dev, cp, status, 3);
2648 }
2649 #endif
2650 spin_unlock_irqrestore(&cp->lock, flags);
2651 if (enable_intr) {
2652 napi_complete(napi);
2653 cas_unmask_intr(cp);
2654 }
2655 return credits;
2656 }
2657 #endif
2658
2659 #ifdef CONFIG_NET_POLL_CONTROLLER
2660 static void cas_netpoll(struct net_device *dev)
2661 {
2662 struct cas *cp = netdev_priv(dev);
2663
2664 cas_disable_irq(cp, 0);
2665 cas_interrupt(cp->pdev->irq, dev);
2666 cas_enable_irq(cp, 0);
2667
2668 #ifdef USE_PCI_INTB
2669 if (N_RX_COMP_RINGS > 1) {
2670 /* cas_interrupt1(); */
2671 }
2672 #endif
2673 #ifdef USE_PCI_INTC
2674 if (N_RX_COMP_RINGS > 2) {
2675 /* cas_interruptN(); */
2676 }
2677 #endif
2678 #ifdef USE_PCI_INTD
2679 if (N_RX_COMP_RINGS > 3) {
2680 /* cas_interruptN(); */
2681 }
2682 #endif
2683 }
2684 #endif
2685
2686 static void cas_tx_timeout(struct net_device *dev)
2687 {
2688 struct cas *cp = netdev_priv(dev);
2689
2690 netdev_err(dev, "transmit timed out, resetting\n");
2691 if (!cp->hw_running) {
2692 netdev_err(dev, "hrm.. hw not running!\n");
2693 return;
2694 }
2695
2696 netdev_err(dev, "MIF_STATE[%08x]\n",
2697 readl(cp->regs + REG_MIF_STATE_MACHINE));
2698
2699 netdev_err(dev, "MAC_STATE[%08x]\n",
2700 readl(cp->regs + REG_MAC_STATE_MACHINE));
2701
2702 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2703 readl(cp->regs + REG_TX_CFG),
2704 readl(cp->regs + REG_MAC_TX_STATUS),
2705 readl(cp->regs + REG_MAC_TX_CFG),
2706 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2707 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2708 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2709 readl(cp->regs + REG_TX_SM_1),
2710 readl(cp->regs + REG_TX_SM_2));
2711
2712 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2713 readl(cp->regs + REG_RX_CFG),
2714 readl(cp->regs + REG_MAC_RX_STATUS),
2715 readl(cp->regs + REG_MAC_RX_CFG));
2716
2717 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2718 readl(cp->regs + REG_HP_STATE_MACHINE),
2719 readl(cp->regs + REG_HP_STATUS0),
2720 readl(cp->regs + REG_HP_STATUS1),
2721 readl(cp->regs + REG_HP_STATUS2));
2722
2723 #if 1
2724 atomic_inc(&cp->reset_task_pending);
2725 atomic_inc(&cp->reset_task_pending_all);
2726 schedule_work(&cp->reset_task);
2727 #else
2728 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2729 schedule_work(&cp->reset_task);
2730 #endif
2731 }
2732
2733 static inline int cas_intme(int ring, int entry)
2734 {
2735 /* Algorithm: IRQ every 1/2 of descriptors. */
2736 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2737 return 1;
2738 return 0;
2739 }
2740
2741
2742 static void cas_write_txd(struct cas *cp, int ring, int entry,
2743 dma_addr_t mapping, int len, u64 ctrl, int last)
2744 {
2745 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2746
2747 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2748 if (cas_intme(ring, entry))
2749 ctrl |= TX_DESC_INTME;
2750 if (last)
2751 ctrl |= TX_DESC_EOF;
2752 txd->control = cpu_to_le64(ctrl);
2753 txd->buffer = cpu_to_le64(mapping);
2754 }
2755
2756 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2757 const int entry)
2758 {
2759 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2760 }
2761
2762 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2763 const int entry, const int tentry)
2764 {
2765 cp->tx_tiny_use[ring][tentry].nbufs++;
2766 cp->tx_tiny_use[ring][entry].used = 1;
2767 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2768 }
2769
2770 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2771 struct sk_buff *skb)
2772 {
2773 struct net_device *dev = cp->dev;
2774 int entry, nr_frags, frag, tabort, tentry;
2775 dma_addr_t mapping;
2776 unsigned long flags;
2777 u64 ctrl;
2778 u32 len;
2779
2780 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2781
2782 /* This is a hard error, log it. */
2783 if (TX_BUFFS_AVAIL(cp, ring) <=
2784 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2785 netif_stop_queue(dev);
2786 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2787 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2788 return 1;
2789 }
2790
2791 ctrl = 0;
2792 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2793 const u64 csum_start_off = skb_checksum_start_offset(skb);
2794 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2795
2796 ctrl = TX_DESC_CSUM_EN |
2797 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2798 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2799 }
2800
2801 entry = cp->tx_new[ring];
2802 cp->tx_skbs[ring][entry] = skb;
2803
2804 nr_frags = skb_shinfo(skb)->nr_frags;
2805 len = skb_headlen(skb);
2806 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2807 offset_in_page(skb->data), len,
2808 PCI_DMA_TODEVICE);
2809
2810 tentry = entry;
2811 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2812 if (unlikely(tabort)) {
2813 /* NOTE: len is always > tabort */
2814 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2815 ctrl | TX_DESC_SOF, 0);
2816 entry = TX_DESC_NEXT(ring, entry);
2817
2818 skb_copy_from_linear_data_offset(skb, len - tabort,
2819 tx_tiny_buf(cp, ring, entry), tabort);
2820 mapping = tx_tiny_map(cp, ring, entry, tentry);
2821 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2822 (nr_frags == 0));
2823 } else {
2824 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2825 TX_DESC_SOF, (nr_frags == 0));
2826 }
2827 entry = TX_DESC_NEXT(ring, entry);
2828
2829 for (frag = 0; frag < nr_frags; frag++) {
2830 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2831
2832 len = fragp->size;
2833 mapping = pci_map_page(cp->pdev, fragp->page,
2834 fragp->page_offset, len,
2835 PCI_DMA_TODEVICE);
2836
2837 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2838 if (unlikely(tabort)) {
2839 void *addr;
2840
2841 /* NOTE: len is always > tabort */
2842 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2843 ctrl, 0);
2844 entry = TX_DESC_NEXT(ring, entry);
2845
2846 addr = cas_page_map(fragp->page);
2847 memcpy(tx_tiny_buf(cp, ring, entry),
2848 addr + fragp->page_offset + len - tabort,
2849 tabort);
2850 cas_page_unmap(addr);
2851 mapping = tx_tiny_map(cp, ring, entry, tentry);
2852 len = tabort;
2853 }
2854
2855 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2856 (frag + 1 == nr_frags));
2857 entry = TX_DESC_NEXT(ring, entry);
2858 }
2859
2860 cp->tx_new[ring] = entry;
2861 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2862 netif_stop_queue(dev);
2863
2864 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2865 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2866 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2867 writel(entry, cp->regs + REG_TX_KICKN(ring));
2868 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2869 return 0;
2870 }
2871
2872 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2873 {
2874 struct cas *cp = netdev_priv(dev);
2875
2876 /* this is only used as a load-balancing hint, so it doesn't
2877 * need to be SMP safe
2878 */
2879 static int ring;
2880
2881 if (skb_padto(skb, cp->min_frame_size))
2882 return NETDEV_TX_OK;
2883
2884 /* XXX: we need some higher-level QoS hooks to steer packets to
2885 * individual queues.
2886 */
2887 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2888 return NETDEV_TX_BUSY;
2889 return NETDEV_TX_OK;
2890 }
2891
2892 static void cas_init_tx_dma(struct cas *cp)
2893 {
2894 u64 desc_dma = cp->block_dvma;
2895 unsigned long off;
2896 u32 val;
2897 int i;
2898
2899 /* set up tx completion writeback registers. must be 8-byte aligned */
2900 #ifdef USE_TX_COMPWB
2901 off = offsetof(struct cas_init_block, tx_compwb);
2902 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2903 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2904 #endif
2905
2906 /* enable completion writebacks, enable paced mode,
2907 * disable read pipe, and disable pre-interrupt compwbs
2908 */
2909 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2910 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2911 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2912 TX_CFG_INTR_COMPWB_DIS;
2913
2914 /* write out tx ring info and tx desc bases */
2915 for (i = 0; i < MAX_TX_RINGS; i++) {
2916 off = (unsigned long) cp->init_txds[i] -
2917 (unsigned long) cp->init_block;
2918
2919 val |= CAS_TX_RINGN_BASE(i);
2920 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2921 writel((desc_dma + off) & 0xffffffff, cp->regs +
2922 REG_TX_DBN_LOW(i));
2923 /* don't zero out the kick register here as the system
2924 * will wedge
2925 */
2926 }
2927 writel(val, cp->regs + REG_TX_CFG);
2928
2929 /* program max burst sizes. these numbers should be different
2930 * if doing QoS.
2931 */
2932 #ifdef USE_QOS
2933 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2934 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2935 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2936 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2937 #else
2938 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2939 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2940 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2941 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2942 #endif
2943 }
2944
2945 /* Must be invoked under cp->lock. */
2946 static inline void cas_init_dma(struct cas *cp)
2947 {
2948 cas_init_tx_dma(cp);
2949 cas_init_rx_dma(cp);
2950 }
2951
2952 static void cas_process_mc_list(struct cas *cp)
2953 {
2954 u16 hash_table[16];
2955 u32 crc;
2956 struct netdev_hw_addr *ha;
2957 int i = 1;
2958
2959 memset(hash_table, 0, sizeof(hash_table));
2960 netdev_for_each_mc_addr(ha, cp->dev) {
2961 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2962 /* use the alternate mac address registers for the
2963 * first 15 multicast addresses
2964 */
2965 writel((ha->addr[4] << 8) | ha->addr[5],
2966 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2967 writel((ha->addr[2] << 8) | ha->addr[3],
2968 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2969 writel((ha->addr[0] << 8) | ha->addr[1],
2970 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2971 i++;
2972 }
2973 else {
2974 /* use hw hash table for the next series of
2975 * multicast addresses
2976 */
2977 crc = ether_crc_le(ETH_ALEN, ha->addr);
2978 crc >>= 24;
2979 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2980 }
2981 }
2982 for (i = 0; i < 16; i++)
2983 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2984 }
2985
2986 /* Must be invoked under cp->lock. */
2987 static u32 cas_setup_multicast(struct cas *cp)
2988 {
2989 u32 rxcfg = 0;
2990 int i;
2991
2992 if (cp->dev->flags & IFF_PROMISC) {
2993 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2994
2995 } else if (cp->dev->flags & IFF_ALLMULTI) {
2996 for (i=0; i < 16; i++)
2997 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2998 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2999
3000 } else {
3001 cas_process_mc_list(cp);
3002 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3003 }
3004
3005 return rxcfg;
3006 }
3007
3008 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3009 static void cas_clear_mac_err(struct cas *cp)
3010 {
3011 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3012 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3013 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3014 writel(0, cp->regs + REG_MAC_COLL_LATE);
3015 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3016 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3017 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3018 writel(0, cp->regs + REG_MAC_LEN_ERR);
3019 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3020 writel(0, cp->regs + REG_MAC_FCS_ERR);
3021 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3022 }
3023
3024
3025 static void cas_mac_reset(struct cas *cp)
3026 {
3027 int i;
3028
3029 /* do both TX and RX reset */
3030 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3031 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3032
3033 /* wait for TX */
3034 i = STOP_TRIES;
3035 while (i-- > 0) {
3036 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3037 break;
3038 udelay(10);
3039 }
3040
3041 /* wait for RX */
3042 i = STOP_TRIES;
3043 while (i-- > 0) {
3044 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3045 break;
3046 udelay(10);
3047 }
3048
3049 if (readl(cp->regs + REG_MAC_TX_RESET) |
3050 readl(cp->regs + REG_MAC_RX_RESET))
3051 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3052 readl(cp->regs + REG_MAC_TX_RESET),
3053 readl(cp->regs + REG_MAC_RX_RESET),
3054 readl(cp->regs + REG_MAC_STATE_MACHINE));
3055 }
3056
3057
3058 /* Must be invoked under cp->lock. */
3059 static void cas_init_mac(struct cas *cp)
3060 {
3061 unsigned char *e = &cp->dev->dev_addr[0];
3062 int i;
3063 cas_mac_reset(cp);
3064
3065 /* setup core arbitration weight register */
3066 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3067
3068 /* XXX Use pci_dma_burst_advice() */
3069 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3070 /* set the infinite burst register for chips that don't have
3071 * pci issues.
3072 */
3073 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3074 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3075 #endif
3076
3077 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3078
3079 writel(0x00, cp->regs + REG_MAC_IPG0);
3080 writel(0x08, cp->regs + REG_MAC_IPG1);
3081 writel(0x04, cp->regs + REG_MAC_IPG2);
3082
3083 /* change later for 802.3z */
3084 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3085
3086 /* min frame + FCS */
3087 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3088
3089 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3090 * specify the maximum frame size to prevent RX tag errors on
3091 * oversized frames.
3092 */
3093 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3094 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3095 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3096 cp->regs + REG_MAC_FRAMESIZE_MAX);
3097
3098 /* NOTE: crc_size is used as a surrogate for half-duplex.
3099 * workaround saturn half-duplex issue by increasing preamble
3100 * size to 65 bytes.
3101 */
3102 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3103 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3104 else
3105 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3106 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3107 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3108 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3109
3110 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3111
3112 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3113 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3114 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3115 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3116 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3117
3118 /* setup mac address in perfect filter array */
3119 for (i = 0; i < 45; i++)
3120 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3121
3122 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3123 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3124 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3125
3126 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3127 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3128 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3129
3130 cp->mac_rx_cfg = cas_setup_multicast(cp);
3131
3132 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3133 cas_clear_mac_err(cp);
3134 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3135
3136 /* Setup MAC interrupts. We want to get all of the interesting
3137 * counter expiration events, but we do not want to hear about
3138 * normal rx/tx as the DMA engine tells us that.
3139 */
3140 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3141 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3142
3143 /* Don't enable even the PAUSE interrupts for now, we
3144 * make no use of those events other than to record them.
3145 */
3146 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3147 }
3148
3149 /* Must be invoked under cp->lock. */
3150 static void cas_init_pause_thresholds(struct cas *cp)
3151 {
3152 /* Calculate pause thresholds. Setting the OFF threshold to the
3153 * full RX fifo size effectively disables PAUSE generation
3154 */
3155 if (cp->rx_fifo_size <= (2 * 1024)) {
3156 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3157 } else {
3158 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3159 if (max_frame * 3 > cp->rx_fifo_size) {
3160 cp->rx_pause_off = 7104;
3161 cp->rx_pause_on = 960;
3162 } else {
3163 int off = (cp->rx_fifo_size - (max_frame * 2));
3164 int on = off - max_frame;
3165 cp->rx_pause_off = off;
3166 cp->rx_pause_on = on;
3167 }
3168 }
3169 }
3170
3171 static int cas_vpd_match(const void __iomem *p, const char *str)
3172 {
3173 int len = strlen(str) + 1;
3174 int i;
3175
3176 for (i = 0; i < len; i++) {
3177 if (readb(p + i) != str[i])
3178 return 0;
3179 }
3180 return 1;
3181 }
3182
3183
3184 /* get the mac address by reading the vpd information in the rom.
3185 * also get the phy type and determine if there's an entropy generator.
3186 * NOTE: this is a bit convoluted for the following reasons:
3187 * 1) vpd info has order-dependent mac addresses for multinic cards
3188 * 2) the only way to determine the nic order is to use the slot
3189 * number.
3190 * 3) fiber cards don't have bridges, so their slot numbers don't
3191 * mean anything.
3192 * 4) we don't actually know we have a fiber card until after
3193 * the mac addresses are parsed.
3194 */
3195 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3196 const int offset)
3197 {
3198 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3199 void __iomem *base, *kstart;
3200 int i, len;
3201 int found = 0;
3202 #define VPD_FOUND_MAC 0x01
3203 #define VPD_FOUND_PHY 0x02
3204
3205 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3206 int mac_off = 0;
3207
3208 #if defined(CONFIG_SPARC)
3209 const unsigned char *addr;
3210 #endif
3211
3212 /* give us access to the PROM */
3213 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3214 cp->regs + REG_BIM_LOCAL_DEV_EN);
3215
3216 /* check for an expansion rom */
3217 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3218 goto use_random_mac_addr;
3219
3220 /* search for beginning of vpd */
3221 base = NULL;
3222 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3223 /* check for PCIR */
3224 if ((readb(p + i + 0) == 0x50) &&
3225 (readb(p + i + 1) == 0x43) &&
3226 (readb(p + i + 2) == 0x49) &&
3227 (readb(p + i + 3) == 0x52)) {
3228 base = p + (readb(p + i + 8) |
3229 (readb(p + i + 9) << 8));
3230 break;
3231 }
3232 }
3233
3234 if (!base || (readb(base) != 0x82))
3235 goto use_random_mac_addr;
3236
3237 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3238 while (i < EXPANSION_ROM_SIZE) {
3239 if (readb(base + i) != 0x90) /* no vpd found */
3240 goto use_random_mac_addr;
3241
3242 /* found a vpd field */
3243 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3244
3245 /* extract keywords */
3246 kstart = base + i + 3;
3247 p = kstart;
3248 while ((p - kstart) < len) {
3249 int klen = readb(p + 2);
3250 int j;
3251 char type;
3252
3253 p += 3;
3254
3255 /* look for the following things:
3256 * -- correct length == 29
3257 * 3 (type) + 2 (size) +
3258 * 18 (strlen("local-mac-address") + 1) +
3259 * 6 (mac addr)
3260 * -- VPD Instance 'I'
3261 * -- VPD Type Bytes 'B'
3262 * -- VPD data length == 6
3263 * -- property string == local-mac-address
3264 *
3265 * -- correct length == 24
3266 * 3 (type) + 2 (size) +
3267 * 12 (strlen("entropy-dev") + 1) +
3268 * 7 (strlen("vms110") + 1)
3269 * -- VPD Instance 'I'
3270 * -- VPD Type String 'B'
3271 * -- VPD data length == 7
3272 * -- property string == entropy-dev
3273 *
3274 * -- correct length == 18
3275 * 3 (type) + 2 (size) +
3276 * 9 (strlen("phy-type") + 1) +
3277 * 4 (strlen("pcs") + 1)
3278 * -- VPD Instance 'I'
3279 * -- VPD Type String 'S'
3280 * -- VPD data length == 4
3281 * -- property string == phy-type
3282 *
3283 * -- correct length == 23
3284 * 3 (type) + 2 (size) +
3285 * 14 (strlen("phy-interface") + 1) +
3286 * 4 (strlen("pcs") + 1)
3287 * -- VPD Instance 'I'
3288 * -- VPD Type String 'S'
3289 * -- VPD data length == 4
3290 * -- property string == phy-interface
3291 */
3292 if (readb(p) != 'I')
3293 goto next;
3294
3295 /* finally, check string and length */
3296 type = readb(p + 3);
3297 if (type == 'B') {
3298 if ((klen == 29) && readb(p + 4) == 6 &&
3299 cas_vpd_match(p + 5,
3300 "local-mac-address")) {
3301 if (mac_off++ > offset)
3302 goto next;
3303
3304 /* set mac address */
3305 for (j = 0; j < 6; j++)
3306 dev_addr[j] =
3307 readb(p + 23 + j);
3308 goto found_mac;
3309 }
3310 }
3311
3312 if (type != 'S')
3313 goto next;
3314
3315 #ifdef USE_ENTROPY_DEV
3316 if ((klen == 24) &&
3317 cas_vpd_match(p + 5, "entropy-dev") &&
3318 cas_vpd_match(p + 17, "vms110")) {
3319 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3320 goto next;
3321 }
3322 #endif
3323
3324 if (found & VPD_FOUND_PHY)
3325 goto next;
3326
3327 if ((klen == 18) && readb(p + 4) == 4 &&
3328 cas_vpd_match(p + 5, "phy-type")) {
3329 if (cas_vpd_match(p + 14, "pcs")) {
3330 phy_type = CAS_PHY_SERDES;
3331 goto found_phy;
3332 }
3333 }
3334
3335 if ((klen == 23) && readb(p + 4) == 4 &&
3336 cas_vpd_match(p + 5, "phy-interface")) {
3337 if (cas_vpd_match(p + 19, "pcs")) {
3338 phy_type = CAS_PHY_SERDES;
3339 goto found_phy;
3340 }
3341 }
3342 found_mac:
3343 found |= VPD_FOUND_MAC;
3344 goto next;
3345
3346 found_phy:
3347 found |= VPD_FOUND_PHY;
3348
3349 next:
3350 p += klen;
3351 }
3352 i += len + 3;
3353 }
3354
3355 use_random_mac_addr:
3356 if (found & VPD_FOUND_MAC)
3357 goto done;
3358
3359 #if defined(CONFIG_SPARC)
3360 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3361 if (addr != NULL) {
3362 memcpy(dev_addr, addr, 6);
3363 goto done;
3364 }
3365 #endif
3366
3367 /* Sun MAC prefix then 3 random bytes. */
3368 pr_info("MAC address not found in ROM VPD\n");
3369 dev_addr[0] = 0x08;
3370 dev_addr[1] = 0x00;
3371 dev_addr[2] = 0x20;
3372 get_random_bytes(dev_addr + 3, 3);
3373
3374 done:
3375 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3376 return phy_type;
3377 }
3378
3379 /* check pci invariants */
3380 static void cas_check_pci_invariants(struct cas *cp)
3381 {
3382 struct pci_dev *pdev = cp->pdev;
3383
3384 cp->cas_flags = 0;
3385 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3386 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3387 if (pdev->revision >= CAS_ID_REVPLUS)
3388 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3389 if (pdev->revision < CAS_ID_REVPLUS02u)
3390 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3391
3392 /* Original Cassini supports HW CSUM, but it's not
3393 * enabled by default as it can trigger TX hangs.
3394 */
3395 if (pdev->revision < CAS_ID_REV2)
3396 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3397 } else {
3398 /* Only sun has original cassini chips. */
3399 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3400
3401 /* We use a flag because the same phy might be externally
3402 * connected.
3403 */
3404 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3405 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3406 cp->cas_flags |= CAS_FLAG_SATURN;
3407 }
3408 }
3409
3410
3411 static int cas_check_invariants(struct cas *cp)
3412 {
3413 struct pci_dev *pdev = cp->pdev;
3414 u32 cfg;
3415 int i;
3416
3417 /* get page size for rx buffers. */
3418 cp->page_order = 0;
3419 #ifdef USE_PAGE_ORDER
3420 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3421 /* see if we can allocate larger pages */
3422 struct page *page = alloc_pages(GFP_ATOMIC,
3423 CAS_JUMBO_PAGE_SHIFT -
3424 PAGE_SHIFT);
3425 if (page) {
3426 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3427 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3428 } else {
3429 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3430 }
3431 }
3432 #endif
3433 cp->page_size = (PAGE_SIZE << cp->page_order);
3434
3435 /* Fetch the FIFO configurations. */
3436 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3437 cp->rx_fifo_size = RX_FIFO_SIZE;
3438
3439 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3440 * they're both connected.
3441 */
3442 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3443 PCI_SLOT(pdev->devfn));
3444 if (cp->phy_type & CAS_PHY_SERDES) {
3445 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3446 return 0; /* no more checking needed */
3447 }
3448
3449 /* MII */
3450 cfg = readl(cp->regs + REG_MIF_CFG);
3451 if (cfg & MIF_CFG_MDIO_1) {
3452 cp->phy_type = CAS_PHY_MII_MDIO1;
3453 } else if (cfg & MIF_CFG_MDIO_0) {
3454 cp->phy_type = CAS_PHY_MII_MDIO0;
3455 }
3456
3457 cas_mif_poll(cp, 0);
3458 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3459
3460 for (i = 0; i < 32; i++) {
3461 u32 phy_id;
3462 int j;
3463
3464 for (j = 0; j < 3; j++) {
3465 cp->phy_addr = i;
3466 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3467 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3468 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3469 cp->phy_id = phy_id;
3470 goto done;
3471 }
3472 }
3473 }
3474 pr_err("MII phy did not respond [%08x]\n",
3475 readl(cp->regs + REG_MIF_STATE_MACHINE));
3476 return -1;
3477
3478 done:
3479 /* see if we can do gigabit */
3480 cfg = cas_phy_read(cp, MII_BMSR);
3481 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3482 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3483 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3484 return 0;
3485 }
3486
3487 /* Must be invoked under cp->lock. */
3488 static inline void cas_start_dma(struct cas *cp)
3489 {
3490 int i;
3491 u32 val;
3492 int txfailed = 0;
3493
3494 /* enable dma */
3495 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3496 writel(val, cp->regs + REG_TX_CFG);
3497 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3498 writel(val, cp->regs + REG_RX_CFG);
3499
3500 /* enable the mac */
3501 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3502 writel(val, cp->regs + REG_MAC_TX_CFG);
3503 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3504 writel(val, cp->regs + REG_MAC_RX_CFG);
3505
3506 i = STOP_TRIES;
3507 while (i-- > 0) {
3508 val = readl(cp->regs + REG_MAC_TX_CFG);
3509 if ((val & MAC_TX_CFG_EN))
3510 break;
3511 udelay(10);
3512 }
3513 if (i < 0) txfailed = 1;
3514 i = STOP_TRIES;
3515 while (i-- > 0) {
3516 val = readl(cp->regs + REG_MAC_RX_CFG);
3517 if ((val & MAC_RX_CFG_EN)) {
3518 if (txfailed) {
3519 netdev_err(cp->dev,
3520 "enabling mac failed [tx:%08x:%08x]\n",
3521 readl(cp->regs + REG_MIF_STATE_MACHINE),
3522 readl(cp->regs + REG_MAC_STATE_MACHINE));
3523 }
3524 goto enable_rx_done;
3525 }
3526 udelay(10);
3527 }
3528 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3529 (txfailed ? "tx,rx" : "rx"),
3530 readl(cp->regs + REG_MIF_STATE_MACHINE),
3531 readl(cp->regs + REG_MAC_STATE_MACHINE));
3532
3533 enable_rx_done:
3534 cas_unmask_intr(cp); /* enable interrupts */
3535 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3536 writel(0, cp->regs + REG_RX_COMP_TAIL);
3537
3538 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3539 if (N_RX_DESC_RINGS > 1)
3540 writel(RX_DESC_RINGN_SIZE(1) - 4,
3541 cp->regs + REG_PLUS_RX_KICK1);
3542
3543 for (i = 1; i < N_RX_COMP_RINGS; i++)
3544 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3545 }
3546 }
3547
3548 /* Must be invoked under cp->lock. */
3549 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3550 int *pause)
3551 {
3552 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3553 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3554 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3555 if (val & PCS_MII_LPA_ASYM_PAUSE)
3556 *pause |= 0x10;
3557 *spd = 1000;
3558 }
3559
3560 /* Must be invoked under cp->lock. */
3561 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3562 int *pause)
3563 {
3564 u32 val;
3565
3566 *fd = 0;
3567 *spd = 10;
3568 *pause = 0;
3569
3570 /* use GMII registers */
3571 val = cas_phy_read(cp, MII_LPA);
3572 if (val & CAS_LPA_PAUSE)
3573 *pause = 0x01;
3574
3575 if (val & CAS_LPA_ASYM_PAUSE)
3576 *pause |= 0x10;
3577
3578 if (val & LPA_DUPLEX)
3579 *fd = 1;
3580 if (val & LPA_100)
3581 *spd = 100;
3582
3583 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3584 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3585 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3586 *spd = 1000;
3587 if (val & CAS_LPA_1000FULL)
3588 *fd = 1;
3589 }
3590 }
3591
3592 /* A link-up condition has occurred, initialize and enable the
3593 * rest of the chip.
3594 *
3595 * Must be invoked under cp->lock.
3596 */
3597 static void cas_set_link_modes(struct cas *cp)
3598 {
3599 u32 val;
3600 int full_duplex, speed, pause;
3601
3602 full_duplex = 0;
3603 speed = 10;
3604 pause = 0;
3605
3606 if (CAS_PHY_MII(cp->phy_type)) {
3607 cas_mif_poll(cp, 0);
3608 val = cas_phy_read(cp, MII_BMCR);
3609 if (val & BMCR_ANENABLE) {
3610 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3611 &pause);
3612 } else {
3613 if (val & BMCR_FULLDPLX)
3614 full_duplex = 1;
3615
3616 if (val & BMCR_SPEED100)
3617 speed = 100;
3618 else if (val & CAS_BMCR_SPEED1000)
3619 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3620 1000 : 100;
3621 }
3622 cas_mif_poll(cp, 1);
3623
3624 } else {
3625 val = readl(cp->regs + REG_PCS_MII_CTRL);
3626 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3627 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3628 if (val & PCS_MII_CTRL_DUPLEX)
3629 full_duplex = 1;
3630 }
3631 }
3632
3633 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3634 speed, full_duplex ? "full" : "half");
3635
3636 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3637 if (CAS_PHY_MII(cp->phy_type)) {
3638 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3639 if (!full_duplex)
3640 val |= MAC_XIF_DISABLE_ECHO;
3641 }
3642 if (full_duplex)
3643 val |= MAC_XIF_FDPLX_LED;
3644 if (speed == 1000)
3645 val |= MAC_XIF_GMII_MODE;
3646 writel(val, cp->regs + REG_MAC_XIF_CFG);
3647
3648 /* deal with carrier and collision detect. */
3649 val = MAC_TX_CFG_IPG_EN;
3650 if (full_duplex) {
3651 val |= MAC_TX_CFG_IGNORE_CARRIER;
3652 val |= MAC_TX_CFG_IGNORE_COLL;
3653 } else {
3654 #ifndef USE_CSMA_CD_PROTO
3655 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3656 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3657 #endif
3658 }
3659 /* val now set up for REG_MAC_TX_CFG */
3660
3661 /* If gigabit and half-duplex, enable carrier extension
3662 * mode. increase slot time to 512 bytes as well.
3663 * else, disable it and make sure slot time is 64 bytes.
3664 * also activate checksum bug workaround
3665 */
3666 if ((speed == 1000) && !full_duplex) {
3667 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3668 cp->regs + REG_MAC_TX_CFG);
3669
3670 val = readl(cp->regs + REG_MAC_RX_CFG);
3671 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3672 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3673 cp->regs + REG_MAC_RX_CFG);
3674
3675 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3676
3677 cp->crc_size = 4;
3678 /* minimum size gigabit frame at half duplex */
3679 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3680
3681 } else {
3682 writel(val, cp->regs + REG_MAC_TX_CFG);
3683
3684 /* checksum bug workaround. don't strip FCS when in
3685 * half-duplex mode
3686 */
3687 val = readl(cp->regs + REG_MAC_RX_CFG);
3688 if (full_duplex) {
3689 val |= MAC_RX_CFG_STRIP_FCS;
3690 cp->crc_size = 0;
3691 cp->min_frame_size = CAS_MIN_MTU;
3692 } else {
3693 val &= ~MAC_RX_CFG_STRIP_FCS;
3694 cp->crc_size = 4;
3695 cp->min_frame_size = CAS_MIN_FRAME;
3696 }
3697 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3698 cp->regs + REG_MAC_RX_CFG);
3699 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3700 }
3701
3702 if (netif_msg_link(cp)) {
3703 if (pause & 0x01) {
3704 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3705 cp->rx_fifo_size,
3706 cp->rx_pause_off,
3707 cp->rx_pause_on);
3708 } else if (pause & 0x10) {
3709 netdev_info(cp->dev, "TX pause enabled\n");
3710 } else {
3711 netdev_info(cp->dev, "Pause is disabled\n");
3712 }
3713 }
3714
3715 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3716 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3717 if (pause) { /* symmetric or asymmetric pause */
3718 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3719 if (pause & 0x01) { /* symmetric pause */
3720 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3721 }
3722 }
3723 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3724 cas_start_dma(cp);
3725 }
3726
3727 /* Must be invoked under cp->lock. */
3728 static void cas_init_hw(struct cas *cp, int restart_link)
3729 {
3730 if (restart_link)
3731 cas_phy_init(cp);
3732
3733 cas_init_pause_thresholds(cp);
3734 cas_init_mac(cp);
3735 cas_init_dma(cp);
3736
3737 if (restart_link) {
3738 /* Default aneg parameters */
3739 cp->timer_ticks = 0;
3740 cas_begin_auto_negotiation(cp, NULL);
3741 } else if (cp->lstate == link_up) {
3742 cas_set_link_modes(cp);
3743 netif_carrier_on(cp->dev);
3744 }
3745 }
3746
3747 /* Must be invoked under cp->lock. on earlier cassini boards,
3748 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3749 * let it settle out, and then restore pci state.
3750 */
3751 static void cas_hard_reset(struct cas *cp)
3752 {
3753 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3754 udelay(20);
3755 pci_restore_state(cp->pdev);
3756 }
3757
3758
3759 static void cas_global_reset(struct cas *cp, int blkflag)
3760 {
3761 int limit;
3762
3763 /* issue a global reset. don't use RSTOUT. */
3764 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3765 /* For PCS, when the blkflag is set, we should set the
3766 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3767 * the last autonegotiation from being cleared. We'll
3768 * need some special handling if the chip is set into a
3769 * loopback mode.
3770 */
3771 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3772 cp->regs + REG_SW_RESET);
3773 } else {
3774 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3775 }
3776
3777 /* need to wait at least 3ms before polling register */
3778 mdelay(3);
3779
3780 limit = STOP_TRIES;
3781 while (limit-- > 0) {
3782 u32 val = readl(cp->regs + REG_SW_RESET);
3783 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3784 goto done;
3785 udelay(10);
3786 }
3787 netdev_err(cp->dev, "sw reset failed\n");
3788
3789 done:
3790 /* enable various BIM interrupts */
3791 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3792 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3793
3794 /* clear out pci error status mask for handled errors.
3795 * we don't deal with DMA counter overflows as they happen
3796 * all the time.
3797 */
3798 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3799 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3800 PCI_ERR_BIM_DMA_READ), cp->regs +
3801 REG_PCI_ERR_STATUS_MASK);
3802
3803 /* set up for MII by default to address mac rx reset timeout
3804 * issue
3805 */
3806 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3807 }
3808
3809 static void cas_reset(struct cas *cp, int blkflag)
3810 {
3811 u32 val;
3812
3813 cas_mask_intr(cp);
3814 cas_global_reset(cp, blkflag);
3815 cas_mac_reset(cp);
3816 cas_entropy_reset(cp);
3817
3818 /* disable dma engines. */
3819 val = readl(cp->regs + REG_TX_CFG);
3820 val &= ~TX_CFG_DMA_EN;
3821 writel(val, cp->regs + REG_TX_CFG);
3822
3823 val = readl(cp->regs + REG_RX_CFG);
3824 val &= ~RX_CFG_DMA_EN;
3825 writel(val, cp->regs + REG_RX_CFG);
3826
3827 /* program header parser */
3828 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3829 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3830 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3831 } else {
3832 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3833 }
3834
3835 /* clear out error registers */
3836 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3837 cas_clear_mac_err(cp);
3838 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3839 }
3840
3841 /* Shut down the chip, must be called with pm_mutex held. */
3842 static void cas_shutdown(struct cas *cp)
3843 {
3844 unsigned long flags;
3845
3846 /* Make us not-running to avoid timers respawning */
3847 cp->hw_running = 0;
3848
3849 del_timer_sync(&cp->link_timer);
3850
3851 /* Stop the reset task */
3852 #if 0
3853 while (atomic_read(&cp->reset_task_pending_mtu) ||
3854 atomic_read(&cp->reset_task_pending_spare) ||
3855 atomic_read(&cp->reset_task_pending_all))
3856 schedule();
3857
3858 #else
3859 while (atomic_read(&cp->reset_task_pending))
3860 schedule();
3861 #endif
3862 /* Actually stop the chip */
3863 cas_lock_all_save(cp, flags);
3864 cas_reset(cp, 0);
3865 if (cp->cas_flags & CAS_FLAG_SATURN)
3866 cas_phy_powerdown(cp);
3867 cas_unlock_all_restore(cp, flags);
3868 }
3869
3870 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3871 {
3872 struct cas *cp = netdev_priv(dev);
3873
3874 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3875 return -EINVAL;
3876
3877 dev->mtu = new_mtu;
3878 if (!netif_running(dev) || !netif_device_present(dev))
3879 return 0;
3880
3881 /* let the reset task handle it */
3882 #if 1
3883 atomic_inc(&cp->reset_task_pending);
3884 if ((cp->phy_type & CAS_PHY_SERDES)) {
3885 atomic_inc(&cp->reset_task_pending_all);
3886 } else {
3887 atomic_inc(&cp->reset_task_pending_mtu);
3888 }
3889 schedule_work(&cp->reset_task);
3890 #else
3891 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3892 CAS_RESET_ALL : CAS_RESET_MTU);
3893 pr_err("reset called in cas_change_mtu\n");
3894 schedule_work(&cp->reset_task);
3895 #endif
3896
3897 flush_work_sync(&cp->reset_task);
3898 return 0;
3899 }
3900
3901 static void cas_clean_txd(struct cas *cp, int ring)
3902 {
3903 struct cas_tx_desc *txd = cp->init_txds[ring];
3904 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3905 u64 daddr, dlen;
3906 int i, size;
3907
3908 size = TX_DESC_RINGN_SIZE(ring);
3909 for (i = 0; i < size; i++) {
3910 int frag;
3911
3912 if (skbs[i] == NULL)
3913 continue;
3914
3915 skb = skbs[i];
3916 skbs[i] = NULL;
3917
3918 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3919 int ent = i & (size - 1);
3920
3921 /* first buffer is never a tiny buffer and so
3922 * needs to be unmapped.
3923 */
3924 daddr = le64_to_cpu(txd[ent].buffer);
3925 dlen = CAS_VAL(TX_DESC_BUFLEN,
3926 le64_to_cpu(txd[ent].control));
3927 pci_unmap_page(cp->pdev, daddr, dlen,
3928 PCI_DMA_TODEVICE);
3929
3930 if (frag != skb_shinfo(skb)->nr_frags) {
3931 i++;
3932
3933 /* next buffer might by a tiny buffer.
3934 * skip past it.
3935 */
3936 ent = i & (size - 1);
3937 if (cp->tx_tiny_use[ring][ent].used)
3938 i++;
3939 }
3940 }
3941 dev_kfree_skb_any(skb);
3942 }
3943
3944 /* zero out tiny buf usage */
3945 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3946 }
3947
3948 /* freed on close */
3949 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3950 {
3951 cas_page_t **page = cp->rx_pages[ring];
3952 int i, size;
3953
3954 size = RX_DESC_RINGN_SIZE(ring);
3955 for (i = 0; i < size; i++) {
3956 if (page[i]) {
3957 cas_page_free(cp, page[i]);
3958 page[i] = NULL;
3959 }
3960 }
3961 }
3962
3963 static void cas_free_rxds(struct cas *cp)
3964 {
3965 int i;
3966
3967 for (i = 0; i < N_RX_DESC_RINGS; i++)
3968 cas_free_rx_desc(cp, i);
3969 }
3970
3971 /* Must be invoked under cp->lock. */
3972 static void cas_clean_rings(struct cas *cp)
3973 {
3974 int i;
3975
3976 /* need to clean all tx rings */
3977 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3978 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3979 for (i = 0; i < N_TX_RINGS; i++)
3980 cas_clean_txd(cp, i);
3981
3982 /* zero out init block */
3983 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3984 cas_clean_rxds(cp);
3985 cas_clean_rxcs(cp);
3986 }
3987
3988 /* allocated on open */
3989 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3990 {
3991 cas_page_t **page = cp->rx_pages[ring];
3992 int size, i = 0;
3993
3994 size = RX_DESC_RINGN_SIZE(ring);
3995 for (i = 0; i < size; i++) {
3996 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3997 return -1;
3998 }
3999 return 0;
4000 }
4001
4002 static int cas_alloc_rxds(struct cas *cp)
4003 {
4004 int i;
4005
4006 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4007 if (cas_alloc_rx_desc(cp, i) < 0) {
4008 cas_free_rxds(cp);
4009 return -1;
4010 }
4011 }
4012 return 0;
4013 }
4014
4015 static void cas_reset_task(struct work_struct *work)
4016 {
4017 struct cas *cp = container_of(work, struct cas, reset_task);
4018 #if 0
4019 int pending = atomic_read(&cp->reset_task_pending);
4020 #else
4021 int pending_all = atomic_read(&cp->reset_task_pending_all);
4022 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4023 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4024
4025 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4026 /* We can have more tasks scheduled than actually
4027 * needed.
4028 */
4029 atomic_dec(&cp->reset_task_pending);
4030 return;
4031 }
4032 #endif
4033 /* The link went down, we reset the ring, but keep
4034 * DMA stopped. Use this function for reset
4035 * on error as well.
4036 */
4037 if (cp->hw_running) {
4038 unsigned long flags;
4039
4040 /* Make sure we don't get interrupts or tx packets */
4041 netif_device_detach(cp->dev);
4042 cas_lock_all_save(cp, flags);
4043
4044 if (cp->opened) {
4045 /* We call cas_spare_recover when we call cas_open.
4046 * but we do not initialize the lists cas_spare_recover
4047 * uses until cas_open is called.
4048 */
4049 cas_spare_recover(cp, GFP_ATOMIC);
4050 }
4051 #if 1
4052 /* test => only pending_spare set */
4053 if (!pending_all && !pending_mtu)
4054 goto done;
4055 #else
4056 if (pending == CAS_RESET_SPARE)
4057 goto done;
4058 #endif
4059 /* when pending == CAS_RESET_ALL, the following
4060 * call to cas_init_hw will restart auto negotiation.
4061 * Setting the second argument of cas_reset to
4062 * !(pending == CAS_RESET_ALL) will set this argument
4063 * to 1 (avoiding reinitializing the PHY for the normal
4064 * PCS case) when auto negotiation is not restarted.
4065 */
4066 #if 1
4067 cas_reset(cp, !(pending_all > 0));
4068 if (cp->opened)
4069 cas_clean_rings(cp);
4070 cas_init_hw(cp, (pending_all > 0));
4071 #else
4072 cas_reset(cp, !(pending == CAS_RESET_ALL));
4073 if (cp->opened)
4074 cas_clean_rings(cp);
4075 cas_init_hw(cp, pending == CAS_RESET_ALL);
4076 #endif
4077
4078 done:
4079 cas_unlock_all_restore(cp, flags);
4080 netif_device_attach(cp->dev);
4081 }
4082 #if 1
4083 atomic_sub(pending_all, &cp->reset_task_pending_all);
4084 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4085 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4086 atomic_dec(&cp->reset_task_pending);
4087 #else
4088 atomic_set(&cp->reset_task_pending, 0);
4089 #endif
4090 }
4091
4092 static void cas_link_timer(unsigned long data)
4093 {
4094 struct cas *cp = (struct cas *) data;
4095 int mask, pending = 0, reset = 0;
4096 unsigned long flags;
4097
4098 if (link_transition_timeout != 0 &&
4099 cp->link_transition_jiffies_valid &&
4100 ((jiffies - cp->link_transition_jiffies) >
4101 (link_transition_timeout))) {
4102 /* One-second counter so link-down workaround doesn't
4103 * cause resets to occur so fast as to fool the switch
4104 * into thinking the link is down.
4105 */
4106 cp->link_transition_jiffies_valid = 0;
4107 }
4108
4109 if (!cp->hw_running)
4110 return;
4111
4112 spin_lock_irqsave(&cp->lock, flags);
4113 cas_lock_tx(cp);
4114 cas_entropy_gather(cp);
4115
4116 /* If the link task is still pending, we just
4117 * reschedule the link timer
4118 */
4119 #if 1
4120 if (atomic_read(&cp->reset_task_pending_all) ||
4121 atomic_read(&cp->reset_task_pending_spare) ||
4122 atomic_read(&cp->reset_task_pending_mtu))
4123 goto done;
4124 #else
4125 if (atomic_read(&cp->reset_task_pending))
4126 goto done;
4127 #endif
4128
4129 /* check for rx cleaning */
4130 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4131 int i, rmask;
4132
4133 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4134 rmask = CAS_FLAG_RXD_POST(i);
4135 if ((mask & rmask) == 0)
4136 continue;
4137
4138 /* post_rxds will do a mod_timer */
4139 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4140 pending = 1;
4141 continue;
4142 }
4143 cp->cas_flags &= ~rmask;
4144 }
4145 }
4146
4147 if (CAS_PHY_MII(cp->phy_type)) {
4148 u16 bmsr;
4149 cas_mif_poll(cp, 0);
4150 bmsr = cas_phy_read(cp, MII_BMSR);
4151 /* WTZ: Solaris driver reads this twice, but that
4152 * may be due to the PCS case and the use of a
4153 * common implementation. Read it twice here to be
4154 * safe.
4155 */
4156 bmsr = cas_phy_read(cp, MII_BMSR);
4157 cas_mif_poll(cp, 1);
4158 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4159 reset = cas_mii_link_check(cp, bmsr);
4160 } else {
4161 reset = cas_pcs_link_check(cp);
4162 }
4163
4164 if (reset)
4165 goto done;
4166
4167 /* check for tx state machine confusion */
4168 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4169 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4170 u32 wptr, rptr;
4171 int tlm = CAS_VAL(MAC_SM_TLM, val);
4172
4173 if (((tlm == 0x5) || (tlm == 0x3)) &&
4174 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4175 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4176 "tx err: MAC_STATE[%08x]\n", val);
4177 reset = 1;
4178 goto done;
4179 }
4180
4181 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4182 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4183 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4184 if ((val == 0) && (wptr != rptr)) {
4185 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4186 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4187 val, wptr, rptr);
4188 reset = 1;
4189 }
4190
4191 if (reset)
4192 cas_hard_reset(cp);
4193 }
4194
4195 done:
4196 if (reset) {
4197 #if 1
4198 atomic_inc(&cp->reset_task_pending);
4199 atomic_inc(&cp->reset_task_pending_all);
4200 schedule_work(&cp->reset_task);
4201 #else
4202 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4203 pr_err("reset called in cas_link_timer\n");
4204 schedule_work(&cp->reset_task);
4205 #endif
4206 }
4207
4208 if (!pending)
4209 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4210 cas_unlock_tx(cp);
4211 spin_unlock_irqrestore(&cp->lock, flags);
4212 }
4213
4214 /* tiny buffers are used to avoid target abort issues with
4215 * older cassini's
4216 */
4217 static void cas_tx_tiny_free(struct cas *cp)
4218 {
4219 struct pci_dev *pdev = cp->pdev;
4220 int i;
4221
4222 for (i = 0; i < N_TX_RINGS; i++) {
4223 if (!cp->tx_tiny_bufs[i])
4224 continue;
4225
4226 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4227 cp->tx_tiny_bufs[i],
4228 cp->tx_tiny_dvma[i]);
4229 cp->tx_tiny_bufs[i] = NULL;
4230 }
4231 }
4232
4233 static int cas_tx_tiny_alloc(struct cas *cp)
4234 {
4235 struct pci_dev *pdev = cp->pdev;
4236 int i;
4237
4238 for (i = 0; i < N_TX_RINGS; i++) {
4239 cp->tx_tiny_bufs[i] =
4240 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4241 &cp->tx_tiny_dvma[i]);
4242 if (!cp->tx_tiny_bufs[i]) {
4243 cas_tx_tiny_free(cp);
4244 return -1;
4245 }
4246 }
4247 return 0;
4248 }
4249
4250
4251 static int cas_open(struct net_device *dev)
4252 {
4253 struct cas *cp = netdev_priv(dev);
4254 int hw_was_up, err;
4255 unsigned long flags;
4256
4257 mutex_lock(&cp->pm_mutex);
4258
4259 hw_was_up = cp->hw_running;
4260
4261 /* The power-management mutex protects the hw_running
4262 * etc. state so it is safe to do this bit without cp->lock
4263 */
4264 if (!cp->hw_running) {
4265 /* Reset the chip */
4266 cas_lock_all_save(cp, flags);
4267 /* We set the second arg to cas_reset to zero
4268 * because cas_init_hw below will have its second
4269 * argument set to non-zero, which will force
4270 * autonegotiation to start.
4271 */
4272 cas_reset(cp, 0);
4273 cp->hw_running = 1;
4274 cas_unlock_all_restore(cp, flags);
4275 }
4276
4277 err = -ENOMEM;
4278 if (cas_tx_tiny_alloc(cp) < 0)
4279 goto err_unlock;
4280
4281 /* alloc rx descriptors */
4282 if (cas_alloc_rxds(cp) < 0)
4283 goto err_tx_tiny;
4284
4285 /* allocate spares */
4286 cas_spare_init(cp);
4287 cas_spare_recover(cp, GFP_KERNEL);
4288
4289 /* We can now request the interrupt as we know it's masked
4290 * on the controller. cassini+ has up to 4 interrupts
4291 * that can be used, but you need to do explicit pci interrupt
4292 * mapping to expose them
4293 */
4294 if (request_irq(cp->pdev->irq, cas_interrupt,
4295 IRQF_SHARED, dev->name, (void *) dev)) {
4296 netdev_err(cp->dev, "failed to request irq !\n");
4297 err = -EAGAIN;
4298 goto err_spare;
4299 }
4300
4301 #ifdef USE_NAPI
4302 napi_enable(&cp->napi);
4303 #endif
4304 /* init hw */
4305 cas_lock_all_save(cp, flags);
4306 cas_clean_rings(cp);
4307 cas_init_hw(cp, !hw_was_up);
4308 cp->opened = 1;
4309 cas_unlock_all_restore(cp, flags);
4310
4311 netif_start_queue(dev);
4312 mutex_unlock(&cp->pm_mutex);
4313 return 0;
4314
4315 err_spare:
4316 cas_spare_free(cp);
4317 cas_free_rxds(cp);
4318 err_tx_tiny:
4319 cas_tx_tiny_free(cp);
4320 err_unlock:
4321 mutex_unlock(&cp->pm_mutex);
4322 return err;
4323 }
4324
4325 static int cas_close(struct net_device *dev)
4326 {
4327 unsigned long flags;
4328 struct cas *cp = netdev_priv(dev);
4329
4330 #ifdef USE_NAPI
4331 napi_disable(&cp->napi);
4332 #endif
4333 /* Make sure we don't get distracted by suspend/resume */
4334 mutex_lock(&cp->pm_mutex);
4335
4336 netif_stop_queue(dev);
4337
4338 /* Stop traffic, mark us closed */
4339 cas_lock_all_save(cp, flags);
4340 cp->opened = 0;
4341 cas_reset(cp, 0);
4342 cas_phy_init(cp);
4343 cas_begin_auto_negotiation(cp, NULL);
4344 cas_clean_rings(cp);
4345 cas_unlock_all_restore(cp, flags);
4346
4347 free_irq(cp->pdev->irq, (void *) dev);
4348 cas_spare_free(cp);
4349 cas_free_rxds(cp);
4350 cas_tx_tiny_free(cp);
4351 mutex_unlock(&cp->pm_mutex);
4352 return 0;
4353 }
4354
4355 static struct {
4356 const char name[ETH_GSTRING_LEN];
4357 } ethtool_cassini_statnames[] = {
4358 {"collisions"},
4359 {"rx_bytes"},
4360 {"rx_crc_errors"},
4361 {"rx_dropped"},
4362 {"rx_errors"},
4363 {"rx_fifo_errors"},
4364 {"rx_frame_errors"},
4365 {"rx_length_errors"},
4366 {"rx_over_errors"},
4367 {"rx_packets"},
4368 {"tx_aborted_errors"},
4369 {"tx_bytes"},
4370 {"tx_dropped"},
4371 {"tx_errors"},
4372 {"tx_fifo_errors"},
4373 {"tx_packets"}
4374 };
4375 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4376
4377 static struct {
4378 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4379 } ethtool_register_table[] = {
4380 {-MII_BMSR},
4381 {-MII_BMCR},
4382 {REG_CAWR},
4383 {REG_INF_BURST},
4384 {REG_BIM_CFG},
4385 {REG_RX_CFG},
4386 {REG_HP_CFG},
4387 {REG_MAC_TX_CFG},
4388 {REG_MAC_RX_CFG},
4389 {REG_MAC_CTRL_CFG},
4390 {REG_MAC_XIF_CFG},
4391 {REG_MIF_CFG},
4392 {REG_PCS_CFG},
4393 {REG_SATURN_PCFG},
4394 {REG_PCS_MII_STATUS},
4395 {REG_PCS_STATE_MACHINE},
4396 {REG_MAC_COLL_EXCESS},
4397 {REG_MAC_COLL_LATE}
4398 };
4399 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4400 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4401
4402 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4403 {
4404 u8 *p;
4405 int i;
4406 unsigned long flags;
4407
4408 spin_lock_irqsave(&cp->lock, flags);
4409 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4410 u16 hval;
4411 u32 val;
4412 if (ethtool_register_table[i].offsets < 0) {
4413 hval = cas_phy_read(cp,
4414 -ethtool_register_table[i].offsets);
4415 val = hval;
4416 } else {
4417 val= readl(cp->regs+ethtool_register_table[i].offsets);
4418 }
4419 memcpy(p, (u8 *)&val, sizeof(u32));
4420 }
4421 spin_unlock_irqrestore(&cp->lock, flags);
4422 }
4423
4424 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4425 {
4426 struct cas *cp = netdev_priv(dev);
4427 struct net_device_stats *stats = cp->net_stats;
4428 unsigned long flags;
4429 int i;
4430 unsigned long tmp;
4431
4432 /* we collate all of the stats into net_stats[N_TX_RING] */
4433 if (!cp->hw_running)
4434 return stats + N_TX_RINGS;
4435
4436 /* collect outstanding stats */
4437 /* WTZ: the Cassini spec gives these as 16 bit counters but
4438 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4439 * in case the chip somehow puts any garbage in the other bits.
4440 * Also, counter usage didn't seem to mach what Adrian did
4441 * in the parts of the code that set these quantities. Made
4442 * that consistent.
4443 */
4444 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4445 stats[N_TX_RINGS].rx_crc_errors +=
4446 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4447 stats[N_TX_RINGS].rx_frame_errors +=
4448 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4449 stats[N_TX_RINGS].rx_length_errors +=
4450 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4451 #if 1
4452 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4453 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4454 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4455 stats[N_TX_RINGS].collisions +=
4456 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4457 #else
4458 stats[N_TX_RINGS].tx_aborted_errors +=
4459 readl(cp->regs + REG_MAC_COLL_EXCESS);
4460 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4461 readl(cp->regs + REG_MAC_COLL_LATE);
4462 #endif
4463 cas_clear_mac_err(cp);
4464
4465 /* saved bits that are unique to ring 0 */
4466 spin_lock(&cp->stat_lock[0]);
4467 stats[N_TX_RINGS].collisions += stats[0].collisions;
4468 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4469 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4470 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4471 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4472 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4473 spin_unlock(&cp->stat_lock[0]);
4474
4475 for (i = 0; i < N_TX_RINGS; i++) {
4476 spin_lock(&cp->stat_lock[i]);
4477 stats[N_TX_RINGS].rx_length_errors +=
4478 stats[i].rx_length_errors;
4479 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4480 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4481 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4482 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4483 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4484 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4485 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4486 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4487 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4488 memset(stats + i, 0, sizeof(struct net_device_stats));
4489 spin_unlock(&cp->stat_lock[i]);
4490 }
4491 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4492 return stats + N_TX_RINGS;
4493 }
4494
4495
4496 static void cas_set_multicast(struct net_device *dev)
4497 {
4498 struct cas *cp = netdev_priv(dev);
4499 u32 rxcfg, rxcfg_new;
4500 unsigned long flags;
4501 int limit = STOP_TRIES;
4502
4503 if (!cp->hw_running)
4504 return;
4505
4506 spin_lock_irqsave(&cp->lock, flags);
4507 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4508
4509 /* disable RX MAC and wait for completion */
4510 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4511 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4512 if (!limit--)
4513 break;
4514 udelay(10);
4515 }
4516
4517 /* disable hash filter and wait for completion */
4518 limit = STOP_TRIES;
4519 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4520 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4521 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4522 if (!limit--)
4523 break;
4524 udelay(10);
4525 }
4526
4527 /* program hash filters */
4528 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4529 rxcfg |= rxcfg_new;
4530 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4531 spin_unlock_irqrestore(&cp->lock, flags);
4532 }
4533
4534 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4535 {
4536 struct cas *cp = netdev_priv(dev);
4537 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4538 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4539 info->fw_version[0] = '\0';
4540 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4541 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4542 cp->casreg_len : CAS_MAX_REGS;
4543 info->n_stats = CAS_NUM_STAT_KEYS;
4544 }
4545
4546 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4547 {
4548 struct cas *cp = netdev_priv(dev);
4549 u16 bmcr;
4550 int full_duplex, speed, pause;
4551 unsigned long flags;
4552 enum link_state linkstate = link_up;
4553
4554 cmd->advertising = 0;
4555 cmd->supported = SUPPORTED_Autoneg;
4556 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4557 cmd->supported |= SUPPORTED_1000baseT_Full;
4558 cmd->advertising |= ADVERTISED_1000baseT_Full;
4559 }
4560
4561 /* Record PHY settings if HW is on. */
4562 spin_lock_irqsave(&cp->lock, flags);
4563 bmcr = 0;
4564 linkstate = cp->lstate;
4565 if (CAS_PHY_MII(cp->phy_type)) {
4566 cmd->port = PORT_MII;
4567 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4568 XCVR_INTERNAL : XCVR_EXTERNAL;
4569 cmd->phy_address = cp->phy_addr;
4570 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4571 ADVERTISED_10baseT_Half |
4572 ADVERTISED_10baseT_Full |
4573 ADVERTISED_100baseT_Half |
4574 ADVERTISED_100baseT_Full;
4575
4576 cmd->supported |=
4577 (SUPPORTED_10baseT_Half |
4578 SUPPORTED_10baseT_Full |
4579 SUPPORTED_100baseT_Half |
4580 SUPPORTED_100baseT_Full |
4581 SUPPORTED_TP | SUPPORTED_MII);
4582
4583 if (cp->hw_running) {
4584 cas_mif_poll(cp, 0);
4585 bmcr = cas_phy_read(cp, MII_BMCR);
4586 cas_read_mii_link_mode(cp, &full_duplex,
4587 &speed, &pause);
4588 cas_mif_poll(cp, 1);
4589 }
4590
4591 } else {
4592 cmd->port = PORT_FIBRE;
4593 cmd->transceiver = XCVR_INTERNAL;
4594 cmd->phy_address = 0;
4595 cmd->supported |= SUPPORTED_FIBRE;
4596 cmd->advertising |= ADVERTISED_FIBRE;
4597
4598 if (cp->hw_running) {
4599 /* pcs uses the same bits as mii */
4600 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4601 cas_read_pcs_link_mode(cp, &full_duplex,
4602 &speed, &pause);
4603 }
4604 }
4605 spin_unlock_irqrestore(&cp->lock, flags);
4606
4607 if (bmcr & BMCR_ANENABLE) {
4608 cmd->advertising |= ADVERTISED_Autoneg;
4609 cmd->autoneg = AUTONEG_ENABLE;
4610 ethtool_cmd_speed_set(cmd, ((speed == 10) ?
4611 SPEED_10 :
4612 ((speed == 1000) ?
4613 SPEED_1000 : SPEED_100)));
4614 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4615 } else {
4616 cmd->autoneg = AUTONEG_DISABLE;
4617 ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
4618 SPEED_1000 :
4619 ((bmcr & BMCR_SPEED100) ?
4620 SPEED_100 : SPEED_10)));
4621 cmd->duplex =
4622 (bmcr & BMCR_FULLDPLX) ?
4623 DUPLEX_FULL : DUPLEX_HALF;
4624 }
4625 if (linkstate != link_up) {
4626 /* Force these to "unknown" if the link is not up and
4627 * autonogotiation in enabled. We can set the link
4628 * speed to 0, but not cmd->duplex,
4629 * because its legal values are 0 and 1. Ethtool will
4630 * print the value reported in parentheses after the
4631 * word "Unknown" for unrecognized values.
4632 *
4633 * If in forced mode, we report the speed and duplex
4634 * settings that we configured.
4635 */
4636 if (cp->link_cntl & BMCR_ANENABLE) {
4637 ethtool_cmd_speed_set(cmd, 0);
4638 cmd->duplex = 0xff;
4639 } else {
4640 ethtool_cmd_speed_set(cmd, SPEED_10);
4641 if (cp->link_cntl & BMCR_SPEED100) {
4642 ethtool_cmd_speed_set(cmd, SPEED_100);
4643 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4644 ethtool_cmd_speed_set(cmd, SPEED_1000);
4645 }
4646 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4647 DUPLEX_FULL : DUPLEX_HALF;
4648 }
4649 }
4650 return 0;
4651 }
4652
4653 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4654 {
4655 struct cas *cp = netdev_priv(dev);
4656 unsigned long flags;
4657 u32 speed = ethtool_cmd_speed(cmd);
4658
4659 /* Verify the settings we care about. */
4660 if (cmd->autoneg != AUTONEG_ENABLE &&
4661 cmd->autoneg != AUTONEG_DISABLE)
4662 return -EINVAL;
4663
4664 if (cmd->autoneg == AUTONEG_DISABLE &&
4665 ((speed != SPEED_1000 &&
4666 speed != SPEED_100 &&
4667 speed != SPEED_10) ||
4668 (cmd->duplex != DUPLEX_HALF &&
4669 cmd->duplex != DUPLEX_FULL)))
4670 return -EINVAL;
4671
4672 /* Apply settings and restart link process. */
4673 spin_lock_irqsave(&cp->lock, flags);
4674 cas_begin_auto_negotiation(cp, cmd);
4675 spin_unlock_irqrestore(&cp->lock, flags);
4676 return 0;
4677 }
4678
4679 static int cas_nway_reset(struct net_device *dev)
4680 {
4681 struct cas *cp = netdev_priv(dev);
4682 unsigned long flags;
4683
4684 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4685 return -EINVAL;
4686
4687 /* Restart link process. */
4688 spin_lock_irqsave(&cp->lock, flags);
4689 cas_begin_auto_negotiation(cp, NULL);
4690 spin_unlock_irqrestore(&cp->lock, flags);
4691
4692 return 0;
4693 }
4694
4695 static u32 cas_get_link(struct net_device *dev)
4696 {
4697 struct cas *cp = netdev_priv(dev);
4698 return cp->lstate == link_up;
4699 }
4700
4701 static u32 cas_get_msglevel(struct net_device *dev)
4702 {
4703 struct cas *cp = netdev_priv(dev);
4704 return cp->msg_enable;
4705 }
4706
4707 static void cas_set_msglevel(struct net_device *dev, u32 value)
4708 {
4709 struct cas *cp = netdev_priv(dev);
4710 cp->msg_enable = value;
4711 }
4712
4713 static int cas_get_regs_len(struct net_device *dev)
4714 {
4715 struct cas *cp = netdev_priv(dev);
4716 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4717 }
4718
4719 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4720 void *p)
4721 {
4722 struct cas *cp = netdev_priv(dev);
4723 regs->version = 0;
4724 /* cas_read_regs handles locks (cp->lock). */
4725 cas_read_regs(cp, p, regs->len / sizeof(u32));
4726 }
4727
4728 static int cas_get_sset_count(struct net_device *dev, int sset)
4729 {
4730 switch (sset) {
4731 case ETH_SS_STATS:
4732 return CAS_NUM_STAT_KEYS;
4733 default:
4734 return -EOPNOTSUPP;
4735 }
4736 }
4737
4738 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4739 {
4740 memcpy(data, &ethtool_cassini_statnames,
4741 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4742 }
4743
4744 static void cas_get_ethtool_stats(struct net_device *dev,
4745 struct ethtool_stats *estats, u64 *data)
4746 {
4747 struct cas *cp = netdev_priv(dev);
4748 struct net_device_stats *stats = cas_get_stats(cp->dev);
4749 int i = 0;
4750 data[i++] = stats->collisions;
4751 data[i++] = stats->rx_bytes;
4752 data[i++] = stats->rx_crc_errors;
4753 data[i++] = stats->rx_dropped;
4754 data[i++] = stats->rx_errors;
4755 data[i++] = stats->rx_fifo_errors;
4756 data[i++] = stats->rx_frame_errors;
4757 data[i++] = stats->rx_length_errors;
4758 data[i++] = stats->rx_over_errors;
4759 data[i++] = stats->rx_packets;
4760 data[i++] = stats->tx_aborted_errors;
4761 data[i++] = stats->tx_bytes;
4762 data[i++] = stats->tx_dropped;
4763 data[i++] = stats->tx_errors;
4764 data[i++] = stats->tx_fifo_errors;
4765 data[i++] = stats->tx_packets;
4766 BUG_ON(i != CAS_NUM_STAT_KEYS);
4767 }
4768
4769 static const struct ethtool_ops cas_ethtool_ops = {
4770 .get_drvinfo = cas_get_drvinfo,
4771 .get_settings = cas_get_settings,
4772 .set_settings = cas_set_settings,
4773 .nway_reset = cas_nway_reset,
4774 .get_link = cas_get_link,
4775 .get_msglevel = cas_get_msglevel,
4776 .set_msglevel = cas_set_msglevel,
4777 .get_regs_len = cas_get_regs_len,
4778 .get_regs = cas_get_regs,
4779 .get_sset_count = cas_get_sset_count,
4780 .get_strings = cas_get_strings,
4781 .get_ethtool_stats = cas_get_ethtool_stats,
4782 };
4783
4784 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4785 {
4786 struct cas *cp = netdev_priv(dev);
4787 struct mii_ioctl_data *data = if_mii(ifr);
4788 unsigned long flags;
4789 int rc = -EOPNOTSUPP;
4790
4791 /* Hold the PM mutex while doing ioctl's or we may collide
4792 * with open/close and power management and oops.
4793 */
4794 mutex_lock(&cp->pm_mutex);
4795 switch (cmd) {
4796 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4797 data->phy_id = cp->phy_addr;
4798 /* Fallthrough... */
4799
4800 case SIOCGMIIREG: /* Read MII PHY register. */
4801 spin_lock_irqsave(&cp->lock, flags);
4802 cas_mif_poll(cp, 0);
4803 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4804 cas_mif_poll(cp, 1);
4805 spin_unlock_irqrestore(&cp->lock, flags);
4806 rc = 0;
4807 break;
4808
4809 case SIOCSMIIREG: /* Write MII PHY register. */
4810 spin_lock_irqsave(&cp->lock, flags);
4811 cas_mif_poll(cp, 0);
4812 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4813 cas_mif_poll(cp, 1);
4814 spin_unlock_irqrestore(&cp->lock, flags);
4815 break;
4816 default:
4817 break;
4818 }
4819
4820 mutex_unlock(&cp->pm_mutex);
4821 return rc;
4822 }
4823
4824 /* When this chip sits underneath an Intel 31154 bridge, it is the
4825 * only subordinate device and we can tweak the bridge settings to
4826 * reflect that fact.
4827 */
4828 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4829 {
4830 struct pci_dev *pdev = cas_pdev->bus->self;
4831 u32 val;
4832
4833 if (!pdev)
4834 return;
4835
4836 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4837 return;
4838
4839 /* Clear bit 10 (Bus Parking Control) in the Secondary
4840 * Arbiter Control/Status Register which lives at offset
4841 * 0x41. Using a 32-bit word read/modify/write at 0x40
4842 * is much simpler so that's how we do this.
4843 */
4844 pci_read_config_dword(pdev, 0x40, &val);
4845 val &= ~0x00040000;
4846 pci_write_config_dword(pdev, 0x40, val);
4847
4848 /* Max out the Multi-Transaction Timer settings since
4849 * Cassini is the only device present.
4850 *
4851 * The register is 16-bit and lives at 0x50. When the
4852 * settings are enabled, it extends the GRANT# signal
4853 * for a requestor after a transaction is complete. This
4854 * allows the next request to run without first needing
4855 * to negotiate the GRANT# signal back.
4856 *
4857 * Bits 12:10 define the grant duration:
4858 *
4859 * 1 -- 16 clocks
4860 * 2 -- 32 clocks
4861 * 3 -- 64 clocks
4862 * 4 -- 128 clocks
4863 * 5 -- 256 clocks
4864 *
4865 * All other values are illegal.
4866 *
4867 * Bits 09:00 define which REQ/GNT signal pairs get the
4868 * GRANT# signal treatment. We set them all.
4869 */
4870 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4871
4872 /* The Read Prefecth Policy register is 16-bit and sits at
4873 * offset 0x52. It enables a "smart" pre-fetch policy. We
4874 * enable it and max out all of the settings since only one
4875 * device is sitting underneath and thus bandwidth sharing is
4876 * not an issue.
4877 *
4878 * The register has several 3 bit fields, which indicates a
4879 * multiplier applied to the base amount of prefetching the
4880 * chip would do. These fields are at:
4881 *
4882 * 15:13 --- ReRead Primary Bus
4883 * 12:10 --- FirstRead Primary Bus
4884 * 09:07 --- ReRead Secondary Bus
4885 * 06:04 --- FirstRead Secondary Bus
4886 *
4887 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4888 * get enabled on. Bit 3 is a grouped enabler which controls
4889 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4890 * the individual REQ/GNT pairs [2:0].
4891 */
4892 pci_write_config_word(pdev, 0x52,
4893 (0x7 << 13) |
4894 (0x7 << 10) |
4895 (0x7 << 7) |
4896 (0x7 << 4) |
4897 (0xf << 0));
4898
4899 /* Force cacheline size to 0x8 */
4900 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4901
4902 /* Force latency timer to maximum setting so Cassini can
4903 * sit on the bus as long as it likes.
4904 */
4905 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4906 }
4907
4908 static const struct net_device_ops cas_netdev_ops = {
4909 .ndo_open = cas_open,
4910 .ndo_stop = cas_close,
4911 .ndo_start_xmit = cas_start_xmit,
4912 .ndo_get_stats = cas_get_stats,
4913 .ndo_set_multicast_list = cas_set_multicast,
4914 .ndo_do_ioctl = cas_ioctl,
4915 .ndo_tx_timeout = cas_tx_timeout,
4916 .ndo_change_mtu = cas_change_mtu,
4917 .ndo_set_mac_address = eth_mac_addr,
4918 .ndo_validate_addr = eth_validate_addr,
4919 #ifdef CONFIG_NET_POLL_CONTROLLER
4920 .ndo_poll_controller = cas_netpoll,
4921 #endif
4922 };
4923
4924 static int __devinit cas_init_one(struct pci_dev *pdev,
4925 const struct pci_device_id *ent)
4926 {
4927 static int cas_version_printed = 0;
4928 unsigned long casreg_len;
4929 struct net_device *dev;
4930 struct cas *cp;
4931 int i, err, pci_using_dac;
4932 u16 pci_cmd;
4933 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4934
4935 if (cas_version_printed++ == 0)
4936 pr_info("%s", version);
4937
4938 err = pci_enable_device(pdev);
4939 if (err) {
4940 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4941 return err;
4942 }
4943
4944 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4945 dev_err(&pdev->dev, "Cannot find proper PCI device "
4946 "base address, aborting\n");
4947 err = -ENODEV;
4948 goto err_out_disable_pdev;
4949 }
4950
4951 dev = alloc_etherdev(sizeof(*cp));
4952 if (!dev) {
4953 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
4954 err = -ENOMEM;
4955 goto err_out_disable_pdev;
4956 }
4957 SET_NETDEV_DEV(dev, &pdev->dev);
4958
4959 err = pci_request_regions(pdev, dev->name);
4960 if (err) {
4961 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4962 goto err_out_free_netdev;
4963 }
4964 pci_set_master(pdev);
4965
4966 /* we must always turn on parity response or else parity
4967 * doesn't get generated properly. disable SERR/PERR as well.
4968 * in addition, we want to turn MWI on.
4969 */
4970 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4971 pci_cmd &= ~PCI_COMMAND_SERR;
4972 pci_cmd |= PCI_COMMAND_PARITY;
4973 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4974 if (pci_try_set_mwi(pdev))
4975 pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
4976
4977 cas_program_bridge(pdev);
4978
4979 /*
4980 * On some architectures, the default cache line size set
4981 * by pci_try_set_mwi reduces perforamnce. We have to increase
4982 * it for this case. To start, we'll print some configuration
4983 * data.
4984 */
4985 #if 1
4986 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4987 &orig_cacheline_size);
4988 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4989 cas_cacheline_size =
4990 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4991 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4992 if (pci_write_config_byte(pdev,
4993 PCI_CACHE_LINE_SIZE,
4994 cas_cacheline_size)) {
4995 dev_err(&pdev->dev, "Could not set PCI cache "
4996 "line size\n");
4997 goto err_write_cacheline;
4998 }
4999 }
5000 #endif
5001
5002
5003 /* Configure DMA attributes. */
5004 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5005 pci_using_dac = 1;
5006 err = pci_set_consistent_dma_mask(pdev,
5007 DMA_BIT_MASK(64));
5008 if (err < 0) {
5009 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5010 "for consistent allocations\n");
5011 goto err_out_free_res;
5012 }
5013
5014 } else {
5015 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5016 if (err) {
5017 dev_err(&pdev->dev, "No usable DMA configuration, "
5018 "aborting\n");
5019 goto err_out_free_res;
5020 }
5021 pci_using_dac = 0;
5022 }
5023
5024 casreg_len = pci_resource_len(pdev, 0);
5025
5026 cp = netdev_priv(dev);
5027 cp->pdev = pdev;
5028 #if 1
5029 /* A value of 0 indicates we never explicitly set it */
5030 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5031 #endif
5032 cp->dev = dev;
5033 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5034 cassini_debug;
5035
5036 #if defined(CONFIG_SPARC)
5037 cp->of_node = pci_device_to_OF_node(pdev);
5038 #endif
5039
5040 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5041 cp->link_transition_jiffies_valid = 0;
5042
5043 spin_lock_init(&cp->lock);
5044 spin_lock_init(&cp->rx_inuse_lock);
5045 spin_lock_init(&cp->rx_spare_lock);
5046 for (i = 0; i < N_TX_RINGS; i++) {
5047 spin_lock_init(&cp->stat_lock[i]);
5048 spin_lock_init(&cp->tx_lock[i]);
5049 }
5050 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5051 mutex_init(&cp->pm_mutex);
5052
5053 init_timer(&cp->link_timer);
5054 cp->link_timer.function = cas_link_timer;
5055 cp->link_timer.data = (unsigned long) cp;
5056
5057 #if 1
5058 /* Just in case the implementation of atomic operations
5059 * change so that an explicit initialization is necessary.
5060 */
5061 atomic_set(&cp->reset_task_pending, 0);
5062 atomic_set(&cp->reset_task_pending_all, 0);
5063 atomic_set(&cp->reset_task_pending_spare, 0);
5064 atomic_set(&cp->reset_task_pending_mtu, 0);
5065 #endif
5066 INIT_WORK(&cp->reset_task, cas_reset_task);
5067
5068 /* Default link parameters */
5069 if (link_mode >= 0 && link_mode < 6)
5070 cp->link_cntl = link_modes[link_mode];
5071 else
5072 cp->link_cntl = BMCR_ANENABLE;
5073 cp->lstate = link_down;
5074 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5075 netif_carrier_off(cp->dev);
5076 cp->timer_ticks = 0;
5077
5078 /* give us access to cassini registers */
5079 cp->regs = pci_iomap(pdev, 0, casreg_len);
5080 if (!cp->regs) {
5081 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5082 goto err_out_free_res;
5083 }
5084 cp->casreg_len = casreg_len;
5085
5086 pci_save_state(pdev);
5087 cas_check_pci_invariants(cp);
5088 cas_hard_reset(cp);
5089 cas_reset(cp, 0);
5090 if (cas_check_invariants(cp))
5091 goto err_out_iounmap;
5092 if (cp->cas_flags & CAS_FLAG_SATURN)
5093 if (cas_saturn_firmware_init(cp))
5094 goto err_out_iounmap;
5095
5096 cp->init_block = (struct cas_init_block *)
5097 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5098 &cp->block_dvma);
5099 if (!cp->init_block) {
5100 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5101 goto err_out_iounmap;
5102 }
5103
5104 for (i = 0; i < N_TX_RINGS; i++)
5105 cp->init_txds[i] = cp->init_block->txds[i];
5106
5107 for (i = 0; i < N_RX_DESC_RINGS; i++)
5108 cp->init_rxds[i] = cp->init_block->rxds[i];
5109
5110 for (i = 0; i < N_RX_COMP_RINGS; i++)
5111 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5112
5113 for (i = 0; i < N_RX_FLOWS; i++)
5114 skb_queue_head_init(&cp->rx_flows[i]);
5115
5116 dev->netdev_ops = &cas_netdev_ops;
5117 dev->ethtool_ops = &cas_ethtool_ops;
5118 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5119
5120 #ifdef USE_NAPI
5121 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5122 #endif
5123 dev->irq = pdev->irq;
5124 dev->dma = 0;
5125
5126 /* Cassini features. */
5127 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5128 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5129
5130 if (pci_using_dac)
5131 dev->features |= NETIF_F_HIGHDMA;
5132
5133 if (register_netdev(dev)) {
5134 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5135 goto err_out_free_consistent;
5136 }
5137
5138 i = readl(cp->regs + REG_BIM_CFG);
5139 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5140 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5141 (i & BIM_CFG_32BIT) ? "32" : "64",
5142 (i & BIM_CFG_66MHZ) ? "66" : "33",
5143 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5144 dev->dev_addr);
5145
5146 pci_set_drvdata(pdev, dev);
5147 cp->hw_running = 1;
5148 cas_entropy_reset(cp);
5149 cas_phy_init(cp);
5150 cas_begin_auto_negotiation(cp, NULL);
5151 return 0;
5152
5153 err_out_free_consistent:
5154 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5155 cp->init_block, cp->block_dvma);
5156
5157 err_out_iounmap:
5158 mutex_lock(&cp->pm_mutex);
5159 if (cp->hw_running)
5160 cas_shutdown(cp);
5161 mutex_unlock(&cp->pm_mutex);
5162
5163 pci_iounmap(pdev, cp->regs);
5164
5165
5166 err_out_free_res:
5167 pci_release_regions(pdev);
5168
5169 err_write_cacheline:
5170 /* Try to restore it in case the error occurred after we
5171 * set it.
5172 */
5173 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5174
5175 err_out_free_netdev:
5176 free_netdev(dev);
5177
5178 err_out_disable_pdev:
5179 pci_disable_device(pdev);
5180 pci_set_drvdata(pdev, NULL);
5181 return -ENODEV;
5182 }
5183
5184 static void __devexit cas_remove_one(struct pci_dev *pdev)
5185 {
5186 struct net_device *dev = pci_get_drvdata(pdev);
5187 struct cas *cp;
5188 if (!dev)
5189 return;
5190
5191 cp = netdev_priv(dev);
5192 unregister_netdev(dev);
5193
5194 if (cp->fw_data)
5195 vfree(cp->fw_data);
5196
5197 mutex_lock(&cp->pm_mutex);
5198 cancel_work_sync(&cp->reset_task);
5199 if (cp->hw_running)
5200 cas_shutdown(cp);
5201 mutex_unlock(&cp->pm_mutex);
5202
5203 #if 1
5204 if (cp->orig_cacheline_size) {
5205 /* Restore the cache line size if we had modified
5206 * it.
5207 */
5208 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5209 cp->orig_cacheline_size);
5210 }
5211 #endif
5212 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5213 cp->init_block, cp->block_dvma);
5214 pci_iounmap(pdev, cp->regs);
5215 free_netdev(dev);
5216 pci_release_regions(pdev);
5217 pci_disable_device(pdev);
5218 pci_set_drvdata(pdev, NULL);
5219 }
5220
5221 #ifdef CONFIG_PM
5222 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5223 {
5224 struct net_device *dev = pci_get_drvdata(pdev);
5225 struct cas *cp = netdev_priv(dev);
5226 unsigned long flags;
5227
5228 mutex_lock(&cp->pm_mutex);
5229
5230 /* If the driver is opened, we stop the DMA */
5231 if (cp->opened) {
5232 netif_device_detach(dev);
5233
5234 cas_lock_all_save(cp, flags);
5235
5236 /* We can set the second arg of cas_reset to 0
5237 * because on resume, we'll call cas_init_hw with
5238 * its second arg set so that autonegotiation is
5239 * restarted.
5240 */
5241 cas_reset(cp, 0);
5242 cas_clean_rings(cp);
5243 cas_unlock_all_restore(cp, flags);
5244 }
5245
5246 if (cp->hw_running)
5247 cas_shutdown(cp);
5248 mutex_unlock(&cp->pm_mutex);
5249
5250 return 0;
5251 }
5252
5253 static int cas_resume(struct pci_dev *pdev)
5254 {
5255 struct net_device *dev = pci_get_drvdata(pdev);
5256 struct cas *cp = netdev_priv(dev);
5257
5258 netdev_info(dev, "resuming\n");
5259
5260 mutex_lock(&cp->pm_mutex);
5261 cas_hard_reset(cp);
5262 if (cp->opened) {
5263 unsigned long flags;
5264 cas_lock_all_save(cp, flags);
5265 cas_reset(cp, 0);
5266 cp->hw_running = 1;
5267 cas_clean_rings(cp);
5268 cas_init_hw(cp, 1);
5269 cas_unlock_all_restore(cp, flags);
5270
5271 netif_device_attach(dev);
5272 }
5273 mutex_unlock(&cp->pm_mutex);
5274 return 0;
5275 }
5276 #endif /* CONFIG_PM */
5277
5278 static struct pci_driver cas_driver = {
5279 .name = DRV_MODULE_NAME,
5280 .id_table = cas_pci_tbl,
5281 .probe = cas_init_one,
5282 .remove = __devexit_p(cas_remove_one),
5283 #ifdef CONFIG_PM
5284 .suspend = cas_suspend,
5285 .resume = cas_resume
5286 #endif
5287 };
5288
5289 static int __init cas_init(void)
5290 {
5291 if (linkdown_timeout > 0)
5292 link_transition_timeout = linkdown_timeout * HZ;
5293 else
5294 link_transition_timeout = 0;
5295
5296 return pci_register_driver(&cas_driver);
5297 }
5298
5299 static void __exit cas_cleanup(void)
5300 {
5301 pci_unregister_driver(&cas_driver);
5302 }
5303
5304 module_init(cas_init);
5305 module_exit(cas_cleanup);
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