drivers/net/davinci_emac.c

   1 /*
   2  * DaVinci Ethernet Medium Access Controller
   3  *
   4  * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
   5  *
   6  * Copyright (C) 2009 Texas Instruments.
   7  *
   8  * ---------------------------------------------------------------------------
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  * ---------------------------------------------------------------------------
  24  * History:
  25  * 0-5 A number of folks worked on this driver in bits and pieces but the major
  26  *     contribution came from Suraj Iyer and Anant Gole
  27  * 6.0 Anant Gole - rewrote the driver as per Linux conventions
  28  * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
  29  *     PHY layer usage
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/sched.h>
  35 #include <linux/string.h>
  36 #include <linux/timer.h>
  37 #include <linux/errno.h>
  38 #include <linux/in.h>
  39 #include <linux/ioport.h>
  40 #include <linux/slab.h>
  41 #include <linux/mm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/init.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/skbuff.h>
  47 #include <linux/ethtool.h>
  48 #include <linux/highmem.h>
  49 #include <linux/proc_fs.h>
  50 #include <linux/ctype.h>
  51 #include <linux/spinlock.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/clk.h>
  54 #include <linux/platform_device.h>
  55 #include <linux/semaphore.h>
  56 #include <linux/phy.h>
  57 #include <linux/bitops.h>
  58 #include <linux/io.h>
  59 #include <linux/uaccess.h>
  60 #include <linux/davinci_emac.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/page.h>
  64
  65 #include "davinci_cpdma.h"
  66
  67 static int debug_level;
  68 module_param(debug_level, int, 0);
  69 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
  70
  71 /* Netif debug messages possible */
  72 #define DAVINCI_EMAC_DEBUG      (NETIF_MSG_DRV | \
  73                                 NETIF_MSG_PROBE | \
  74                                 NETIF_MSG_LINK | \
  75                                 NETIF_MSG_TIMER | \
  76                                 NETIF_MSG_IFDOWN | \
  77                                 NETIF_MSG_IFUP | \
  78                                 NETIF_MSG_RX_ERR | \
  79                                 NETIF_MSG_TX_ERR | \
  80                                 NETIF_MSG_TX_QUEUED | \
  81                                 NETIF_MSG_INTR | \
  82                                 NETIF_MSG_TX_DONE | \
  83                                 NETIF_MSG_RX_STATUS | \
  84                                 NETIF_MSG_PKTDATA | \
  85                                 NETIF_MSG_HW | \
  86                                 NETIF_MSG_WOL)
  87
  88 /* version info */
  89 #define EMAC_MAJOR_VERSION      6
  90 #define EMAC_MINOR_VERSION      1
  91 #define EMAC_MODULE_VERSION     "6.1"
  92 MODULE_VERSION(EMAC_MODULE_VERSION);
  93 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
  94
  95 /* Configuration items */
  96 #define EMAC_DEF_PASS_CRC               (0) /* Do not pass CRC up to frames */
  97 #define EMAC_DEF_QOS_EN                 (0) /* EMAC proprietary QoS disabled */
  98 #define EMAC_DEF_NO_BUFF_CHAIN          (0) /* No buffer chain */
  99 #define EMAC_DEF_MACCTRL_FRAME_EN       (0) /* Discard Maccontrol frames */
 100 #define EMAC_DEF_SHORT_FRAME_EN         (0) /* Discard short frames */
 101 #define EMAC_DEF_ERROR_FRAME_EN         (0) /* Discard error frames */
 102 #define EMAC_DEF_PROM_EN                (0) /* Promiscuous disabled */
 103 #define EMAC_DEF_PROM_CH                (0) /* Promiscuous channel is 0 */
 104 #define EMAC_DEF_BCAST_EN               (1) /* Broadcast enabled */
 105 #define EMAC_DEF_BCAST_CH               (0) /* Broadcast channel is 0 */
 106 #define EMAC_DEF_MCAST_EN               (1) /* Multicast enabled */
 107 #define EMAC_DEF_MCAST_CH               (0) /* Multicast channel is 0 */
 108
 109 #define EMAC_DEF_TXPRIO_FIXED           (1) /* TX Priority is fixed */
 110 #define EMAC_DEF_TXPACING_EN            (0) /* TX pacing NOT supported*/
 111
 112 #define EMAC_DEF_BUFFER_OFFSET          (0) /* Buffer offset to DMA (future) */
 113 #define EMAC_DEF_MIN_ETHPKTSIZE         (60) /* Minimum ethernet pkt size */
 114 #define EMAC_DEF_MAX_FRAME_SIZE         (1500 + 14 + 4 + 4)
 115 #define EMAC_DEF_TX_CH                  (0) /* Default 0th channel */
 116 #define EMAC_DEF_RX_CH                  (0) /* Default 0th channel */
 117 #define EMAC_DEF_RX_NUM_DESC            (128)
 118 #define EMAC_DEF_MAX_TX_CH              (1) /* Max TX channels configured */
 119 #define EMAC_DEF_MAX_RX_CH              (1) /* Max RX channels configured */
 120 #define EMAC_POLL_WEIGHT                (64) /* Default NAPI poll weight */
 121
 122 /* Buffer descriptor parameters */
 123 #define EMAC_DEF_TX_MAX_SERVICE         (32) /* TX max service BD's */
 124 #define EMAC_DEF_RX_MAX_SERVICE         (64) /* should = netdev->weight */
 125
 126 /* EMAC register related defines */
 127 #define EMAC_ALL_MULTI_REG_VALUE        (0xFFFFFFFF)
 128 #define EMAC_NUM_MULTICAST_BITS         (64)
 129 #define EMAC_TX_CONTROL_TX_ENABLE_VAL   (0x1)
 130 #define EMAC_RX_CONTROL_RX_ENABLE_VAL   (0x1)
 131 #define EMAC_MAC_HOST_ERR_INTMASK_VAL   (0x2)
 132 #define EMAC_RX_UNICAST_CLEAR_ALL       (0xFF)
 133 #define EMAC_INT_MASK_CLEAR             (0xFF)
 134
 135 /* RX MBP register bit positions */
 136 #define EMAC_RXMBP_PASSCRC_MASK         BIT(30)
 137 #define EMAC_RXMBP_QOSEN_MASK           BIT(29)
 138 #define EMAC_RXMBP_NOCHAIN_MASK         BIT(28)
 139 #define EMAC_RXMBP_CMFEN_MASK           BIT(24)
 140 #define EMAC_RXMBP_CSFEN_MASK           BIT(23)
 141 #define EMAC_RXMBP_CEFEN_MASK           BIT(22)
 142 #define EMAC_RXMBP_CAFEN_MASK           BIT(21)
 143 #define EMAC_RXMBP_PROMCH_SHIFT         (16)
 144 #define EMAC_RXMBP_PROMCH_MASK          (0x7 << 16)
 145 #define EMAC_RXMBP_BROADEN_MASK         BIT(13)
 146 #define EMAC_RXMBP_BROADCH_SHIFT        (8)
 147 #define EMAC_RXMBP_BROADCH_MASK         (0x7 << 8)
 148 #define EMAC_RXMBP_MULTIEN_MASK         BIT(5)
 149 #define EMAC_RXMBP_MULTICH_SHIFT        (0)
 150 #define EMAC_RXMBP_MULTICH_MASK         (0x7)
 151 #define EMAC_RXMBP_CHMASK               (0x7)
 152
 153 /* EMAC register definitions/bit maps used */
 154 # define EMAC_MBP_RXPROMISC             (0x00200000)
 155 # define EMAC_MBP_PROMISCCH(ch)         (((ch) & 0x7) << 16)
 156 # define EMAC_MBP_RXBCAST               (0x00002000)
 157 # define EMAC_MBP_BCASTCHAN(ch)         (((ch) & 0x7) << 8)
 158 # define EMAC_MBP_RXMCAST               (0x00000020)
 159 # define EMAC_MBP_MCASTCHAN(ch)         ((ch) & 0x7)
 160
 161 /* EMAC mac_control register */
 162 #define EMAC_MACCONTROL_TXPTYPE         BIT(9)
 163 #define EMAC_MACCONTROL_TXPACEEN        BIT(6)
 164 #define EMAC_MACCONTROL_GMIIEN          BIT(5)
 165 #define EMAC_MACCONTROL_GIGABITEN       BIT(7)
 166 #define EMAC_MACCONTROL_FULLDUPLEXEN    BIT(0)
 167 #define EMAC_MACCONTROL_RMIISPEED_MASK  BIT(15)
 168
 169 /* GIGABIT MODE related bits */
 170 #define EMAC_DM646X_MACCONTORL_GIG      BIT(7)
 171 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
 172
 173 /* EMAC mac_status register */
 174 #define EMAC_MACSTATUS_TXERRCODE_MASK   (0xF00000)
 175 #define EMAC_MACSTATUS_TXERRCODE_SHIFT  (20)
 176 #define EMAC_MACSTATUS_TXERRCH_MASK     (0x7)
 177 #define EMAC_MACSTATUS_TXERRCH_SHIFT    (16)
 178 #define EMAC_MACSTATUS_RXERRCODE_MASK   (0xF000)
 179 #define EMAC_MACSTATUS_RXERRCODE_SHIFT  (12)
 180 #define EMAC_MACSTATUS_RXERRCH_MASK     (0x7)
 181 #define EMAC_MACSTATUS_RXERRCH_SHIFT    (8)
 182
 183 /* EMAC RX register masks */
 184 #define EMAC_RX_MAX_LEN_MASK            (0xFFFF)
 185 #define EMAC_RX_BUFFER_OFFSET_MASK      (0xFFFF)
 186
 187 /* MAC_IN_VECTOR (0x180) register bit fields */
 188 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT      BIT(17)
 189 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT  BIT(16)
 190 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC    BIT(8)
 191 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC    BIT(0)
 192
 193 /** NOTE:: For DM646x the IN_VECTOR has changed */
 194 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC    BIT(EMAC_DEF_RX_CH)
 195 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC    BIT(16 + EMAC_DEF_TX_CH)
 196 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT      BIT(26)
 197 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT  BIT(27)
 198
 199 /* CPPI bit positions */
 200 #define EMAC_CPPI_SOP_BIT               BIT(31)
 201 #define EMAC_CPPI_EOP_BIT               BIT(30)
 202 #define EMAC_CPPI_OWNERSHIP_BIT         BIT(29)
 203 #define EMAC_CPPI_EOQ_BIT               BIT(28)
 204 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
 205 #define EMAC_CPPI_PASS_CRC_BIT          BIT(26)
 206 #define EMAC_RX_BD_BUF_SIZE             (0xFFFF)
 207 #define EMAC_BD_LENGTH_FOR_CACHE        (16) /* only CPPI bytes */
 208 #define EMAC_RX_BD_PKT_LENGTH_MASK      (0xFFFF)
 209
 210 /* Max hardware defines */
 211 #define EMAC_MAX_TXRX_CHANNELS           (8)  /* Max hardware channels */
 212 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
 213
 214 /* EMAC Peripheral Device Register Memory Layout structure */
 215 #define EMAC_MACINVECTOR        0x90
 216
 217 #define EMAC_DM646X_MACEOIVECTOR        0x94
 218
 219 #define EMAC_MACINTSTATRAW      0xB0
 220 #define EMAC_MACINTSTATMASKED   0xB4
 221 #define EMAC_MACINTMASKSET      0xB8
 222 #define EMAC_MACINTMASKCLEAR    0xBC
 223
 224 #define EMAC_RXMBPENABLE        0x100
 225 #define EMAC_RXUNICASTSET       0x104
 226 #define EMAC_RXUNICASTCLEAR     0x108
 227 #define EMAC_RXMAXLEN           0x10C
 228 #define EMAC_RXBUFFEROFFSET     0x110
 229 #define EMAC_RXFILTERLOWTHRESH  0x114
 230
 231 #define EMAC_MACCONTROL         0x160
 232 #define EMAC_MACSTATUS          0x164
 233 #define EMAC_EMCONTROL          0x168
 234 #define EMAC_FIFOCONTROL        0x16C
 235 #define EMAC_MACCONFIG          0x170
 236 #define EMAC_SOFTRESET          0x174
 237 #define EMAC_MACSRCADDRLO       0x1D0
 238 #define EMAC_MACSRCADDRHI       0x1D4
 239 #define EMAC_MACHASH1           0x1D8
 240 #define EMAC_MACHASH2           0x1DC
 241 #define EMAC_MACADDRLO          0x500
 242 #define EMAC_MACADDRHI          0x504
 243 #define EMAC_MACINDEX           0x508
 244
 245 /* EMAC statistics registers */
 246 #define EMAC_RXGOODFRAMES       0x200
 247 #define EMAC_RXBCASTFRAMES      0x204
 248 #define EMAC_RXMCASTFRAMES      0x208
 249 #define EMAC_RXPAUSEFRAMES      0x20C
 250 #define EMAC_RXCRCERRORS        0x210
 251 #define EMAC_RXALIGNCODEERRORS  0x214
 252 #define EMAC_RXOVERSIZED        0x218
 253 #define EMAC_RXJABBER           0x21C
 254 #define EMAC_RXUNDERSIZED       0x220
 255 #define EMAC_RXFRAGMENTS        0x224
 256 #define EMAC_RXFILTERED         0x228
 257 #define EMAC_RXQOSFILTERED      0x22C
 258 #define EMAC_RXOCTETS           0x230
 259 #define EMAC_TXGOODFRAMES       0x234
 260 #define EMAC_TXBCASTFRAMES      0x238
 261 #define EMAC_TXMCASTFRAMES      0x23C
 262 #define EMAC_TXPAUSEFRAMES      0x240
 263 #define EMAC_TXDEFERRED         0x244
 264 #define EMAC_TXCOLLISION        0x248
 265 #define EMAC_TXSINGLECOLL       0x24C
 266 #define EMAC_TXMULTICOLL        0x250
 267 #define EMAC_TXEXCESSIVECOLL    0x254
 268 #define EMAC_TXLATECOLL         0x258
 269 #define EMAC_TXUNDERRUN         0x25C
 270 #define EMAC_TXCARRIERSENSE     0x260
 271 #define EMAC_TXOCTETS           0x264
 272 #define EMAC_NETOCTETS          0x280
 273 #define EMAC_RXSOFOVERRUNS      0x284
 274 #define EMAC_RXMOFOVERRUNS      0x288
 275 #define EMAC_RXDMAOVERRUNS      0x28C
 276
 277 /* EMAC DM644x control registers */
 278 #define EMAC_CTRL_EWCTL         (0x4)
 279 #define EMAC_CTRL_EWINTTCNT     (0x8)
 280
 281 /* EMAC DM644x control module masks */
 282 #define EMAC_DM644X_EWINTCNT_MASK       0x1FFFF
 283 #define EMAC_DM644X_INTMIN_INTVL        0x1
 284 #define EMAC_DM644X_INTMAX_INTVL        (EMAC_DM644X_EWINTCNT_MASK)
 285
 286 /* EMAC DM646X control module registers */
 287 #define EMAC_DM646X_CMINTCTRL   0x0C
 288 #define EMAC_DM646X_CMRXINTEN   0x14
 289 #define EMAC_DM646X_CMTXINTEN   0x18
 290 #define EMAC_DM646X_CMRXINTMAX  0x70
 291 #define EMAC_DM646X_CMTXINTMAX  0x74
 292
 293 /* EMAC DM646X control module masks */
 294 #define EMAC_DM646X_INTPACEEN           (0x3 << 16)
 295 #define EMAC_DM646X_INTPRESCALE_MASK    (0x7FF << 0)
 296 #define EMAC_DM646X_CMINTMAX_CNT        63
 297 #define EMAC_DM646X_CMINTMIN_CNT        2
 298 #define EMAC_DM646X_CMINTMAX_INTVL      (1000 / EMAC_DM646X_CMINTMIN_CNT)
 299 #define EMAC_DM646X_CMINTMIN_INTVL      ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
 300
 301
 302 /* EMAC EOI codes for C0 */
 303 #define EMAC_DM646X_MAC_EOI_C0_RXEN     (0x01)
 304 #define EMAC_DM646X_MAC_EOI_C0_TXEN     (0x02)
 305
 306 /* EMAC Stats Clear Mask */
 307 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
 308
 309 /* emac_priv: EMAC private data structure
 310  *
 311  * EMAC adapter private data structure
 312  */
 313 struct emac_priv {
 314         u32 msg_enable;
 315         struct net_device *ndev;
 316         struct platform_device *pdev;
 317         struct napi_struct napi;
 318         char mac_addr[6];
 319         void __iomem *remap_addr;
 320         u32 emac_base_phys;
 321         void __iomem *emac_base;
 322         void __iomem *ctrl_base;
 323         struct cpdma_ctlr *dma;
 324         struct cpdma_chan *txchan;
 325         struct cpdma_chan *rxchan;
 326         u32 link; /* 1=link on, 0=link off */
 327         u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
 328         u32 duplex; /* Link duplex: 0=Half, 1=Full */
 329         u32 rx_buf_size;
 330         u32 isr_count;
 331         u32 coal_intvl;
 332         u32 bus_freq_mhz;
 333         u8 rmii_en;
 334         u8 version;
 335         u32 mac_hash1;
 336         u32 mac_hash2;
 337         u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
 338         u32 rx_addr_type;
 339         const char *phy_id;
 340         struct phy_device *phydev;
 341         spinlock_t lock;
 342         /*platform specific members*/
 343         void (*int_enable) (void);
 344         void (*int_disable) (void);
 345 };
 346
 347 /* clock frequency for EMAC */
 348 static struct clk *emac_clk;
 349 static unsigned long emac_bus_frequency;
 350
 351 /* EMAC TX Host Error description strings */
 352 static char *emac_txhost_errcodes[16] = {
 353         "No error", "SOP error", "Ownership bit not set in SOP buffer",
 354         "Zero Next Buffer Descriptor Pointer Without EOP",
 355         "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
 356         "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
 357         "Reserved", "Reserved", "Reserved", "Reserved"
 358 };
 359
 360 /* EMAC RX Host Error description strings */
 361 static char *emac_rxhost_errcodes[16] = {
 362         "No error", "Reserved", "Ownership bit not set in input buffer",
 363         "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
 364         "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
 365         "Reserved", "Reserved", "Reserved", "Reserved"
 366 };
 367
 368 /* Helper macros */
 369 #define emac_read(reg)            ioread32(priv->emac_base + (reg))
 370 #define emac_write(reg, val)      iowrite32(val, priv->emac_base + (reg))
 371
 372 #define emac_ctrl_read(reg)       ioread32((priv->ctrl_base + (reg)))
 373 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
 374
 375 /**
 376  * emac_dump_regs: Dump important EMAC registers to debug terminal
 377  * @priv: The DaVinci EMAC private adapter structure
 378  *
 379  * Executes ethtool set cmd & sets phy mode
 380  *
 381  */
 382 static void emac_dump_regs(struct emac_priv *priv)
 383 {
 384         struct device *emac_dev = &priv->ndev->dev;
 385
 386         /* Print important registers in EMAC */
 387         dev_info(emac_dev, "EMAC Basic registers\n");
 388         if (priv->version == EMAC_VERSION_1) {
 389                 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
 390                         emac_ctrl_read(EMAC_CTRL_EWCTL),
 391                         emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
 392         }
 393         dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
 394                 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
 395         dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
 396                 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
 397                 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
 398         dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
 399                 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
 400                 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
 401         dev_info(emac_dev, "EMAC Statistics\n");
 402         dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
 403                 emac_read(EMAC_RXGOODFRAMES));
 404         dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
 405                 emac_read(EMAC_RXBCASTFRAMES));
 406         dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
 407                 emac_read(EMAC_RXMCASTFRAMES));
 408         dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
 409                 emac_read(EMAC_RXPAUSEFRAMES));
 410         dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
 411                 emac_read(EMAC_RXCRCERRORS));
 412         dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
 413                 emac_read(EMAC_RXALIGNCODEERRORS));
 414         dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
 415                 emac_read(EMAC_RXOVERSIZED));
 416         dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
 417                 emac_read(EMAC_RXJABBER));
 418         dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
 419                 emac_read(EMAC_RXUNDERSIZED));
 420         dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
 421                 emac_read(EMAC_RXFRAGMENTS));
 422         dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
 423                 emac_read(EMAC_RXFILTERED));
 424         dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
 425                 emac_read(EMAC_RXQOSFILTERED));
 426         dev_info(emac_dev, "EMAC: rx_octets:%d\n",
 427                 emac_read(EMAC_RXOCTETS));
 428         dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
 429                 emac_read(EMAC_TXGOODFRAMES));
 430         dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
 431                 emac_read(EMAC_TXBCASTFRAMES));
 432         dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
 433                 emac_read(EMAC_TXMCASTFRAMES));
 434         dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
 435                 emac_read(EMAC_TXPAUSEFRAMES));
 436         dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
 437                 emac_read(EMAC_TXDEFERRED));
 438         dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
 439                 emac_read(EMAC_TXCOLLISION));
 440         dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
 441                 emac_read(EMAC_TXSINGLECOLL));
 442         dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
 443                 emac_read(EMAC_TXMULTICOLL));
 444         dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
 445                 emac_read(EMAC_TXEXCESSIVECOLL));
 446         dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
 447                 emac_read(EMAC_TXLATECOLL));
 448         dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
 449                 emac_read(EMAC_TXUNDERRUN));
 450         dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
 451                 emac_read(EMAC_TXCARRIERSENSE));
 452         dev_info(emac_dev, "EMAC: tx_octets:%d\n",
 453                 emac_read(EMAC_TXOCTETS));
 454         dev_info(emac_dev, "EMAC: net_octets:%d\n",
 455                 emac_read(EMAC_NETOCTETS));
 456         dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
 457                 emac_read(EMAC_RXSOFOVERRUNS));
 458         dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
 459                 emac_read(EMAC_RXMOFOVERRUNS));
 460         dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
 461                 emac_read(EMAC_RXDMAOVERRUNS));
 462
 463         cpdma_ctlr_dump(priv->dma);
 464 }
 465
 466 /**
 467  * emac_get_drvinfo: Get EMAC driver information
 468  * @ndev: The DaVinci EMAC network adapter
 469  * @info: ethtool info structure containing name and version
 470  *
 471  * Returns EMAC driver information (name and version)
 472  *
 473  */
 474 static void emac_get_drvinfo(struct net_device *ndev,
 475                              struct ethtool_drvinfo *info)
 476 {
 477         strcpy(info->driver, emac_version_string);
 478         strcpy(info->version, EMAC_MODULE_VERSION);
 479 }
 480
 481 /**
 482  * emac_get_settings: Get EMAC settings
 483  * @ndev: The DaVinci EMAC network adapter
 484  * @ecmd: ethtool command
 485  *
 486  * Executes ethool get command
 487  *
 488  */
 489 static int emac_get_settings(struct net_device *ndev,
 490                              struct ethtool_cmd *ecmd)
 491 {
 492         struct emac_priv *priv = netdev_priv(ndev);
 493         if (priv->phydev)
 494                 return phy_ethtool_gset(priv->phydev, ecmd);
 495         else
 496                 return -EOPNOTSUPP;
 497
 498 }
 499
 500 /**
 501  * emac_set_settings: Set EMAC settings
 502  * @ndev: The DaVinci EMAC network adapter
 503  * @ecmd: ethtool command
 504  *
 505  * Executes ethool set command
 506  *
 507  */
 508 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
 509 {
 510         struct emac_priv *priv = netdev_priv(ndev);
 511         if (priv->phydev)
 512                 return phy_ethtool_sset(priv->phydev, ecmd);
 513         else
 514                 return -EOPNOTSUPP;
 515
 516 }
 517
 518 /**
 519  * emac_get_coalesce : Get interrupt coalesce settings for this device
 520  * @ndev : The DaVinci EMAC network adapter
 521  * @coal : ethtool coalesce settings structure
 522  *
 523  * Fetch the current interrupt coalesce settings
 524  *
 525  */
 526 static int emac_get_coalesce(struct net_device *ndev,
 527                                 struct ethtool_coalesce *coal)
 528 {
 529         struct emac_priv *priv = netdev_priv(ndev);
 530
 531         coal->rx_coalesce_usecs = priv->coal_intvl;
 532         return 0;
 533
 534 }
 535
 536 /**
 537  * emac_set_coalesce : Set interrupt coalesce settings for this device
 538  * @ndev : The DaVinci EMAC network adapter
 539  * @coal : ethtool coalesce settings structure
 540  *
 541  * Set interrupt coalesce parameters
 542  *
 543  */
 544 static int emac_set_coalesce(struct net_device *ndev,
 545                                 struct ethtool_coalesce *coal)
 546 {
 547         struct emac_priv *priv = netdev_priv(ndev);
 548         u32 int_ctrl, num_interrupts = 0;
 549         u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
 550
 551         if (!coal->rx_coalesce_usecs)
 552                 return -EINVAL;
 553
 554         coal_intvl = coal->rx_coalesce_usecs;
 555
 556         switch (priv->version) {
 557         case EMAC_VERSION_2:
 558                 int_ctrl =  emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
 559                 prescale = priv->bus_freq_mhz * 4;
 560
 561                 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
 562                         coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
 563
 564                 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
 565                         /*
 566                          * Interrupt pacer works with 4us Pulse, we can
 567                          * throttle further by dilating the 4us pulse.
 568                          */
 569                         addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
 570
 571                         if (addnl_dvdr > 1) {
 572                                 prescale *= addnl_dvdr;
 573                                 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
 574                                                         * addnl_dvdr))
 575                                         coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
 576                                                         * addnl_dvdr);
 577                         } else {
 578                                 addnl_dvdr = 1;
 579                                 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
 580                         }
 581                 }
 582
 583                 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 584
 585                 int_ctrl |= EMAC_DM646X_INTPACEEN;
 586                 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
 587                 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
 588                 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
 589
 590                 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
 591                 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
 592
 593                 break;
 594         default:
 595                 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
 596                 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
 597                 prescale = coal_intvl * priv->bus_freq_mhz;
 598                 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
 599                         prescale = EMAC_DM644X_EWINTCNT_MASK;
 600                         coal_intvl = prescale / priv->bus_freq_mhz;
 601                 }
 602                 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
 603
 604                 break;
 605         }
 606
 607         printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
 608         priv->coal_intvl = coal_intvl;
 609
 610         return 0;
 611
 612 }
 613
 614
 615 /**
 616  * ethtool_ops: DaVinci EMAC Ethtool structure
 617  *
 618  * Ethtool support for EMAC adapter
 619  *
 620  */
 621 static const struct ethtool_ops ethtool_ops = {
 622         .get_drvinfo = emac_get_drvinfo,
 623         .get_settings = emac_get_settings,
 624         .set_settings = emac_set_settings,
 625         .get_link = ethtool_op_get_link,
 626         .get_coalesce = emac_get_coalesce,
 627         .set_coalesce =  emac_set_coalesce,
 628 };
 629
 630 /**
 631  * emac_update_phystatus: Update Phy status
 632  * @priv: The DaVinci EMAC private adapter structure
 633  *
 634  * Updates phy status and takes action for network queue if required
 635  * based upon link status
 636  *
 637  */
 638 static void emac_update_phystatus(struct emac_priv *priv)
 639 {
 640         u32 mac_control;
 641         u32 new_duplex;
 642         u32 cur_duplex;
 643         struct net_device *ndev = priv->ndev;
 644
 645         mac_control = emac_read(EMAC_MACCONTROL);
 646         cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
 647                         DUPLEX_FULL : DUPLEX_HALF;
 648         if (priv->phydev)
 649                 new_duplex = priv->phydev->duplex;
 650         else
 651                 new_duplex = DUPLEX_FULL;
 652
 653         /* We get called only if link has changed (speed/duplex/status) */
 654         if ((priv->link) && (new_duplex != cur_duplex)) {
 655                 priv->duplex = new_duplex;
 656                 if (DUPLEX_FULL == priv->duplex)
 657                         mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
 658                 else
 659                         mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
 660         }
 661
 662         if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
 663                 mac_control = emac_read(EMAC_MACCONTROL);
 664                 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
 665                                 EMAC_DM646X_MACCONTORL_GIGFORCE);
 666         } else {
 667                 /* Clear the GIG bit and GIGFORCE bit */
 668                 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
 669                                         EMAC_DM646X_MACCONTORL_GIG);
 670
 671                 if (priv->rmii_en && (priv->speed == SPEED_100))
 672                         mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
 673                 else
 674                         mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
 675         }
 676
 677         /* Update mac_control if changed */
 678         emac_write(EMAC_MACCONTROL, mac_control);
 679
 680         if (priv->link) {
 681                 /* link ON */
 682                 if (!netif_carrier_ok(ndev))
 683                         netif_carrier_on(ndev);
 684         /* reactivate the transmit queue if it is stopped */
 685                 if (netif_running(ndev) && netif_queue_stopped(ndev))
 686                         netif_wake_queue(ndev);
 687         } else {
 688                 /* link OFF */
 689                 if (netif_carrier_ok(ndev))
 690                         netif_carrier_off(ndev);
 691                 if (!netif_queue_stopped(ndev))
 692                         netif_stop_queue(ndev);
 693         }
 694 }
 695
 696 /**
 697  * hash_get: Calculate hash value from mac address
 698  * @addr: mac address to delete from hash table
 699  *
 700  * Calculates hash value from mac address
 701  *
 702  */
 703 static u32 hash_get(u8 *addr)
 704 {
 705         u32 hash;
 706         u8 tmpval;
 707         int cnt;
 708         hash = 0;
 709
 710         for (cnt = 0; cnt < 2; cnt++) {
 711                 tmpval = *addr++;
 712                 hash ^= (tmpval >> 2) ^ (tmpval << 4);
 713                 tmpval = *addr++;
 714                 hash ^= (tmpval >> 4) ^ (tmpval << 2);
 715                 tmpval = *addr++;
 716                 hash ^= (tmpval >> 6) ^ (tmpval);
 717         }
 718
 719         return hash & 0x3F;
 720 }
 721
 722 /**
 723  * hash_add: Hash function to add mac addr from hash table
 724  * @priv: The DaVinci EMAC private adapter structure
 725  * mac_addr: mac address to delete from hash table
 726  *
 727  * Adds mac address to the internal hash table
 728  *
 729  */
 730 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
 731 {
 732         struct device *emac_dev = &priv->ndev->dev;
 733         u32 rc = 0;
 734         u32 hash_bit;
 735         u32 hash_value = hash_get(mac_addr);
 736
 737         if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
 738                 if (netif_msg_drv(priv)) {
 739                         dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
 740                                 "Hash %08x, should not be greater than %08x",
 741                                 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
 742                 }
 743                 return -1;
 744         }
 745
 746         /* set the hash bit only if not previously set */
 747         if (priv->multicast_hash_cnt[hash_value] == 0) {
 748                 rc = 1; /* hash value changed */
 749                 if (hash_value < 32) {
 750                         hash_bit = BIT(hash_value);
 751                         priv->mac_hash1 |= hash_bit;
 752                 } else {
 753                         hash_bit = BIT((hash_value - 32));
 754                         priv->mac_hash2 |= hash_bit;
 755                 }
 756         }
 757
 758         /* incr counter for num of mcast addr's mapped to "this" hash bit */
 759         ++priv->multicast_hash_cnt[hash_value];
 760
 761         return rc;
 762 }
 763
 764 /**
 765  * hash_del: Hash function to delete mac addr from hash table
 766  * @priv: The DaVinci EMAC private adapter structure
 767  * mac_addr: mac address to delete from hash table
 768  *
 769  * Removes mac address from the internal hash table
 770  *
 771  */
 772 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
 773 {
 774         u32 hash_value;
 775         u32 hash_bit;
 776
 777         hash_value = hash_get(mac_addr);
 778         if (priv->multicast_hash_cnt[hash_value] > 0) {
 779                 /* dec cntr for num of mcast addr's mapped to this hash bit */
 780                 --priv->multicast_hash_cnt[hash_value];
 781         }
 782
 783         /* if counter still > 0, at least one multicast address refers
 784          * to this hash bit. so return 0 */
 785         if (priv->multicast_hash_cnt[hash_value] > 0)
 786                 return 0;
 787
 788         if (hash_value < 32) {
 789                 hash_bit = BIT(hash_value);
 790                 priv->mac_hash1 &= ~hash_bit;
 791         } else {
 792                 hash_bit = BIT((hash_value - 32));
 793                 priv->mac_hash2 &= ~hash_bit;
 794         }
 795
 796         /* return 1 to indicate change in mac_hash registers reqd */
 797         return 1;
 798 }
 799
 800 /* EMAC multicast operation */
 801 #define EMAC_MULTICAST_ADD      0
 802 #define EMAC_MULTICAST_DEL      1
 803 #define EMAC_ALL_MULTI_SET      2
 804 #define EMAC_ALL_MULTI_CLR      3
 805
 806 /**
 807  * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
 808  * @priv: The DaVinci EMAC private adapter structure
 809  * @action: multicast operation to perform
 810  * mac_addr: mac address to set
 811  *
 812  * Set multicast addresses in EMAC adapter - internal function
 813  *
 814  */
 815 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
 816 {
 817         struct device *emac_dev = &priv->ndev->dev;
 818         int update = -1;
 819
 820         switch (action) {
 821         case EMAC_MULTICAST_ADD:
 822                 update = hash_add(priv, mac_addr);
 823                 break;
 824         case EMAC_MULTICAST_DEL:
 825                 update = hash_del(priv, mac_addr);
 826                 break;
 827         case EMAC_ALL_MULTI_SET:
 828                 update = 1;
 829                 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
 830                 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
 831                 break;
 832         case EMAC_ALL_MULTI_CLR:
 833                 update = 1;
 834                 priv->mac_hash1 = 0;
 835                 priv->mac_hash2 = 0;
 836                 memset(&(priv->multicast_hash_cnt[0]), 0,
 837                 sizeof(priv->multicast_hash_cnt[0]) *
 838                        EMAC_NUM_MULTICAST_BITS);
 839                 break;
 840         default:
 841                 if (netif_msg_drv(priv))
 842                         dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
 843                                 ": bad operation %d", action);
 844                 break;
 845         }
 846
 847         /* write to the hardware only if the register status chances */
 848         if (update > 0) {
 849                 emac_write(EMAC_MACHASH1, priv->mac_hash1);
 850                 emac_write(EMAC_MACHASH2, priv->mac_hash2);
 851         }
 852 }
 853
 854 /**
 855  * emac_dev_mcast_set: Set multicast address in the EMAC adapter
 856  * @ndev: The DaVinci EMAC network adapter
 857  *
 858  * Set multicast addresses in EMAC adapter
 859  *
 860  */
 861 static void emac_dev_mcast_set(struct net_device *ndev)
 862 {
 863         u32 mbp_enable;
 864         struct emac_priv *priv = netdev_priv(ndev);
 865
 866         mbp_enable = emac_read(EMAC_RXMBPENABLE);
 867         if (ndev->flags & IFF_PROMISC) {
 868                 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
 869                 mbp_enable |= (EMAC_MBP_RXPROMISC);
 870         } else {
 871                 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
 872                 if ((ndev->flags & IFF_ALLMULTI) ||
 873                     netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
 874                         mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
 875                         emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
 876                 }
 877                 if (!netdev_mc_empty(ndev)) {
 878                         struct netdev_hw_addr *ha;
 879
 880                         mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
 881                         emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
 882                         /* program multicast address list into EMAC hardware */
 883                         netdev_for_each_mc_addr(ha, ndev) {
 884                                 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
 885                                                (u8 *) ha->addr);
 886                         }
 887                 } else {
 888                         mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
 889                         emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
 890                 }
 891         }
 892         /* Set mbp config register */
 893         emac_write(EMAC_RXMBPENABLE, mbp_enable);
 894 }
 895
 896 /*************************************************************************
 897  *  EMAC Hardware manipulation
 898  *************************************************************************/
 899
 900 /**
 901  * emac_int_disable: Disable EMAC module interrupt (from adapter)
 902  * @priv: The DaVinci EMAC private adapter structure
 903  *
 904  * Disable EMAC interrupt on the adapter
 905  *
 906  */
 907 static void emac_int_disable(struct emac_priv *priv)
 908 {
 909         if (priv->version == EMAC_VERSION_2) {
 910                 unsigned long flags;
 911
 912                 local_irq_save(flags);
 913
 914                 /* Program C0_Int_En to zero to turn off
 915                 * interrupts to the CPU */
 916                 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
 917                 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
 918                 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
 919                 if (priv->int_disable)
 920                         priv->int_disable();
 921
 922                 local_irq_restore(flags);
 923
 924         } else {
 925                 /* Set DM644x control registers for interrupt control */
 926                 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
 927         }
 928 }
 929
 930 /**
 931  * emac_int_enable: Enable EMAC module interrupt (from adapter)
 932  * @priv: The DaVinci EMAC private adapter structure
 933  *
 934  * Enable EMAC interrupt on the adapter
 935  *
 936  */
 937 static void emac_int_enable(struct emac_priv *priv)
 938 {
 939         if (priv->version == EMAC_VERSION_2) {
 940                 if (priv->int_enable)
 941                         priv->int_enable();
 942
 943                 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
 944                 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
 945
 946                 /* In addition to turning on interrupt Enable, we need
 947                  * ack by writing appropriate values to the EOI
 948                  * register */
 949
 950                 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
 951
 952                 /* ack rxen only then a new pulse will be generated */
 953                 emac_write(EMAC_DM646X_MACEOIVECTOR,
 954                         EMAC_DM646X_MAC_EOI_C0_RXEN);
 955
 956                 /* ack txen- only then a new pulse will be generated */
 957                 emac_write(EMAC_DM646X_MACEOIVECTOR,
 958                         EMAC_DM646X_MAC_EOI_C0_TXEN);
 959
 960         } else {
 961                 /* Set DM644x control registers for interrupt control */
 962                 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
 963         }
 964 }
 965
 966 /**
 967  * emac_irq: EMAC interrupt handler
 968  * @irq: interrupt number
 969  * @dev_id: EMAC network adapter data structure ptr
 970  *
 971  * EMAC Interrupt handler - we only schedule NAPI and not process any packets
 972  * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
 973  *
 974  * Returns interrupt handled condition
 975  */
 976 static irqreturn_t emac_irq(int irq, void *dev_id)
 977 {
 978         struct net_device *ndev = (struct net_device *)dev_id;
 979         struct emac_priv *priv = netdev_priv(ndev);
 980
 981         ++priv->isr_count;
 982         if (likely(netif_running(priv->ndev))) {
 983                 emac_int_disable(priv);
 984                 napi_schedule(&priv->napi);
 985         } else {
 986                 /* we are closing down, so dont process anything */
 987         }
 988         return IRQ_HANDLED;
 989 }
 990
 991 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
 992 {
 993         struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
 994         if (WARN_ON(!skb))
 995                 return NULL;
 996         skb->dev = priv->ndev;
 997         skb_reserve(skb, NET_IP_ALIGN);
 998         return skb;
 999 }
1000
1001 static void emac_rx_handler(void *token, int len, int status)
1002 {
1003         struct sk_buff          *skb = token;
1004         struct net_device       *ndev = skb->dev;
1005         struct emac_priv        *priv = netdev_priv(ndev);
1006         struct device           *emac_dev = &ndev->dev;
1007         int                     ret;
1008
1009         /* free and bail if we are shutting down */
1010         if (unlikely(!netif_running(ndev) || !netif_carrier_ok(ndev))) {
1011                 dev_kfree_skb_any(skb);
1012                 return;
1013         }
1014
1015         /* recycle on receive error */
1016         if (status < 0) {
1017                 ndev->stats.rx_errors++;
1018                 goto recycle;
1019         }
1020
1021         /* feed received packet up the stack */
1022         skb_put(skb, len);
1023         skb->protocol = eth_type_trans(skb, ndev);
1024         netif_receive_skb(skb);
1025         ndev->stats.rx_bytes += len;
1026         ndev->stats.rx_packets++;
1027
1028         /* alloc a new packet for receive */
1029         skb = emac_rx_alloc(priv);
1030         if (!skb) {
1031                 if (netif_msg_rx_err(priv) && net_ratelimit())
1032                         dev_err(emac_dev, "failed rx buffer alloc\n");
1033                 return;
1034         }
1035
1036 recycle:
1037         ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1038                         skb_tailroom(skb), GFP_KERNEL);
1039         if (WARN_ON(ret < 0))
1040                 dev_kfree_skb_any(skb);
1041 }
1042
1043 static void emac_tx_handler(void *token, int len, int status)
1044 {
1045         struct sk_buff          *skb = token;
1046         struct net_device       *ndev = skb->dev;
1047
1048         if (unlikely(netif_queue_stopped(ndev)))
1049                 netif_start_queue(ndev);
1050         ndev->stats.tx_packets++;
1051         ndev->stats.tx_bytes += len;
1052         dev_kfree_skb_any(skb);
1053 }
1054
1055 /**
1056  * emac_dev_xmit: EMAC Transmit function
1057  * @skb: SKB pointer
1058  * @ndev: The DaVinci EMAC network adapter
1059  *
1060  * Called by the system to transmit a packet  - we queue the packet in
1061  * EMAC hardware transmit queue
1062  *
1063  * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1064  */
1065 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1066 {
1067         struct device *emac_dev = &ndev->dev;
1068         int ret_code;
1069         struct emac_priv *priv = netdev_priv(ndev);
1070
1071         /* If no link, return */
1072         if (unlikely(!priv->link)) {
1073                 if (netif_msg_tx_err(priv) && net_ratelimit())
1074                         dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1075                 goto fail_tx;
1076         }
1077
1078         ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1079         if (unlikely(ret_code < 0)) {
1080                 if (netif_msg_tx_err(priv) && net_ratelimit())
1081                         dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1082                 goto fail_tx;
1083         }
1084
1085         skb_tx_timestamp(skb);
1086
1087         ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1088                                      GFP_KERNEL);
1089         if (unlikely(ret_code != 0)) {
1090                 if (netif_msg_tx_err(priv) && net_ratelimit())
1091                         dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1092                 goto fail_tx;
1093         }
1094
1095         return NETDEV_TX_OK;
1096
1097 fail_tx:
1098         ndev->stats.tx_dropped++;
1099         netif_stop_queue(ndev);
1100         return NETDEV_TX_BUSY;
1101 }
1102
1103 /**
1104  * emac_dev_tx_timeout: EMAC Transmit timeout function
1105  * @ndev: The DaVinci EMAC network adapter
1106  *
1107  * Called when system detects that a skb timeout period has expired
1108  * potentially due to a fault in the adapter in not being able to send
1109  * it out on the wire. We teardown the TX channel assuming a hardware
1110  * error and re-initialize the TX channel for hardware operation
1111  *
1112  */
1113 static void emac_dev_tx_timeout(struct net_device *ndev)
1114 {
1115         struct emac_priv *priv = netdev_priv(ndev);
1116         struct device *emac_dev = &ndev->dev;
1117
1118         if (netif_msg_tx_err(priv))
1119                 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1120
1121         emac_dump_regs(priv);
1122
1123         ndev->stats.tx_errors++;
1124         emac_int_disable(priv);
1125         cpdma_chan_stop(priv->txchan);
1126         cpdma_chan_start(priv->txchan);
1127         emac_int_enable(priv);
1128 }
1129
1130 /**
1131  * emac_set_type0addr: Set EMAC Type0 mac address
1132  * @priv: The DaVinci EMAC private adapter structure
1133  * @ch: RX channel number
1134  * @mac_addr: MAC address to set in device
1135  *
1136  * Called internally to set Type0 mac address of the adapter (Device)
1137  *
1138  * Returns success (0) or appropriate error code (none as of now)
1139  */
1140 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1141 {
1142         u32 val;
1143         val = ((mac_addr[5] << 8) | (mac_addr[4]));
1144         emac_write(EMAC_MACSRCADDRLO, val);
1145
1146         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1147                (mac_addr[1] << 8) | (mac_addr[0]));
1148         emac_write(EMAC_MACSRCADDRHI, val);
1149         val = emac_read(EMAC_RXUNICASTSET);
1150         val |= BIT(ch);
1151         emac_write(EMAC_RXUNICASTSET, val);
1152         val = emac_read(EMAC_RXUNICASTCLEAR);
1153         val &= ~BIT(ch);
1154         emac_write(EMAC_RXUNICASTCLEAR, val);
1155 }
1156
1157 /**
1158  * emac_set_type1addr: Set EMAC Type1 mac address
1159  * @priv: The DaVinci EMAC private adapter structure
1160  * @ch: RX channel number
1161  * @mac_addr: MAC address to set in device
1162  *
1163  * Called internally to set Type1 mac address of the adapter (Device)
1164  *
1165  * Returns success (0) or appropriate error code (none as of now)
1166  */
1167 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1168 {
1169         u32 val;
1170         emac_write(EMAC_MACINDEX, ch);
1171         val = ((mac_addr[5] << 8) | mac_addr[4]);
1172         emac_write(EMAC_MACADDRLO, val);
1173         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1174                (mac_addr[1] << 8) | (mac_addr[0]));
1175         emac_write(EMAC_MACADDRHI, val);
1176         emac_set_type0addr(priv, ch, mac_addr);
1177 }
1178
1179 /**
1180  * emac_set_type2addr: Set EMAC Type2 mac address
1181  * @priv: The DaVinci EMAC private adapter structure
1182  * @ch: RX channel number
1183  * @mac_addr: MAC address to set in device
1184  * @index: index into RX address entries
1185  * @match: match parameter for RX address matching logic
1186  *
1187  * Called internally to set Type2 mac address of the adapter (Device)
1188  *
1189  * Returns success (0) or appropriate error code (none as of now)
1190  */
1191 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1192                                char *mac_addr, int index, int match)
1193 {
1194         u32 val;
1195         emac_write(EMAC_MACINDEX, index);
1196         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1197                (mac_addr[1] << 8) | (mac_addr[0]));
1198         emac_write(EMAC_MACADDRHI, val);
1199         val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1200                (match << 19) | BIT(20));
1201         emac_write(EMAC_MACADDRLO, val);
1202         emac_set_type0addr(priv, ch, mac_addr);
1203 }
1204
1205 /**
1206  * emac_setmac: Set mac address in the adapter (internal function)
1207  * @priv: The DaVinci EMAC private adapter structure
1208  * @ch: RX channel number
1209  * @mac_addr: MAC address to set in device
1210  *
1211  * Called internally to set the mac address of the adapter (Device)
1212  *
1213  * Returns success (0) or appropriate error code (none as of now)
1214  */
1215 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1216 {
1217         struct device *emac_dev = &priv->ndev->dev;
1218
1219         if (priv->rx_addr_type == 0) {
1220                 emac_set_type0addr(priv, ch, mac_addr);
1221         } else if (priv->rx_addr_type == 1) {
1222                 u32 cnt;
1223                 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1224                         emac_set_type1addr(priv, ch, mac_addr);
1225         } else if (priv->rx_addr_type == 2) {
1226                 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1227                 emac_set_type0addr(priv, ch, mac_addr);
1228         } else {
1229                 if (netif_msg_drv(priv))
1230                         dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1231         }
1232 }
1233
1234 /**
1235  * emac_dev_setmac_addr: Set mac address in the adapter
1236  * @ndev: The DaVinci EMAC network adapter
1237  * @addr: MAC address to set in device
1238  *
1239  * Called by the system to set the mac address of the adapter (Device)
1240  *
1241  * Returns success (0) or appropriate error code (none as of now)
1242  */
1243 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1244 {
1245         struct emac_priv *priv = netdev_priv(ndev);
1246         struct device *emac_dev = &priv->ndev->dev;
1247         struct sockaddr *sa = addr;
1248
1249         if (!is_valid_ether_addr(sa->sa_data))
1250                 return -EINVAL;
1251
1252         /* Store mac addr in priv and rx channel and set it in EMAC hw */
1253         memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1254         memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1255
1256         /* MAC address is configured only after the interface is enabled. */
1257         if (netif_running(ndev)) {
1258                 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1259                 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1260         }
1261
1262         if (netif_msg_drv(priv))
1263                 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1264                                         priv->mac_addr);
1265
1266         return 0;
1267 }
1268
1269 /**
1270  * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
1271  * @priv: The DaVinci EMAC private adapter structure
1272  *
1273  * Enables EMAC hardware for packet processing - enables PHY, enables RX
1274  * for packet reception and enables device interrupts and then NAPI
1275  *
1276  * Returns success (0) or appropriate error code (none right now)
1277  */
1278 static int emac_hw_enable(struct emac_priv *priv)
1279 {
1280         u32 val, mbp_enable, mac_control;
1281
1282         /* Soft reset */
1283         emac_write(EMAC_SOFTRESET, 1);
1284         while (emac_read(EMAC_SOFTRESET))
1285                 cpu_relax();
1286
1287         /* Disable interrupt & Set pacing for more interrupts initially */
1288         emac_int_disable(priv);
1289
1290         /* Full duplex enable bit set when auto negotiation happens */
1291         mac_control =
1292                 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1293                 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1294                 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1295                 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1296         emac_write(EMAC_MACCONTROL, mac_control);
1297
1298         mbp_enable =
1299                 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1300                 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1301                  ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1302                  ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1303                  ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1304                  ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1305                  ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1306                  ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1307                         EMAC_RXMBP_PROMCH_SHIFT) |
1308                  ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1309                  ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1310                         EMAC_RXMBP_BROADCH_SHIFT) |
1311                  ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1312                  ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1313                         EMAC_RXMBP_MULTICH_SHIFT));
1314         emac_write(EMAC_RXMBPENABLE, mbp_enable);
1315         emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1316                                    EMAC_RX_MAX_LEN_MASK));
1317         emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1318                                          EMAC_RX_BUFFER_OFFSET_MASK));
1319         emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1320         emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1321         priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1322
1323         emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1324
1325         emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1326
1327         /* Enable MII */
1328         val = emac_read(EMAC_MACCONTROL);
1329         val |= (EMAC_MACCONTROL_GMIIEN);
1330         emac_write(EMAC_MACCONTROL, val);
1331
1332         /* Enable NAPI and interrupts */
1333         napi_enable(&priv->napi);
1334         emac_int_enable(priv);
1335         return 0;
1336
1337 }
1338
1339 /**
1340  * emac_poll: EMAC NAPI Poll function
1341  * @ndev: The DaVinci EMAC network adapter
1342  * @budget: Number of receive packets to process (as told by NAPI layer)
1343  *
1344  * NAPI Poll function implemented to process packets as per budget. We check
1345  * the type of interrupt on the device and accordingly call the TX or RX
1346  * packet processing functions. We follow the budget for RX processing and
1347  * also put a cap on number of TX pkts processed through config param. The
1348  * NAPI schedule function is called if more packets pending.
1349  *
1350  * Returns number of packets received (in most cases; else TX pkts - rarely)
1351  */
1352 static int emac_poll(struct napi_struct *napi, int budget)
1353 {
1354         unsigned int mask;
1355         struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1356         struct net_device *ndev = priv->ndev;
1357         struct device *emac_dev = &ndev->dev;
1358         u32 status = 0;
1359         u32 num_tx_pkts = 0, num_rx_pkts = 0;
1360
1361         /* Check interrupt vectors and call packet processing */
1362         status = emac_read(EMAC_MACINVECTOR);
1363
1364         mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1365
1366         if (priv->version == EMAC_VERSION_2)
1367                 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1368
1369         if (status & mask) {
1370                 num_tx_pkts = cpdma_chan_process(priv->txchan,
1371                                               EMAC_DEF_TX_MAX_SERVICE);
1372         } /* TX processing */
1373
1374         mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1375
1376         if (priv->version == EMAC_VERSION_2)
1377                 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1378
1379         if (status & mask) {
1380                 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1381         } /* RX processing */
1382
1383         mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1384         if (priv->version == EMAC_VERSION_2)
1385                 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1386
1387         if (unlikely(status & mask)) {
1388                 u32 ch, cause;
1389                 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1390                 netif_stop_queue(ndev);
1391                 napi_disable(&priv->napi);
1392
1393                 status = emac_read(EMAC_MACSTATUS);
1394                 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1395                          EMAC_MACSTATUS_TXERRCODE_SHIFT);
1396                 if (cause) {
1397                         ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1398                               EMAC_MACSTATUS_TXERRCH_SHIFT);
1399                         if (net_ratelimit()) {
1400                                 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1401                                         &emac_txhost_errcodes[cause][0], ch);
1402                         }
1403                 }
1404                 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1405                          EMAC_MACSTATUS_RXERRCODE_SHIFT);
1406                 if (cause) {
1407                         ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1408                               EMAC_MACSTATUS_RXERRCH_SHIFT);
1409                         if (netif_msg_hw(priv) && net_ratelimit())
1410                                 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1411                                         &emac_rxhost_errcodes[cause][0], ch);
1412                 }
1413         } else if (num_rx_pkts < budget) {
1414                 napi_complete(napi);
1415                 emac_int_enable(priv);
1416         }
1417
1418         return num_rx_pkts;
1419 }
1420
1421 #ifdef CONFIG_NET_POLL_CONTROLLER
1422 /**
1423  * emac_poll_controller: EMAC Poll controller function
1424  * @ndev: The DaVinci EMAC network adapter
1425  *
1426  * Polled functionality used by netconsole and others in non interrupt mode
1427  *
1428  */
1429 void emac_poll_controller(struct net_device *ndev)
1430 {
1431         struct emac_priv *priv = netdev_priv(ndev);
1432
1433         emac_int_disable(priv);
1434         emac_irq(ndev->irq, ndev);
1435         emac_int_enable(priv);
1436 }
1437 #endif
1438
1439 static void emac_adjust_link(struct net_device *ndev)
1440 {
1441         struct emac_priv *priv = netdev_priv(ndev);
1442         struct phy_device *phydev = priv->phydev;
1443         unsigned long flags;
1444         int new_state = 0;
1445
1446         spin_lock_irqsave(&priv->lock, flags);
1447
1448         if (phydev->link) {
1449                 /* check the mode of operation - full/half duplex */
1450                 if (phydev->duplex != priv->duplex) {
1451                         new_state = 1;
1452                         priv->duplex = phydev->duplex;
1453                 }
1454                 if (phydev->speed != priv->speed) {
1455                         new_state = 1;
1456                         priv->speed = phydev->speed;
1457                 }
1458                 if (!priv->link) {
1459                         new_state = 1;
1460                         priv->link = 1;
1461                 }
1462
1463         } else if (priv->link) {
1464                 new_state = 1;
1465                 priv->link = 0;
1466                 priv->speed = 0;
1467                 priv->duplex = ~0;
1468         }
1469         if (new_state) {
1470                 emac_update_phystatus(priv);
1471                 phy_print_status(priv->phydev);
1472         }
1473
1474         spin_unlock_irqrestore(&priv->lock, flags);
1475 }
1476
1477 /*************************************************************************
1478  *  Linux Driver Model
1479  *************************************************************************/
1480
1481 /**
1482  * emac_devioctl: EMAC adapter ioctl
1483  * @ndev: The DaVinci EMAC network adapter
1484  * @ifrq: request parameter
1485  * @cmd: command parameter
1486  *
1487  * EMAC driver ioctl function
1488  *
1489  * Returns success(0) or appropriate error code
1490  */
1491 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1492 {
1493         struct emac_priv *priv = netdev_priv(ndev);
1494
1495         if (!(netif_running(ndev)))
1496                 return -EINVAL;
1497
1498         /* TODO: Add phy read and write and private statistics get feature */
1499
1500         return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1501 }
1502
1503 static int match_first_device(struct device *dev, void *data)
1504 {
1505         return 1;
1506 }
1507
1508 /**
1509  * emac_dev_open: EMAC device open
1510  * @ndev: The DaVinci EMAC network adapter
1511  *
1512  * Called when system wants to start the interface. We init TX/RX channels
1513  * and enable the hardware for packet reception/transmission and start the
1514  * network queue.
1515  *
1516  * Returns 0 for a successful open, or appropriate error code
1517  */
1518 static int emac_dev_open(struct net_device *ndev)
1519 {
1520         struct device *emac_dev = &ndev->dev;
1521         u32 cnt;
1522         struct resource *res;
1523         int q, m, ret;
1524         int i = 0;
1525         int k = 0;
1526         struct emac_priv *priv = netdev_priv(ndev);
1527
1528         netif_carrier_off(ndev);
1529         for (cnt = 0; cnt < ETH_ALEN; cnt++)
1530                 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1531
1532         /* Configuration items */
1533         priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1534
1535         priv->mac_hash1 = 0;
1536         priv->mac_hash2 = 0;
1537         emac_write(EMAC_MACHASH1, 0);
1538         emac_write(EMAC_MACHASH2, 0);
1539
1540         for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1541                 struct sk_buff *skb = emac_rx_alloc(priv);
1542
1543                 if (!skb)
1544                         break;
1545
1546                 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1547                                         skb_tailroom(skb), GFP_KERNEL);
1548                 if (WARN_ON(ret < 0))
1549                         break;
1550         }
1551
1552         /* Request IRQ */
1553
1554         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1555                 for (i = res->start; i <= res->end; i++) {
1556                         if (request_irq(i, emac_irq, IRQF_DISABLED,
1557                                         ndev->name, ndev))
1558                                 goto rollback;
1559                 }
1560                 k++;
1561         }
1562
1563         /* Start/Enable EMAC hardware */
1564         emac_hw_enable(priv);
1565
1566         /* Enable Interrupt pacing if configured */
1567         if (priv->coal_intvl != 0) {
1568                 struct ethtool_coalesce coal;
1569
1570                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1571                 emac_set_coalesce(ndev, &coal);
1572         }
1573
1574         cpdma_ctlr_start(priv->dma);
1575
1576         priv->phydev = NULL;
1577         /* use the first phy on the bus if pdata did not give us a phy id */
1578         if (!priv->phy_id) {
1579                 struct device *phy;
1580
1581                 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1582                                       match_first_device);
1583                 if (phy)
1584                         priv->phy_id = dev_name(phy);
1585         }
1586
1587         if (priv->phy_id && *priv->phy_id) {
1588                 priv->phydev = phy_connect(ndev, priv->phy_id,
1589                                            &emac_adjust_link, 0,
1590                                            PHY_INTERFACE_MODE_MII);
1591
1592                 if (IS_ERR(priv->phydev)) {
1593                         dev_err(emac_dev, "could not connect to phy %s\n",
1594                                 priv->phy_id);
1595                         priv->phydev = NULL;
1596                         return PTR_ERR(priv->phydev);
1597                 }
1598
1599                 priv->link = 0;
1600                 priv->speed = 0;
1601                 priv->duplex = ~0;
1602
1603                 dev_info(emac_dev, "attached PHY driver [%s] "
1604                         "(mii_bus:phy_addr=%s, id=%x)\n",
1605                         priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1606                         priv->phydev->phy_id);
1607         } else {
1608                 /* No PHY , fix the link, speed and duplex settings */
1609                 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1610                 priv->link = 1;
1611                 priv->speed = SPEED_100;
1612                 priv->duplex = DUPLEX_FULL;
1613                 emac_update_phystatus(priv);
1614         }
1615
1616         if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1617                 emac_dump_regs(priv);
1618
1619         if (netif_msg_drv(priv))
1620                 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1621
1622         if (priv->phydev)
1623                 phy_start(priv->phydev);
1624
1625         return 0;
1626
1627 rollback:
1628
1629         dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1630
1631         for (q = k; k >= 0; k--) {
1632                 for (m = i; m >= res->start; m--)
1633                         free_irq(m, ndev);
1634                 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1635                 m = res->end;
1636         }
1637         return -EBUSY;
1638 }
1639
1640 /**
1641  * emac_dev_stop: EMAC device stop
1642  * @ndev: The DaVinci EMAC network adapter
1643  *
1644  * Called when system wants to stop or down the interface. We stop the network
1645  * queue, disable interrupts and cleanup TX/RX channels.
1646  *
1647  * We return the statistics in net_device_stats structure pulled from emac
1648  */
1649 static int emac_dev_stop(struct net_device *ndev)
1650 {
1651         struct resource *res;
1652         int i = 0;
1653         int irq_num;
1654         struct emac_priv *priv = netdev_priv(ndev);
1655         struct device *emac_dev = &ndev->dev;
1656
1657         /* inform the upper layers. */
1658         netif_stop_queue(ndev);
1659         napi_disable(&priv->napi);
1660
1661         netif_carrier_off(ndev);
1662         emac_int_disable(priv);
1663         cpdma_ctlr_stop(priv->dma);
1664         emac_write(EMAC_SOFTRESET, 1);
1665
1666         if (priv->phydev)
1667                 phy_disconnect(priv->phydev);
1668
1669         /* Free IRQ */
1670         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1671                 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1672                         free_irq(irq_num, priv->ndev);
1673                 i++;
1674         }
1675
1676         if (netif_msg_drv(priv))
1677                 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1678
1679         return 0;
1680 }
1681
1682 /**
1683  * emac_dev_getnetstats: EMAC get statistics function
1684  * @ndev: The DaVinci EMAC network adapter
1685  *
1686  * Called when system wants to get statistics from the device.
1687  *
1688  * We return the statistics in net_device_stats structure pulled from emac
1689  */
1690 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1691 {
1692         struct emac_priv *priv = netdev_priv(ndev);
1693         u32 mac_control;
1694         u32 stats_clear_mask;
1695
1696         /* update emac hardware stats and reset the registers*/
1697
1698         mac_control = emac_read(EMAC_MACCONTROL);
1699
1700         if (mac_control & EMAC_MACCONTROL_GMIIEN)
1701                 stats_clear_mask = EMAC_STATS_CLR_MASK;
1702         else
1703                 stats_clear_mask = 0;
1704
1705         ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1706         emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1707
1708         ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1709                                            emac_read(EMAC_TXSINGLECOLL) +
1710                                            emac_read(EMAC_TXMULTICOLL));
1711         emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1712         emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1713         emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1714
1715         ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1716                                                 emac_read(EMAC_RXJABBER) +
1717                                                 emac_read(EMAC_RXUNDERSIZED));
1718         emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1719         emac_write(EMAC_RXJABBER, stats_clear_mask);
1720         emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1721
1722         ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1723                                                emac_read(EMAC_RXMOFOVERRUNS));
1724         emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1725         emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1726
1727         ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1728         emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1729
1730         ndev->stats.tx_carrier_errors +=
1731                 emac_read(EMAC_TXCARRIERSENSE);
1732         emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1733
1734         ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1735         emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1736
1737         return &ndev->stats;
1738 }
1739
1740 static const struct net_device_ops emac_netdev_ops = {
1741         .ndo_open               = emac_dev_open,
1742         .ndo_stop               = emac_dev_stop,
1743         .ndo_start_xmit         = emac_dev_xmit,
1744         .ndo_set_multicast_list = emac_dev_mcast_set,
1745         .ndo_set_mac_address    = emac_dev_setmac_addr,
1746         .ndo_do_ioctl           = emac_devioctl,
1747         .ndo_tx_timeout         = emac_dev_tx_timeout,
1748         .ndo_get_stats          = emac_dev_getnetstats,
1749 #ifdef CONFIG_NET_POLL_CONTROLLER
1750         .ndo_poll_controller    = emac_poll_controller,
1751 #endif
1752 };
1753
1754 /**
1755  * davinci_emac_probe: EMAC device probe
1756  * @pdev: The DaVinci EMAC device that we are removing
1757  *
1758  * Called when probing for emac devicesr. We get details of instances and
1759  * resource information from platform init and register a network device
1760  * and allocate resources necessary for driver to perform
1761  */
1762 static int __devinit davinci_emac_probe(struct platform_device *pdev)
1763 {
1764         int rc = 0;
1765         struct resource *res;
1766         struct net_device *ndev;
1767         struct emac_priv *priv;
1768         unsigned long size, hw_ram_addr;
1769         struct emac_platform_data *pdata;
1770         struct device *emac_dev;
1771         struct cpdma_params dma_params;
1772
1773         /* obtain emac clock from kernel */
1774         emac_clk = clk_get(&pdev->dev, NULL);
1775         if (IS_ERR(emac_clk)) {
1776                 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1777                 return -EBUSY;
1778         }
1779         emac_bus_frequency = clk_get_rate(emac_clk);
1780         /* TODO: Probe PHY here if possible */
1781
1782         ndev = alloc_etherdev(sizeof(struct emac_priv));
1783         if (!ndev) {
1784                 dev_err(&pdev->dev, "error allocating net_device\n");
1785                 rc = -ENOMEM;
1786                 goto free_clk;
1787         }
1788
1789         platform_set_drvdata(pdev, ndev);
1790         priv = netdev_priv(ndev);
1791         priv->pdev = pdev;
1792         priv->ndev = ndev;
1793         priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1794
1795         spin_lock_init(&priv->lock);
1796
1797         pdata = pdev->dev.platform_data;
1798         if (!pdata) {
1799                 dev_err(&pdev->dev, "no platform data\n");
1800                 rc = -ENODEV;
1801                 goto probe_quit;
1802         }
1803
1804         /* MAC addr and PHY mask , RMII enable info from platform_data */
1805         memcpy(priv->mac_addr, pdata->mac_addr, 6);
1806         priv->phy_id = pdata->phy_id;
1807         priv->rmii_en = pdata->rmii_en;
1808         priv->version = pdata->version;
1809         priv->int_enable = pdata->interrupt_enable;
1810         priv->int_disable = pdata->interrupt_disable;
1811
1812         priv->coal_intvl = 0;
1813         priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1814
1815         emac_dev = &ndev->dev;
1816         /* Get EMAC platform data */
1817         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1818         if (!res) {
1819                 dev_err(&pdev->dev,"error getting res\n");
1820                 rc = -ENOENT;
1821                 goto probe_quit;
1822         }
1823
1824         priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1825         size = resource_size(res);
1826         if (!request_mem_region(res->start, size, ndev->name)) {
1827                 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1828                 rc = -ENXIO;
1829                 goto probe_quit;
1830         }
1831
1832         priv->remap_addr = ioremap(res->start, size);
1833         if (!priv->remap_addr) {
1834                 dev_err(&pdev->dev, "unable to map IO\n");
1835                 rc = -ENOMEM;
1836                 release_mem_region(res->start, size);
1837                 goto probe_quit;
1838         }
1839         priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1840         ndev->base_addr = (unsigned long)priv->remap_addr;
1841
1842         priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1843
1844         hw_ram_addr = pdata->hw_ram_addr;
1845         if (!hw_ram_addr)
1846                 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1847
1848         memset(&dma_params, 0, sizeof(dma_params));
1849         dma_params.dev                  = emac_dev;
1850         dma_params.dmaregs              = priv->emac_base;
1851         dma_params.rxthresh             = priv->emac_base + 0x120;
1852         dma_params.rxfree               = priv->emac_base + 0x140;
1853         dma_params.txhdp                = priv->emac_base + 0x600;
1854         dma_params.rxhdp                = priv->emac_base + 0x620;
1855         dma_params.txcp                 = priv->emac_base + 0x640;
1856         dma_params.rxcp                 = priv->emac_base + 0x660;
1857         dma_params.num_chan             = EMAC_MAX_TXRX_CHANNELS;
1858         dma_params.min_packet_size      = EMAC_DEF_MIN_ETHPKTSIZE;
1859         dma_params.desc_hw_addr         = hw_ram_addr;
1860         dma_params.desc_mem_size        = pdata->ctrl_ram_size;
1861         dma_params.desc_align           = 16;
1862
1863         dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1864                         (u32 __force)res->start + pdata->ctrl_ram_offset;
1865
1866         priv->dma = cpdma_ctlr_create(&dma_params);
1867         if (!priv->dma) {
1868                 dev_err(&pdev->dev, "error initializing DMA\n");
1869                 rc = -ENOMEM;
1870                 goto no_dma;
1871         }
1872
1873         priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1874                                        emac_tx_handler);
1875         priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1876                                        emac_rx_handler);
1877         if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1878                 rc = -ENOMEM;
1879                 goto no_irq_res;
1880         }
1881
1882         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1883         if (!res) {
1884                 dev_err(&pdev->dev, "error getting irq res\n");
1885                 rc = -ENOENT;
1886                 goto no_irq_res;
1887         }
1888         ndev->irq = res->start;
1889
1890         if (!is_valid_ether_addr(priv->mac_addr)) {
1891                 /* Use random MAC if none passed */
1892                 random_ether_addr(priv->mac_addr);
1893                 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1894                                                         priv->mac_addr);
1895         }
1896
1897         ndev->netdev_ops = &emac_netdev_ops;
1898         SET_ETHTOOL_OPS(ndev, &ethtool_ops);
1899         netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1900
1901         clk_enable(emac_clk);
1902
1903         /* register the network device */
1904         SET_NETDEV_DEV(ndev, &pdev->dev);
1905         rc = register_netdev(ndev);
1906         if (rc) {
1907                 dev_err(&pdev->dev, "error in register_netdev\n");
1908                 rc = -ENODEV;
1909                 goto netdev_reg_err;
1910         }
1911
1912
1913         if (netif_msg_probe(priv)) {
1914                 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
1915                            "(regs: %p, irq: %d)\n",
1916                            (void *)priv->emac_base_phys, ndev->irq);
1917         }
1918         return 0;
1919
1920 netdev_reg_err:
1921         clk_disable(emac_clk);
1922 no_irq_res:
1923         if (priv->txchan)
1924                 cpdma_chan_destroy(priv->txchan);
1925         if (priv->rxchan)
1926                 cpdma_chan_destroy(priv->rxchan);
1927         cpdma_ctlr_destroy(priv->dma);
1928 no_dma:
1929         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1930         release_mem_region(res->start, resource_size(res));
1931         iounmap(priv->remap_addr);
1932
1933 probe_quit:
1934         free_netdev(ndev);
1935 free_clk:
1936         clk_put(emac_clk);
1937         return rc;
1938 }
1939
1940 /**
1941  * davinci_emac_remove: EMAC device remove
1942  * @pdev: The DaVinci EMAC device that we are removing
1943  *
1944  * Called when removing the device driver. We disable clock usage and release
1945  * the resources taken up by the driver and unregister network device
1946  */
1947 static int __devexit davinci_emac_remove(struct platform_device *pdev)
1948 {
1949         struct resource *res;
1950         struct net_device *ndev = platform_get_drvdata(pdev);
1951         struct emac_priv *priv = netdev_priv(ndev);
1952
1953         dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1954
1955         platform_set_drvdata(pdev, NULL);
1956         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1957
1958         if (priv->txchan)
1959                 cpdma_chan_destroy(priv->txchan);
1960         if (priv->rxchan)
1961                 cpdma_chan_destroy(priv->rxchan);
1962         cpdma_ctlr_destroy(priv->dma);
1963
1964         release_mem_region(res->start, resource_size(res));
1965
1966         unregister_netdev(ndev);
1967         iounmap(priv->remap_addr);
1968         free_netdev(ndev);
1969
1970         clk_disable(emac_clk);
1971         clk_put(emac_clk);
1972
1973         return 0;
1974 }
1975
1976 static int davinci_emac_suspend(struct device *dev)
1977 {
1978         struct platform_device *pdev = to_platform_device(dev);
1979         struct net_device *ndev = platform_get_drvdata(pdev);
1980
1981         if (netif_running(ndev))
1982                 emac_dev_stop(ndev);
1983
1984         clk_disable(emac_clk);
1985
1986         return 0;
1987 }
1988
1989 static int davinci_emac_resume(struct device *dev)
1990 {
1991         struct platform_device *pdev = to_platform_device(dev);
1992         struct net_device *ndev = platform_get_drvdata(pdev);
1993
1994         clk_enable(emac_clk);
1995
1996         if (netif_running(ndev))
1997                 emac_dev_open(ndev);
1998
1999         return 0;
2000 }
2001
2002 static const struct dev_pm_ops davinci_emac_pm_ops = {
2003         .suspend        = davinci_emac_suspend,
2004         .resume         = davinci_emac_resume,
2005 };
2006
2007 /**
2008  * davinci_emac_driver: EMAC platform driver structure
2009  */
2010 static struct platform_driver davinci_emac_driver = {
2011         .driver = {
2012                 .name    = "davinci_emac",
2013                 .owner   = THIS_MODULE,
2014                 .pm      = &davinci_emac_pm_ops,
2015         },
2016         .probe = davinci_emac_probe,
2017         .remove = __devexit_p(davinci_emac_remove),
2018 };
2019
2020 /**
2021  * davinci_emac_init: EMAC driver module init
2022  *
2023  * Called when initializing the driver. We register the driver with
2024  * the platform.
2025  */
2026 static int __init davinci_emac_init(void)
2027 {
2028         return platform_driver_register(&davinci_emac_driver);
2029 }
2030 late_initcall(davinci_emac_init);
2031
2032 /**
2033  * davinci_emac_exit: EMAC driver module exit
2034  *
2035  * Called when exiting the driver completely. We unregister the driver with
2036  * the platform and exit
2037  */
2038 static void __exit davinci_emac_exit(void)
2039 {
2040         platform_driver_unregister(&davinci_emac_driver);
2041 }
2042 module_exit(davinci_emac_exit);
2043
2044 MODULE_LICENSE("GPL");
2045 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2046 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2047 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");