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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / forcedeth.c
blob6d5fbd4d4256ba527ea295030e91c6dd5b7373f6
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/io.h>
69
70 #include <asm/irq.h>
71 #include <asm/system.h>
72
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
75
76 /*
77 * Hardware access:
78 */
79
80 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
92 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
93 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
107
108 enum {
109 NvRegIrqStatus = 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask = 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
128
129 NvRegUnknownSetupReg6 = 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
131
132 /*
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
135 */
136 NvRegPollingInterval = 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
143 NvRegMisc1 = 0x080,
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
147
148 NvRegMacReset = 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
167
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
174
175 NvRegOffloadConfig = 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus = 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
183
184 NvRegSlotTime = 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
191
192 NvRegTxDeferral = 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral = 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB = 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
210
211 NvRegPhyInterface = 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl = 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
218
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll = 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed = 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark = 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl = 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
252 NvRegTxPauseFrame = 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit = 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus = 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask = 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
266
267 NvRegAdapterControl = 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
284 NvRegWakeUpFlags = 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
296
297 NvRegMgmtUnitGetVersion = 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl = 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
315 NvRegTxCnt = 0x280,
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
327 NvRegRxRunt = 0x2b0,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
336 NvRegTxDef = 0x2d4,
337 NvRegTxFrame = 0x2d8,
338 NvRegRxCnt = 0x2dc,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
342 NvRegVlanControl = 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
347
348 NvRegPowerState2 = 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
353 };
354
355 /* Big endian: should work, but is untested */
356 struct ring_desc {
357 __le32 buf;
358 __le32 flaglen;
359 };
360
361 struct ring_desc_ex {
362 __le32 bufhigh;
363 __le32 buflow;
364 __le32 txvlan;
365 __le32 flaglen;
366 };
367
368 union ring_type {
369 struct ring_desc *orig;
370 struct ring_desc_ex *ex;
371 };
372
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
377
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
388
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
406
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
408
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
422
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
440
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
443
444 /* Miscellaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
449
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
466
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
469
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
472
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
479
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
484
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
488
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
493
494 /*
495 * desc_ver values:
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
500 */
501 #define DESC_VER_1 1
502 #define DESC_VER_2 2
503 #define DESC_VER_3 3
504
505 /* PHY defines */
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
564
565 #define PHY_GIGABIT 0x0100
566
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
569
570 #define PHY_100 0x1
571 #define PHY_1000 0x2
572 #define PHY_HALF 0x100
573
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
581
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
589
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
594
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
597
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
600
601 #define NV_TX_LIMIT_COUNT 16
602
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
605
606 /* statistics */
607 struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
609 };
610
611 static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" },
613 { "tx_zero_rexmt" },
614 { "tx_one_rexmt" },
615 { "tx_many_rexmt" },
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
622 { "rx_extra_byte" },
623 { "rx_late_collision" },
624 { "rx_runt" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
627 { "rx_crc_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
630 { "rx_unicast" },
631 { "rx_multicast" },
632 { "rx_broadcast" },
633 { "rx_packets" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
636
637 /* version 2 stats */
638 { "tx_deferral" },
639 { "tx_packets" },
640 { "rx_bytes" },
641 { "tx_pause" },
642 { "rx_pause" },
643 { "rx_drop_frame" },
644
645 /* version 3 stats */
646 { "tx_unicast" },
647 { "tx_multicast" },
648 { "tx_broadcast" }
649 };
650
651 struct nv_ethtool_stats {
652 u64 tx_bytes;
653 u64 tx_zero_rexmt;
654 u64 tx_one_rexmt;
655 u64 tx_many_rexmt;
656 u64 tx_late_collision;
657 u64 tx_fifo_errors;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
660 u64 tx_retry_error;
661 u64 rx_frame_error;
662 u64 rx_extra_byte;
663 u64 rx_late_collision;
664 u64 rx_runt;
665 u64 rx_frame_too_long;
666 u64 rx_over_errors;
667 u64 rx_crc_errors;
668 u64 rx_frame_align_error;
669 u64 rx_length_error;
670 u64 rx_unicast;
671 u64 rx_multicast;
672 u64 rx_broadcast;
673 u64 rx_packets;
674 u64 rx_errors_total;
675 u64 tx_errors_total;
676
677 /* version 2 stats */
678 u64 tx_deferral;
679 u64 tx_packets;
680 u64 rx_bytes;
681 u64 tx_pause;
682 u64 rx_pause;
683 u64 rx_drop_frame;
684
685 /* version 3 stats */
686 u64 tx_unicast;
687 u64 tx_multicast;
688 u64 tx_broadcast;
689 };
690
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
694
695 /* diagnostics */
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
698
699 static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
704 };
705
706 struct register_test {
707 __u32 reg;
708 __u32 mask;
709 };
710
711 static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
716 { NvRegTxWatermark, 0x0ff },
717 { NvRegWakeUpFlags, 0x07777 },
718 { 0, 0 }
719 };
720
721 struct nv_skb_map {
722 struct sk_buff *skb;
723 dma_addr_t dma;
724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
728 };
729
730 /*
731 * SMP locking:
732 * All hardware access under netdev_priv(dev)->lock, except the performance
733 * critical parts:
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
739 */
740
741 /* in dev: base, irq */
742 struct fe_priv {
743 spinlock_t lock;
744
745 struct net_device *dev;
746 struct napi_struct napi;
747
748 /* General data:
749 * Locking: spin_lock(&np->lock); */
750 struct nv_ethtool_stats estats;
751 int in_shutdown;
752 u32 linkspeed;
753 int duplex;
754 int autoneg;
755 int fixed_mode;
756 int phyaddr;
757 int wolenabled;
758 unsigned int phy_oui;
759 unsigned int phy_model;
760 unsigned int phy_rev;
761 u16 gigabit;
762 int intr_test;
763 int recover_error;
764 int quiet_count;
765
766 /* General data: RO fields */
767 dma_addr_t ring_addr;
768 struct pci_dev *pci_dev;
769 u32 orig_mac[2];
770 u32 events;
771 u32 irqmask;
772 u32 desc_ver;
773 u32 txrxctl_bits;
774 u32 vlanctl_bits;
775 u32 driver_data;
776 u32 device_id;
777 u32 register_size;
778 u32 mac_in_use;
779 int mgmt_version;
780 int mgmt_sema;
781
782 void __iomem *base;
783
784 /* rx specific fields.
785 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786 */
787 union ring_type get_rx, put_rx, first_rx, last_rx;
788 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790 struct nv_skb_map *rx_skb;
791
792 union ring_type rx_ring;
793 unsigned int rx_buf_sz;
794 unsigned int pkt_limit;
795 struct timer_list oom_kick;
796 struct timer_list nic_poll;
797 struct timer_list stats_poll;
798 u32 nic_poll_irq;
799 int rx_ring_size;
800
801 /* media detection workaround.
802 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803 */
804 int need_linktimer;
805 unsigned long link_timeout;
806 /*
807 * tx specific fields.
808 */
809 union ring_type get_tx, put_tx, first_tx, last_tx;
810 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812 struct nv_skb_map *tx_skb;
813
814 union ring_type tx_ring;
815 u32 tx_flags;
816 int tx_ring_size;
817 int tx_limit;
818 u32 tx_pkts_in_progress;
819 struct nv_skb_map *tx_change_owner;
820 struct nv_skb_map *tx_end_flip;
821 int tx_stop;
822
823 /* msi/msi-x fields */
824 u32 msi_flags;
825 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
826
827 /* flow control */
828 u32 pause_flags;
829
830 /* power saved state */
831 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
832
833 /* for different msi-x irq type */
834 char name_rx[IFNAMSIZ + 3]; /* -rx */
835 char name_tx[IFNAMSIZ + 3]; /* -tx */
836 char name_other[IFNAMSIZ + 6]; /* -other */
837 };
838
839 /*
840 * Maximum number of loops until we assume that a bit in the irq mask
841 * is stuck. Overridable with module param.
842 */
843 static int max_interrupt_work = 4;
844
845 /*
846 * Optimization can be either throuput mode or cpu mode
847 *
848 * Throughput Mode: Every tx and rx packet will generate an interrupt.
849 * CPU Mode: Interrupts are controlled by a timer.
850 */
851 enum {
852 NV_OPTIMIZATION_MODE_THROUGHPUT,
853 NV_OPTIMIZATION_MODE_CPU,
854 NV_OPTIMIZATION_MODE_DYNAMIC
855 };
856 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
857
858 /*
859 * Poll interval for timer irq
860 *
861 * This interval determines how frequent an interrupt is generated.
862 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
863 * Min = 0, and Max = 65535
864 */
865 static int poll_interval = -1;
866
867 /*
868 * MSI interrupts
869 */
870 enum {
871 NV_MSI_INT_DISABLED,
872 NV_MSI_INT_ENABLED
873 };
874 static int msi = NV_MSI_INT_ENABLED;
875
876 /*
877 * MSIX interrupts
878 */
879 enum {
880 NV_MSIX_INT_DISABLED,
881 NV_MSIX_INT_ENABLED
882 };
883 static int msix = NV_MSIX_INT_ENABLED;
884
885 /*
886 * DMA 64bit
887 */
888 enum {
889 NV_DMA_64BIT_DISABLED,
890 NV_DMA_64BIT_ENABLED
891 };
892 static int dma_64bit = NV_DMA_64BIT_ENABLED;
893
894 /*
895 * Crossover Detection
896 * Realtek 8201 phy + some OEM boards do not work properly.
897 */
898 enum {
899 NV_CROSSOVER_DETECTION_DISABLED,
900 NV_CROSSOVER_DETECTION_ENABLED
901 };
902 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
903
904 /*
905 * Power down phy when interface is down (persists through reboot;
906 * older Linux and other OSes may not power it up again)
907 */
908 static int phy_power_down;
909
910 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
911 {
912 return netdev_priv(dev);
913 }
914
915 static inline u8 __iomem *get_hwbase(struct net_device *dev)
916 {
917 return ((struct fe_priv *)netdev_priv(dev))->base;
918 }
919
920 static inline void pci_push(u8 __iomem *base)
921 {
922 /* force out pending posted writes */
923 readl(base);
924 }
925
926 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
927 {
928 return le32_to_cpu(prd->flaglen)
929 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
930 }
931
932 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
933 {
934 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
935 }
936
937 static bool nv_optimized(struct fe_priv *np)
938 {
939 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
940 return false;
941 return true;
942 }
943
944 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
945 int delay, int delaymax)
946 {
947 u8 __iomem *base = get_hwbase(dev);
948
949 pci_push(base);
950 do {
951 udelay(delay);
952 delaymax -= delay;
953 if (delaymax < 0)
954 return 1;
955 } while ((readl(base + offset) & mask) != target);
956 return 0;
957 }
958
959 #define NV_SETUP_RX_RING 0x01
960 #define NV_SETUP_TX_RING 0x02
961
962 static inline u32 dma_low(dma_addr_t addr)
963 {
964 return addr;
965 }
966
967 static inline u32 dma_high(dma_addr_t addr)
968 {
969 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
970 }
971
972 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
973 {
974 struct fe_priv *np = get_nvpriv(dev);
975 u8 __iomem *base = get_hwbase(dev);
976
977 if (!nv_optimized(np)) {
978 if (rxtx_flags & NV_SETUP_RX_RING)
979 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
980 if (rxtx_flags & NV_SETUP_TX_RING)
981 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
982 } else {
983 if (rxtx_flags & NV_SETUP_RX_RING) {
984 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
985 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
986 }
987 if (rxtx_flags & NV_SETUP_TX_RING) {
988 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
989 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
990 }
991 }
992 }
993
994 static void free_rings(struct net_device *dev)
995 {
996 struct fe_priv *np = get_nvpriv(dev);
997
998 if (!nv_optimized(np)) {
999 if (np->rx_ring.orig)
1000 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1001 np->rx_ring.orig, np->ring_addr);
1002 } else {
1003 if (np->rx_ring.ex)
1004 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1005 np->rx_ring.ex, np->ring_addr);
1006 }
1007 kfree(np->rx_skb);
1008 kfree(np->tx_skb);
1009 }
1010
1011 static int using_multi_irqs(struct net_device *dev)
1012 {
1013 struct fe_priv *np = get_nvpriv(dev);
1014
1015 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1016 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1017 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1018 return 0;
1019 else
1020 return 1;
1021 }
1022
1023 static void nv_txrx_gate(struct net_device *dev, bool gate)
1024 {
1025 struct fe_priv *np = get_nvpriv(dev);
1026 u8 __iomem *base = get_hwbase(dev);
1027 u32 powerstate;
1028
1029 if (!np->mac_in_use &&
1030 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1031 powerstate = readl(base + NvRegPowerState2);
1032 if (gate)
1033 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1034 else
1035 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1036 writel(powerstate, base + NvRegPowerState2);
1037 }
1038 }
1039
1040 static void nv_enable_irq(struct net_device *dev)
1041 {
1042 struct fe_priv *np = get_nvpriv(dev);
1043
1044 if (!using_multi_irqs(dev)) {
1045 if (np->msi_flags & NV_MSI_X_ENABLED)
1046 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1047 else
1048 enable_irq(np->pci_dev->irq);
1049 } else {
1050 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1051 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1053 }
1054 }
1055
1056 static void nv_disable_irq(struct net_device *dev)
1057 {
1058 struct fe_priv *np = get_nvpriv(dev);
1059
1060 if (!using_multi_irqs(dev)) {
1061 if (np->msi_flags & NV_MSI_X_ENABLED)
1062 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1063 else
1064 disable_irq(np->pci_dev->irq);
1065 } else {
1066 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1067 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1069 }
1070 }
1071
1072 /* In MSIX mode, a write to irqmask behaves as XOR */
1073 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1074 {
1075 u8 __iomem *base = get_hwbase(dev);
1076
1077 writel(mask, base + NvRegIrqMask);
1078 }
1079
1080 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1081 {
1082 struct fe_priv *np = get_nvpriv(dev);
1083 u8 __iomem *base = get_hwbase(dev);
1084
1085 if (np->msi_flags & NV_MSI_X_ENABLED) {
1086 writel(mask, base + NvRegIrqMask);
1087 } else {
1088 if (np->msi_flags & NV_MSI_ENABLED)
1089 writel(0, base + NvRegMSIIrqMask);
1090 writel(0, base + NvRegIrqMask);
1091 }
1092 }
1093
1094 static void nv_napi_enable(struct net_device *dev)
1095 {
1096 struct fe_priv *np = get_nvpriv(dev);
1097
1098 napi_enable(&np->napi);
1099 }
1100
1101 static void nv_napi_disable(struct net_device *dev)
1102 {
1103 struct fe_priv *np = get_nvpriv(dev);
1104
1105 napi_disable(&np->napi);
1106 }
1107
1108 #define MII_READ (-1)
1109 /* mii_rw: read/write a register on the PHY.
1110 *
1111 * Caller must guarantee serialization
1112 */
1113 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1114 {
1115 u8 __iomem *base = get_hwbase(dev);
1116 u32 reg;
1117 int retval;
1118
1119 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1120
1121 reg = readl(base + NvRegMIIControl);
1122 if (reg & NVREG_MIICTL_INUSE) {
1123 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1124 udelay(NV_MIIBUSY_DELAY);
1125 }
1126
1127 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1128 if (value != MII_READ) {
1129 writel(value, base + NvRegMIIData);
1130 reg |= NVREG_MIICTL_WRITE;
1131 }
1132 writel(reg, base + NvRegMIIControl);
1133
1134 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1135 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1136 retval = -1;
1137 } else if (value != MII_READ) {
1138 /* it was a write operation - fewer failures are detectable */
1139 retval = 0;
1140 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1141 retval = -1;
1142 } else {
1143 retval = readl(base + NvRegMIIData);
1144 }
1145
1146 return retval;
1147 }
1148
1149 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1150 {
1151 struct fe_priv *np = netdev_priv(dev);
1152 u32 miicontrol;
1153 unsigned int tries = 0;
1154
1155 miicontrol = BMCR_RESET | bmcr_setup;
1156 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1157 return -1;
1158
1159 /* wait for 500ms */
1160 msleep(500);
1161
1162 /* must wait till reset is deasserted */
1163 while (miicontrol & BMCR_RESET) {
1164 usleep_range(10000, 20000);
1165 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1166 /* FIXME: 100 tries seem excessive */
1167 if (tries++ > 100)
1168 return -1;
1169 }
1170 return 0;
1171 }
1172
1173 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1174 {
1175 static const struct {
1176 int reg;
1177 int init;
1178 } ri[] = {
1179 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1180 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1181 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1182 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1183 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1184 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1185 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1186 };
1187 int i;
1188
1189 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1190 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1191 return PHY_ERROR;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1198 {
1199 u32 reg;
1200 u8 __iomem *base = get_hwbase(dev);
1201 u32 powerstate = readl(base + NvRegPowerState2);
1202
1203 /* need to perform hw phy reset */
1204 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1205 writel(powerstate, base + NvRegPowerState2);
1206 msleep(25);
1207
1208 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1209 writel(powerstate, base + NvRegPowerState2);
1210 msleep(25);
1211
1212 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1213 reg |= PHY_REALTEK_INIT9;
1214 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1215 return PHY_ERROR;
1216 if (mii_rw(dev, np->phyaddr,
1217 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1218 return PHY_ERROR;
1219 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1220 if (!(reg & PHY_REALTEK_INIT11)) {
1221 reg |= PHY_REALTEK_INIT11;
1222 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1223 return PHY_ERROR;
1224 }
1225 if (mii_rw(dev, np->phyaddr,
1226 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1227 return PHY_ERROR;
1228
1229 return 0;
1230 }
1231
1232 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1233 {
1234 u32 phy_reserved;
1235
1236 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1237 phy_reserved = mii_rw(dev, np->phyaddr,
1238 PHY_REALTEK_INIT_REG6, MII_READ);
1239 phy_reserved |= PHY_REALTEK_INIT7;
1240 if (mii_rw(dev, np->phyaddr,
1241 PHY_REALTEK_INIT_REG6, phy_reserved))
1242 return PHY_ERROR;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1249 {
1250 u32 phy_reserved;
1251
1252 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1253 if (mii_rw(dev, np->phyaddr,
1254 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1255 return PHY_ERROR;
1256 phy_reserved = mii_rw(dev, np->phyaddr,
1257 PHY_REALTEK_INIT_REG2, MII_READ);
1258 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1259 phy_reserved |= PHY_REALTEK_INIT3;
1260 if (mii_rw(dev, np->phyaddr,
1261 PHY_REALTEK_INIT_REG2, phy_reserved))
1262 return PHY_ERROR;
1263 if (mii_rw(dev, np->phyaddr,
1264 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1265 return PHY_ERROR;
1266 }
1267
1268 return 0;
1269 }
1270
1271 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1272 u32 phyinterface)
1273 {
1274 u32 phy_reserved;
1275
1276 if (phyinterface & PHY_RGMII) {
1277 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1278 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1279 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1280 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1281 return PHY_ERROR;
1282 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1283 phy_reserved |= PHY_CICADA_INIT5;
1284 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1285 return PHY_ERROR;
1286 }
1287 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1288 phy_reserved |= PHY_CICADA_INIT6;
1289 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1290 return PHY_ERROR;
1291
1292 return 0;
1293 }
1294
1295 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1296 {
1297 u32 phy_reserved;
1298
1299 if (mii_rw(dev, np->phyaddr,
1300 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1301 return PHY_ERROR;
1302 if (mii_rw(dev, np->phyaddr,
1303 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1304 return PHY_ERROR;
1305 phy_reserved = mii_rw(dev, np->phyaddr,
1306 PHY_VITESSE_INIT_REG4, MII_READ);
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1308 return PHY_ERROR;
1309 phy_reserved = mii_rw(dev, np->phyaddr,
1310 PHY_VITESSE_INIT_REG3, MII_READ);
1311 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1312 phy_reserved |= PHY_VITESSE_INIT3;
1313 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1314 return PHY_ERROR;
1315 if (mii_rw(dev, np->phyaddr,
1316 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1317 return PHY_ERROR;
1318 if (mii_rw(dev, np->phyaddr,
1319 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1320 return PHY_ERROR;
1321 phy_reserved = mii_rw(dev, np->phyaddr,
1322 PHY_VITESSE_INIT_REG4, MII_READ);
1323 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1324 phy_reserved |= PHY_VITESSE_INIT3;
1325 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1326 return PHY_ERROR;
1327 phy_reserved = mii_rw(dev, np->phyaddr,
1328 PHY_VITESSE_INIT_REG3, MII_READ);
1329 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1330 return PHY_ERROR;
1331 if (mii_rw(dev, np->phyaddr,
1332 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1333 return PHY_ERROR;
1334 if (mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1336 return PHY_ERROR;
1337 phy_reserved = mii_rw(dev, np->phyaddr,
1338 PHY_VITESSE_INIT_REG4, MII_READ);
1339 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1340 return PHY_ERROR;
1341 phy_reserved = mii_rw(dev, np->phyaddr,
1342 PHY_VITESSE_INIT_REG3, MII_READ);
1343 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1344 phy_reserved |= PHY_VITESSE_INIT8;
1345 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1346 return PHY_ERROR;
1347 if (mii_rw(dev, np->phyaddr,
1348 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1349 return PHY_ERROR;
1350 if (mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1352 return PHY_ERROR;
1353
1354 return 0;
1355 }
1356
1357 static int phy_init(struct net_device *dev)
1358 {
1359 struct fe_priv *np = get_nvpriv(dev);
1360 u8 __iomem *base = get_hwbase(dev);
1361 u32 phyinterface;
1362 u32 mii_status, mii_control, mii_control_1000, reg;
1363
1364 /* phy errata for E3016 phy */
1365 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1366 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1367 reg &= ~PHY_MARVELL_E3016_INITMASK;
1368 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1369 netdev_info(dev, "%s: phy write to errata reg failed\n",
1370 pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 }
1374 if (np->phy_oui == PHY_OUI_REALTEK) {
1375 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1376 np->phy_rev == PHY_REV_REALTEK_8211B) {
1377 if (init_realtek_8211b(dev, np)) {
1378 netdev_info(dev, "%s: phy init failed\n",
1379 pci_name(np->pci_dev));
1380 return PHY_ERROR;
1381 }
1382 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1383 np->phy_rev == PHY_REV_REALTEK_8211C) {
1384 if (init_realtek_8211c(dev, np)) {
1385 netdev_info(dev, "%s: phy init failed\n",
1386 pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1390 if (init_realtek_8201(dev, np)) {
1391 netdev_info(dev, "%s: phy init failed\n",
1392 pci_name(np->pci_dev));
1393 return PHY_ERROR;
1394 }
1395 }
1396 }
1397
1398 /* set advertise register */
1399 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1400 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1401 ADVERTISE_100HALF | ADVERTISE_100FULL |
1402 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1403 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1404 netdev_info(dev, "%s: phy write to advertise failed\n",
1405 pci_name(np->pci_dev));
1406 return PHY_ERROR;
1407 }
1408
1409 /* get phy interface type */
1410 phyinterface = readl(base + NvRegPhyInterface);
1411
1412 /* see if gigabit phy */
1413 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1414 if (mii_status & PHY_GIGABIT) {
1415 np->gigabit = PHY_GIGABIT;
1416 mii_control_1000 = mii_rw(dev, np->phyaddr,
1417 MII_CTRL1000, MII_READ);
1418 mii_control_1000 &= ~ADVERTISE_1000HALF;
1419 if (phyinterface & PHY_RGMII)
1420 mii_control_1000 |= ADVERTISE_1000FULL;
1421 else
1422 mii_control_1000 &= ~ADVERTISE_1000FULL;
1423
1424 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1425 netdev_info(dev, "%s: phy init failed\n",
1426 pci_name(np->pci_dev));
1427 return PHY_ERROR;
1428 }
1429 } else
1430 np->gigabit = 0;
1431
1432 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1433 mii_control |= BMCR_ANENABLE;
1434
1435 if (np->phy_oui == PHY_OUI_REALTEK &&
1436 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1437 np->phy_rev == PHY_REV_REALTEK_8211C) {
1438 /* start autoneg since we already performed hw reset above */
1439 mii_control |= BMCR_ANRESTART;
1440 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1441 netdev_info(dev, "%s: phy init failed\n",
1442 pci_name(np->pci_dev));
1443 return PHY_ERROR;
1444 }
1445 } else {
1446 /* reset the phy
1447 * (certain phys need bmcr to be setup with reset)
1448 */
1449 if (phy_reset(dev, mii_control)) {
1450 netdev_info(dev, "%s: phy reset failed\n",
1451 pci_name(np->pci_dev));
1452 return PHY_ERROR;
1453 }
1454 }
1455
1456 /* phy vendor specific configuration */
1457 if ((np->phy_oui == PHY_OUI_CICADA)) {
1458 if (init_cicada(dev, np, phyinterface)) {
1459 netdev_info(dev, "%s: phy init failed\n",
1460 pci_name(np->pci_dev));
1461 return PHY_ERROR;
1462 }
1463 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1464 if (init_vitesse(dev, np)) {
1465 netdev_info(dev, "%s: phy init failed\n",
1466 pci_name(np->pci_dev));
1467 return PHY_ERROR;
1468 }
1469 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1470 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1471 np->phy_rev == PHY_REV_REALTEK_8211B) {
1472 /* reset could have cleared these out, set them back */
1473 if (init_realtek_8211b(dev, np)) {
1474 netdev_info(dev, "%s: phy init failed\n",
1475 pci_name(np->pci_dev));
1476 return PHY_ERROR;
1477 }
1478 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1479 if (init_realtek_8201(dev, np) ||
1480 init_realtek_8201_cross(dev, np)) {
1481 netdev_info(dev, "%s: phy init failed\n",
1482 pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 }
1486 }
1487
1488 /* some phys clear out pause advertisement on reset, set it back */
1489 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1490
1491 /* restart auto negotiation, power down phy */
1492 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1493 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1494 if (phy_power_down)
1495 mii_control |= BMCR_PDOWN;
1496 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1497 return PHY_ERROR;
1498
1499 return 0;
1500 }
1501
1502 static void nv_start_rx(struct net_device *dev)
1503 {
1504 struct fe_priv *np = netdev_priv(dev);
1505 u8 __iomem *base = get_hwbase(dev);
1506 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1507
1508 /* Already running? Stop it. */
1509 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1510 rx_ctrl &= ~NVREG_RCVCTL_START;
1511 writel(rx_ctrl, base + NvRegReceiverControl);
1512 pci_push(base);
1513 }
1514 writel(np->linkspeed, base + NvRegLinkSpeed);
1515 pci_push(base);
1516 rx_ctrl |= NVREG_RCVCTL_START;
1517 if (np->mac_in_use)
1518 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1519 writel(rx_ctrl, base + NvRegReceiverControl);
1520 pci_push(base);
1521 }
1522
1523 static void nv_stop_rx(struct net_device *dev)
1524 {
1525 struct fe_priv *np = netdev_priv(dev);
1526 u8 __iomem *base = get_hwbase(dev);
1527 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1528
1529 if (!np->mac_in_use)
1530 rx_ctrl &= ~NVREG_RCVCTL_START;
1531 else
1532 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1533 writel(rx_ctrl, base + NvRegReceiverControl);
1534 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1535 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1536 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1537 __func__);
1538
1539 udelay(NV_RXSTOP_DELAY2);
1540 if (!np->mac_in_use)
1541 writel(0, base + NvRegLinkSpeed);
1542 }
1543
1544 static void nv_start_tx(struct net_device *dev)
1545 {
1546 struct fe_priv *np = netdev_priv(dev);
1547 u8 __iomem *base = get_hwbase(dev);
1548 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1549
1550 tx_ctrl |= NVREG_XMITCTL_START;
1551 if (np->mac_in_use)
1552 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1553 writel(tx_ctrl, base + NvRegTransmitterControl);
1554 pci_push(base);
1555 }
1556
1557 static void nv_stop_tx(struct net_device *dev)
1558 {
1559 struct fe_priv *np = netdev_priv(dev);
1560 u8 __iomem *base = get_hwbase(dev);
1561 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1562
1563 if (!np->mac_in_use)
1564 tx_ctrl &= ~NVREG_XMITCTL_START;
1565 else
1566 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1567 writel(tx_ctrl, base + NvRegTransmitterControl);
1568 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1569 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1570 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1571 __func__);
1572
1573 udelay(NV_TXSTOP_DELAY2);
1574 if (!np->mac_in_use)
1575 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1576 base + NvRegTransmitPoll);
1577 }
1578
1579 static void nv_start_rxtx(struct net_device *dev)
1580 {
1581 nv_start_rx(dev);
1582 nv_start_tx(dev);
1583 }
1584
1585 static void nv_stop_rxtx(struct net_device *dev)
1586 {
1587 nv_stop_rx(dev);
1588 nv_stop_tx(dev);
1589 }
1590
1591 static void nv_txrx_reset(struct net_device *dev)
1592 {
1593 struct fe_priv *np = netdev_priv(dev);
1594 u8 __iomem *base = get_hwbase(dev);
1595
1596 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1597 pci_push(base);
1598 udelay(NV_TXRX_RESET_DELAY);
1599 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1600 pci_push(base);
1601 }
1602
1603 static void nv_mac_reset(struct net_device *dev)
1604 {
1605 struct fe_priv *np = netdev_priv(dev);
1606 u8 __iomem *base = get_hwbase(dev);
1607 u32 temp1, temp2, temp3;
1608
1609 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1610 pci_push(base);
1611
1612 /* save registers since they will be cleared on reset */
1613 temp1 = readl(base + NvRegMacAddrA);
1614 temp2 = readl(base + NvRegMacAddrB);
1615 temp3 = readl(base + NvRegTransmitPoll);
1616
1617 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1618 pci_push(base);
1619 udelay(NV_MAC_RESET_DELAY);
1620 writel(0, base + NvRegMacReset);
1621 pci_push(base);
1622 udelay(NV_MAC_RESET_DELAY);
1623
1624 /* restore saved registers */
1625 writel(temp1, base + NvRegMacAddrA);
1626 writel(temp2, base + NvRegMacAddrB);
1627 writel(temp3, base + NvRegTransmitPoll);
1628
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631 }
1632
1633 static void nv_get_hw_stats(struct net_device *dev)
1634 {
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637
1638 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1639 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1640 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1641 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1642 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1643 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1644 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1645 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1646 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1647 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1648 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1649 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1650 np->estats.rx_runt += readl(base + NvRegRxRunt);
1651 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1652 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1653 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1654 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1655 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1656 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1657 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1658 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1659 np->estats.rx_packets =
1660 np->estats.rx_unicast +
1661 np->estats.rx_multicast +
1662 np->estats.rx_broadcast;
1663 np->estats.rx_errors_total =
1664 np->estats.rx_crc_errors +
1665 np->estats.rx_over_errors +
1666 np->estats.rx_frame_error +
1667 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1668 np->estats.rx_late_collision +
1669 np->estats.rx_runt +
1670 np->estats.rx_frame_too_long;
1671 np->estats.tx_errors_total =
1672 np->estats.tx_late_collision +
1673 np->estats.tx_fifo_errors +
1674 np->estats.tx_carrier_errors +
1675 np->estats.tx_excess_deferral +
1676 np->estats.tx_retry_error;
1677
1678 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1679 np->estats.tx_deferral += readl(base + NvRegTxDef);
1680 np->estats.tx_packets += readl(base + NvRegTxFrame);
1681 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1682 np->estats.tx_pause += readl(base + NvRegTxPause);
1683 np->estats.rx_pause += readl(base + NvRegRxPause);
1684 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1685 }
1686
1687 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1688 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1689 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1690 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1691 }
1692 }
1693
1694 /*
1695 * nv_get_stats: dev->get_stats function
1696 * Get latest stats value from the nic.
1697 * Called with read_lock(&dev_base_lock) held for read -
1698 * only synchronized against unregister_netdevice.
1699 */
1700 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1701 {
1702 struct fe_priv *np = netdev_priv(dev);
1703
1704 /* If the nic supports hw counters then retrieve latest values */
1705 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1706 nv_get_hw_stats(dev);
1707
1708 /* copy to net_device stats */
1709 dev->stats.tx_bytes = np->estats.tx_bytes;
1710 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1711 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1712 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1713 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1714 dev->stats.rx_errors = np->estats.rx_errors_total;
1715 dev->stats.tx_errors = np->estats.tx_errors_total;
1716 }
1717
1718 return &dev->stats;
1719 }
1720
1721 /*
1722 * nv_alloc_rx: fill rx ring entries.
1723 * Return 1 if the allocations for the skbs failed and the
1724 * rx engine is without Available descriptors
1725 */
1726 static int nv_alloc_rx(struct net_device *dev)
1727 {
1728 struct fe_priv *np = netdev_priv(dev);
1729 struct ring_desc *less_rx;
1730
1731 less_rx = np->get_rx.orig;
1732 if (less_rx-- == np->first_rx.orig)
1733 less_rx = np->last_rx.orig;
1734
1735 while (np->put_rx.orig != less_rx) {
1736 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1737 if (skb) {
1738 np->put_rx_ctx->skb = skb;
1739 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1740 skb->data,
1741 skb_tailroom(skb),
1742 PCI_DMA_FROMDEVICE);
1743 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1744 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1745 wmb();
1746 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1747 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1748 np->put_rx.orig = np->first_rx.orig;
1749 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1750 np->put_rx_ctx = np->first_rx_ctx;
1751 } else
1752 return 1;
1753 }
1754 return 0;
1755 }
1756
1757 static int nv_alloc_rx_optimized(struct net_device *dev)
1758 {
1759 struct fe_priv *np = netdev_priv(dev);
1760 struct ring_desc_ex *less_rx;
1761
1762 less_rx = np->get_rx.ex;
1763 if (less_rx-- == np->first_rx.ex)
1764 less_rx = np->last_rx.ex;
1765
1766 while (np->put_rx.ex != less_rx) {
1767 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1768 if (skb) {
1769 np->put_rx_ctx->skb = skb;
1770 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1771 skb->data,
1772 skb_tailroom(skb),
1773 PCI_DMA_FROMDEVICE);
1774 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1775 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1776 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1777 wmb();
1778 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1779 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1780 np->put_rx.ex = np->first_rx.ex;
1781 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1782 np->put_rx_ctx = np->first_rx_ctx;
1783 } else
1784 return 1;
1785 }
1786 return 0;
1787 }
1788
1789 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1790 static void nv_do_rx_refill(unsigned long data)
1791 {
1792 struct net_device *dev = (struct net_device *) data;
1793 struct fe_priv *np = netdev_priv(dev);
1794
1795 /* Just reschedule NAPI rx processing */
1796 napi_schedule(&np->napi);
1797 }
1798
1799 static void nv_init_rx(struct net_device *dev)
1800 {
1801 struct fe_priv *np = netdev_priv(dev);
1802 int i;
1803
1804 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1805
1806 if (!nv_optimized(np))
1807 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1808 else
1809 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1810 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1811 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1812
1813 for (i = 0; i < np->rx_ring_size; i++) {
1814 if (!nv_optimized(np)) {
1815 np->rx_ring.orig[i].flaglen = 0;
1816 np->rx_ring.orig[i].buf = 0;
1817 } else {
1818 np->rx_ring.ex[i].flaglen = 0;
1819 np->rx_ring.ex[i].txvlan = 0;
1820 np->rx_ring.ex[i].bufhigh = 0;
1821 np->rx_ring.ex[i].buflow = 0;
1822 }
1823 np->rx_skb[i].skb = NULL;
1824 np->rx_skb[i].dma = 0;
1825 }
1826 }
1827
1828 static void nv_init_tx(struct net_device *dev)
1829 {
1830 struct fe_priv *np = netdev_priv(dev);
1831 int i;
1832
1833 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1834
1835 if (!nv_optimized(np))
1836 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1837 else
1838 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1839 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1840 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1841 np->tx_pkts_in_progress = 0;
1842 np->tx_change_owner = NULL;
1843 np->tx_end_flip = NULL;
1844 np->tx_stop = 0;
1845
1846 for (i = 0; i < np->tx_ring_size; i++) {
1847 if (!nv_optimized(np)) {
1848 np->tx_ring.orig[i].flaglen = 0;
1849 np->tx_ring.orig[i].buf = 0;
1850 } else {
1851 np->tx_ring.ex[i].flaglen = 0;
1852 np->tx_ring.ex[i].txvlan = 0;
1853 np->tx_ring.ex[i].bufhigh = 0;
1854 np->tx_ring.ex[i].buflow = 0;
1855 }
1856 np->tx_skb[i].skb = NULL;
1857 np->tx_skb[i].dma = 0;
1858 np->tx_skb[i].dma_len = 0;
1859 np->tx_skb[i].dma_single = 0;
1860 np->tx_skb[i].first_tx_desc = NULL;
1861 np->tx_skb[i].next_tx_ctx = NULL;
1862 }
1863 }
1864
1865 static int nv_init_ring(struct net_device *dev)
1866 {
1867 struct fe_priv *np = netdev_priv(dev);
1868
1869 nv_init_tx(dev);
1870 nv_init_rx(dev);
1871
1872 if (!nv_optimized(np))
1873 return nv_alloc_rx(dev);
1874 else
1875 return nv_alloc_rx_optimized(dev);
1876 }
1877
1878 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1879 {
1880 if (tx_skb->dma) {
1881 if (tx_skb->dma_single)
1882 pci_unmap_single(np->pci_dev, tx_skb->dma,
1883 tx_skb->dma_len,
1884 PCI_DMA_TODEVICE);
1885 else
1886 pci_unmap_page(np->pci_dev, tx_skb->dma,
1887 tx_skb->dma_len,
1888 PCI_DMA_TODEVICE);
1889 tx_skb->dma = 0;
1890 }
1891 }
1892
1893 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1894 {
1895 nv_unmap_txskb(np, tx_skb);
1896 if (tx_skb->skb) {
1897 dev_kfree_skb_any(tx_skb->skb);
1898 tx_skb->skb = NULL;
1899 return 1;
1900 }
1901 return 0;
1902 }
1903
1904 static void nv_drain_tx(struct net_device *dev)
1905 {
1906 struct fe_priv *np = netdev_priv(dev);
1907 unsigned int i;
1908
1909 for (i = 0; i < np->tx_ring_size; i++) {
1910 if (!nv_optimized(np)) {
1911 np->tx_ring.orig[i].flaglen = 0;
1912 np->tx_ring.orig[i].buf = 0;
1913 } else {
1914 np->tx_ring.ex[i].flaglen = 0;
1915 np->tx_ring.ex[i].txvlan = 0;
1916 np->tx_ring.ex[i].bufhigh = 0;
1917 np->tx_ring.ex[i].buflow = 0;
1918 }
1919 if (nv_release_txskb(np, &np->tx_skb[i]))
1920 dev->stats.tx_dropped++;
1921 np->tx_skb[i].dma = 0;
1922 np->tx_skb[i].dma_len = 0;
1923 np->tx_skb[i].dma_single = 0;
1924 np->tx_skb[i].first_tx_desc = NULL;
1925 np->tx_skb[i].next_tx_ctx = NULL;
1926 }
1927 np->tx_pkts_in_progress = 0;
1928 np->tx_change_owner = NULL;
1929 np->tx_end_flip = NULL;
1930 }
1931
1932 static void nv_drain_rx(struct net_device *dev)
1933 {
1934 struct fe_priv *np = netdev_priv(dev);
1935 int i;
1936
1937 for (i = 0; i < np->rx_ring_size; i++) {
1938 if (!nv_optimized(np)) {
1939 np->rx_ring.orig[i].flaglen = 0;
1940 np->rx_ring.orig[i].buf = 0;
1941 } else {
1942 np->rx_ring.ex[i].flaglen = 0;
1943 np->rx_ring.ex[i].txvlan = 0;
1944 np->rx_ring.ex[i].bufhigh = 0;
1945 np->rx_ring.ex[i].buflow = 0;
1946 }
1947 wmb();
1948 if (np->rx_skb[i].skb) {
1949 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1950 (skb_end_pointer(np->rx_skb[i].skb) -
1951 np->rx_skb[i].skb->data),
1952 PCI_DMA_FROMDEVICE);
1953 dev_kfree_skb(np->rx_skb[i].skb);
1954 np->rx_skb[i].skb = NULL;
1955 }
1956 }
1957 }
1958
1959 static void nv_drain_rxtx(struct net_device *dev)
1960 {
1961 nv_drain_tx(dev);
1962 nv_drain_rx(dev);
1963 }
1964
1965 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1966 {
1967 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1968 }
1969
1970 static void nv_legacybackoff_reseed(struct net_device *dev)
1971 {
1972 u8 __iomem *base = get_hwbase(dev);
1973 u32 reg;
1974 u32 low;
1975 int tx_status = 0;
1976
1977 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1978 get_random_bytes(&low, sizeof(low));
1979 reg |= low & NVREG_SLOTTIME_MASK;
1980
1981 /* Need to stop tx before change takes effect.
1982 * Caller has already gained np->lock.
1983 */
1984 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1985 if (tx_status)
1986 nv_stop_tx(dev);
1987 nv_stop_rx(dev);
1988 writel(reg, base + NvRegSlotTime);
1989 if (tx_status)
1990 nv_start_tx(dev);
1991 nv_start_rx(dev);
1992 }
1993
1994 /* Gear Backoff Seeds */
1995 #define BACKOFF_SEEDSET_ROWS 8
1996 #define BACKOFF_SEEDSET_LFSRS 15
1997
1998 /* Known Good seed sets */
1999 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2000 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2001 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2002 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2003 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2004 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2005 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2006 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2007 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2008
2009 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2010 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2011 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2012 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2013 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2014 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2015 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2016 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2017 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2018
2019 static void nv_gear_backoff_reseed(struct net_device *dev)
2020 {
2021 u8 __iomem *base = get_hwbase(dev);
2022 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2023 u32 temp, seedset, combinedSeed;
2024 int i;
2025
2026 /* Setup seed for free running LFSR */
2027 /* We are going to read the time stamp counter 3 times
2028 and swizzle bits around to increase randomness */
2029 get_random_bytes(&miniseed1, sizeof(miniseed1));
2030 miniseed1 &= 0x0fff;
2031 if (miniseed1 == 0)
2032 miniseed1 = 0xabc;
2033
2034 get_random_bytes(&miniseed2, sizeof(miniseed2));
2035 miniseed2 &= 0x0fff;
2036 if (miniseed2 == 0)
2037 miniseed2 = 0xabc;
2038 miniseed2_reversed =
2039 ((miniseed2 & 0xF00) >> 8) |
2040 (miniseed2 & 0x0F0) |
2041 ((miniseed2 & 0x00F) << 8);
2042
2043 get_random_bytes(&miniseed3, sizeof(miniseed3));
2044 miniseed3 &= 0x0fff;
2045 if (miniseed3 == 0)
2046 miniseed3 = 0xabc;
2047 miniseed3_reversed =
2048 ((miniseed3 & 0xF00) >> 8) |
2049 (miniseed3 & 0x0F0) |
2050 ((miniseed3 & 0x00F) << 8);
2051
2052 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2053 (miniseed2 ^ miniseed3_reversed);
2054
2055 /* Seeds can not be zero */
2056 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2057 combinedSeed |= 0x08;
2058 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2059 combinedSeed |= 0x8000;
2060
2061 /* No need to disable tx here */
2062 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2063 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2064 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2065 writel(temp, base + NvRegBackOffControl);
2066
2067 /* Setup seeds for all gear LFSRs. */
2068 get_random_bytes(&seedset, sizeof(seedset));
2069 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2070 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2071 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2072 temp |= main_seedset[seedset][i-1] & 0x3ff;
2073 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2074 writel(temp, base + NvRegBackOffControl);
2075 }
2076 }
2077
2078 /*
2079 * nv_start_xmit: dev->hard_start_xmit function
2080 * Called with netif_tx_lock held.
2081 */
2082 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2083 {
2084 struct fe_priv *np = netdev_priv(dev);
2085 u32 tx_flags = 0;
2086 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2087 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2088 unsigned int i;
2089 u32 offset = 0;
2090 u32 bcnt;
2091 u32 size = skb_headlen(skb);
2092 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2093 u32 empty_slots;
2094 struct ring_desc *put_tx;
2095 struct ring_desc *start_tx;
2096 struct ring_desc *prev_tx;
2097 struct nv_skb_map *prev_tx_ctx;
2098 unsigned long flags;
2099
2100 /* add fragments to entries count */
2101 for (i = 0; i < fragments; i++) {
2102 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2103 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2104 }
2105
2106 spin_lock_irqsave(&np->lock, flags);
2107 empty_slots = nv_get_empty_tx_slots(np);
2108 if (unlikely(empty_slots <= entries)) {
2109 netif_stop_queue(dev);
2110 np->tx_stop = 1;
2111 spin_unlock_irqrestore(&np->lock, flags);
2112 return NETDEV_TX_BUSY;
2113 }
2114 spin_unlock_irqrestore(&np->lock, flags);
2115
2116 start_tx = put_tx = np->put_tx.orig;
2117
2118 /* setup the header buffer */
2119 do {
2120 prev_tx = put_tx;
2121 prev_tx_ctx = np->put_tx_ctx;
2122 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2123 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2124 PCI_DMA_TODEVICE);
2125 np->put_tx_ctx->dma_len = bcnt;
2126 np->put_tx_ctx->dma_single = 1;
2127 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2128 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2129
2130 tx_flags = np->tx_flags;
2131 offset += bcnt;
2132 size -= bcnt;
2133 if (unlikely(put_tx++ == np->last_tx.orig))
2134 put_tx = np->first_tx.orig;
2135 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2136 np->put_tx_ctx = np->first_tx_ctx;
2137 } while (size);
2138
2139 /* setup the fragments */
2140 for (i = 0; i < fragments; i++) {
2141 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2142 u32 size = frag->size;
2143 offset = 0;
2144
2145 do {
2146 prev_tx = put_tx;
2147 prev_tx_ctx = np->put_tx_ctx;
2148 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2149 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2150 PCI_DMA_TODEVICE);
2151 np->put_tx_ctx->dma_len = bcnt;
2152 np->put_tx_ctx->dma_single = 0;
2153 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2154 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2155
2156 offset += bcnt;
2157 size -= bcnt;
2158 if (unlikely(put_tx++ == np->last_tx.orig))
2159 put_tx = np->first_tx.orig;
2160 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2161 np->put_tx_ctx = np->first_tx_ctx;
2162 } while (size);
2163 }
2164
2165 /* set last fragment flag */
2166 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2167
2168 /* save skb in this slot's context area */
2169 prev_tx_ctx->skb = skb;
2170
2171 if (skb_is_gso(skb))
2172 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2173 else
2174 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2175 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 /* set tx flags */
2180 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2181 np->put_tx.orig = put_tx;
2182
2183 spin_unlock_irqrestore(&np->lock, flags);
2184
2185 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2186 return NETDEV_TX_OK;
2187 }
2188
2189 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2190 struct net_device *dev)
2191 {
2192 struct fe_priv *np = netdev_priv(dev);
2193 u32 tx_flags = 0;
2194 u32 tx_flags_extra;
2195 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2196 unsigned int i;
2197 u32 offset = 0;
2198 u32 bcnt;
2199 u32 size = skb_headlen(skb);
2200 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2201 u32 empty_slots;
2202 struct ring_desc_ex *put_tx;
2203 struct ring_desc_ex *start_tx;
2204 struct ring_desc_ex *prev_tx;
2205 struct nv_skb_map *prev_tx_ctx;
2206 struct nv_skb_map *start_tx_ctx;
2207 unsigned long flags;
2208
2209 /* add fragments to entries count */
2210 for (i = 0; i < fragments; i++) {
2211 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2212 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2213 }
2214
2215 spin_lock_irqsave(&np->lock, flags);
2216 empty_slots = nv_get_empty_tx_slots(np);
2217 if (unlikely(empty_slots <= entries)) {
2218 netif_stop_queue(dev);
2219 np->tx_stop = 1;
2220 spin_unlock_irqrestore(&np->lock, flags);
2221 return NETDEV_TX_BUSY;
2222 }
2223 spin_unlock_irqrestore(&np->lock, flags);
2224
2225 start_tx = put_tx = np->put_tx.ex;
2226 start_tx_ctx = np->put_tx_ctx;
2227
2228 /* setup the header buffer */
2229 do {
2230 prev_tx = put_tx;
2231 prev_tx_ctx = np->put_tx_ctx;
2232 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2233 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2234 PCI_DMA_TODEVICE);
2235 np->put_tx_ctx->dma_len = bcnt;
2236 np->put_tx_ctx->dma_single = 1;
2237 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2238 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2239 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2240
2241 tx_flags = NV_TX2_VALID;
2242 offset += bcnt;
2243 size -= bcnt;
2244 if (unlikely(put_tx++ == np->last_tx.ex))
2245 put_tx = np->first_tx.ex;
2246 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2247 np->put_tx_ctx = np->first_tx_ctx;
2248 } while (size);
2249
2250 /* setup the fragments */
2251 for (i = 0; i < fragments; i++) {
2252 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2253 u32 size = frag->size;
2254 offset = 0;
2255
2256 do {
2257 prev_tx = put_tx;
2258 prev_tx_ctx = np->put_tx_ctx;
2259 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2261 PCI_DMA_TODEVICE);
2262 np->put_tx_ctx->dma_len = bcnt;
2263 np->put_tx_ctx->dma_single = 0;
2264 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2265 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2266 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2267
2268 offset += bcnt;
2269 size -= bcnt;
2270 if (unlikely(put_tx++ == np->last_tx.ex))
2271 put_tx = np->first_tx.ex;
2272 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2273 np->put_tx_ctx = np->first_tx_ctx;
2274 } while (size);
2275 }
2276
2277 /* set last fragment flag */
2278 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2279
2280 /* save skb in this slot's context area */
2281 prev_tx_ctx->skb = skb;
2282
2283 if (skb_is_gso(skb))
2284 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2285 else
2286 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2287 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2288
2289 /* vlan tag */
2290 if (vlan_tx_tag_present(skb))
2291 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2292 vlan_tx_tag_get(skb));
2293 else
2294 start_tx->txvlan = 0;
2295
2296 spin_lock_irqsave(&np->lock, flags);
2297
2298 if (np->tx_limit) {
2299 /* Limit the number of outstanding tx. Setup all fragments, but
2300 * do not set the VALID bit on the first descriptor. Save a pointer
2301 * to that descriptor and also for next skb_map element.
2302 */
2303
2304 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2305 if (!np->tx_change_owner)
2306 np->tx_change_owner = start_tx_ctx;
2307
2308 /* remove VALID bit */
2309 tx_flags &= ~NV_TX2_VALID;
2310 start_tx_ctx->first_tx_desc = start_tx;
2311 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2312 np->tx_end_flip = np->put_tx_ctx;
2313 } else {
2314 np->tx_pkts_in_progress++;
2315 }
2316 }
2317
2318 /* set tx flags */
2319 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2320 np->put_tx.ex = put_tx;
2321
2322 spin_unlock_irqrestore(&np->lock, flags);
2323
2324 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2325 return NETDEV_TX_OK;
2326 }
2327
2328 static inline void nv_tx_flip_ownership(struct net_device *dev)
2329 {
2330 struct fe_priv *np = netdev_priv(dev);
2331
2332 np->tx_pkts_in_progress--;
2333 if (np->tx_change_owner) {
2334 np->tx_change_owner->first_tx_desc->flaglen |=
2335 cpu_to_le32(NV_TX2_VALID);
2336 np->tx_pkts_in_progress++;
2337
2338 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2339 if (np->tx_change_owner == np->tx_end_flip)
2340 np->tx_change_owner = NULL;
2341
2342 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2343 }
2344 }
2345
2346 /*
2347 * nv_tx_done: check for completed packets, release the skbs.
2348 *
2349 * Caller must own np->lock.
2350 */
2351 static int nv_tx_done(struct net_device *dev, int limit)
2352 {
2353 struct fe_priv *np = netdev_priv(dev);
2354 u32 flags;
2355 int tx_work = 0;
2356 struct ring_desc *orig_get_tx = np->get_tx.orig;
2357
2358 while ((np->get_tx.orig != np->put_tx.orig) &&
2359 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2360 (tx_work < limit)) {
2361
2362 nv_unmap_txskb(np, np->get_tx_ctx);
2363
2364 if (np->desc_ver == DESC_VER_1) {
2365 if (flags & NV_TX_LASTPACKET) {
2366 if (flags & NV_TX_ERROR) {
2367 if (flags & NV_TX_UNDERFLOW)
2368 dev->stats.tx_fifo_errors++;
2369 if (flags & NV_TX_CARRIERLOST)
2370 dev->stats.tx_carrier_errors++;
2371 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2372 nv_legacybackoff_reseed(dev);
2373 dev->stats.tx_errors++;
2374 } else {
2375 dev->stats.tx_packets++;
2376 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2377 }
2378 dev_kfree_skb_any(np->get_tx_ctx->skb);
2379 np->get_tx_ctx->skb = NULL;
2380 tx_work++;
2381 }
2382 } else {
2383 if (flags & NV_TX2_LASTPACKET) {
2384 if (flags & NV_TX2_ERROR) {
2385 if (flags & NV_TX2_UNDERFLOW)
2386 dev->stats.tx_fifo_errors++;
2387 if (flags & NV_TX2_CARRIERLOST)
2388 dev->stats.tx_carrier_errors++;
2389 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2390 nv_legacybackoff_reseed(dev);
2391 dev->stats.tx_errors++;
2392 } else {
2393 dev->stats.tx_packets++;
2394 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2395 }
2396 dev_kfree_skb_any(np->get_tx_ctx->skb);
2397 np->get_tx_ctx->skb = NULL;
2398 tx_work++;
2399 }
2400 }
2401 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2402 np->get_tx.orig = np->first_tx.orig;
2403 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2404 np->get_tx_ctx = np->first_tx_ctx;
2405 }
2406 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2407 np->tx_stop = 0;
2408 netif_wake_queue(dev);
2409 }
2410 return tx_work;
2411 }
2412
2413 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2414 {
2415 struct fe_priv *np = netdev_priv(dev);
2416 u32 flags;
2417 int tx_work = 0;
2418 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2419
2420 while ((np->get_tx.ex != np->put_tx.ex) &&
2421 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2422 (tx_work < limit)) {
2423
2424 nv_unmap_txskb(np, np->get_tx_ctx);
2425
2426 if (flags & NV_TX2_LASTPACKET) {
2427 if (!(flags & NV_TX2_ERROR))
2428 dev->stats.tx_packets++;
2429 else {
2430 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2431 if (np->driver_data & DEV_HAS_GEAR_MODE)
2432 nv_gear_backoff_reseed(dev);
2433 else
2434 nv_legacybackoff_reseed(dev);
2435 }
2436 }
2437
2438 dev_kfree_skb_any(np->get_tx_ctx->skb);
2439 np->get_tx_ctx->skb = NULL;
2440 tx_work++;
2441
2442 if (np->tx_limit)
2443 nv_tx_flip_ownership(dev);
2444 }
2445 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2446 np->get_tx.ex = np->first_tx.ex;
2447 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2448 np->get_tx_ctx = np->first_tx_ctx;
2449 }
2450 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2451 np->tx_stop = 0;
2452 netif_wake_queue(dev);
2453 }
2454 return tx_work;
2455 }
2456
2457 /*
2458 * nv_tx_timeout: dev->tx_timeout function
2459 * Called with netif_tx_lock held.
2460 */
2461 static void nv_tx_timeout(struct net_device *dev)
2462 {
2463 struct fe_priv *np = netdev_priv(dev);
2464 u8 __iomem *base = get_hwbase(dev);
2465 u32 status;
2466 union ring_type put_tx;
2467 int saved_tx_limit;
2468 int i;
2469
2470 if (np->msi_flags & NV_MSI_X_ENABLED)
2471 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2472 else
2473 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2474
2475 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2476
2477 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2478 netdev_info(dev, "Dumping tx registers\n");
2479 for (i = 0; i <= np->register_size; i += 32) {
2480 netdev_info(dev,
2481 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2482 i,
2483 readl(base + i + 0), readl(base + i + 4),
2484 readl(base + i + 8), readl(base + i + 12),
2485 readl(base + i + 16), readl(base + i + 20),
2486 readl(base + i + 24), readl(base + i + 28));
2487 }
2488 netdev_info(dev, "Dumping tx ring\n");
2489 for (i = 0; i < np->tx_ring_size; i += 4) {
2490 if (!nv_optimized(np)) {
2491 netdev_info(dev,
2492 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2493 i,
2494 le32_to_cpu(np->tx_ring.orig[i].buf),
2495 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2496 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2497 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2498 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2499 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2500 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2501 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2502 } else {
2503 netdev_info(dev,
2504 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2505 i,
2506 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2507 le32_to_cpu(np->tx_ring.ex[i].buflow),
2508 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2509 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2510 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2511 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2512 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2513 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2514 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2515 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2516 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2517 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2518 }
2519 }
2520
2521 spin_lock_irq(&np->lock);
2522
2523 /* 1) stop tx engine */
2524 nv_stop_tx(dev);
2525
2526 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2527 saved_tx_limit = np->tx_limit;
2528 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2529 np->tx_stop = 0; /* prevent waking tx queue */
2530 if (!nv_optimized(np))
2531 nv_tx_done(dev, np->tx_ring_size);
2532 else
2533 nv_tx_done_optimized(dev, np->tx_ring_size);
2534
2535 /* save current HW position */
2536 if (np->tx_change_owner)
2537 put_tx.ex = np->tx_change_owner->first_tx_desc;
2538 else
2539 put_tx = np->put_tx;
2540
2541 /* 3) clear all tx state */
2542 nv_drain_tx(dev);
2543 nv_init_tx(dev);
2544
2545 /* 4) restore state to current HW position */
2546 np->get_tx = np->put_tx = put_tx;
2547 np->tx_limit = saved_tx_limit;
2548
2549 /* 5) restart tx engine */
2550 nv_start_tx(dev);
2551 netif_wake_queue(dev);
2552 spin_unlock_irq(&np->lock);
2553 }
2554
2555 /*
2556 * Called when the nic notices a mismatch between the actual data len on the
2557 * wire and the len indicated in the 802 header
2558 */
2559 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2560 {
2561 int hdrlen; /* length of the 802 header */
2562 int protolen; /* length as stored in the proto field */
2563
2564 /* 1) calculate len according to header */
2565 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2566 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2567 hdrlen = VLAN_HLEN;
2568 } else {
2569 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2570 hdrlen = ETH_HLEN;
2571 }
2572 if (protolen > ETH_DATA_LEN)
2573 return datalen; /* Value in proto field not a len, no checks possible */
2574
2575 protolen += hdrlen;
2576 /* consistency checks: */
2577 if (datalen > ETH_ZLEN) {
2578 if (datalen >= protolen) {
2579 /* more data on wire than in 802 header, trim of
2580 * additional data.
2581 */
2582 return protolen;
2583 } else {
2584 /* less data on wire than mentioned in header.
2585 * Discard the packet.
2586 */
2587 return -1;
2588 }
2589 } else {
2590 /* short packet. Accept only if 802 values are also short */
2591 if (protolen > ETH_ZLEN) {
2592 return -1;
2593 }
2594 return datalen;
2595 }
2596 }
2597
2598 static int nv_rx_process(struct net_device *dev, int limit)
2599 {
2600 struct fe_priv *np = netdev_priv(dev);
2601 u32 flags;
2602 int rx_work = 0;
2603 struct sk_buff *skb;
2604 int len;
2605
2606 while ((np->get_rx.orig != np->put_rx.orig) &&
2607 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2608 (rx_work < limit)) {
2609
2610 /*
2611 * the packet is for us - immediately tear down the pci mapping.
2612 * TODO: check if a prefetch of the first cacheline improves
2613 * the performance.
2614 */
2615 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2616 np->get_rx_ctx->dma_len,
2617 PCI_DMA_FROMDEVICE);
2618 skb = np->get_rx_ctx->skb;
2619 np->get_rx_ctx->skb = NULL;
2620
2621 /* look at what we actually got: */
2622 if (np->desc_ver == DESC_VER_1) {
2623 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2624 len = flags & LEN_MASK_V1;
2625 if (unlikely(flags & NV_RX_ERROR)) {
2626 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2627 len = nv_getlen(dev, skb->data, len);
2628 if (len < 0) {
2629 dev->stats.rx_errors++;
2630 dev_kfree_skb(skb);
2631 goto next_pkt;
2632 }
2633 }
2634 /* framing errors are soft errors */
2635 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2636 if (flags & NV_RX_SUBSTRACT1)
2637 len--;
2638 }
2639 /* the rest are hard errors */
2640 else {
2641 if (flags & NV_RX_MISSEDFRAME)
2642 dev->stats.rx_missed_errors++;
2643 if (flags & NV_RX_CRCERR)
2644 dev->stats.rx_crc_errors++;
2645 if (flags & NV_RX_OVERFLOW)
2646 dev->stats.rx_over_errors++;
2647 dev->stats.rx_errors++;
2648 dev_kfree_skb(skb);
2649 goto next_pkt;
2650 }
2651 }
2652 } else {
2653 dev_kfree_skb(skb);
2654 goto next_pkt;
2655 }
2656 } else {
2657 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2658 len = flags & LEN_MASK_V2;
2659 if (unlikely(flags & NV_RX2_ERROR)) {
2660 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2661 len = nv_getlen(dev, skb->data, len);
2662 if (len < 0) {
2663 dev->stats.rx_errors++;
2664 dev_kfree_skb(skb);
2665 goto next_pkt;
2666 }
2667 }
2668 /* framing errors are soft errors */
2669 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2670 if (flags & NV_RX2_SUBSTRACT1)
2671 len--;
2672 }
2673 /* the rest are hard errors */
2674 else {
2675 if (flags & NV_RX2_CRCERR)
2676 dev->stats.rx_crc_errors++;
2677 if (flags & NV_RX2_OVERFLOW)
2678 dev->stats.rx_over_errors++;
2679 dev->stats.rx_errors++;
2680 dev_kfree_skb(skb);
2681 goto next_pkt;
2682 }
2683 }
2684 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2685 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2686 skb->ip_summed = CHECKSUM_UNNECESSARY;
2687 } else {
2688 dev_kfree_skb(skb);
2689 goto next_pkt;
2690 }
2691 }
2692 /* got a valid packet - forward it to the network core */
2693 skb_put(skb, len);
2694 skb->protocol = eth_type_trans(skb, dev);
2695 napi_gro_receive(&np->napi, skb);
2696 dev->stats.rx_packets++;
2697 dev->stats.rx_bytes += len;
2698 next_pkt:
2699 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2700 np->get_rx.orig = np->first_rx.orig;
2701 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2702 np->get_rx_ctx = np->first_rx_ctx;
2703
2704 rx_work++;
2705 }
2706
2707 return rx_work;
2708 }
2709
2710 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2711 {
2712 struct fe_priv *np = netdev_priv(dev);
2713 u32 flags;
2714 u32 vlanflags = 0;
2715 int rx_work = 0;
2716 struct sk_buff *skb;
2717 int len;
2718
2719 while ((np->get_rx.ex != np->put_rx.ex) &&
2720 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2721 (rx_work < limit)) {
2722
2723 /*
2724 * the packet is for us - immediately tear down the pci mapping.
2725 * TODO: check if a prefetch of the first cacheline improves
2726 * the performance.
2727 */
2728 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2729 np->get_rx_ctx->dma_len,
2730 PCI_DMA_FROMDEVICE);
2731 skb = np->get_rx_ctx->skb;
2732 np->get_rx_ctx->skb = NULL;
2733
2734 /* look at what we actually got: */
2735 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2736 len = flags & LEN_MASK_V2;
2737 if (unlikely(flags & NV_RX2_ERROR)) {
2738 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2739 len = nv_getlen(dev, skb->data, len);
2740 if (len < 0) {
2741 dev_kfree_skb(skb);
2742 goto next_pkt;
2743 }
2744 }
2745 /* framing errors are soft errors */
2746 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2747 if (flags & NV_RX2_SUBSTRACT1)
2748 len--;
2749 }
2750 /* the rest are hard errors */
2751 else {
2752 dev_kfree_skb(skb);
2753 goto next_pkt;
2754 }
2755 }
2756
2757 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2758 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2759 skb->ip_summed = CHECKSUM_UNNECESSARY;
2760
2761 /* got a valid packet - forward it to the network core */
2762 skb_put(skb, len);
2763 skb->protocol = eth_type_trans(skb, dev);
2764 prefetch(skb->data);
2765
2766 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2767
2768 /*
2769 * There's need to check for NETIF_F_HW_VLAN_RX here.
2770 * Even if vlan rx accel is disabled,
2771 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2772 */
2773 if (dev->features & NETIF_F_HW_VLAN_RX &&
2774 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2775 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2776
2777 __vlan_hwaccel_put_tag(skb, vid);
2778 }
2779 napi_gro_receive(&np->napi, skb);
2780
2781 dev->stats.rx_packets++;
2782 dev->stats.rx_bytes += len;
2783 } else {
2784 dev_kfree_skb(skb);
2785 }
2786 next_pkt:
2787 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2788 np->get_rx.ex = np->first_rx.ex;
2789 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2790 np->get_rx_ctx = np->first_rx_ctx;
2791
2792 rx_work++;
2793 }
2794
2795 return rx_work;
2796 }
2797
2798 static void set_bufsize(struct net_device *dev)
2799 {
2800 struct fe_priv *np = netdev_priv(dev);
2801
2802 if (dev->mtu <= ETH_DATA_LEN)
2803 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2804 else
2805 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2806 }
2807
2808 /*
2809 * nv_change_mtu: dev->change_mtu function
2810 * Called with dev_base_lock held for read.
2811 */
2812 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2813 {
2814 struct fe_priv *np = netdev_priv(dev);
2815 int old_mtu;
2816
2817 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2818 return -EINVAL;
2819
2820 old_mtu = dev->mtu;
2821 dev->mtu = new_mtu;
2822
2823 /* return early if the buffer sizes will not change */
2824 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2825 return 0;
2826 if (old_mtu == new_mtu)
2827 return 0;
2828
2829 /* synchronized against open : rtnl_lock() held by caller */
2830 if (netif_running(dev)) {
2831 u8 __iomem *base = get_hwbase(dev);
2832 /*
2833 * It seems that the nic preloads valid ring entries into an
2834 * internal buffer. The procedure for flushing everything is
2835 * guessed, there is probably a simpler approach.
2836 * Changing the MTU is a rare event, it shouldn't matter.
2837 */
2838 nv_disable_irq(dev);
2839 nv_napi_disable(dev);
2840 netif_tx_lock_bh(dev);
2841 netif_addr_lock(dev);
2842 spin_lock(&np->lock);
2843 /* stop engines */
2844 nv_stop_rxtx(dev);
2845 nv_txrx_reset(dev);
2846 /* drain rx queue */
2847 nv_drain_rxtx(dev);
2848 /* reinit driver view of the rx queue */
2849 set_bufsize(dev);
2850 if (nv_init_ring(dev)) {
2851 if (!np->in_shutdown)
2852 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2853 }
2854 /* reinit nic view of the rx queue */
2855 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2856 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2857 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2858 base + NvRegRingSizes);
2859 pci_push(base);
2860 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2861 pci_push(base);
2862
2863 /* restart rx engine */
2864 nv_start_rxtx(dev);
2865 spin_unlock(&np->lock);
2866 netif_addr_unlock(dev);
2867 netif_tx_unlock_bh(dev);
2868 nv_napi_enable(dev);
2869 nv_enable_irq(dev);
2870 }
2871 return 0;
2872 }
2873
2874 static void nv_copy_mac_to_hw(struct net_device *dev)
2875 {
2876 u8 __iomem *base = get_hwbase(dev);
2877 u32 mac[2];
2878
2879 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2880 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2881 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2882
2883 writel(mac[0], base + NvRegMacAddrA);
2884 writel(mac[1], base + NvRegMacAddrB);
2885 }
2886
2887 /*
2888 * nv_set_mac_address: dev->set_mac_address function
2889 * Called with rtnl_lock() held.
2890 */
2891 static int nv_set_mac_address(struct net_device *dev, void *addr)
2892 {
2893 struct fe_priv *np = netdev_priv(dev);
2894 struct sockaddr *macaddr = (struct sockaddr *)addr;
2895
2896 if (!is_valid_ether_addr(macaddr->sa_data))
2897 return -EADDRNOTAVAIL;
2898
2899 /* synchronized against open : rtnl_lock() held by caller */
2900 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2901
2902 if (netif_running(dev)) {
2903 netif_tx_lock_bh(dev);
2904 netif_addr_lock(dev);
2905 spin_lock_irq(&np->lock);
2906
2907 /* stop rx engine */
2908 nv_stop_rx(dev);
2909
2910 /* set mac address */
2911 nv_copy_mac_to_hw(dev);
2912
2913 /* restart rx engine */
2914 nv_start_rx(dev);
2915 spin_unlock_irq(&np->lock);
2916 netif_addr_unlock(dev);
2917 netif_tx_unlock_bh(dev);
2918 } else {
2919 nv_copy_mac_to_hw(dev);
2920 }
2921 return 0;
2922 }
2923
2924 /*
2925 * nv_set_multicast: dev->set_multicast function
2926 * Called with netif_tx_lock held.
2927 */
2928 static void nv_set_multicast(struct net_device *dev)
2929 {
2930 struct fe_priv *np = netdev_priv(dev);
2931 u8 __iomem *base = get_hwbase(dev);
2932 u32 addr[2];
2933 u32 mask[2];
2934 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2935
2936 memset(addr, 0, sizeof(addr));
2937 memset(mask, 0, sizeof(mask));
2938
2939 if (dev->flags & IFF_PROMISC) {
2940 pff |= NVREG_PFF_PROMISC;
2941 } else {
2942 pff |= NVREG_PFF_MYADDR;
2943
2944 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2945 u32 alwaysOff[2];
2946 u32 alwaysOn[2];
2947
2948 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2949 if (dev->flags & IFF_ALLMULTI) {
2950 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2951 } else {
2952 struct netdev_hw_addr *ha;
2953
2954 netdev_for_each_mc_addr(ha, dev) {
2955 unsigned char *addr = ha->addr;
2956 u32 a, b;
2957
2958 a = le32_to_cpu(*(__le32 *) addr);
2959 b = le16_to_cpu(*(__le16 *) (&addr[4]));
2960 alwaysOn[0] &= a;
2961 alwaysOff[0] &= ~a;
2962 alwaysOn[1] &= b;
2963 alwaysOff[1] &= ~b;
2964 }
2965 }
2966 addr[0] = alwaysOn[0];
2967 addr[1] = alwaysOn[1];
2968 mask[0] = alwaysOn[0] | alwaysOff[0];
2969 mask[1] = alwaysOn[1] | alwaysOff[1];
2970 } else {
2971 mask[0] = NVREG_MCASTMASKA_NONE;
2972 mask[1] = NVREG_MCASTMASKB_NONE;
2973 }
2974 }
2975 addr[0] |= NVREG_MCASTADDRA_FORCE;
2976 pff |= NVREG_PFF_ALWAYS;
2977 spin_lock_irq(&np->lock);
2978 nv_stop_rx(dev);
2979 writel(addr[0], base + NvRegMulticastAddrA);
2980 writel(addr[1], base + NvRegMulticastAddrB);
2981 writel(mask[0], base + NvRegMulticastMaskA);
2982 writel(mask[1], base + NvRegMulticastMaskB);
2983 writel(pff, base + NvRegPacketFilterFlags);
2984 nv_start_rx(dev);
2985 spin_unlock_irq(&np->lock);
2986 }
2987
2988 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2989 {
2990 struct fe_priv *np = netdev_priv(dev);
2991 u8 __iomem *base = get_hwbase(dev);
2992
2993 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2994
2995 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2996 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2997 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2998 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2999 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3000 } else {
3001 writel(pff, base + NvRegPacketFilterFlags);
3002 }
3003 }
3004 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3005 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3006 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3007 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3008 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3009 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3010 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3011 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3012 /* limit the number of tx pause frames to a default of 8 */
3013 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3014 }
3015 writel(pause_enable, base + NvRegTxPauseFrame);
3016 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3017 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3018 } else {
3019 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3020 writel(regmisc, base + NvRegMisc1);
3021 }
3022 }
3023 }
3024
3025 /**
3026 * nv_update_linkspeed: Setup the MAC according to the link partner
3027 * @dev: Network device to be configured
3028 *
3029 * The function queries the PHY and checks if there is a link partner.
3030 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3031 * set to 10 MBit HD.
3032 *
3033 * The function returns 0 if there is no link partner and 1 if there is
3034 * a good link partner.
3035 */
3036 static int nv_update_linkspeed(struct net_device *dev)
3037 {
3038 struct fe_priv *np = netdev_priv(dev);
3039 u8 __iomem *base = get_hwbase(dev);
3040 int adv = 0;
3041 int lpa = 0;
3042 int adv_lpa, adv_pause, lpa_pause;
3043 int newls = np->linkspeed;
3044 int newdup = np->duplex;
3045 int mii_status;
3046 int retval = 0;
3047 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3048 u32 txrxFlags = 0;
3049 u32 phy_exp;
3050
3051 /* BMSR_LSTATUS is latched, read it twice:
3052 * we want the current value.
3053 */
3054 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3055 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3056
3057 if (!(mii_status & BMSR_LSTATUS)) {
3058 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3059 newdup = 0;
3060 retval = 0;
3061 goto set_speed;
3062 }
3063
3064 if (np->autoneg == 0) {
3065 if (np->fixed_mode & LPA_100FULL) {
3066 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3067 newdup = 1;
3068 } else if (np->fixed_mode & LPA_100HALF) {
3069 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3070 newdup = 0;
3071 } else if (np->fixed_mode & LPA_10FULL) {
3072 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3073 newdup = 1;
3074 } else {
3075 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3076 newdup = 0;
3077 }
3078 retval = 1;
3079 goto set_speed;
3080 }
3081 /* check auto negotiation is complete */
3082 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3083 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3084 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3085 newdup = 0;
3086 retval = 0;
3087 goto set_speed;
3088 }
3089
3090 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3091 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3092
3093 retval = 1;
3094 if (np->gigabit == PHY_GIGABIT) {
3095 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3096 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3097
3098 if ((control_1000 & ADVERTISE_1000FULL) &&
3099 (status_1000 & LPA_1000FULL)) {
3100 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3101 newdup = 1;
3102 goto set_speed;
3103 }
3104 }
3105
3106 /* FIXME: handle parallel detection properly */
3107 adv_lpa = lpa & adv;
3108 if (adv_lpa & LPA_100FULL) {
3109 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3110 newdup = 1;
3111 } else if (adv_lpa & LPA_100HALF) {
3112 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3113 newdup = 0;
3114 } else if (adv_lpa & LPA_10FULL) {
3115 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3116 newdup = 1;
3117 } else if (adv_lpa & LPA_10HALF) {
3118 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3119 newdup = 0;
3120 } else {
3121 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3122 newdup = 0;
3123 }
3124
3125 set_speed:
3126 if (np->duplex == newdup && np->linkspeed == newls)
3127 return retval;
3128
3129 np->duplex = newdup;
3130 np->linkspeed = newls;
3131
3132 /* The transmitter and receiver must be restarted for safe update */
3133 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3134 txrxFlags |= NV_RESTART_TX;
3135 nv_stop_tx(dev);
3136 }
3137 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3138 txrxFlags |= NV_RESTART_RX;
3139 nv_stop_rx(dev);
3140 }
3141
3142 if (np->gigabit == PHY_GIGABIT) {
3143 phyreg = readl(base + NvRegSlotTime);
3144 phyreg &= ~(0x3FF00);
3145 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3146 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3147 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3148 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3149 phyreg |= NVREG_SLOTTIME_1000_FULL;
3150 writel(phyreg, base + NvRegSlotTime);
3151 }
3152
3153 phyreg = readl(base + NvRegPhyInterface);
3154 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3155 if (np->duplex == 0)
3156 phyreg |= PHY_HALF;
3157 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3158 phyreg |= PHY_100;
3159 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3160 phyreg |= PHY_1000;
3161 writel(phyreg, base + NvRegPhyInterface);
3162
3163 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3164 if (phyreg & PHY_RGMII) {
3165 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3166 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3167 } else {
3168 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3169 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3170 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3171 else
3172 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3173 } else {
3174 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3175 }
3176 }
3177 } else {
3178 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3179 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3180 else
3181 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3182 }
3183 writel(txreg, base + NvRegTxDeferral);
3184
3185 if (np->desc_ver == DESC_VER_1) {
3186 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3187 } else {
3188 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3189 txreg = NVREG_TX_WM_DESC2_3_1000;
3190 else
3191 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3192 }
3193 writel(txreg, base + NvRegTxWatermark);
3194
3195 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3196 base + NvRegMisc1);
3197 pci_push(base);
3198 writel(np->linkspeed, base + NvRegLinkSpeed);
3199 pci_push(base);
3200
3201 pause_flags = 0;
3202 /* setup pause frame */
3203 if (np->duplex != 0) {
3204 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3205 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3206 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3207
3208 switch (adv_pause) {
3209 case ADVERTISE_PAUSE_CAP:
3210 if (lpa_pause & LPA_PAUSE_CAP) {
3211 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3212 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3213 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214 }
3215 break;
3216 case ADVERTISE_PAUSE_ASYM:
3217 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3218 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3219 break;
3220 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3221 if (lpa_pause & LPA_PAUSE_CAP) {
3222 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3223 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3224 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3225 }
3226 if (lpa_pause == LPA_PAUSE_ASYM)
3227 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3228 break;
3229 }
3230 } else {
3231 pause_flags = np->pause_flags;
3232 }
3233 }
3234 nv_update_pause(dev, pause_flags);
3235
3236 if (txrxFlags & NV_RESTART_TX)
3237 nv_start_tx(dev);
3238 if (txrxFlags & NV_RESTART_RX)
3239 nv_start_rx(dev);
3240
3241 return retval;
3242 }
3243
3244 static void nv_linkchange(struct net_device *dev)
3245 {
3246 if (nv_update_linkspeed(dev)) {
3247 if (!netif_carrier_ok(dev)) {
3248 netif_carrier_on(dev);
3249 netdev_info(dev, "link up\n");
3250 nv_txrx_gate(dev, false);
3251 nv_start_rx(dev);
3252 }
3253 } else {
3254 if (netif_carrier_ok(dev)) {
3255 netif_carrier_off(dev);
3256 netdev_info(dev, "link down\n");
3257 nv_txrx_gate(dev, true);
3258 nv_stop_rx(dev);
3259 }
3260 }
3261 }
3262
3263 static void nv_link_irq(struct net_device *dev)
3264 {
3265 u8 __iomem *base = get_hwbase(dev);
3266 u32 miistat;
3267
3268 miistat = readl(base + NvRegMIIStatus);
3269 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3270
3271 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3272 nv_linkchange(dev);
3273 }
3274
3275 static void nv_msi_workaround(struct fe_priv *np)
3276 {
3277
3278 /* Need to toggle the msi irq mask within the ethernet device,
3279 * otherwise, future interrupts will not be detected.
3280 */
3281 if (np->msi_flags & NV_MSI_ENABLED) {
3282 u8 __iomem *base = np->base;
3283
3284 writel(0, base + NvRegMSIIrqMask);
3285 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3286 }
3287 }
3288
3289 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3290 {
3291 struct fe_priv *np = netdev_priv(dev);
3292
3293 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3294 if (total_work > NV_DYNAMIC_THRESHOLD) {
3295 /* transition to poll based interrupts */
3296 np->quiet_count = 0;
3297 if (np->irqmask != NVREG_IRQMASK_CPU) {
3298 np->irqmask = NVREG_IRQMASK_CPU;
3299 return 1;
3300 }
3301 } else {
3302 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3303 np->quiet_count++;
3304 } else {
3305 /* reached a period of low activity, switch
3306 to per tx/rx packet interrupts */
3307 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3308 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3309 return 1;
3310 }
3311 }
3312 }
3313 }
3314 return 0;
3315 }
3316
3317 static irqreturn_t nv_nic_irq(int foo, void *data)
3318 {
3319 struct net_device *dev = (struct net_device *) data;
3320 struct fe_priv *np = netdev_priv(dev);
3321 u8 __iomem *base = get_hwbase(dev);
3322
3323 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3324 np->events = readl(base + NvRegIrqStatus);
3325 writel(np->events, base + NvRegIrqStatus);
3326 } else {
3327 np->events = readl(base + NvRegMSIXIrqStatus);
3328 writel(np->events, base + NvRegMSIXIrqStatus);
3329 }
3330 if (!(np->events & np->irqmask))
3331 return IRQ_NONE;
3332
3333 nv_msi_workaround(np);
3334
3335 if (napi_schedule_prep(&np->napi)) {
3336 /*
3337 * Disable further irq's (msix not enabled with napi)
3338 */
3339 writel(0, base + NvRegIrqMask);
3340 __napi_schedule(&np->napi);
3341 }
3342
3343 return IRQ_HANDLED;
3344 }
3345
3346 /**
3347 * All _optimized functions are used to help increase performance
3348 * (reduce CPU and increase throughput). They use descripter version 3,
3349 * compiler directives, and reduce memory accesses.
3350 */
3351 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3352 {
3353 struct net_device *dev = (struct net_device *) data;
3354 struct fe_priv *np = netdev_priv(dev);
3355 u8 __iomem *base = get_hwbase(dev);
3356
3357 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3358 np->events = readl(base + NvRegIrqStatus);
3359 writel(np->events, base + NvRegIrqStatus);
3360 } else {
3361 np->events = readl(base + NvRegMSIXIrqStatus);
3362 writel(np->events, base + NvRegMSIXIrqStatus);
3363 }
3364 if (!(np->events & np->irqmask))
3365 return IRQ_NONE;
3366
3367 nv_msi_workaround(np);
3368
3369 if (napi_schedule_prep(&np->napi)) {
3370 /*
3371 * Disable further irq's (msix not enabled with napi)
3372 */
3373 writel(0, base + NvRegIrqMask);
3374 __napi_schedule(&np->napi);
3375 }
3376
3377 return IRQ_HANDLED;
3378 }
3379
3380 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3381 {
3382 struct net_device *dev = (struct net_device *) data;
3383 struct fe_priv *np = netdev_priv(dev);
3384 u8 __iomem *base = get_hwbase(dev);
3385 u32 events;
3386 int i;
3387 unsigned long flags;
3388
3389 for (i = 0;; i++) {
3390 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3391 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3392 if (!(events & np->irqmask))
3393 break;
3394
3395 spin_lock_irqsave(&np->lock, flags);
3396 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3397 spin_unlock_irqrestore(&np->lock, flags);
3398
3399 if (unlikely(i > max_interrupt_work)) {
3400 spin_lock_irqsave(&np->lock, flags);
3401 /* disable interrupts on the nic */
3402 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3403 pci_push(base);
3404
3405 if (!np->in_shutdown) {
3406 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3407 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3408 }
3409 spin_unlock_irqrestore(&np->lock, flags);
3410 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3411 __func__, i);
3412 break;
3413 }
3414
3415 }
3416
3417 return IRQ_RETVAL(i);
3418 }
3419
3420 static int nv_napi_poll(struct napi_struct *napi, int budget)
3421 {
3422 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3423 struct net_device *dev = np->dev;
3424 u8 __iomem *base = get_hwbase(dev);
3425 unsigned long flags;
3426 int retcode;
3427 int rx_count, tx_work = 0, rx_work = 0;
3428
3429 do {
3430 if (!nv_optimized(np)) {
3431 spin_lock_irqsave(&np->lock, flags);
3432 tx_work += nv_tx_done(dev, np->tx_ring_size);
3433 spin_unlock_irqrestore(&np->lock, flags);
3434
3435 rx_count = nv_rx_process(dev, budget - rx_work);
3436 retcode = nv_alloc_rx(dev);
3437 } else {
3438 spin_lock_irqsave(&np->lock, flags);
3439 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3440 spin_unlock_irqrestore(&np->lock, flags);
3441
3442 rx_count = nv_rx_process_optimized(dev,
3443 budget - rx_work);
3444 retcode = nv_alloc_rx_optimized(dev);
3445 }
3446 } while (retcode == 0 &&
3447 rx_count > 0 && (rx_work += rx_count) < budget);
3448
3449 if (retcode) {
3450 spin_lock_irqsave(&np->lock, flags);
3451 if (!np->in_shutdown)
3452 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3453 spin_unlock_irqrestore(&np->lock, flags);
3454 }
3455
3456 nv_change_interrupt_mode(dev, tx_work + rx_work);
3457
3458 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3459 spin_lock_irqsave(&np->lock, flags);
3460 nv_link_irq(dev);
3461 spin_unlock_irqrestore(&np->lock, flags);
3462 }
3463 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3464 spin_lock_irqsave(&np->lock, flags);
3465 nv_linkchange(dev);
3466 spin_unlock_irqrestore(&np->lock, flags);
3467 np->link_timeout = jiffies + LINK_TIMEOUT;
3468 }
3469 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3470 spin_lock_irqsave(&np->lock, flags);
3471 if (!np->in_shutdown) {
3472 np->nic_poll_irq = np->irqmask;
3473 np->recover_error = 1;
3474 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3475 }
3476 spin_unlock_irqrestore(&np->lock, flags);
3477 napi_complete(napi);
3478 return rx_work;
3479 }
3480
3481 if (rx_work < budget) {
3482 /* re-enable interrupts
3483 (msix not enabled in napi) */
3484 napi_complete(napi);
3485
3486 writel(np->irqmask, base + NvRegIrqMask);
3487 }
3488 return rx_work;
3489 }
3490
3491 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3492 {
3493 struct net_device *dev = (struct net_device *) data;
3494 struct fe_priv *np = netdev_priv(dev);
3495 u8 __iomem *base = get_hwbase(dev);
3496 u32 events;
3497 int i;
3498 unsigned long flags;
3499
3500 for (i = 0;; i++) {
3501 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3502 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3503 if (!(events & np->irqmask))
3504 break;
3505
3506 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3507 if (unlikely(nv_alloc_rx_optimized(dev))) {
3508 spin_lock_irqsave(&np->lock, flags);
3509 if (!np->in_shutdown)
3510 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3511 spin_unlock_irqrestore(&np->lock, flags);
3512 }
3513 }
3514
3515 if (unlikely(i > max_interrupt_work)) {
3516 spin_lock_irqsave(&np->lock, flags);
3517 /* disable interrupts on the nic */
3518 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3519 pci_push(base);
3520
3521 if (!np->in_shutdown) {
3522 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3523 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3524 }
3525 spin_unlock_irqrestore(&np->lock, flags);
3526 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3527 __func__, i);
3528 break;
3529 }
3530 }
3531
3532 return IRQ_RETVAL(i);
3533 }
3534
3535 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3536 {
3537 struct net_device *dev = (struct net_device *) data;
3538 struct fe_priv *np = netdev_priv(dev);
3539 u8 __iomem *base = get_hwbase(dev);
3540 u32 events;
3541 int i;
3542 unsigned long flags;
3543
3544 for (i = 0;; i++) {
3545 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3546 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3547 if (!(events & np->irqmask))
3548 break;
3549
3550 /* check tx in case we reached max loop limit in tx isr */
3551 spin_lock_irqsave(&np->lock, flags);
3552 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3553 spin_unlock_irqrestore(&np->lock, flags);
3554
3555 if (events & NVREG_IRQ_LINK) {
3556 spin_lock_irqsave(&np->lock, flags);
3557 nv_link_irq(dev);
3558 spin_unlock_irqrestore(&np->lock, flags);
3559 }
3560 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3561 spin_lock_irqsave(&np->lock, flags);
3562 nv_linkchange(dev);
3563 spin_unlock_irqrestore(&np->lock, flags);
3564 np->link_timeout = jiffies + LINK_TIMEOUT;
3565 }
3566 if (events & NVREG_IRQ_RECOVER_ERROR) {
3567 spin_lock_irq(&np->lock);
3568 /* disable interrupts on the nic */
3569 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3570 pci_push(base);
3571
3572 if (!np->in_shutdown) {
3573 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3574 np->recover_error = 1;
3575 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3576 }
3577 spin_unlock_irq(&np->lock);
3578 break;
3579 }
3580 if (unlikely(i > max_interrupt_work)) {
3581 spin_lock_irqsave(&np->lock, flags);
3582 /* disable interrupts on the nic */
3583 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3584 pci_push(base);
3585
3586 if (!np->in_shutdown) {
3587 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3588 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3589 }
3590 spin_unlock_irqrestore(&np->lock, flags);
3591 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3592 __func__, i);
3593 break;
3594 }
3595
3596 }
3597
3598 return IRQ_RETVAL(i);
3599 }
3600
3601 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3602 {
3603 struct net_device *dev = (struct net_device *) data;
3604 struct fe_priv *np = netdev_priv(dev);
3605 u8 __iomem *base = get_hwbase(dev);
3606 u32 events;
3607
3608 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3609 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3610 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3611 } else {
3612 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3613 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3614 }
3615 pci_push(base);
3616 if (!(events & NVREG_IRQ_TIMER))
3617 return IRQ_RETVAL(0);
3618
3619 nv_msi_workaround(np);
3620
3621 spin_lock(&np->lock);
3622 np->intr_test = 1;
3623 spin_unlock(&np->lock);
3624
3625 return IRQ_RETVAL(1);
3626 }
3627
3628 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3629 {
3630 u8 __iomem *base = get_hwbase(dev);
3631 int i;
3632 u32 msixmap = 0;
3633
3634 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3635 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3636 * the remaining 8 interrupts.
3637 */
3638 for (i = 0; i < 8; i++) {
3639 if ((irqmask >> i) & 0x1)
3640 msixmap |= vector << (i << 2);
3641 }
3642 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3643
3644 msixmap = 0;
3645 for (i = 0; i < 8; i++) {
3646 if ((irqmask >> (i + 8)) & 0x1)
3647 msixmap |= vector << (i << 2);
3648 }
3649 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3650 }
3651
3652 static int nv_request_irq(struct net_device *dev, int intr_test)
3653 {
3654 struct fe_priv *np = get_nvpriv(dev);
3655 u8 __iomem *base = get_hwbase(dev);
3656 int ret = 1;
3657 int i;
3658 irqreturn_t (*handler)(int foo, void *data);
3659
3660 if (intr_test) {
3661 handler = nv_nic_irq_test;
3662 } else {
3663 if (nv_optimized(np))
3664 handler = nv_nic_irq_optimized;
3665 else
3666 handler = nv_nic_irq;
3667 }
3668
3669 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3670 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3671 np->msi_x_entry[i].entry = i;
3672 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3673 if (ret == 0) {
3674 np->msi_flags |= NV_MSI_X_ENABLED;
3675 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3676 /* Request irq for rx handling */
3677 sprintf(np->name_rx, "%s-rx", dev->name);
3678 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3679 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3680 netdev_info(dev,
3681 "request_irq failed for rx %d\n",
3682 ret);
3683 pci_disable_msix(np->pci_dev);
3684 np->msi_flags &= ~NV_MSI_X_ENABLED;
3685 goto out_err;
3686 }
3687 /* Request irq for tx handling */
3688 sprintf(np->name_tx, "%s-tx", dev->name);
3689 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3690 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3691 netdev_info(dev,
3692 "request_irq failed for tx %d\n",
3693 ret);
3694 pci_disable_msix(np->pci_dev);
3695 np->msi_flags &= ~NV_MSI_X_ENABLED;
3696 goto out_free_rx;
3697 }
3698 /* Request irq for link and timer handling */
3699 sprintf(np->name_other, "%s-other", dev->name);
3700 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3701 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3702 netdev_info(dev,
3703 "request_irq failed for link %d\n",
3704 ret);
3705 pci_disable_msix(np->pci_dev);
3706 np->msi_flags &= ~NV_MSI_X_ENABLED;
3707 goto out_free_tx;
3708 }
3709 /* map interrupts to their respective vector */
3710 writel(0, base + NvRegMSIXMap0);
3711 writel(0, base + NvRegMSIXMap1);
3712 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3713 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3714 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3715 } else {
3716 /* Request irq for all interrupts */
3717 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3718 netdev_info(dev,
3719 "request_irq failed %d\n",
3720 ret);
3721 pci_disable_msix(np->pci_dev);
3722 np->msi_flags &= ~NV_MSI_X_ENABLED;
3723 goto out_err;
3724 }
3725
3726 /* map interrupts to vector 0 */
3727 writel(0, base + NvRegMSIXMap0);
3728 writel(0, base + NvRegMSIXMap1);
3729 }
3730 }
3731 }
3732 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3733 ret = pci_enable_msi(np->pci_dev);
3734 if (ret == 0) {
3735 np->msi_flags |= NV_MSI_ENABLED;
3736 dev->irq = np->pci_dev->irq;
3737 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3738 netdev_info(dev, "request_irq failed %d\n",
3739 ret);
3740 pci_disable_msi(np->pci_dev);
3741 np->msi_flags &= ~NV_MSI_ENABLED;
3742 dev->irq = np->pci_dev->irq;
3743 goto out_err;
3744 }
3745
3746 /* map interrupts to vector 0 */
3747 writel(0, base + NvRegMSIMap0);
3748 writel(0, base + NvRegMSIMap1);
3749 /* enable msi vector 0 */
3750 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3751 }
3752 }
3753 if (ret != 0) {
3754 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3755 goto out_err;
3756
3757 }
3758
3759 return 0;
3760 out_free_tx:
3761 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3762 out_free_rx:
3763 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3764 out_err:
3765 return 1;
3766 }
3767
3768 static void nv_free_irq(struct net_device *dev)
3769 {
3770 struct fe_priv *np = get_nvpriv(dev);
3771 int i;
3772
3773 if (np->msi_flags & NV_MSI_X_ENABLED) {
3774 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3775 free_irq(np->msi_x_entry[i].vector, dev);
3776 pci_disable_msix(np->pci_dev);
3777 np->msi_flags &= ~NV_MSI_X_ENABLED;
3778 } else {
3779 free_irq(np->pci_dev->irq, dev);
3780 if (np->msi_flags & NV_MSI_ENABLED) {
3781 pci_disable_msi(np->pci_dev);
3782 np->msi_flags &= ~NV_MSI_ENABLED;
3783 }
3784 }
3785 }
3786
3787 static void nv_do_nic_poll(unsigned long data)
3788 {
3789 struct net_device *dev = (struct net_device *) data;
3790 struct fe_priv *np = netdev_priv(dev);
3791 u8 __iomem *base = get_hwbase(dev);
3792 u32 mask = 0;
3793
3794 /*
3795 * First disable irq(s) and then
3796 * reenable interrupts on the nic, we have to do this before calling
3797 * nv_nic_irq because that may decide to do otherwise
3798 */
3799
3800 if (!using_multi_irqs(dev)) {
3801 if (np->msi_flags & NV_MSI_X_ENABLED)
3802 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3803 else
3804 disable_irq_lockdep(np->pci_dev->irq);
3805 mask = np->irqmask;
3806 } else {
3807 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3808 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3809 mask |= NVREG_IRQ_RX_ALL;
3810 }
3811 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3812 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3813 mask |= NVREG_IRQ_TX_ALL;
3814 }
3815 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3816 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3817 mask |= NVREG_IRQ_OTHER;
3818 }
3819 }
3820 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3821
3822 if (np->recover_error) {
3823 np->recover_error = 0;
3824 netdev_info(dev, "MAC in recoverable error state\n");
3825 if (netif_running(dev)) {
3826 netif_tx_lock_bh(dev);
3827 netif_addr_lock(dev);
3828 spin_lock(&np->lock);
3829 /* stop engines */
3830 nv_stop_rxtx(dev);
3831 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3832 nv_mac_reset(dev);
3833 nv_txrx_reset(dev);
3834 /* drain rx queue */
3835 nv_drain_rxtx(dev);
3836 /* reinit driver view of the rx queue */
3837 set_bufsize(dev);
3838 if (nv_init_ring(dev)) {
3839 if (!np->in_shutdown)
3840 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3841 }
3842 /* reinit nic view of the rx queue */
3843 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3844 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3845 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3846 base + NvRegRingSizes);
3847 pci_push(base);
3848 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3849 pci_push(base);
3850 /* clear interrupts */
3851 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3852 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3853 else
3854 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3855
3856 /* restart rx engine */
3857 nv_start_rxtx(dev);
3858 spin_unlock(&np->lock);
3859 netif_addr_unlock(dev);
3860 netif_tx_unlock_bh(dev);
3861 }
3862 }
3863
3864 writel(mask, base + NvRegIrqMask);
3865 pci_push(base);
3866
3867 if (!using_multi_irqs(dev)) {
3868 np->nic_poll_irq = 0;
3869 if (nv_optimized(np))
3870 nv_nic_irq_optimized(0, dev);
3871 else
3872 nv_nic_irq(0, dev);
3873 if (np->msi_flags & NV_MSI_X_ENABLED)
3874 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3875 else
3876 enable_irq_lockdep(np->pci_dev->irq);
3877 } else {
3878 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3879 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3880 nv_nic_irq_rx(0, dev);
3881 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3882 }
3883 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3884 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3885 nv_nic_irq_tx(0, dev);
3886 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3887 }
3888 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3889 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3890 nv_nic_irq_other(0, dev);
3891 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3892 }
3893 }
3894
3895 }
3896
3897 #ifdef CONFIG_NET_POLL_CONTROLLER
3898 static void nv_poll_controller(struct net_device *dev)
3899 {
3900 nv_do_nic_poll((unsigned long) dev);
3901 }
3902 #endif
3903
3904 static void nv_do_stats_poll(unsigned long data)
3905 {
3906 struct net_device *dev = (struct net_device *) data;
3907 struct fe_priv *np = netdev_priv(dev);
3908
3909 nv_get_hw_stats(dev);
3910
3911 if (!np->in_shutdown)
3912 mod_timer(&np->stats_poll,
3913 round_jiffies(jiffies + STATS_INTERVAL));
3914 }
3915
3916 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3917 {
3918 struct fe_priv *np = netdev_priv(dev);
3919 strcpy(info->driver, DRV_NAME);
3920 strcpy(info->version, FORCEDETH_VERSION);
3921 strcpy(info->bus_info, pci_name(np->pci_dev));
3922 }
3923
3924 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3925 {
3926 struct fe_priv *np = netdev_priv(dev);
3927 wolinfo->supported = WAKE_MAGIC;
3928
3929 spin_lock_irq(&np->lock);
3930 if (np->wolenabled)
3931 wolinfo->wolopts = WAKE_MAGIC;
3932 spin_unlock_irq(&np->lock);
3933 }
3934
3935 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3936 {
3937 struct fe_priv *np = netdev_priv(dev);
3938 u8 __iomem *base = get_hwbase(dev);
3939 u32 flags = 0;
3940
3941 if (wolinfo->wolopts == 0) {
3942 np->wolenabled = 0;
3943 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3944 np->wolenabled = 1;
3945 flags = NVREG_WAKEUPFLAGS_ENABLE;
3946 }
3947 if (netif_running(dev)) {
3948 spin_lock_irq(&np->lock);
3949 writel(flags, base + NvRegWakeUpFlags);
3950 spin_unlock_irq(&np->lock);
3951 }
3952 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3953 return 0;
3954 }
3955
3956 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3957 {
3958 struct fe_priv *np = netdev_priv(dev);
3959 u32 speed;
3960 int adv;
3961
3962 spin_lock_irq(&np->lock);
3963 ecmd->port = PORT_MII;
3964 if (!netif_running(dev)) {
3965 /* We do not track link speed / duplex setting if the
3966 * interface is disabled. Force a link check */
3967 if (nv_update_linkspeed(dev)) {
3968 if (!netif_carrier_ok(dev))
3969 netif_carrier_on(dev);
3970 } else {
3971 if (netif_carrier_ok(dev))
3972 netif_carrier_off(dev);
3973 }
3974 }
3975
3976 if (netif_carrier_ok(dev)) {
3977 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3978 case NVREG_LINKSPEED_10:
3979 speed = SPEED_10;
3980 break;
3981 case NVREG_LINKSPEED_100:
3982 speed = SPEED_100;
3983 break;
3984 case NVREG_LINKSPEED_1000:
3985 speed = SPEED_1000;
3986 break;
3987 default:
3988 speed = -1;
3989 break;
3990 }
3991 ecmd->duplex = DUPLEX_HALF;
3992 if (np->duplex)
3993 ecmd->duplex = DUPLEX_FULL;
3994 } else {
3995 speed = -1;
3996 ecmd->duplex = -1;
3997 }
3998 ethtool_cmd_speed_set(ecmd, speed);
3999 ecmd->autoneg = np->autoneg;
4000
4001 ecmd->advertising = ADVERTISED_MII;
4002 if (np->autoneg) {
4003 ecmd->advertising |= ADVERTISED_Autoneg;
4004 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4005 if (adv & ADVERTISE_10HALF)
4006 ecmd->advertising |= ADVERTISED_10baseT_Half;
4007 if (adv & ADVERTISE_10FULL)
4008 ecmd->advertising |= ADVERTISED_10baseT_Full;
4009 if (adv & ADVERTISE_100HALF)
4010 ecmd->advertising |= ADVERTISED_100baseT_Half;
4011 if (adv & ADVERTISE_100FULL)
4012 ecmd->advertising |= ADVERTISED_100baseT_Full;
4013 if (np->gigabit == PHY_GIGABIT) {
4014 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4015 if (adv & ADVERTISE_1000FULL)
4016 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4017 }
4018 }
4019 ecmd->supported = (SUPPORTED_Autoneg |
4020 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4021 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4022 SUPPORTED_MII);
4023 if (np->gigabit == PHY_GIGABIT)
4024 ecmd->supported |= SUPPORTED_1000baseT_Full;
4025
4026 ecmd->phy_address = np->phyaddr;
4027 ecmd->transceiver = XCVR_EXTERNAL;
4028
4029 /* ignore maxtxpkt, maxrxpkt for now */
4030 spin_unlock_irq(&np->lock);
4031 return 0;
4032 }
4033
4034 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4035 {
4036 struct fe_priv *np = netdev_priv(dev);
4037 u32 speed = ethtool_cmd_speed(ecmd);
4038
4039 if (ecmd->port != PORT_MII)
4040 return -EINVAL;
4041 if (ecmd->transceiver != XCVR_EXTERNAL)
4042 return -EINVAL;
4043 if (ecmd->phy_address != np->phyaddr) {
4044 /* TODO: support switching between multiple phys. Should be
4045 * trivial, but not enabled due to lack of test hardware. */
4046 return -EINVAL;
4047 }
4048 if (ecmd->autoneg == AUTONEG_ENABLE) {
4049 u32 mask;
4050
4051 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4052 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4053 if (np->gigabit == PHY_GIGABIT)
4054 mask |= ADVERTISED_1000baseT_Full;
4055
4056 if ((ecmd->advertising & mask) == 0)
4057 return -EINVAL;
4058
4059 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4060 /* Note: autonegotiation disable, speed 1000 intentionally
4061 * forbidden - no one should need that. */
4062
4063 if (speed != SPEED_10 && speed != SPEED_100)
4064 return -EINVAL;
4065 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4066 return -EINVAL;
4067 } else {
4068 return -EINVAL;
4069 }
4070
4071 netif_carrier_off(dev);
4072 if (netif_running(dev)) {
4073 unsigned long flags;
4074
4075 nv_disable_irq(dev);
4076 netif_tx_lock_bh(dev);
4077 netif_addr_lock(dev);
4078 /* with plain spinlock lockdep complains */
4079 spin_lock_irqsave(&np->lock, flags);
4080 /* stop engines */
4081 /* FIXME:
4082 * this can take some time, and interrupts are disabled
4083 * due to spin_lock_irqsave, but let's hope no daemon
4084 * is going to change the settings very often...
4085 * Worst case:
4086 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4087 * + some minor delays, which is up to a second approximately
4088 */
4089 nv_stop_rxtx(dev);
4090 spin_unlock_irqrestore(&np->lock, flags);
4091 netif_addr_unlock(dev);
4092 netif_tx_unlock_bh(dev);
4093 }
4094
4095 if (ecmd->autoneg == AUTONEG_ENABLE) {
4096 int adv, bmcr;
4097
4098 np->autoneg = 1;
4099
4100 /* advertise only what has been requested */
4101 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4102 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4103 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4104 adv |= ADVERTISE_10HALF;
4105 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4106 adv |= ADVERTISE_10FULL;
4107 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4108 adv |= ADVERTISE_100HALF;
4109 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4110 adv |= ADVERTISE_100FULL;
4111 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4112 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4113 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4114 adv |= ADVERTISE_PAUSE_ASYM;
4115 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4116
4117 if (np->gigabit == PHY_GIGABIT) {
4118 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4119 adv &= ~ADVERTISE_1000FULL;
4120 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4121 adv |= ADVERTISE_1000FULL;
4122 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4123 }
4124
4125 if (netif_running(dev))
4126 netdev_info(dev, "link down\n");
4127 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4128 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4129 bmcr |= BMCR_ANENABLE;
4130 /* reset the phy in order for settings to stick,
4131 * and cause autoneg to start */
4132 if (phy_reset(dev, bmcr)) {
4133 netdev_info(dev, "phy reset failed\n");
4134 return -EINVAL;
4135 }
4136 } else {
4137 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4138 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4139 }
4140 } else {
4141 int adv, bmcr;
4142
4143 np->autoneg = 0;
4144
4145 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4146 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4147 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4148 adv |= ADVERTISE_10HALF;
4149 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4150 adv |= ADVERTISE_10FULL;
4151 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4152 adv |= ADVERTISE_100HALF;
4153 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4154 adv |= ADVERTISE_100FULL;
4155 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4156 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4157 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4158 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4159 }
4160 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4161 adv |= ADVERTISE_PAUSE_ASYM;
4162 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4163 }
4164 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4165 np->fixed_mode = adv;
4166
4167 if (np->gigabit == PHY_GIGABIT) {
4168 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4169 adv &= ~ADVERTISE_1000FULL;
4170 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4171 }
4172
4173 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4174 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4175 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4176 bmcr |= BMCR_FULLDPLX;
4177 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4178 bmcr |= BMCR_SPEED100;
4179 if (np->phy_oui == PHY_OUI_MARVELL) {
4180 /* reset the phy in order for forced mode settings to stick */
4181 if (phy_reset(dev, bmcr)) {
4182 netdev_info(dev, "phy reset failed\n");
4183 return -EINVAL;
4184 }
4185 } else {
4186 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4187 if (netif_running(dev)) {
4188 /* Wait a bit and then reconfigure the nic. */
4189 udelay(10);
4190 nv_linkchange(dev);
4191 }
4192 }
4193 }
4194
4195 if (netif_running(dev)) {
4196 nv_start_rxtx(dev);
4197 nv_enable_irq(dev);
4198 }
4199
4200 return 0;
4201 }
4202
4203 #define FORCEDETH_REGS_VER 1
4204
4205 static int nv_get_regs_len(struct net_device *dev)
4206 {
4207 struct fe_priv *np = netdev_priv(dev);
4208 return np->register_size;
4209 }
4210
4211 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4212 {
4213 struct fe_priv *np = netdev_priv(dev);
4214 u8 __iomem *base = get_hwbase(dev);
4215 u32 *rbuf = buf;
4216 int i;
4217
4218 regs->version = FORCEDETH_REGS_VER;
4219 spin_lock_irq(&np->lock);
4220 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4221 rbuf[i] = readl(base + i*sizeof(u32));
4222 spin_unlock_irq(&np->lock);
4223 }
4224
4225 static int nv_nway_reset(struct net_device *dev)
4226 {
4227 struct fe_priv *np = netdev_priv(dev);
4228 int ret;
4229
4230 if (np->autoneg) {
4231 int bmcr;
4232
4233 netif_carrier_off(dev);
4234 if (netif_running(dev)) {
4235 nv_disable_irq(dev);
4236 netif_tx_lock_bh(dev);
4237 netif_addr_lock(dev);
4238 spin_lock(&np->lock);
4239 /* stop engines */
4240 nv_stop_rxtx(dev);
4241 spin_unlock(&np->lock);
4242 netif_addr_unlock(dev);
4243 netif_tx_unlock_bh(dev);
4244 netdev_info(dev, "link down\n");
4245 }
4246
4247 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4248 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4249 bmcr |= BMCR_ANENABLE;
4250 /* reset the phy in order for settings to stick*/
4251 if (phy_reset(dev, bmcr)) {
4252 netdev_info(dev, "phy reset failed\n");
4253 return -EINVAL;
4254 }
4255 } else {
4256 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4257 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4258 }
4259
4260 if (netif_running(dev)) {
4261 nv_start_rxtx(dev);
4262 nv_enable_irq(dev);
4263 }
4264 ret = 0;
4265 } else {
4266 ret = -EINVAL;
4267 }
4268
4269 return ret;
4270 }
4271
4272 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4273 {
4274 struct fe_priv *np = netdev_priv(dev);
4275
4276 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4277 ring->rx_mini_max_pending = 0;
4278 ring->rx_jumbo_max_pending = 0;
4279 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4280
4281 ring->rx_pending = np->rx_ring_size;
4282 ring->rx_mini_pending = 0;
4283 ring->rx_jumbo_pending = 0;
4284 ring->tx_pending = np->tx_ring_size;
4285 }
4286
4287 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4288 {
4289 struct fe_priv *np = netdev_priv(dev);
4290 u8 __iomem *base = get_hwbase(dev);
4291 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4292 dma_addr_t ring_addr;
4293
4294 if (ring->rx_pending < RX_RING_MIN ||
4295 ring->tx_pending < TX_RING_MIN ||
4296 ring->rx_mini_pending != 0 ||
4297 ring->rx_jumbo_pending != 0 ||
4298 (np->desc_ver == DESC_VER_1 &&
4299 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4300 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4301 (np->desc_ver != DESC_VER_1 &&
4302 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4303 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4304 return -EINVAL;
4305 }
4306
4307 /* allocate new rings */
4308 if (!nv_optimized(np)) {
4309 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4310 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4311 &ring_addr);
4312 } else {
4313 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4314 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4315 &ring_addr);
4316 }
4317 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4318 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4319 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4320 /* fall back to old rings */
4321 if (!nv_optimized(np)) {
4322 if (rxtx_ring)
4323 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4324 rxtx_ring, ring_addr);
4325 } else {
4326 if (rxtx_ring)
4327 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4328 rxtx_ring, ring_addr);
4329 }
4330
4331 kfree(rx_skbuff);
4332 kfree(tx_skbuff);
4333 goto exit;
4334 }
4335
4336 if (netif_running(dev)) {
4337 nv_disable_irq(dev);
4338 nv_napi_disable(dev);
4339 netif_tx_lock_bh(dev);
4340 netif_addr_lock(dev);
4341 spin_lock(&np->lock);
4342 /* stop engines */
4343 nv_stop_rxtx(dev);
4344 nv_txrx_reset(dev);
4345 /* drain queues */
4346 nv_drain_rxtx(dev);
4347 /* delete queues */
4348 free_rings(dev);
4349 }
4350
4351 /* set new values */
4352 np->rx_ring_size = ring->rx_pending;
4353 np->tx_ring_size = ring->tx_pending;
4354
4355 if (!nv_optimized(np)) {
4356 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4357 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4358 } else {
4359 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4360 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4361 }
4362 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4363 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4364 np->ring_addr = ring_addr;
4365
4366 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4367 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4368
4369 if (netif_running(dev)) {
4370 /* reinit driver view of the queues */
4371 set_bufsize(dev);
4372 if (nv_init_ring(dev)) {
4373 if (!np->in_shutdown)
4374 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4375 }
4376
4377 /* reinit nic view of the queues */
4378 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4379 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4380 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4381 base + NvRegRingSizes);
4382 pci_push(base);
4383 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4384 pci_push(base);
4385
4386 /* restart engines */
4387 nv_start_rxtx(dev);
4388 spin_unlock(&np->lock);
4389 netif_addr_unlock(dev);
4390 netif_tx_unlock_bh(dev);
4391 nv_napi_enable(dev);
4392 nv_enable_irq(dev);
4393 }
4394 return 0;
4395 exit:
4396 return -ENOMEM;
4397 }
4398
4399 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4400 {
4401 struct fe_priv *np = netdev_priv(dev);
4402
4403 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4404 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4405 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4406 }
4407
4408 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4409 {
4410 struct fe_priv *np = netdev_priv(dev);
4411 int adv, bmcr;
4412
4413 if ((!np->autoneg && np->duplex == 0) ||
4414 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4415 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4416 return -EINVAL;
4417 }
4418 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4419 netdev_info(dev, "hardware does not support tx pause frames\n");
4420 return -EINVAL;
4421 }
4422
4423 netif_carrier_off(dev);
4424 if (netif_running(dev)) {
4425 nv_disable_irq(dev);
4426 netif_tx_lock_bh(dev);
4427 netif_addr_lock(dev);
4428 spin_lock(&np->lock);
4429 /* stop engines */
4430 nv_stop_rxtx(dev);
4431 spin_unlock(&np->lock);
4432 netif_addr_unlock(dev);
4433 netif_tx_unlock_bh(dev);
4434 }
4435
4436 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4437 if (pause->rx_pause)
4438 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4439 if (pause->tx_pause)
4440 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4441
4442 if (np->autoneg && pause->autoneg) {
4443 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4444
4445 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4446 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4447 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4448 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4449 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4450 adv |= ADVERTISE_PAUSE_ASYM;
4451 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4452
4453 if (netif_running(dev))
4454 netdev_info(dev, "link down\n");
4455 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4456 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4457 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4458 } else {
4459 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4460 if (pause->rx_pause)
4461 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4462 if (pause->tx_pause)
4463 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4464
4465 if (!netif_running(dev))
4466 nv_update_linkspeed(dev);
4467 else
4468 nv_update_pause(dev, np->pause_flags);
4469 }
4470
4471 if (netif_running(dev)) {
4472 nv_start_rxtx(dev);
4473 nv_enable_irq(dev);
4474 }
4475 return 0;
4476 }
4477
4478 static u32 nv_fix_features(struct net_device *dev, u32 features)
4479 {
4480 /* vlan is dependent on rx checksum offload */
4481 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4482 features |= NETIF_F_RXCSUM;
4483
4484 return features;
4485 }
4486
4487 static void nv_vlan_mode(struct net_device *dev, u32 features)
4488 {
4489 struct fe_priv *np = get_nvpriv(dev);
4490
4491 spin_lock_irq(&np->lock);
4492
4493 if (features & NETIF_F_HW_VLAN_RX)
4494 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4495 else
4496 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4497
4498 if (features & NETIF_F_HW_VLAN_TX)
4499 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4500 else
4501 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4502
4503 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4504
4505 spin_unlock_irq(&np->lock);
4506 }
4507
4508 static int nv_set_features(struct net_device *dev, u32 features)
4509 {
4510 struct fe_priv *np = netdev_priv(dev);
4511 u8 __iomem *base = get_hwbase(dev);
4512 u32 changed = dev->features ^ features;
4513
4514 if (changed & NETIF_F_RXCSUM) {
4515 spin_lock_irq(&np->lock);
4516
4517 if (features & NETIF_F_RXCSUM)
4518 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4519 else
4520 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4521
4522 if (netif_running(dev))
4523 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4524
4525 spin_unlock_irq(&np->lock);
4526 }
4527
4528 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4529 nv_vlan_mode(dev, features);
4530
4531 return 0;
4532 }
4533
4534 static int nv_get_sset_count(struct net_device *dev, int sset)
4535 {
4536 struct fe_priv *np = netdev_priv(dev);
4537
4538 switch (sset) {
4539 case ETH_SS_TEST:
4540 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4541 return NV_TEST_COUNT_EXTENDED;
4542 else
4543 return NV_TEST_COUNT_BASE;
4544 case ETH_SS_STATS:
4545 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4546 return NV_DEV_STATISTICS_V3_COUNT;
4547 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4548 return NV_DEV_STATISTICS_V2_COUNT;
4549 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4550 return NV_DEV_STATISTICS_V1_COUNT;
4551 else
4552 return 0;
4553 default:
4554 return -EOPNOTSUPP;
4555 }
4556 }
4557
4558 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4559 {
4560 struct fe_priv *np = netdev_priv(dev);
4561
4562 /* update stats */
4563 nv_do_stats_poll((unsigned long)dev);
4564
4565 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4566 }
4567
4568 static int nv_link_test(struct net_device *dev)
4569 {
4570 struct fe_priv *np = netdev_priv(dev);
4571 int mii_status;
4572
4573 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4574 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4575
4576 /* check phy link status */
4577 if (!(mii_status & BMSR_LSTATUS))
4578 return 0;
4579 else
4580 return 1;
4581 }
4582
4583 static int nv_register_test(struct net_device *dev)
4584 {
4585 u8 __iomem *base = get_hwbase(dev);
4586 int i = 0;
4587 u32 orig_read, new_read;
4588
4589 do {
4590 orig_read = readl(base + nv_registers_test[i].reg);
4591
4592 /* xor with mask to toggle bits */
4593 orig_read ^= nv_registers_test[i].mask;
4594
4595 writel(orig_read, base + nv_registers_test[i].reg);
4596
4597 new_read = readl(base + nv_registers_test[i].reg);
4598
4599 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4600 return 0;
4601
4602 /* restore original value */
4603 orig_read ^= nv_registers_test[i].mask;
4604 writel(orig_read, base + nv_registers_test[i].reg);
4605
4606 } while (nv_registers_test[++i].reg != 0);
4607
4608 return 1;
4609 }
4610
4611 static int nv_interrupt_test(struct net_device *dev)
4612 {
4613 struct fe_priv *np = netdev_priv(dev);
4614 u8 __iomem *base = get_hwbase(dev);
4615 int ret = 1;
4616 int testcnt;
4617 u32 save_msi_flags, save_poll_interval = 0;
4618
4619 if (netif_running(dev)) {
4620 /* free current irq */
4621 nv_free_irq(dev);
4622 save_poll_interval = readl(base+NvRegPollingInterval);
4623 }
4624
4625 /* flag to test interrupt handler */
4626 np->intr_test = 0;
4627
4628 /* setup test irq */
4629 save_msi_flags = np->msi_flags;
4630 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4631 np->msi_flags |= 0x001; /* setup 1 vector */
4632 if (nv_request_irq(dev, 1))
4633 return 0;
4634
4635 /* setup timer interrupt */
4636 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4637 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4638
4639 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4640
4641 /* wait for at least one interrupt */
4642 msleep(100);
4643
4644 spin_lock_irq(&np->lock);
4645
4646 /* flag should be set within ISR */
4647 testcnt = np->intr_test;
4648 if (!testcnt)
4649 ret = 2;
4650
4651 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4652 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4653 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4654 else
4655 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4656
4657 spin_unlock_irq(&np->lock);
4658
4659 nv_free_irq(dev);
4660
4661 np->msi_flags = save_msi_flags;
4662
4663 if (netif_running(dev)) {
4664 writel(save_poll_interval, base + NvRegPollingInterval);
4665 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4666 /* restore original irq */
4667 if (nv_request_irq(dev, 0))
4668 return 0;
4669 }
4670
4671 return ret;
4672 }
4673
4674 static int nv_loopback_test(struct net_device *dev)
4675 {
4676 struct fe_priv *np = netdev_priv(dev);
4677 u8 __iomem *base = get_hwbase(dev);
4678 struct sk_buff *tx_skb, *rx_skb;
4679 dma_addr_t test_dma_addr;
4680 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4681 u32 flags;
4682 int len, i, pkt_len;
4683 u8 *pkt_data;
4684 u32 filter_flags = 0;
4685 u32 misc1_flags = 0;
4686 int ret = 1;
4687
4688 if (netif_running(dev)) {
4689 nv_disable_irq(dev);
4690 filter_flags = readl(base + NvRegPacketFilterFlags);
4691 misc1_flags = readl(base + NvRegMisc1);
4692 } else {
4693 nv_txrx_reset(dev);
4694 }
4695
4696 /* reinit driver view of the rx queue */
4697 set_bufsize(dev);
4698 nv_init_ring(dev);
4699
4700 /* setup hardware for loopback */
4701 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4702 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4703
4704 /* reinit nic view of the rx queue */
4705 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4706 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4707 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4708 base + NvRegRingSizes);
4709 pci_push(base);
4710
4711 /* restart rx engine */
4712 nv_start_rxtx(dev);
4713
4714 /* setup packet for tx */
4715 pkt_len = ETH_DATA_LEN;
4716 tx_skb = dev_alloc_skb(pkt_len);
4717 if (!tx_skb) {
4718 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4719 ret = 0;
4720 goto out;
4721 }
4722 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4723 skb_tailroom(tx_skb),
4724 PCI_DMA_FROMDEVICE);
4725 pkt_data = skb_put(tx_skb, pkt_len);
4726 for (i = 0; i < pkt_len; i++)
4727 pkt_data[i] = (u8)(i & 0xff);
4728
4729 if (!nv_optimized(np)) {
4730 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4731 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4732 } else {
4733 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4734 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4735 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4736 }
4737 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4738 pci_push(get_hwbase(dev));
4739
4740 msleep(500);
4741
4742 /* check for rx of the packet */
4743 if (!nv_optimized(np)) {
4744 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4745 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4746
4747 } else {
4748 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4749 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4750 }
4751
4752 if (flags & NV_RX_AVAIL) {
4753 ret = 0;
4754 } else if (np->desc_ver == DESC_VER_1) {
4755 if (flags & NV_RX_ERROR)
4756 ret = 0;
4757 } else {
4758 if (flags & NV_RX2_ERROR)
4759 ret = 0;
4760 }
4761
4762 if (ret) {
4763 if (len != pkt_len) {
4764 ret = 0;
4765 } else {
4766 rx_skb = np->rx_skb[0].skb;
4767 for (i = 0; i < pkt_len; i++) {
4768 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4769 ret = 0;
4770 break;
4771 }
4772 }
4773 }
4774 }
4775
4776 pci_unmap_single(np->pci_dev, test_dma_addr,
4777 (skb_end_pointer(tx_skb) - tx_skb->data),
4778 PCI_DMA_TODEVICE);
4779 dev_kfree_skb_any(tx_skb);
4780 out:
4781 /* stop engines */
4782 nv_stop_rxtx(dev);
4783 nv_txrx_reset(dev);
4784 /* drain rx queue */
4785 nv_drain_rxtx(dev);
4786
4787 if (netif_running(dev)) {
4788 writel(misc1_flags, base + NvRegMisc1);
4789 writel(filter_flags, base + NvRegPacketFilterFlags);
4790 nv_enable_irq(dev);
4791 }
4792
4793 return ret;
4794 }
4795
4796 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4797 {
4798 struct fe_priv *np = netdev_priv(dev);
4799 u8 __iomem *base = get_hwbase(dev);
4800 int result;
4801 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4802
4803 if (!nv_link_test(dev)) {
4804 test->flags |= ETH_TEST_FL_FAILED;
4805 buffer[0] = 1;
4806 }
4807
4808 if (test->flags & ETH_TEST_FL_OFFLINE) {
4809 if (netif_running(dev)) {
4810 netif_stop_queue(dev);
4811 nv_napi_disable(dev);
4812 netif_tx_lock_bh(dev);
4813 netif_addr_lock(dev);
4814 spin_lock_irq(&np->lock);
4815 nv_disable_hw_interrupts(dev, np->irqmask);
4816 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4817 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4818 else
4819 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4820 /* stop engines */
4821 nv_stop_rxtx(dev);
4822 nv_txrx_reset(dev);
4823 /* drain rx queue */
4824 nv_drain_rxtx(dev);
4825 spin_unlock_irq(&np->lock);
4826 netif_addr_unlock(dev);
4827 netif_tx_unlock_bh(dev);
4828 }
4829
4830 if (!nv_register_test(dev)) {
4831 test->flags |= ETH_TEST_FL_FAILED;
4832 buffer[1] = 1;
4833 }
4834
4835 result = nv_interrupt_test(dev);
4836 if (result != 1) {
4837 test->flags |= ETH_TEST_FL_FAILED;
4838 buffer[2] = 1;
4839 }
4840 if (result == 0) {
4841 /* bail out */
4842 return;
4843 }
4844
4845 if (!nv_loopback_test(dev)) {
4846 test->flags |= ETH_TEST_FL_FAILED;
4847 buffer[3] = 1;
4848 }
4849
4850 if (netif_running(dev)) {
4851 /* reinit driver view of the rx queue */
4852 set_bufsize(dev);
4853 if (nv_init_ring(dev)) {
4854 if (!np->in_shutdown)
4855 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4856 }
4857 /* reinit nic view of the rx queue */
4858 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4859 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4860 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4861 base + NvRegRingSizes);
4862 pci_push(base);
4863 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4864 pci_push(base);
4865 /* restart rx engine */
4866 nv_start_rxtx(dev);
4867 netif_start_queue(dev);
4868 nv_napi_enable(dev);
4869 nv_enable_hw_interrupts(dev, np->irqmask);
4870 }
4871 }
4872 }
4873
4874 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4875 {
4876 switch (stringset) {
4877 case ETH_SS_STATS:
4878 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4879 break;
4880 case ETH_SS_TEST:
4881 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4882 break;
4883 }
4884 }
4885
4886 static const struct ethtool_ops ops = {
4887 .get_drvinfo = nv_get_drvinfo,
4888 .get_link = ethtool_op_get_link,
4889 .get_wol = nv_get_wol,
4890 .set_wol = nv_set_wol,
4891 .get_settings = nv_get_settings,
4892 .set_settings = nv_set_settings,
4893 .get_regs_len = nv_get_regs_len,
4894 .get_regs = nv_get_regs,
4895 .nway_reset = nv_nway_reset,
4896 .get_ringparam = nv_get_ringparam,
4897 .set_ringparam = nv_set_ringparam,
4898 .get_pauseparam = nv_get_pauseparam,
4899 .set_pauseparam = nv_set_pauseparam,
4900 .get_strings = nv_get_strings,
4901 .get_ethtool_stats = nv_get_ethtool_stats,
4902 .get_sset_count = nv_get_sset_count,
4903 .self_test = nv_self_test,
4904 };
4905
4906 /* The mgmt unit and driver use a semaphore to access the phy during init */
4907 static int nv_mgmt_acquire_sema(struct net_device *dev)
4908 {
4909 struct fe_priv *np = netdev_priv(dev);
4910 u8 __iomem *base = get_hwbase(dev);
4911 int i;
4912 u32 tx_ctrl, mgmt_sema;
4913
4914 for (i = 0; i < 10; i++) {
4915 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4916 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4917 break;
4918 msleep(500);
4919 }
4920
4921 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4922 return 0;
4923
4924 for (i = 0; i < 2; i++) {
4925 tx_ctrl = readl(base + NvRegTransmitterControl);
4926 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4927 writel(tx_ctrl, base + NvRegTransmitterControl);
4928
4929 /* verify that semaphore was acquired */
4930 tx_ctrl = readl(base + NvRegTransmitterControl);
4931 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4932 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4933 np->mgmt_sema = 1;
4934 return 1;
4935 } else
4936 udelay(50);
4937 }
4938
4939 return 0;
4940 }
4941
4942 static void nv_mgmt_release_sema(struct net_device *dev)
4943 {
4944 struct fe_priv *np = netdev_priv(dev);
4945 u8 __iomem *base = get_hwbase(dev);
4946 u32 tx_ctrl;
4947
4948 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4949 if (np->mgmt_sema) {
4950 tx_ctrl = readl(base + NvRegTransmitterControl);
4951 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4952 writel(tx_ctrl, base + NvRegTransmitterControl);
4953 }
4954 }
4955 }
4956
4957
4958 static int nv_mgmt_get_version(struct net_device *dev)
4959 {
4960 struct fe_priv *np = netdev_priv(dev);
4961 u8 __iomem *base = get_hwbase(dev);
4962 u32 data_ready = readl(base + NvRegTransmitterControl);
4963 u32 data_ready2 = 0;
4964 unsigned long start;
4965 int ready = 0;
4966
4967 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4968 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4969 start = jiffies;
4970 while (time_before(jiffies, start + 5*HZ)) {
4971 data_ready2 = readl(base + NvRegTransmitterControl);
4972 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4973 ready = 1;
4974 break;
4975 }
4976 schedule_timeout_uninterruptible(1);
4977 }
4978
4979 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4980 return 0;
4981
4982 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4983
4984 return 1;
4985 }
4986
4987 static int nv_open(struct net_device *dev)
4988 {
4989 struct fe_priv *np = netdev_priv(dev);
4990 u8 __iomem *base = get_hwbase(dev);
4991 int ret = 1;
4992 int oom, i;
4993 u32 low;
4994
4995 /* power up phy */
4996 mii_rw(dev, np->phyaddr, MII_BMCR,
4997 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
4998
4999 nv_txrx_gate(dev, false);
5000 /* erase previous misconfiguration */
5001 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5002 nv_mac_reset(dev);
5003 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5004 writel(0, base + NvRegMulticastAddrB);
5005 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5006 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5007 writel(0, base + NvRegPacketFilterFlags);
5008
5009 writel(0, base + NvRegTransmitterControl);
5010 writel(0, base + NvRegReceiverControl);
5011
5012 writel(0, base + NvRegAdapterControl);
5013
5014 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5015 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5016
5017 /* initialize descriptor rings */
5018 set_bufsize(dev);
5019 oom = nv_init_ring(dev);
5020
5021 writel(0, base + NvRegLinkSpeed);
5022 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5023 nv_txrx_reset(dev);
5024 writel(0, base + NvRegUnknownSetupReg6);
5025
5026 np->in_shutdown = 0;
5027
5028 /* give hw rings */
5029 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5030 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5031 base + NvRegRingSizes);
5032
5033 writel(np->linkspeed, base + NvRegLinkSpeed);
5034 if (np->desc_ver == DESC_VER_1)
5035 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5036 else
5037 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5038 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5039 writel(np->vlanctl_bits, base + NvRegVlanControl);
5040 pci_push(base);
5041 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5042 if (reg_delay(dev, NvRegUnknownSetupReg5,
5043 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5044 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5045 netdev_info(dev,
5046 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5047
5048 writel(0, base + NvRegMIIMask);
5049 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5050 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5051
5052 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5053 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5054 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5055 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5056
5057 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5058
5059 get_random_bytes(&low, sizeof(low));
5060 low &= NVREG_SLOTTIME_MASK;
5061 if (np->desc_ver == DESC_VER_1) {
5062 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5063 } else {
5064 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5065 /* setup legacy backoff */
5066 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5067 } else {
5068 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5069 nv_gear_backoff_reseed(dev);
5070 }
5071 }
5072 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5073 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5074 if (poll_interval == -1) {
5075 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5076 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5077 else
5078 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5079 } else
5080 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5081 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5082 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5083 base + NvRegAdapterControl);
5084 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5085 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5086 if (np->wolenabled)
5087 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5088
5089 i = readl(base + NvRegPowerState);
5090 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5091 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5092
5093 pci_push(base);
5094 udelay(10);
5095 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5096
5097 nv_disable_hw_interrupts(dev, np->irqmask);
5098 pci_push(base);
5099 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5100 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5101 pci_push(base);
5102
5103 if (nv_request_irq(dev, 0))
5104 goto out_drain;
5105
5106 /* ask for interrupts */
5107 nv_enable_hw_interrupts(dev, np->irqmask);
5108
5109 spin_lock_irq(&np->lock);
5110 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5111 writel(0, base + NvRegMulticastAddrB);
5112 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5113 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5114 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5115 /* One manual link speed update: Interrupts are enabled, future link
5116 * speed changes cause interrupts and are handled by nv_link_irq().
5117 */
5118 {
5119 u32 miistat;
5120 miistat = readl(base + NvRegMIIStatus);
5121 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5122 }
5123 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5124 * to init hw */
5125 np->linkspeed = 0;
5126 ret = nv_update_linkspeed(dev);
5127 nv_start_rxtx(dev);
5128 netif_start_queue(dev);
5129 nv_napi_enable(dev);
5130
5131 if (ret) {
5132 netif_carrier_on(dev);
5133 } else {
5134 netdev_info(dev, "no link during initialization\n");
5135 netif_carrier_off(dev);
5136 }
5137 if (oom)
5138 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5139
5140 /* start statistics timer */
5141 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5142 mod_timer(&np->stats_poll,
5143 round_jiffies(jiffies + STATS_INTERVAL));
5144
5145 spin_unlock_irq(&np->lock);
5146
5147 return 0;
5148 out_drain:
5149 nv_drain_rxtx(dev);
5150 return ret;
5151 }
5152
5153 static int nv_close(struct net_device *dev)
5154 {
5155 struct fe_priv *np = netdev_priv(dev);
5156 u8 __iomem *base;
5157
5158 spin_lock_irq(&np->lock);
5159 np->in_shutdown = 1;
5160 spin_unlock_irq(&np->lock);
5161 nv_napi_disable(dev);
5162 synchronize_irq(np->pci_dev->irq);
5163
5164 del_timer_sync(&np->oom_kick);
5165 del_timer_sync(&np->nic_poll);
5166 del_timer_sync(&np->stats_poll);
5167
5168 netif_stop_queue(dev);
5169 spin_lock_irq(&np->lock);
5170 nv_stop_rxtx(dev);
5171 nv_txrx_reset(dev);
5172
5173 /* disable interrupts on the nic or we will lock up */
5174 base = get_hwbase(dev);
5175 nv_disable_hw_interrupts(dev, np->irqmask);
5176 pci_push(base);
5177
5178 spin_unlock_irq(&np->lock);
5179
5180 nv_free_irq(dev);
5181
5182 nv_drain_rxtx(dev);
5183
5184 if (np->wolenabled || !phy_power_down) {
5185 nv_txrx_gate(dev, false);
5186 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5187 nv_start_rx(dev);
5188 } else {
5189 /* power down phy */
5190 mii_rw(dev, np->phyaddr, MII_BMCR,
5191 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5192 nv_txrx_gate(dev, true);
5193 }
5194
5195 /* FIXME: power down nic */
5196
5197 return 0;
5198 }
5199
5200 static const struct net_device_ops nv_netdev_ops = {
5201 .ndo_open = nv_open,
5202 .ndo_stop = nv_close,
5203 .ndo_get_stats = nv_get_stats,
5204 .ndo_start_xmit = nv_start_xmit,
5205 .ndo_tx_timeout = nv_tx_timeout,
5206 .ndo_change_mtu = nv_change_mtu,
5207 .ndo_fix_features = nv_fix_features,
5208 .ndo_set_features = nv_set_features,
5209 .ndo_validate_addr = eth_validate_addr,
5210 .ndo_set_mac_address = nv_set_mac_address,
5211 .ndo_set_multicast_list = nv_set_multicast,
5212 #ifdef CONFIG_NET_POLL_CONTROLLER
5213 .ndo_poll_controller = nv_poll_controller,
5214 #endif
5215 };
5216
5217 static const struct net_device_ops nv_netdev_ops_optimized = {
5218 .ndo_open = nv_open,
5219 .ndo_stop = nv_close,
5220 .ndo_get_stats = nv_get_stats,
5221 .ndo_start_xmit = nv_start_xmit_optimized,
5222 .ndo_tx_timeout = nv_tx_timeout,
5223 .ndo_change_mtu = nv_change_mtu,
5224 .ndo_fix_features = nv_fix_features,
5225 .ndo_set_features = nv_set_features,
5226 .ndo_validate_addr = eth_validate_addr,
5227 .ndo_set_mac_address = nv_set_mac_address,
5228 .ndo_set_multicast_list = nv_set_multicast,
5229 #ifdef CONFIG_NET_POLL_CONTROLLER
5230 .ndo_poll_controller = nv_poll_controller,
5231 #endif
5232 };
5233
5234 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5235 {
5236 struct net_device *dev;
5237 struct fe_priv *np;
5238 unsigned long addr;
5239 u8 __iomem *base;
5240 int err, i;
5241 u32 powerstate, txreg;
5242 u32 phystate_orig = 0, phystate;
5243 int phyinitialized = 0;
5244 static int printed_version;
5245
5246 if (!printed_version++)
5247 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5248 FORCEDETH_VERSION);
5249
5250 dev = alloc_etherdev(sizeof(struct fe_priv));
5251 err = -ENOMEM;
5252 if (!dev)
5253 goto out;
5254
5255 np = netdev_priv(dev);
5256 np->dev = dev;
5257 np->pci_dev = pci_dev;
5258 spin_lock_init(&np->lock);
5259 SET_NETDEV_DEV(dev, &pci_dev->dev);
5260
5261 init_timer(&np->oom_kick);
5262 np->oom_kick.data = (unsigned long) dev;
5263 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5264 init_timer(&np->nic_poll);
5265 np->nic_poll.data = (unsigned long) dev;
5266 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5267 init_timer(&np->stats_poll);
5268 np->stats_poll.data = (unsigned long) dev;
5269 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5270
5271 err = pci_enable_device(pci_dev);
5272 if (err)
5273 goto out_free;
5274
5275 pci_set_master(pci_dev);
5276
5277 err = pci_request_regions(pci_dev, DRV_NAME);
5278 if (err < 0)
5279 goto out_disable;
5280
5281 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5282 np->register_size = NV_PCI_REGSZ_VER3;
5283 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5284 np->register_size = NV_PCI_REGSZ_VER2;
5285 else
5286 np->register_size = NV_PCI_REGSZ_VER1;
5287
5288 err = -EINVAL;
5289 addr = 0;
5290 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5291 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5292 pci_resource_len(pci_dev, i) >= np->register_size) {
5293 addr = pci_resource_start(pci_dev, i);
5294 break;
5295 }
5296 }
5297 if (i == DEVICE_COUNT_RESOURCE) {
5298 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5299 goto out_relreg;
5300 }
5301
5302 /* copy of driver data */
5303 np->driver_data = id->driver_data;
5304 /* copy of device id */
5305 np->device_id = id->device;
5306
5307 /* handle different descriptor versions */
5308 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5309 /* packet format 3: supports 40-bit addressing */
5310 np->desc_ver = DESC_VER_3;
5311 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5312 if (dma_64bit) {
5313 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5314 dev_info(&pci_dev->dev,
5315 "64-bit DMA failed, using 32-bit addressing\n");
5316 else
5317 dev->features |= NETIF_F_HIGHDMA;
5318 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5319 dev_info(&pci_dev->dev,
5320 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5321 }
5322 }
5323 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5324 /* packet format 2: supports jumbo frames */
5325 np->desc_ver = DESC_VER_2;
5326 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5327 } else {
5328 /* original packet format */
5329 np->desc_ver = DESC_VER_1;
5330 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5331 }
5332
5333 np->pkt_limit = NV_PKTLIMIT_1;
5334 if (id->driver_data & DEV_HAS_LARGEDESC)
5335 np->pkt_limit = NV_PKTLIMIT_2;
5336
5337 if (id->driver_data & DEV_HAS_CHECKSUM) {
5338 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5339 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5340 NETIF_F_TSO | NETIF_F_RXCSUM;
5341 }
5342
5343 np->vlanctl_bits = 0;
5344 if (id->driver_data & DEV_HAS_VLAN) {
5345 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5346 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5347 }
5348
5349 dev->features |= dev->hw_features;
5350
5351 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5352 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5353 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5354 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5355 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5356 }
5357
5358 err = -ENOMEM;
5359 np->base = ioremap(addr, np->register_size);
5360 if (!np->base)
5361 goto out_relreg;
5362 dev->base_addr = (unsigned long)np->base;
5363
5364 dev->irq = pci_dev->irq;
5365
5366 np->rx_ring_size = RX_RING_DEFAULT;
5367 np->tx_ring_size = TX_RING_DEFAULT;
5368
5369 if (!nv_optimized(np)) {
5370 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5371 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5372 &np->ring_addr);
5373 if (!np->rx_ring.orig)
5374 goto out_unmap;
5375 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5376 } else {
5377 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5378 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5379 &np->ring_addr);
5380 if (!np->rx_ring.ex)
5381 goto out_unmap;
5382 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5383 }
5384 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5385 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5386 if (!np->rx_skb || !np->tx_skb)
5387 goto out_freering;
5388
5389 if (!nv_optimized(np))
5390 dev->netdev_ops = &nv_netdev_ops;
5391 else
5392 dev->netdev_ops = &nv_netdev_ops_optimized;
5393
5394 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5395 SET_ETHTOOL_OPS(dev, &ops);
5396 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5397
5398 pci_set_drvdata(pci_dev, dev);
5399
5400 /* read the mac address */
5401 base = get_hwbase(dev);
5402 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5403 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5404
5405 /* check the workaround bit for correct mac address order */
5406 txreg = readl(base + NvRegTransmitPoll);
5407 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5408 /* mac address is already in correct order */
5409 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5410 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5411 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5412 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5413 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5414 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5415 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5416 /* mac address is already in correct order */
5417 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5418 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5419 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5420 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5421 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5422 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5423 /*
5424 * Set orig mac address back to the reversed version.
5425 * This flag will be cleared during low power transition.
5426 * Therefore, we should always put back the reversed address.
5427 */
5428 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5429 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5430 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5431 } else {
5432 /* need to reverse mac address to correct order */
5433 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5434 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5435 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5436 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5437 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5438 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5439 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5440 dev_dbg(&pci_dev->dev,
5441 "%s: set workaround bit for reversed mac addr\n",
5442 __func__);
5443 }
5444 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5445
5446 if (!is_valid_ether_addr(dev->perm_addr)) {
5447 /*
5448 * Bad mac address. At least one bios sets the mac address
5449 * to 01:23:45:67:89:ab
5450 */
5451 dev_err(&pci_dev->dev,
5452 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5453 dev->dev_addr);
5454 random_ether_addr(dev->dev_addr);
5455 dev_err(&pci_dev->dev,
5456 "Using random MAC address: %pM\n", dev->dev_addr);
5457 }
5458
5459 /* set mac address */
5460 nv_copy_mac_to_hw(dev);
5461
5462 /* disable WOL */
5463 writel(0, base + NvRegWakeUpFlags);
5464 np->wolenabled = 0;
5465 device_set_wakeup_enable(&pci_dev->dev, false);
5466
5467 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5468
5469 /* take phy and nic out of low power mode */
5470 powerstate = readl(base + NvRegPowerState2);
5471 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5472 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5473 pci_dev->revision >= 0xA3)
5474 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5475 writel(powerstate, base + NvRegPowerState2);
5476 }
5477
5478 if (np->desc_ver == DESC_VER_1)
5479 np->tx_flags = NV_TX_VALID;
5480 else
5481 np->tx_flags = NV_TX2_VALID;
5482
5483 np->msi_flags = 0;
5484 if ((id->driver_data & DEV_HAS_MSI) && msi)
5485 np->msi_flags |= NV_MSI_CAPABLE;
5486
5487 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5488 /* msix has had reported issues when modifying irqmask
5489 as in the case of napi, therefore, disable for now
5490 */
5491 #if 0
5492 np->msi_flags |= NV_MSI_X_CAPABLE;
5493 #endif
5494 }
5495
5496 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5497 np->irqmask = NVREG_IRQMASK_CPU;
5498 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5499 np->msi_flags |= 0x0001;
5500 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5501 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5502 /* start off in throughput mode */
5503 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5504 /* remove support for msix mode */
5505 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5506 } else {
5507 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5508 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5509 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5510 np->msi_flags |= 0x0003;
5511 }
5512
5513 if (id->driver_data & DEV_NEED_TIMERIRQ)
5514 np->irqmask |= NVREG_IRQ_TIMER;
5515 if (id->driver_data & DEV_NEED_LINKTIMER) {
5516 np->need_linktimer = 1;
5517 np->link_timeout = jiffies + LINK_TIMEOUT;
5518 } else {
5519 np->need_linktimer = 0;
5520 }
5521
5522 /* Limit the number of tx's outstanding for hw bug */
5523 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5524 np->tx_limit = 1;
5525 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5526 pci_dev->revision >= 0xA2)
5527 np->tx_limit = 0;
5528 }
5529
5530 /* clear phy state and temporarily halt phy interrupts */
5531 writel(0, base + NvRegMIIMask);
5532 phystate = readl(base + NvRegAdapterControl);
5533 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5534 phystate_orig = 1;
5535 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5536 writel(phystate, base + NvRegAdapterControl);
5537 }
5538 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5539
5540 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5541 /* management unit running on the mac? */
5542 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5543 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5544 nv_mgmt_acquire_sema(dev) &&
5545 nv_mgmt_get_version(dev)) {
5546 np->mac_in_use = 1;
5547 if (np->mgmt_version > 0)
5548 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5549 /* management unit setup the phy already? */
5550 if (np->mac_in_use &&
5551 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5552 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5553 /* phy is inited by mgmt unit */
5554 phyinitialized = 1;
5555 } else {
5556 /* we need to init the phy */
5557 }
5558 }
5559 }
5560
5561 /* find a suitable phy */
5562 for (i = 1; i <= 32; i++) {
5563 int id1, id2;
5564 int phyaddr = i & 0x1F;
5565
5566 spin_lock_irq(&np->lock);
5567 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5568 spin_unlock_irq(&np->lock);
5569 if (id1 < 0 || id1 == 0xffff)
5570 continue;
5571 spin_lock_irq(&np->lock);
5572 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5573 spin_unlock_irq(&np->lock);
5574 if (id2 < 0 || id2 == 0xffff)
5575 continue;
5576
5577 np->phy_model = id2 & PHYID2_MODEL_MASK;
5578 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5579 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5580 np->phyaddr = phyaddr;
5581 np->phy_oui = id1 | id2;
5582
5583 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5584 if (np->phy_oui == PHY_OUI_REALTEK2)
5585 np->phy_oui = PHY_OUI_REALTEK;
5586 /* Setup phy revision for Realtek */
5587 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5588 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5589
5590 break;
5591 }
5592 if (i == 33) {
5593 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5594 goto out_error;
5595 }
5596
5597 if (!phyinitialized) {
5598 /* reset it */
5599 phy_init(dev);
5600 } else {
5601 /* see if it is a gigabit phy */
5602 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5603 if (mii_status & PHY_GIGABIT)
5604 np->gigabit = PHY_GIGABIT;
5605 }
5606
5607 /* set default link speed settings */
5608 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5609 np->duplex = 0;
5610 np->autoneg = 1;
5611
5612 err = register_netdev(dev);
5613 if (err) {
5614 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5615 goto out_error;
5616 }
5617
5618 if (id->driver_data & DEV_HAS_VLAN)
5619 nv_vlan_mode(dev, dev->features);
5620
5621 netif_carrier_off(dev);
5622
5623 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5624 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5625
5626 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5627 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5628 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5629 "csum " : "",
5630 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5631 "vlan " : "",
5632 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5633 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5634 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5635 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5636 np->need_linktimer ? "lnktim " : "",
5637 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5638 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5639 np->desc_ver);
5640
5641 return 0;
5642
5643 out_error:
5644 if (phystate_orig)
5645 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5646 pci_set_drvdata(pci_dev, NULL);
5647 out_freering:
5648 free_rings(dev);
5649 out_unmap:
5650 iounmap(get_hwbase(dev));
5651 out_relreg:
5652 pci_release_regions(pci_dev);
5653 out_disable:
5654 pci_disable_device(pci_dev);
5655 out_free:
5656 free_netdev(dev);
5657 out:
5658 return err;
5659 }
5660
5661 static void nv_restore_phy(struct net_device *dev)
5662 {
5663 struct fe_priv *np = netdev_priv(dev);
5664 u16 phy_reserved, mii_control;
5665
5666 if (np->phy_oui == PHY_OUI_REALTEK &&
5667 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5668 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5669 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5670 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5671 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5672 phy_reserved |= PHY_REALTEK_INIT8;
5673 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5674 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5675
5676 /* restart auto negotiation */
5677 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5678 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5679 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5680 }
5681 }
5682
5683 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5684 {
5685 struct net_device *dev = pci_get_drvdata(pci_dev);
5686 struct fe_priv *np = netdev_priv(dev);
5687 u8 __iomem *base = get_hwbase(dev);
5688
5689 /* special op: write back the misordered MAC address - otherwise
5690 * the next nv_probe would see a wrong address.
5691 */
5692 writel(np->orig_mac[0], base + NvRegMacAddrA);
5693 writel(np->orig_mac[1], base + NvRegMacAddrB);
5694 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5695 base + NvRegTransmitPoll);
5696 }
5697
5698 static void __devexit nv_remove(struct pci_dev *pci_dev)
5699 {
5700 struct net_device *dev = pci_get_drvdata(pci_dev);
5701
5702 unregister_netdev(dev);
5703
5704 nv_restore_mac_addr(pci_dev);
5705
5706 /* restore any phy related changes */
5707 nv_restore_phy(dev);
5708
5709 nv_mgmt_release_sema(dev);
5710
5711 /* free all structures */
5712 free_rings(dev);
5713 iounmap(get_hwbase(dev));
5714 pci_release_regions(pci_dev);
5715 pci_disable_device(pci_dev);
5716 free_netdev(dev);
5717 pci_set_drvdata(pci_dev, NULL);
5718 }
5719
5720 #ifdef CONFIG_PM_SLEEP
5721 static int nv_suspend(struct device *device)
5722 {
5723 struct pci_dev *pdev = to_pci_dev(device);
5724 struct net_device *dev = pci_get_drvdata(pdev);
5725 struct fe_priv *np = netdev_priv(dev);
5726 u8 __iomem *base = get_hwbase(dev);
5727 int i;
5728
5729 if (netif_running(dev)) {
5730 /* Gross. */
5731 nv_close(dev);
5732 }
5733 netif_device_detach(dev);
5734
5735 /* save non-pci configuration space */
5736 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5737 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5738
5739 return 0;
5740 }
5741
5742 static int nv_resume(struct device *device)
5743 {
5744 struct pci_dev *pdev = to_pci_dev(device);
5745 struct net_device *dev = pci_get_drvdata(pdev);
5746 struct fe_priv *np = netdev_priv(dev);
5747 u8 __iomem *base = get_hwbase(dev);
5748 int i, rc = 0;
5749
5750 /* restore non-pci configuration space */
5751 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5752 writel(np->saved_config_space[i], base+i*sizeof(u32));
5753
5754 if (np->driver_data & DEV_NEED_MSI_FIX)
5755 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5756
5757 /* restore phy state, including autoneg */
5758 phy_init(dev);
5759
5760 netif_device_attach(dev);
5761 if (netif_running(dev)) {
5762 rc = nv_open(dev);
5763 nv_set_multicast(dev);
5764 }
5765 return rc;
5766 }
5767
5768 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5769 #define NV_PM_OPS (&nv_pm_ops)
5770
5771 #else
5772 #define NV_PM_OPS NULL
5773 #endif /* CONFIG_PM_SLEEP */
5774
5775 #ifdef CONFIG_PM
5776 static void nv_shutdown(struct pci_dev *pdev)
5777 {
5778 struct net_device *dev = pci_get_drvdata(pdev);
5779 struct fe_priv *np = netdev_priv(dev);
5780
5781 if (netif_running(dev))
5782 nv_close(dev);
5783
5784 /*
5785 * Restore the MAC so a kernel started by kexec won't get confused.
5786 * If we really go for poweroff, we must not restore the MAC,
5787 * otherwise the MAC for WOL will be reversed at least on some boards.
5788 */
5789 if (system_state != SYSTEM_POWER_OFF)
5790 nv_restore_mac_addr(pdev);
5791
5792 pci_disable_device(pdev);
5793 /*
5794 * Apparently it is not possible to reinitialise from D3 hot,
5795 * only put the device into D3 if we really go for poweroff.
5796 */
5797 if (system_state == SYSTEM_POWER_OFF) {
5798 pci_wake_from_d3(pdev, np->wolenabled);
5799 pci_set_power_state(pdev, PCI_D3hot);
5800 }
5801 }
5802 #else
5803 #define nv_shutdown NULL
5804 #endif /* CONFIG_PM */
5805
5806 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5807 { /* nForce Ethernet Controller */
5808 PCI_DEVICE(0x10DE, 0x01C3),
5809 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5810 },
5811 { /* nForce2 Ethernet Controller */
5812 PCI_DEVICE(0x10DE, 0x0066),
5813 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5814 },
5815 { /* nForce3 Ethernet Controller */
5816 PCI_DEVICE(0x10DE, 0x00D6),
5817 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5818 },
5819 { /* nForce3 Ethernet Controller */
5820 PCI_DEVICE(0x10DE, 0x0086),
5821 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5822 },
5823 { /* nForce3 Ethernet Controller */
5824 PCI_DEVICE(0x10DE, 0x008C),
5825 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5826 },
5827 { /* nForce3 Ethernet Controller */
5828 PCI_DEVICE(0x10DE, 0x00E6),
5829 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5830 },
5831 { /* nForce3 Ethernet Controller */
5832 PCI_DEVICE(0x10DE, 0x00DF),
5833 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5834 },
5835 { /* CK804 Ethernet Controller */
5836 PCI_DEVICE(0x10DE, 0x0056),
5837 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5838 },
5839 { /* CK804 Ethernet Controller */
5840 PCI_DEVICE(0x10DE, 0x0057),
5841 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5842 },
5843 { /* MCP04 Ethernet Controller */
5844 PCI_DEVICE(0x10DE, 0x0037),
5845 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5846 },
5847 { /* MCP04 Ethernet Controller */
5848 PCI_DEVICE(0x10DE, 0x0038),
5849 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5850 },
5851 { /* MCP51 Ethernet Controller */
5852 PCI_DEVICE(0x10DE, 0x0268),
5853 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5854 },
5855 { /* MCP51 Ethernet Controller */
5856 PCI_DEVICE(0x10DE, 0x0269),
5857 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5858 },
5859 { /* MCP55 Ethernet Controller */
5860 PCI_DEVICE(0x10DE, 0x0372),
5861 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5862 },
5863 { /* MCP55 Ethernet Controller */
5864 PCI_DEVICE(0x10DE, 0x0373),
5865 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5866 },
5867 { /* MCP61 Ethernet Controller */
5868 PCI_DEVICE(0x10DE, 0x03E5),
5869 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5870 },
5871 { /* MCP61 Ethernet Controller */
5872 PCI_DEVICE(0x10DE, 0x03E6),
5873 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5874 },
5875 { /* MCP61 Ethernet Controller */
5876 PCI_DEVICE(0x10DE, 0x03EE),
5877 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5878 },
5879 { /* MCP61 Ethernet Controller */
5880 PCI_DEVICE(0x10DE, 0x03EF),
5881 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5882 },
5883 { /* MCP65 Ethernet Controller */
5884 PCI_DEVICE(0x10DE, 0x0450),
5885 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5886 },
5887 { /* MCP65 Ethernet Controller */
5888 PCI_DEVICE(0x10DE, 0x0451),
5889 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5890 },
5891 { /* MCP65 Ethernet Controller */
5892 PCI_DEVICE(0x10DE, 0x0452),
5893 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5894 },
5895 { /* MCP65 Ethernet Controller */
5896 PCI_DEVICE(0x10DE, 0x0453),
5897 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5898 },
5899 { /* MCP67 Ethernet Controller */
5900 PCI_DEVICE(0x10DE, 0x054C),
5901 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5902 },
5903 { /* MCP67 Ethernet Controller */
5904 PCI_DEVICE(0x10DE, 0x054D),
5905 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5906 },
5907 { /* MCP67 Ethernet Controller */
5908 PCI_DEVICE(0x10DE, 0x054E),
5909 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5910 },
5911 { /* MCP67 Ethernet Controller */
5912 PCI_DEVICE(0x10DE, 0x054F),
5913 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5914 },
5915 { /* MCP73 Ethernet Controller */
5916 PCI_DEVICE(0x10DE, 0x07DC),
5917 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5918 },
5919 { /* MCP73 Ethernet Controller */
5920 PCI_DEVICE(0x10DE, 0x07DD),
5921 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5922 },
5923 { /* MCP73 Ethernet Controller */
5924 PCI_DEVICE(0x10DE, 0x07DE),
5925 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5926 },
5927 { /* MCP73 Ethernet Controller */
5928 PCI_DEVICE(0x10DE, 0x07DF),
5929 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5930 },
5931 { /* MCP77 Ethernet Controller */
5932 PCI_DEVICE(0x10DE, 0x0760),
5933 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5934 },
5935 { /* MCP77 Ethernet Controller */
5936 PCI_DEVICE(0x10DE, 0x0761),
5937 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5938 },
5939 { /* MCP77 Ethernet Controller */
5940 PCI_DEVICE(0x10DE, 0x0762),
5941 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5942 },
5943 { /* MCP77 Ethernet Controller */
5944 PCI_DEVICE(0x10DE, 0x0763),
5945 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5946 },
5947 { /* MCP79 Ethernet Controller */
5948 PCI_DEVICE(0x10DE, 0x0AB0),
5949 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5950 },
5951 { /* MCP79 Ethernet Controller */
5952 PCI_DEVICE(0x10DE, 0x0AB1),
5953 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5954 },
5955 { /* MCP79 Ethernet Controller */
5956 PCI_DEVICE(0x10DE, 0x0AB2),
5957 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5958 },
5959 { /* MCP79 Ethernet Controller */
5960 PCI_DEVICE(0x10DE, 0x0AB3),
5961 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5962 },
5963 { /* MCP89 Ethernet Controller */
5964 PCI_DEVICE(0x10DE, 0x0D7D),
5965 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5966 },
5967 {0,},
5968 };
5969
5970 static struct pci_driver driver = {
5971 .name = DRV_NAME,
5972 .id_table = pci_tbl,
5973 .probe = nv_probe,
5974 .remove = __devexit_p(nv_remove),
5975 .shutdown = nv_shutdown,
5976 .driver.pm = NV_PM_OPS,
5977 };
5978
5979 static int __init init_nic(void)
5980 {
5981 return pci_register_driver(&driver);
5982 }
5983
5984 static void __exit exit_nic(void)
5985 {
5986 pci_unregister_driver(&driver);
5987 }
5988
5989 module_param(max_interrupt_work, int, 0);
5990 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5991 module_param(optimization_mode, int, 0);
5992 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
5993 module_param(poll_interval, int, 0);
5994 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5995 module_param(msi, int, 0);
5996 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5997 module_param(msix, int, 0);
5998 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5999 module_param(dma_64bit, int, 0);
6000 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6001 module_param(phy_cross, int, 0);
6002 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6003 module_param(phy_power_down, int, 0);
6004 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6005
6006 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6007 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6008 MODULE_LICENSE("GPL");
6009
6010 MODULE_DEVICE_TABLE(pci, pci_tbl);
6011
6012 module_init(init_nic);
6013 module_exit(exit_nic);
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