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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / sh_eth.c
blob190f619e4215614eae66c3721640805f1d0e7378
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/cache.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/slab.h>
36 #include <linux/ethtool.h>
37
38 #include "sh_eth.h"
39
40 #define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device *ndev)
50 {
51 struct sh_eth_private *mdp = netdev_priv(ndev);
52
53 if (mdp->duplex) /* Full */
54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
55 else /* Half */
56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
57 }
58
59 static void sh_eth_set_rate(struct net_device *ndev)
60 {
61 struct sh_eth_private *mdp = netdev_priv(ndev);
62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
66 break;
67 case 100:/* 100BASE */
68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
69 break;
70 default:
71 break;
72 }
73 }
74
75 /* SH7724 */
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
95 };
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_HAS_BOTH_MODULES 1
98 #define SH_ETH_HAS_TSU 1
99 static void sh_eth_set_duplex(struct net_device *ndev)
100 {
101 struct sh_eth_private *mdp = netdev_priv(ndev);
102
103 if (mdp->duplex) /* Full */
104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
105 else /* Half */
106 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
107 }
108
109 static void sh_eth_set_rate(struct net_device *ndev)
110 {
111 struct sh_eth_private *mdp = netdev_priv(ndev);
112
113 switch (mdp->speed) {
114 case 10: /* 10BASE */
115 sh_eth_write(ndev, 0, RTRATE);
116 break;
117 case 100:/* 100BASE */
118 sh_eth_write(ndev, 1, RTRATE);
119 break;
120 default:
121 break;
122 }
123 }
124
125 /* SH7757 */
126 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
127 .set_duplex = sh_eth_set_duplex,
128 .set_rate = sh_eth_set_rate,
129
130 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
131 .rmcr_value = 0x00000001,
132
133 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
134 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
135 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
136 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
137
138 .apr = 1,
139 .mpr = 1,
140 .tpauser = 1,
141 .hw_swap = 1,
142 .no_ade = 1,
143 .rpadir = 1,
144 .rpadir_value = 2 << 16,
145 };
146
147 #define SH_GIGA_ETH_BASE 0xfee00000
148 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
149 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
150 static void sh_eth_chip_reset_giga(struct net_device *ndev)
151 {
152 int i;
153 unsigned long mahr[2], malr[2];
154
155 /* save MAHR and MALR */
156 for (i = 0; i < 2; i++) {
157 malr[i] = readl(GIGA_MALR(i));
158 mahr[i] = readl(GIGA_MAHR(i));
159 }
160
161 /* reset device */
162 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
163 mdelay(1);
164
165 /* restore MAHR and MALR */
166 for (i = 0; i < 2; i++) {
167 writel(malr[i], GIGA_MALR(i));
168 writel(mahr[i], GIGA_MAHR(i));
169 }
170 }
171
172 static int sh_eth_is_gether(struct sh_eth_private *mdp);
173 static void sh_eth_reset(struct net_device *ndev)
174 {
175 struct sh_eth_private *mdp = netdev_priv(ndev);
176 int cnt = 100;
177
178 if (sh_eth_is_gether(mdp)) {
179 sh_eth_write(ndev, 0x03, EDSR);
180 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
181 EDMR);
182 while (cnt > 0) {
183 if (!(sh_eth_read(ndev, EDMR) & 0x3))
184 break;
185 mdelay(1);
186 cnt--;
187 }
188 if (cnt < 0)
189 printk(KERN_ERR "Device reset fail\n");
190
191 /* Table Init */
192 sh_eth_write(ndev, 0x0, TDLAR);
193 sh_eth_write(ndev, 0x0, TDFAR);
194 sh_eth_write(ndev, 0x0, TDFXR);
195 sh_eth_write(ndev, 0x0, TDFFR);
196 sh_eth_write(ndev, 0x0, RDLAR);
197 sh_eth_write(ndev, 0x0, RDFAR);
198 sh_eth_write(ndev, 0x0, RDFXR);
199 sh_eth_write(ndev, 0x0, RDFFR);
200 } else {
201 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
202 EDMR);
203 mdelay(3);
204 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
205 EDMR);
206 }
207 }
208
209 static void sh_eth_set_duplex_giga(struct net_device *ndev)
210 {
211 struct sh_eth_private *mdp = netdev_priv(ndev);
212
213 if (mdp->duplex) /* Full */
214 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
215 else /* Half */
216 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
217 }
218
219 static void sh_eth_set_rate_giga(struct net_device *ndev)
220 {
221 struct sh_eth_private *mdp = netdev_priv(ndev);
222
223 switch (mdp->speed) {
224 case 10: /* 10BASE */
225 sh_eth_write(ndev, 0x00000000, GECMR);
226 break;
227 case 100:/* 100BASE */
228 sh_eth_write(ndev, 0x00000010, GECMR);
229 break;
230 case 1000: /* 1000BASE */
231 sh_eth_write(ndev, 0x00000020, GECMR);
232 break;
233 default:
234 break;
235 }
236 }
237
238 /* SH7757(GETHERC) */
239 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
240 .chip_reset = sh_eth_chip_reset_giga,
241 .set_duplex = sh_eth_set_duplex_giga,
242 .set_rate = sh_eth_set_rate_giga,
243
244 .ecsr_value = ECSR_ICD | ECSR_MPD,
245 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
246 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
247
248 .tx_check = EESR_TC1 | EESR_FTC,
249 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
250 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
251 EESR_ECI,
252 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
253 EESR_TFE,
254 .fdr_value = 0x0000072f,
255 .rmcr_value = 0x00000001,
256
257 .apr = 1,
258 .mpr = 1,
259 .tpauser = 1,
260 .bculr = 1,
261 .hw_swap = 1,
262 .rpadir = 1,
263 .rpadir_value = 2 << 16,
264 .no_trimd = 1,
265 .no_ade = 1,
266 };
267
268 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
269 {
270 if (sh_eth_is_gether(mdp))
271 return &sh_eth_my_cpu_data_giga;
272 else
273 return &sh_eth_my_cpu_data;
274 }
275
276 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
277 #define SH_ETH_HAS_TSU 1
278 static void sh_eth_chip_reset(struct net_device *ndev)
279 {
280 struct sh_eth_private *mdp = netdev_priv(ndev);
281
282 /* reset device */
283 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
284 mdelay(1);
285 }
286
287 static void sh_eth_reset(struct net_device *ndev)
288 {
289 int cnt = 100;
290
291 sh_eth_write(ndev, EDSR_ENALL, EDSR);
292 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
293 while (cnt > 0) {
294 if (!(sh_eth_read(ndev, EDMR) & 0x3))
295 break;
296 mdelay(1);
297 cnt--;
298 }
299 if (cnt == 0)
300 printk(KERN_ERR "Device reset fail\n");
301
302 /* Table Init */
303 sh_eth_write(ndev, 0x0, TDLAR);
304 sh_eth_write(ndev, 0x0, TDFAR);
305 sh_eth_write(ndev, 0x0, TDFXR);
306 sh_eth_write(ndev, 0x0, TDFFR);
307 sh_eth_write(ndev, 0x0, RDLAR);
308 sh_eth_write(ndev, 0x0, RDFAR);
309 sh_eth_write(ndev, 0x0, RDFXR);
310 sh_eth_write(ndev, 0x0, RDFFR);
311 }
312
313 static void sh_eth_set_duplex(struct net_device *ndev)
314 {
315 struct sh_eth_private *mdp = netdev_priv(ndev);
316
317 if (mdp->duplex) /* Full */
318 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
319 else /* Half */
320 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
321 }
322
323 static void sh_eth_set_rate(struct net_device *ndev)
324 {
325 struct sh_eth_private *mdp = netdev_priv(ndev);
326
327 switch (mdp->speed) {
328 case 10: /* 10BASE */
329 sh_eth_write(ndev, GECMR_10, GECMR);
330 break;
331 case 100:/* 100BASE */
332 sh_eth_write(ndev, GECMR_100, GECMR);
333 break;
334 case 1000: /* 1000BASE */
335 sh_eth_write(ndev, GECMR_1000, GECMR);
336 break;
337 default:
338 break;
339 }
340 }
341
342 /* sh7763 */
343 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
344 .chip_reset = sh_eth_chip_reset,
345 .set_duplex = sh_eth_set_duplex,
346 .set_rate = sh_eth_set_rate,
347
348 .ecsr_value = ECSR_ICD | ECSR_MPD,
349 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
350 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
351
352 .tx_check = EESR_TC1 | EESR_FTC,
353 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
354 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
355 EESR_ECI,
356 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
357 EESR_TFE,
358
359 .apr = 1,
360 .mpr = 1,
361 .tpauser = 1,
362 .bculr = 1,
363 .hw_swap = 1,
364 .no_trimd = 1,
365 .no_ade = 1,
366 .tsu = 1,
367 };
368
369 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
370 #define SH_ETH_RESET_DEFAULT 1
371 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
372 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
373
374 .apr = 1,
375 .mpr = 1,
376 .tpauser = 1,
377 .hw_swap = 1,
378 };
379 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
380 #define SH_ETH_RESET_DEFAULT 1
381 #define SH_ETH_HAS_TSU 1
382 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
383 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
384 .tsu = 1,
385 };
386 #endif
387
388 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
389 {
390 if (!cd->ecsr_value)
391 cd->ecsr_value = DEFAULT_ECSR_INIT;
392
393 if (!cd->ecsipr_value)
394 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
395
396 if (!cd->fcftr_value)
397 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
398 DEFAULT_FIFO_F_D_RFD;
399
400 if (!cd->fdr_value)
401 cd->fdr_value = DEFAULT_FDR_INIT;
402
403 if (!cd->rmcr_value)
404 cd->rmcr_value = DEFAULT_RMCR_VALUE;
405
406 if (!cd->tx_check)
407 cd->tx_check = DEFAULT_TX_CHECK;
408
409 if (!cd->eesr_err_check)
410 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
411
412 if (!cd->tx_error_check)
413 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
414 }
415
416 #if defined(SH_ETH_RESET_DEFAULT)
417 /* Chip Reset */
418 static void sh_eth_reset(struct net_device *ndev)
419 {
420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
421 mdelay(3);
422 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
423 }
424 #endif
425
426 #if defined(CONFIG_CPU_SH4)
427 static void sh_eth_set_receive_align(struct sk_buff *skb)
428 {
429 int reserve;
430
431 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
432 if (reserve)
433 skb_reserve(skb, reserve);
434 }
435 #else
436 static void sh_eth_set_receive_align(struct sk_buff *skb)
437 {
438 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
439 }
440 #endif
441
442
443 /* CPU <-> EDMAC endian convert */
444 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
445 {
446 switch (mdp->edmac_endian) {
447 case EDMAC_LITTLE_ENDIAN:
448 return cpu_to_le32(x);
449 case EDMAC_BIG_ENDIAN:
450 return cpu_to_be32(x);
451 }
452 return x;
453 }
454
455 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
456 {
457 switch (mdp->edmac_endian) {
458 case EDMAC_LITTLE_ENDIAN:
459 return le32_to_cpu(x);
460 case EDMAC_BIG_ENDIAN:
461 return be32_to_cpu(x);
462 }
463 return x;
464 }
465
466 /*
467 * Program the hardware MAC address from dev->dev_addr.
468 */
469 static void update_mac_address(struct net_device *ndev)
470 {
471 sh_eth_write(ndev,
472 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
473 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
474 sh_eth_write(ndev,
475 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
476 }
477
478 /*
479 * Get MAC address from SuperH MAC address register
480 *
481 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
482 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
483 * When you want use this device, you must set MAC address in bootloader.
484 *
485 */
486 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
487 {
488 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
489 memcpy(ndev->dev_addr, mac, 6);
490 } else {
491 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
492 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
493 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
494 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
495 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
496 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
497 }
498 }
499
500 static int sh_eth_is_gether(struct sh_eth_private *mdp)
501 {
502 if (mdp->reg_offset == sh_eth_offset_gigabit)
503 return 1;
504 else
505 return 0;
506 }
507
508 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
509 {
510 if (sh_eth_is_gether(mdp))
511 return EDTRR_TRNS_GETHER;
512 else
513 return EDTRR_TRNS_ETHER;
514 }
515
516 struct bb_info {
517 void (*set_gate)(unsigned long addr);
518 struct mdiobb_ctrl ctrl;
519 u32 addr;
520 u32 mmd_msk;/* MMD */
521 u32 mdo_msk;
522 u32 mdi_msk;
523 u32 mdc_msk;
524 };
525
526 /* PHY bit set */
527 static void bb_set(u32 addr, u32 msk)
528 {
529 writel(readl(addr) | msk, addr);
530 }
531
532 /* PHY bit clear */
533 static void bb_clr(u32 addr, u32 msk)
534 {
535 writel((readl(addr) & ~msk), addr);
536 }
537
538 /* PHY bit read */
539 static int bb_read(u32 addr, u32 msk)
540 {
541 return (readl(addr) & msk) != 0;
542 }
543
544 /* Data I/O pin control */
545 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
546 {
547 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
548
549 if (bitbang->set_gate)
550 bitbang->set_gate(bitbang->addr);
551
552 if (bit)
553 bb_set(bitbang->addr, bitbang->mmd_msk);
554 else
555 bb_clr(bitbang->addr, bitbang->mmd_msk);
556 }
557
558 /* Set bit data*/
559 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
560 {
561 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
562
563 if (bitbang->set_gate)
564 bitbang->set_gate(bitbang->addr);
565
566 if (bit)
567 bb_set(bitbang->addr, bitbang->mdo_msk);
568 else
569 bb_clr(bitbang->addr, bitbang->mdo_msk);
570 }
571
572 /* Get bit data*/
573 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
574 {
575 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
576
577 if (bitbang->set_gate)
578 bitbang->set_gate(bitbang->addr);
579
580 return bb_read(bitbang->addr, bitbang->mdi_msk);
581 }
582
583 /* MDC pin control */
584 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
585 {
586 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
587
588 if (bitbang->set_gate)
589 bitbang->set_gate(bitbang->addr);
590
591 if (bit)
592 bb_set(bitbang->addr, bitbang->mdc_msk);
593 else
594 bb_clr(bitbang->addr, bitbang->mdc_msk);
595 }
596
597 /* mdio bus control struct */
598 static struct mdiobb_ops bb_ops = {
599 .owner = THIS_MODULE,
600 .set_mdc = sh_mdc_ctrl,
601 .set_mdio_dir = sh_mmd_ctrl,
602 .set_mdio_data = sh_set_mdio,
603 .get_mdio_data = sh_get_mdio,
604 };
605
606 /* free skb and descriptor buffer */
607 static void sh_eth_ring_free(struct net_device *ndev)
608 {
609 struct sh_eth_private *mdp = netdev_priv(ndev);
610 int i;
611
612 /* Free Rx skb ringbuffer */
613 if (mdp->rx_skbuff) {
614 for (i = 0; i < RX_RING_SIZE; i++) {
615 if (mdp->rx_skbuff[i])
616 dev_kfree_skb(mdp->rx_skbuff[i]);
617 }
618 }
619 kfree(mdp->rx_skbuff);
620
621 /* Free Tx skb ringbuffer */
622 if (mdp->tx_skbuff) {
623 for (i = 0; i < TX_RING_SIZE; i++) {
624 if (mdp->tx_skbuff[i])
625 dev_kfree_skb(mdp->tx_skbuff[i]);
626 }
627 }
628 kfree(mdp->tx_skbuff);
629 }
630
631 /* format skb and descriptor buffer */
632 static void sh_eth_ring_format(struct net_device *ndev)
633 {
634 struct sh_eth_private *mdp = netdev_priv(ndev);
635 int i;
636 struct sk_buff *skb;
637 struct sh_eth_rxdesc *rxdesc = NULL;
638 struct sh_eth_txdesc *txdesc = NULL;
639 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
640 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
641
642 mdp->cur_rx = mdp->cur_tx = 0;
643 mdp->dirty_rx = mdp->dirty_tx = 0;
644
645 memset(mdp->rx_ring, 0, rx_ringsize);
646
647 /* build Rx ring buffer */
648 for (i = 0; i < RX_RING_SIZE; i++) {
649 /* skb */
650 mdp->rx_skbuff[i] = NULL;
651 skb = dev_alloc_skb(mdp->rx_buf_sz);
652 mdp->rx_skbuff[i] = skb;
653 if (skb == NULL)
654 break;
655 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
656 DMA_FROM_DEVICE);
657 skb->dev = ndev; /* Mark as being used by this device. */
658 sh_eth_set_receive_align(skb);
659
660 /* RX descriptor */
661 rxdesc = &mdp->rx_ring[i];
662 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
663 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
664
665 /* The size of the buffer is 16 byte boundary. */
666 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
667 /* Rx descriptor address set */
668 if (i == 0) {
669 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
670 if (sh_eth_is_gether(mdp))
671 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
672 }
673 }
674
675 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
676
677 /* Mark the last entry as wrapping the ring. */
678 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
679
680 memset(mdp->tx_ring, 0, tx_ringsize);
681
682 /* build Tx ring buffer */
683 for (i = 0; i < TX_RING_SIZE; i++) {
684 mdp->tx_skbuff[i] = NULL;
685 txdesc = &mdp->tx_ring[i];
686 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
687 txdesc->buffer_length = 0;
688 if (i == 0) {
689 /* Tx descriptor address set */
690 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
691 if (sh_eth_is_gether(mdp))
692 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
693 }
694 }
695
696 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
697 }
698
699 /* Get skb and descriptor buffer */
700 static int sh_eth_ring_init(struct net_device *ndev)
701 {
702 struct sh_eth_private *mdp = netdev_priv(ndev);
703 int rx_ringsize, tx_ringsize, ret = 0;
704
705 /*
706 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
707 * card needs room to do 8 byte alignment, +2 so we can reserve
708 * the first 2 bytes, and +16 gets room for the status word from the
709 * card.
710 */
711 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
712 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
713 if (mdp->cd->rpadir)
714 mdp->rx_buf_sz += NET_IP_ALIGN;
715
716 /* Allocate RX and TX skb rings */
717 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
718 GFP_KERNEL);
719 if (!mdp->rx_skbuff) {
720 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
721 ret = -ENOMEM;
722 return ret;
723 }
724
725 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
726 GFP_KERNEL);
727 if (!mdp->tx_skbuff) {
728 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
729 ret = -ENOMEM;
730 goto skb_ring_free;
731 }
732
733 /* Allocate all Rx descriptors. */
734 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
735 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
736 GFP_KERNEL);
737
738 if (!mdp->rx_ring) {
739 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
740 rx_ringsize);
741 ret = -ENOMEM;
742 goto desc_ring_free;
743 }
744
745 mdp->dirty_rx = 0;
746
747 /* Allocate all Tx descriptors. */
748 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
749 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
750 GFP_KERNEL);
751 if (!mdp->tx_ring) {
752 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
753 tx_ringsize);
754 ret = -ENOMEM;
755 goto desc_ring_free;
756 }
757 return ret;
758
759 desc_ring_free:
760 /* free DMA buffer */
761 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
762
763 skb_ring_free:
764 /* Free Rx and Tx skb ring buffer */
765 sh_eth_ring_free(ndev);
766
767 return ret;
768 }
769
770 static int sh_eth_dev_init(struct net_device *ndev)
771 {
772 int ret = 0;
773 struct sh_eth_private *mdp = netdev_priv(ndev);
774 u_int32_t rx_int_var, tx_int_var;
775 u32 val;
776
777 /* Soft Reset */
778 sh_eth_reset(ndev);
779
780 /* Descriptor format */
781 sh_eth_ring_format(ndev);
782 if (mdp->cd->rpadir)
783 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
784
785 /* all sh_eth int mask */
786 sh_eth_write(ndev, 0, EESIPR);
787
788 #if defined(__LITTLE_ENDIAN__)
789 if (mdp->cd->hw_swap)
790 sh_eth_write(ndev, EDMR_EL, EDMR);
791 else
792 #endif
793 sh_eth_write(ndev, 0, EDMR);
794
795 /* FIFO size set */
796 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
797 sh_eth_write(ndev, 0, TFTR);
798
799 /* Frame recv control */
800 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
801
802 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
803 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
804 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
805
806 if (mdp->cd->bculr)
807 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
808
809 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
810
811 if (!mdp->cd->no_trimd)
812 sh_eth_write(ndev, 0, TRIMD);
813
814 /* Recv frame limit set register */
815 sh_eth_write(ndev, RFLR_VALUE, RFLR);
816
817 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
818 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
819
820 /* PAUSE Prohibition */
821 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
822 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
823
824 sh_eth_write(ndev, val, ECMR);
825
826 if (mdp->cd->set_rate)
827 mdp->cd->set_rate(ndev);
828
829 /* E-MAC Status Register clear */
830 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
831
832 /* E-MAC Interrupt Enable register */
833 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
834
835 /* Set MAC address */
836 update_mac_address(ndev);
837
838 /* mask reset */
839 if (mdp->cd->apr)
840 sh_eth_write(ndev, APR_AP, APR);
841 if (mdp->cd->mpr)
842 sh_eth_write(ndev, MPR_MP, MPR);
843 if (mdp->cd->tpauser)
844 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
845
846 /* Setting the Rx mode will start the Rx process. */
847 sh_eth_write(ndev, EDRRR_R, EDRRR);
848
849 netif_start_queue(ndev);
850
851 return ret;
852 }
853
854 /* free Tx skb function */
855 static int sh_eth_txfree(struct net_device *ndev)
856 {
857 struct sh_eth_private *mdp = netdev_priv(ndev);
858 struct sh_eth_txdesc *txdesc;
859 int freeNum = 0;
860 int entry = 0;
861
862 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
863 entry = mdp->dirty_tx % TX_RING_SIZE;
864 txdesc = &mdp->tx_ring[entry];
865 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
866 break;
867 /* Free the original skb. */
868 if (mdp->tx_skbuff[entry]) {
869 dma_unmap_single(&ndev->dev, txdesc->addr,
870 txdesc->buffer_length, DMA_TO_DEVICE);
871 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
872 mdp->tx_skbuff[entry] = NULL;
873 freeNum++;
874 }
875 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
876 if (entry >= TX_RING_SIZE - 1)
877 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
878
879 mdp->stats.tx_packets++;
880 mdp->stats.tx_bytes += txdesc->buffer_length;
881 }
882 return freeNum;
883 }
884
885 /* Packet receive function */
886 static int sh_eth_rx(struct net_device *ndev)
887 {
888 struct sh_eth_private *mdp = netdev_priv(ndev);
889 struct sh_eth_rxdesc *rxdesc;
890
891 int entry = mdp->cur_rx % RX_RING_SIZE;
892 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
893 struct sk_buff *skb;
894 u16 pkt_len = 0;
895 u32 desc_status;
896
897 rxdesc = &mdp->rx_ring[entry];
898 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
899 desc_status = edmac_to_cpu(mdp, rxdesc->status);
900 pkt_len = rxdesc->frame_length;
901
902 if (--boguscnt < 0)
903 break;
904
905 if (!(desc_status & RDFEND))
906 mdp->stats.rx_length_errors++;
907
908 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
909 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
910 mdp->stats.rx_errors++;
911 if (desc_status & RD_RFS1)
912 mdp->stats.rx_crc_errors++;
913 if (desc_status & RD_RFS2)
914 mdp->stats.rx_frame_errors++;
915 if (desc_status & RD_RFS3)
916 mdp->stats.rx_length_errors++;
917 if (desc_status & RD_RFS4)
918 mdp->stats.rx_length_errors++;
919 if (desc_status & RD_RFS6)
920 mdp->stats.rx_missed_errors++;
921 if (desc_status & RD_RFS10)
922 mdp->stats.rx_over_errors++;
923 } else {
924 if (!mdp->cd->hw_swap)
925 sh_eth_soft_swap(
926 phys_to_virt(ALIGN(rxdesc->addr, 4)),
927 pkt_len + 2);
928 skb = mdp->rx_skbuff[entry];
929 mdp->rx_skbuff[entry] = NULL;
930 if (mdp->cd->rpadir)
931 skb_reserve(skb, NET_IP_ALIGN);
932 skb_put(skb, pkt_len);
933 skb->protocol = eth_type_trans(skb, ndev);
934 netif_rx(skb);
935 mdp->stats.rx_packets++;
936 mdp->stats.rx_bytes += pkt_len;
937 }
938 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
939 entry = (++mdp->cur_rx) % RX_RING_SIZE;
940 rxdesc = &mdp->rx_ring[entry];
941 }
942
943 /* Refill the Rx ring buffers. */
944 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
945 entry = mdp->dirty_rx % RX_RING_SIZE;
946 rxdesc = &mdp->rx_ring[entry];
947 /* The size of the buffer is 16 byte boundary. */
948 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
949
950 if (mdp->rx_skbuff[entry] == NULL) {
951 skb = dev_alloc_skb(mdp->rx_buf_sz);
952 mdp->rx_skbuff[entry] = skb;
953 if (skb == NULL)
954 break; /* Better luck next round. */
955 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
956 DMA_FROM_DEVICE);
957 skb->dev = ndev;
958 sh_eth_set_receive_align(skb);
959
960 skb_checksum_none_assert(skb);
961 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
962 }
963 if (entry >= RX_RING_SIZE - 1)
964 rxdesc->status |=
965 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
966 else
967 rxdesc->status |=
968 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
969 }
970
971 /* Restart Rx engine if stopped. */
972 /* If we don't need to check status, don't. -KDU */
973 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
974 sh_eth_write(ndev, EDRRR_R, EDRRR);
975
976 return 0;
977 }
978
979 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
980 {
981 /* disable tx and rx */
982 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
983 ~(ECMR_RE | ECMR_TE), ECMR);
984 }
985
986 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
987 {
988 /* enable tx and rx */
989 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
990 (ECMR_RE | ECMR_TE), ECMR);
991 }
992
993 /* error control function */
994 static void sh_eth_error(struct net_device *ndev, int intr_status)
995 {
996 struct sh_eth_private *mdp = netdev_priv(ndev);
997 u32 felic_stat;
998 u32 link_stat;
999 u32 mask;
1000
1001 if (intr_status & EESR_ECI) {
1002 felic_stat = sh_eth_read(ndev, ECSR);
1003 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1004 if (felic_stat & ECSR_ICD)
1005 mdp->stats.tx_carrier_errors++;
1006 if (felic_stat & ECSR_LCHNG) {
1007 /* Link Changed */
1008 if (mdp->cd->no_psr || mdp->no_ether_link) {
1009 if (mdp->link == PHY_DOWN)
1010 link_stat = 0;
1011 else
1012 link_stat = PHY_ST_LINK;
1013 } else {
1014 link_stat = (sh_eth_read(ndev, PSR));
1015 if (mdp->ether_link_active_low)
1016 link_stat = ~link_stat;
1017 }
1018 if (!(link_stat & PHY_ST_LINK))
1019 sh_eth_rcv_snd_disable(ndev);
1020 else {
1021 /* Link Up */
1022 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1023 ~DMAC_M_ECI, EESIPR);
1024 /*clear int */
1025 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1026 ECSR);
1027 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1028 DMAC_M_ECI, EESIPR);
1029 /* enable tx and rx */
1030 sh_eth_rcv_snd_enable(ndev);
1031 }
1032 }
1033 }
1034
1035 if (intr_status & EESR_TWB) {
1036 /* Write buck end. unused write back interrupt */
1037 if (intr_status & EESR_TABT) /* Transmit Abort int */
1038 mdp->stats.tx_aborted_errors++;
1039 if (netif_msg_tx_err(mdp))
1040 dev_err(&ndev->dev, "Transmit Abort\n");
1041 }
1042
1043 if (intr_status & EESR_RABT) {
1044 /* Receive Abort int */
1045 if (intr_status & EESR_RFRMER) {
1046 /* Receive Frame Overflow int */
1047 mdp->stats.rx_frame_errors++;
1048 if (netif_msg_rx_err(mdp))
1049 dev_err(&ndev->dev, "Receive Abort\n");
1050 }
1051 }
1052
1053 if (intr_status & EESR_TDE) {
1054 /* Transmit Descriptor Empty int */
1055 mdp->stats.tx_fifo_errors++;
1056 if (netif_msg_tx_err(mdp))
1057 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1058 }
1059
1060 if (intr_status & EESR_TFE) {
1061 /* FIFO under flow */
1062 mdp->stats.tx_fifo_errors++;
1063 if (netif_msg_tx_err(mdp))
1064 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1065 }
1066
1067 if (intr_status & EESR_RDE) {
1068 /* Receive Descriptor Empty int */
1069 mdp->stats.rx_over_errors++;
1070
1071 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1072 sh_eth_write(ndev, EDRRR_R, EDRRR);
1073 if (netif_msg_rx_err(mdp))
1074 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1075 }
1076
1077 if (intr_status & EESR_RFE) {
1078 /* Receive FIFO Overflow int */
1079 mdp->stats.rx_fifo_errors++;
1080 if (netif_msg_rx_err(mdp))
1081 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1082 }
1083
1084 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1085 /* Address Error */
1086 mdp->stats.tx_fifo_errors++;
1087 if (netif_msg_tx_err(mdp))
1088 dev_err(&ndev->dev, "Address Error\n");
1089 }
1090
1091 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1092 if (mdp->cd->no_ade)
1093 mask &= ~EESR_ADE;
1094 if (intr_status & mask) {
1095 /* Tx error */
1096 u32 edtrr = sh_eth_read(ndev, EDTRR);
1097 /* dmesg */
1098 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1099 intr_status, mdp->cur_tx);
1100 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1101 mdp->dirty_tx, (u32) ndev->state, edtrr);
1102 /* dirty buffer free */
1103 sh_eth_txfree(ndev);
1104
1105 /* SH7712 BUG */
1106 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1107 /* tx dma start */
1108 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1109 }
1110 /* wakeup */
1111 netif_wake_queue(ndev);
1112 }
1113 }
1114
1115 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1116 {
1117 struct net_device *ndev = netdev;
1118 struct sh_eth_private *mdp = netdev_priv(ndev);
1119 struct sh_eth_cpu_data *cd = mdp->cd;
1120 irqreturn_t ret = IRQ_NONE;
1121 u32 intr_status = 0;
1122
1123 spin_lock(&mdp->lock);
1124
1125 /* Get interrpt stat */
1126 intr_status = sh_eth_read(ndev, EESR);
1127 /* Clear interrupt */
1128 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1129 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1130 cd->tx_check | cd->eesr_err_check)) {
1131 sh_eth_write(ndev, intr_status, EESR);
1132 ret = IRQ_HANDLED;
1133 } else
1134 goto other_irq;
1135
1136 if (intr_status & (EESR_FRC | /* Frame recv*/
1137 EESR_RMAF | /* Multi cast address recv*/
1138 EESR_RRF | /* Bit frame recv */
1139 EESR_RTLF | /* Long frame recv*/
1140 EESR_RTSF | /* short frame recv */
1141 EESR_PRE | /* PHY-LSI recv error */
1142 EESR_CERF)){ /* recv frame CRC error */
1143 sh_eth_rx(ndev);
1144 }
1145
1146 /* Tx Check */
1147 if (intr_status & cd->tx_check) {
1148 sh_eth_txfree(ndev);
1149 netif_wake_queue(ndev);
1150 }
1151
1152 if (intr_status & cd->eesr_err_check)
1153 sh_eth_error(ndev, intr_status);
1154
1155 other_irq:
1156 spin_unlock(&mdp->lock);
1157
1158 return ret;
1159 }
1160
1161 static void sh_eth_timer(unsigned long data)
1162 {
1163 struct net_device *ndev = (struct net_device *)data;
1164 struct sh_eth_private *mdp = netdev_priv(ndev);
1165
1166 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1167 }
1168
1169 /* PHY state control function */
1170 static void sh_eth_adjust_link(struct net_device *ndev)
1171 {
1172 struct sh_eth_private *mdp = netdev_priv(ndev);
1173 struct phy_device *phydev = mdp->phydev;
1174 int new_state = 0;
1175
1176 if (phydev->link != PHY_DOWN) {
1177 if (phydev->duplex != mdp->duplex) {
1178 new_state = 1;
1179 mdp->duplex = phydev->duplex;
1180 if (mdp->cd->set_duplex)
1181 mdp->cd->set_duplex(ndev);
1182 }
1183
1184 if (phydev->speed != mdp->speed) {
1185 new_state = 1;
1186 mdp->speed = phydev->speed;
1187 if (mdp->cd->set_rate)
1188 mdp->cd->set_rate(ndev);
1189 }
1190 if (mdp->link == PHY_DOWN) {
1191 sh_eth_write(ndev,
1192 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1193 new_state = 1;
1194 mdp->link = phydev->link;
1195 }
1196 } else if (mdp->link) {
1197 new_state = 1;
1198 mdp->link = PHY_DOWN;
1199 mdp->speed = 0;
1200 mdp->duplex = -1;
1201 }
1202
1203 if (new_state && netif_msg_link(mdp))
1204 phy_print_status(phydev);
1205 }
1206
1207 /* PHY init function */
1208 static int sh_eth_phy_init(struct net_device *ndev)
1209 {
1210 struct sh_eth_private *mdp = netdev_priv(ndev);
1211 char phy_id[MII_BUS_ID_SIZE + 3];
1212 struct phy_device *phydev = NULL;
1213
1214 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1215 mdp->mii_bus->id , mdp->phy_id);
1216
1217 mdp->link = PHY_DOWN;
1218 mdp->speed = 0;
1219 mdp->duplex = -1;
1220
1221 /* Try connect to PHY */
1222 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1223 0, mdp->phy_interface);
1224 if (IS_ERR(phydev)) {
1225 dev_err(&ndev->dev, "phy_connect failed\n");
1226 return PTR_ERR(phydev);
1227 }
1228
1229 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1230 phydev->addr, phydev->drv->name);
1231
1232 mdp->phydev = phydev;
1233
1234 return 0;
1235 }
1236
1237 /* PHY control start function */
1238 static int sh_eth_phy_start(struct net_device *ndev)
1239 {
1240 struct sh_eth_private *mdp = netdev_priv(ndev);
1241 int ret;
1242
1243 ret = sh_eth_phy_init(ndev);
1244 if (ret)
1245 return ret;
1246
1247 /* reset phy - this also wakes it from PDOWN */
1248 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1249 phy_start(mdp->phydev);
1250
1251 return 0;
1252 }
1253
1254 static int sh_eth_get_settings(struct net_device *ndev,
1255 struct ethtool_cmd *ecmd)
1256 {
1257 struct sh_eth_private *mdp = netdev_priv(ndev);
1258 unsigned long flags;
1259 int ret;
1260
1261 spin_lock_irqsave(&mdp->lock, flags);
1262 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1263 spin_unlock_irqrestore(&mdp->lock, flags);
1264
1265 return ret;
1266 }
1267
1268 static int sh_eth_set_settings(struct net_device *ndev,
1269 struct ethtool_cmd *ecmd)
1270 {
1271 struct sh_eth_private *mdp = netdev_priv(ndev);
1272 unsigned long flags;
1273 int ret;
1274
1275 spin_lock_irqsave(&mdp->lock, flags);
1276
1277 /* disable tx and rx */
1278 sh_eth_rcv_snd_disable(ndev);
1279
1280 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1281 if (ret)
1282 goto error_exit;
1283
1284 if (ecmd->duplex == DUPLEX_FULL)
1285 mdp->duplex = 1;
1286 else
1287 mdp->duplex = 0;
1288
1289 if (mdp->cd->set_duplex)
1290 mdp->cd->set_duplex(ndev);
1291
1292 error_exit:
1293 mdelay(1);
1294
1295 /* enable tx and rx */
1296 sh_eth_rcv_snd_enable(ndev);
1297
1298 spin_unlock_irqrestore(&mdp->lock, flags);
1299
1300 return ret;
1301 }
1302
1303 static int sh_eth_nway_reset(struct net_device *ndev)
1304 {
1305 struct sh_eth_private *mdp = netdev_priv(ndev);
1306 unsigned long flags;
1307 int ret;
1308
1309 spin_lock_irqsave(&mdp->lock, flags);
1310 ret = phy_start_aneg(mdp->phydev);
1311 spin_unlock_irqrestore(&mdp->lock, flags);
1312
1313 return ret;
1314 }
1315
1316 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1317 {
1318 struct sh_eth_private *mdp = netdev_priv(ndev);
1319 return mdp->msg_enable;
1320 }
1321
1322 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1323 {
1324 struct sh_eth_private *mdp = netdev_priv(ndev);
1325 mdp->msg_enable = value;
1326 }
1327
1328 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1329 "rx_current", "tx_current",
1330 "rx_dirty", "tx_dirty",
1331 };
1332 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1333
1334 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1335 {
1336 switch (sset) {
1337 case ETH_SS_STATS:
1338 return SH_ETH_STATS_LEN;
1339 default:
1340 return -EOPNOTSUPP;
1341 }
1342 }
1343
1344 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1345 struct ethtool_stats *stats, u64 *data)
1346 {
1347 struct sh_eth_private *mdp = netdev_priv(ndev);
1348 int i = 0;
1349
1350 /* device-specific stats */
1351 data[i++] = mdp->cur_rx;
1352 data[i++] = mdp->cur_tx;
1353 data[i++] = mdp->dirty_rx;
1354 data[i++] = mdp->dirty_tx;
1355 }
1356
1357 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1358 {
1359 switch (stringset) {
1360 case ETH_SS_STATS:
1361 memcpy(data, *sh_eth_gstrings_stats,
1362 sizeof(sh_eth_gstrings_stats));
1363 break;
1364 }
1365 }
1366
1367 static struct ethtool_ops sh_eth_ethtool_ops = {
1368 .get_settings = sh_eth_get_settings,
1369 .set_settings = sh_eth_set_settings,
1370 .nway_reset = sh_eth_nway_reset,
1371 .get_msglevel = sh_eth_get_msglevel,
1372 .set_msglevel = sh_eth_set_msglevel,
1373 .get_link = ethtool_op_get_link,
1374 .get_strings = sh_eth_get_strings,
1375 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1376 .get_sset_count = sh_eth_get_sset_count,
1377 };
1378
1379 /* network device open function */
1380 static int sh_eth_open(struct net_device *ndev)
1381 {
1382 int ret = 0;
1383 struct sh_eth_private *mdp = netdev_priv(ndev);
1384
1385 pm_runtime_get_sync(&mdp->pdev->dev);
1386
1387 ret = request_irq(ndev->irq, sh_eth_interrupt,
1388 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1389 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1390 defined(CONFIG_CPU_SUBTYPE_SH7757)
1391 IRQF_SHARED,
1392 #else
1393 0,
1394 #endif
1395 ndev->name, ndev);
1396 if (ret) {
1397 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1398 return ret;
1399 }
1400
1401 /* Descriptor set */
1402 ret = sh_eth_ring_init(ndev);
1403 if (ret)
1404 goto out_free_irq;
1405
1406 /* device init */
1407 ret = sh_eth_dev_init(ndev);
1408 if (ret)
1409 goto out_free_irq;
1410
1411 /* PHY control start*/
1412 ret = sh_eth_phy_start(ndev);
1413 if (ret)
1414 goto out_free_irq;
1415
1416 /* Set the timer to check for link beat. */
1417 init_timer(&mdp->timer);
1418 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1419 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1420
1421 return ret;
1422
1423 out_free_irq:
1424 free_irq(ndev->irq, ndev);
1425 pm_runtime_put_sync(&mdp->pdev->dev);
1426 return ret;
1427 }
1428
1429 /* Timeout function */
1430 static void sh_eth_tx_timeout(struct net_device *ndev)
1431 {
1432 struct sh_eth_private *mdp = netdev_priv(ndev);
1433 struct sh_eth_rxdesc *rxdesc;
1434 int i;
1435
1436 netif_stop_queue(ndev);
1437
1438 if (netif_msg_timer(mdp))
1439 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1440 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1441
1442 /* tx_errors count up */
1443 mdp->stats.tx_errors++;
1444
1445 /* timer off */
1446 del_timer_sync(&mdp->timer);
1447
1448 /* Free all the skbuffs in the Rx queue. */
1449 for (i = 0; i < RX_RING_SIZE; i++) {
1450 rxdesc = &mdp->rx_ring[i];
1451 rxdesc->status = 0;
1452 rxdesc->addr = 0xBADF00D0;
1453 if (mdp->rx_skbuff[i])
1454 dev_kfree_skb(mdp->rx_skbuff[i]);
1455 mdp->rx_skbuff[i] = NULL;
1456 }
1457 for (i = 0; i < TX_RING_SIZE; i++) {
1458 if (mdp->tx_skbuff[i])
1459 dev_kfree_skb(mdp->tx_skbuff[i]);
1460 mdp->tx_skbuff[i] = NULL;
1461 }
1462
1463 /* device init */
1464 sh_eth_dev_init(ndev);
1465
1466 /* timer on */
1467 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1468 add_timer(&mdp->timer);
1469 }
1470
1471 /* Packet transmit function */
1472 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1473 {
1474 struct sh_eth_private *mdp = netdev_priv(ndev);
1475 struct sh_eth_txdesc *txdesc;
1476 u32 entry;
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&mdp->lock, flags);
1480 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1481 if (!sh_eth_txfree(ndev)) {
1482 if (netif_msg_tx_queued(mdp))
1483 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1484 netif_stop_queue(ndev);
1485 spin_unlock_irqrestore(&mdp->lock, flags);
1486 return NETDEV_TX_BUSY;
1487 }
1488 }
1489 spin_unlock_irqrestore(&mdp->lock, flags);
1490
1491 entry = mdp->cur_tx % TX_RING_SIZE;
1492 mdp->tx_skbuff[entry] = skb;
1493 txdesc = &mdp->tx_ring[entry];
1494 /* soft swap. */
1495 if (!mdp->cd->hw_swap)
1496 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1497 skb->len + 2);
1498 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1499 DMA_TO_DEVICE);
1500 if (skb->len < ETHERSMALL)
1501 txdesc->buffer_length = ETHERSMALL;
1502 else
1503 txdesc->buffer_length = skb->len;
1504
1505 if (entry >= TX_RING_SIZE - 1)
1506 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1507 else
1508 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1509
1510 mdp->cur_tx++;
1511
1512 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1513 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1514
1515 return NETDEV_TX_OK;
1516 }
1517
1518 /* device close function */
1519 static int sh_eth_close(struct net_device *ndev)
1520 {
1521 struct sh_eth_private *mdp = netdev_priv(ndev);
1522 int ringsize;
1523
1524 netif_stop_queue(ndev);
1525
1526 /* Disable interrupts by clearing the interrupt mask. */
1527 sh_eth_write(ndev, 0x0000, EESIPR);
1528
1529 /* Stop the chip's Tx and Rx processes. */
1530 sh_eth_write(ndev, 0, EDTRR);
1531 sh_eth_write(ndev, 0, EDRRR);
1532
1533 /* PHY Disconnect */
1534 if (mdp->phydev) {
1535 phy_stop(mdp->phydev);
1536 phy_disconnect(mdp->phydev);
1537 }
1538
1539 free_irq(ndev->irq, ndev);
1540
1541 del_timer_sync(&mdp->timer);
1542
1543 /* Free all the skbuffs in the Rx queue. */
1544 sh_eth_ring_free(ndev);
1545
1546 /* free DMA buffer */
1547 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1548 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1549
1550 /* free DMA buffer */
1551 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1552 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1553
1554 pm_runtime_put_sync(&mdp->pdev->dev);
1555
1556 return 0;
1557 }
1558
1559 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1560 {
1561 struct sh_eth_private *mdp = netdev_priv(ndev);
1562
1563 pm_runtime_get_sync(&mdp->pdev->dev);
1564
1565 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1566 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1567 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1568 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1569 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1570 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1571 if (sh_eth_is_gether(mdp)) {
1572 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1573 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1574 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1575 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1576 } else {
1577 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1578 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1579 }
1580 pm_runtime_put_sync(&mdp->pdev->dev);
1581
1582 return &mdp->stats;
1583 }
1584
1585 /* ioctl to device funciotn*/
1586 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1587 int cmd)
1588 {
1589 struct sh_eth_private *mdp = netdev_priv(ndev);
1590 struct phy_device *phydev = mdp->phydev;
1591
1592 if (!netif_running(ndev))
1593 return -EINVAL;
1594
1595 if (!phydev)
1596 return -ENODEV;
1597
1598 return phy_mii_ioctl(phydev, rq, cmd);
1599 }
1600
1601 #if defined(SH_ETH_HAS_TSU)
1602 /* Multicast reception directions set */
1603 static void sh_eth_set_multicast_list(struct net_device *ndev)
1604 {
1605 if (ndev->flags & IFF_PROMISC) {
1606 /* Set promiscuous. */
1607 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1608 ECMR_PRM, ECMR);
1609 } else {
1610 /* Normal, unicast/broadcast-only mode. */
1611 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1612 ECMR_MCT, ECMR);
1613 }
1614 }
1615 #endif /* SH_ETH_HAS_TSU */
1616
1617 /* SuperH's TSU register init function */
1618 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1619 {
1620 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1621 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1622 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1623 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1624 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1625 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1626 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1627 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1628 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1629 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1630 if (sh_eth_is_gether(mdp)) {
1631 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1632 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1633 } else {
1634 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1635 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1636 }
1637 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1638 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1639 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1640 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1641 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1642 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1643 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1644 }
1645
1646 /* MDIO bus release function */
1647 static int sh_mdio_release(struct net_device *ndev)
1648 {
1649 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1650
1651 /* unregister mdio bus */
1652 mdiobus_unregister(bus);
1653
1654 /* remove mdio bus info from net_device */
1655 dev_set_drvdata(&ndev->dev, NULL);
1656
1657 /* free interrupts memory */
1658 kfree(bus->irq);
1659
1660 /* free bitbang info */
1661 free_mdio_bitbang(bus);
1662
1663 return 0;
1664 }
1665
1666 /* MDIO bus init function */
1667 static int sh_mdio_init(struct net_device *ndev, int id,
1668 struct sh_eth_plat_data *pd)
1669 {
1670 int ret, i;
1671 struct bb_info *bitbang;
1672 struct sh_eth_private *mdp = netdev_priv(ndev);
1673
1674 /* create bit control struct for PHY */
1675 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1676 if (!bitbang) {
1677 ret = -ENOMEM;
1678 goto out;
1679 }
1680
1681 /* bitbang init */
1682 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1683 bitbang->set_gate = pd->set_mdio_gate;
1684 bitbang->mdi_msk = 0x08;
1685 bitbang->mdo_msk = 0x04;
1686 bitbang->mmd_msk = 0x02;/* MMD */
1687 bitbang->mdc_msk = 0x01;
1688 bitbang->ctrl.ops = &bb_ops;
1689
1690 /* MII controller setting */
1691 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1692 if (!mdp->mii_bus) {
1693 ret = -ENOMEM;
1694 goto out_free_bitbang;
1695 }
1696
1697 /* Hook up MII support for ethtool */
1698 mdp->mii_bus->name = "sh_mii";
1699 mdp->mii_bus->parent = &ndev->dev;
1700 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1701
1702 /* PHY IRQ */
1703 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1704 if (!mdp->mii_bus->irq) {
1705 ret = -ENOMEM;
1706 goto out_free_bus;
1707 }
1708
1709 for (i = 0; i < PHY_MAX_ADDR; i++)
1710 mdp->mii_bus->irq[i] = PHY_POLL;
1711
1712 /* regist mdio bus */
1713 ret = mdiobus_register(mdp->mii_bus);
1714 if (ret)
1715 goto out_free_irq;
1716
1717 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1718
1719 return 0;
1720
1721 out_free_irq:
1722 kfree(mdp->mii_bus->irq);
1723
1724 out_free_bus:
1725 free_mdio_bitbang(mdp->mii_bus);
1726
1727 out_free_bitbang:
1728 kfree(bitbang);
1729
1730 out:
1731 return ret;
1732 }
1733
1734 static const u16 *sh_eth_get_register_offset(int register_type)
1735 {
1736 const u16 *reg_offset = NULL;
1737
1738 switch (register_type) {
1739 case SH_ETH_REG_GIGABIT:
1740 reg_offset = sh_eth_offset_gigabit;
1741 break;
1742 case SH_ETH_REG_FAST_SH4:
1743 reg_offset = sh_eth_offset_fast_sh4;
1744 break;
1745 case SH_ETH_REG_FAST_SH3_SH2:
1746 reg_offset = sh_eth_offset_fast_sh3_sh2;
1747 break;
1748 default:
1749 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1750 break;
1751 }
1752
1753 return reg_offset;
1754 }
1755
1756 static const struct net_device_ops sh_eth_netdev_ops = {
1757 .ndo_open = sh_eth_open,
1758 .ndo_stop = sh_eth_close,
1759 .ndo_start_xmit = sh_eth_start_xmit,
1760 .ndo_get_stats = sh_eth_get_stats,
1761 #if defined(SH_ETH_HAS_TSU)
1762 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1763 #endif
1764 .ndo_tx_timeout = sh_eth_tx_timeout,
1765 .ndo_do_ioctl = sh_eth_do_ioctl,
1766 .ndo_validate_addr = eth_validate_addr,
1767 .ndo_set_mac_address = eth_mac_addr,
1768 .ndo_change_mtu = eth_change_mtu,
1769 };
1770
1771 static int sh_eth_drv_probe(struct platform_device *pdev)
1772 {
1773 int ret, devno = 0;
1774 struct resource *res;
1775 struct net_device *ndev = NULL;
1776 struct sh_eth_private *mdp = NULL;
1777 struct sh_eth_plat_data *pd;
1778
1779 /* get base addr */
1780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1781 if (unlikely(res == NULL)) {
1782 dev_err(&pdev->dev, "invalid resource\n");
1783 ret = -EINVAL;
1784 goto out;
1785 }
1786
1787 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1788 if (!ndev) {
1789 dev_err(&pdev->dev, "Could not allocate device.\n");
1790 ret = -ENOMEM;
1791 goto out;
1792 }
1793
1794 /* The sh Ether-specific entries in the device structure. */
1795 ndev->base_addr = res->start;
1796 devno = pdev->id;
1797 if (devno < 0)
1798 devno = 0;
1799
1800 ndev->dma = -1;
1801 ret = platform_get_irq(pdev, 0);
1802 if (ret < 0) {
1803 ret = -ENODEV;
1804 goto out_release;
1805 }
1806 ndev->irq = ret;
1807
1808 SET_NETDEV_DEV(ndev, &pdev->dev);
1809
1810 /* Fill in the fields of the device structure with ethernet values. */
1811 ether_setup(ndev);
1812
1813 mdp = netdev_priv(ndev);
1814 spin_lock_init(&mdp->lock);
1815 mdp->pdev = pdev;
1816 pm_runtime_enable(&pdev->dev);
1817 pm_runtime_resume(&pdev->dev);
1818
1819 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1820 /* get PHY ID */
1821 mdp->phy_id = pd->phy;
1822 mdp->phy_interface = pd->phy_interface;
1823 /* EDMAC endian */
1824 mdp->edmac_endian = pd->edmac_endian;
1825 mdp->no_ether_link = pd->no_ether_link;
1826 mdp->ether_link_active_low = pd->ether_link_active_low;
1827 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1828
1829 /* set cpu data */
1830 #if defined(SH_ETH_HAS_BOTH_MODULES)
1831 mdp->cd = sh_eth_get_cpu_data(mdp);
1832 #else
1833 mdp->cd = &sh_eth_my_cpu_data;
1834 #endif
1835 sh_eth_set_default_cpu_data(mdp->cd);
1836
1837 /* set function */
1838 ndev->netdev_ops = &sh_eth_netdev_ops;
1839 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1840 ndev->watchdog_timeo = TX_TIMEOUT;
1841
1842 /* debug message level */
1843 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1844 mdp->post_rx = POST_RX >> (devno << 1);
1845 mdp->post_fw = POST_FW >> (devno << 1);
1846
1847 /* read and set MAC address */
1848 read_mac_address(ndev, pd->mac_addr);
1849
1850 /* First device only init */
1851 if (!devno) {
1852 if (mdp->cd->tsu) {
1853 struct resource *rtsu;
1854 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1855 if (!rtsu) {
1856 dev_err(&pdev->dev, "Not found TSU resource\n");
1857 goto out_release;
1858 }
1859 mdp->tsu_addr = ioremap(rtsu->start,
1860 resource_size(rtsu));
1861 }
1862 if (mdp->cd->chip_reset)
1863 mdp->cd->chip_reset(ndev);
1864
1865 if (mdp->cd->tsu) {
1866 /* TSU init (Init only)*/
1867 sh_eth_tsu_init(mdp);
1868 }
1869 }
1870
1871 /* network device register */
1872 ret = register_netdev(ndev);
1873 if (ret)
1874 goto out_release;
1875
1876 /* mdio bus init */
1877 ret = sh_mdio_init(ndev, pdev->id, pd);
1878 if (ret)
1879 goto out_unregister;
1880
1881 /* print device information */
1882 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1883 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1884
1885 platform_set_drvdata(pdev, ndev);
1886
1887 return ret;
1888
1889 out_unregister:
1890 unregister_netdev(ndev);
1891
1892 out_release:
1893 /* net_dev free */
1894 if (mdp && mdp->tsu_addr)
1895 iounmap(mdp->tsu_addr);
1896 if (ndev)
1897 free_netdev(ndev);
1898
1899 out:
1900 return ret;
1901 }
1902
1903 static int sh_eth_drv_remove(struct platform_device *pdev)
1904 {
1905 struct net_device *ndev = platform_get_drvdata(pdev);
1906 struct sh_eth_private *mdp = netdev_priv(ndev);
1907
1908 iounmap(mdp->tsu_addr);
1909 sh_mdio_release(ndev);
1910 unregister_netdev(ndev);
1911 pm_runtime_disable(&pdev->dev);
1912 free_netdev(ndev);
1913 platform_set_drvdata(pdev, NULL);
1914
1915 return 0;
1916 }
1917
1918 static int sh_eth_runtime_nop(struct device *dev)
1919 {
1920 /*
1921 * Runtime PM callback shared between ->runtime_suspend()
1922 * and ->runtime_resume(). Simply returns success.
1923 *
1924 * This driver re-initializes all registers after
1925 * pm_runtime_get_sync() anyway so there is no need
1926 * to save and restore registers here.
1927 */
1928 return 0;
1929 }
1930
1931 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1932 .runtime_suspend = sh_eth_runtime_nop,
1933 .runtime_resume = sh_eth_runtime_nop,
1934 };
1935
1936 static struct platform_driver sh_eth_driver = {
1937 .probe = sh_eth_drv_probe,
1938 .remove = sh_eth_drv_remove,
1939 .driver = {
1940 .name = CARDNAME,
1941 .pm = &sh_eth_dev_pm_ops,
1942 },
1943 };
1944
1945 static int __init sh_eth_init(void)
1946 {
1947 return platform_driver_register(&sh_eth_driver);
1948 }
1949
1950 static void __exit sh_eth_cleanup(void)
1951 {
1952 platform_driver_unregister(&sh_eth_driver);
1953 }
1954
1955 module_init(sh_eth_init);
1956 module_exit(sh_eth_cleanup);
1957
1958 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1959 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1960 MODULE_LICENSE("GPL v2");
linux-next