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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / smc91x.h
blob5f53fbbf67be84acf2c1fe1e4f0e8541bce86617
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@fluxnic.net>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER) ||\
49 defined(CONFIG_MACH_STARGATE2)
50
51 #include <asm/mach-types.h>
52
53 /* Now the bus width is specified in the platform data
54 * pretend here to support all I/O access types
55 */
56 #define SMC_CAN_USE_8BIT 1
57 #define SMC_CAN_USE_16BIT 1
58 #define SMC_CAN_USE_32BIT 1
59 #define SMC_NOWAIT 1
60
61 #define SMC_IO_SHIFT (lp->io_shift)
62
63 #define SMC_inb(a, r) readb((a) + (r))
64 #define SMC_inw(a, r) readw((a) + (r))
65 #define SMC_inl(a, r) readl((a) + (r))
66 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
67 #define SMC_outl(v, a, r) writel(v, (a) + (r))
68 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
69 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
70 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
71 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
72 #define SMC_IRQ_FLAGS (-1) /* from resource */
73
74 /* We actually can't write halfwords properly if not word aligned */
75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
76 {
77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
78 unsigned int v = val << 16;
79 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
80 writel(v, ioaddr + (reg & ~2));
81 } else {
82 writew(val, ioaddr + reg);
83 }
84 }
85
86 #elif defined(CONFIG_SA1100_PLEB)
87 /* We can only do 16-bit reads and writes in the static memory space. */
88 #define SMC_CAN_USE_8BIT 1
89 #define SMC_CAN_USE_16BIT 1
90 #define SMC_CAN_USE_32BIT 0
91 #define SMC_IO_SHIFT 0
92 #define SMC_NOWAIT 1
93
94 #define SMC_inb(a, r) readb((a) + (r))
95 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
96 #define SMC_inw(a, r) readw((a) + (r))
97 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
98 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
99 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
100 #define SMC_outw(v, a, r) writew(v, (a) + (r))
101 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
102
103 #define SMC_IRQ_FLAGS (-1)
104
105 #elif defined(CONFIG_SA1100_ASSABET)
106
107 #include <mach/neponset.h>
108
109 /* We can only do 8-bit reads and writes in the static memory space. */
110 #define SMC_CAN_USE_8BIT 1
111 #define SMC_CAN_USE_16BIT 0
112 #define SMC_CAN_USE_32BIT 0
113 #define SMC_NOWAIT 1
114
115 /* The first two address lines aren't connected... */
116 #define SMC_IO_SHIFT 2
117
118 #define SMC_inb(a, r) readb((a) + (r))
119 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
120 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
121 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
122 #define SMC_IRQ_FLAGS (-1) /* from resource */
123
124 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
125 defined(CONFIG_MACH_NOMADIK_8815NHK)
126
127 #define SMC_CAN_USE_8BIT 0
128 #define SMC_CAN_USE_16BIT 1
129 #define SMC_CAN_USE_32BIT 0
130 #define SMC_IO_SHIFT 0
131 #define SMC_NOWAIT 1
132
133 #define SMC_inw(a, r) readw((a) + (r))
134 #define SMC_outw(v, a, r) writew(v, (a) + (r))
135 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
136 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
137
138 #elif defined(CONFIG_ARCH_INNOKOM) || \
139 defined(CONFIG_ARCH_PXA_IDP) || \
140 defined(CONFIG_ARCH_RAMSES) || \
141 defined(CONFIG_ARCH_PCM027)
142
143 #define SMC_CAN_USE_8BIT 1
144 #define SMC_CAN_USE_16BIT 1
145 #define SMC_CAN_USE_32BIT 1
146 #define SMC_IO_SHIFT 0
147 #define SMC_NOWAIT 1
148 #define SMC_USE_PXA_DMA 1
149
150 #define SMC_inb(a, r) readb((a) + (r))
151 #define SMC_inw(a, r) readw((a) + (r))
152 #define SMC_inl(a, r) readl((a) + (r))
153 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
154 #define SMC_outl(v, a, r) writel(v, (a) + (r))
155 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
156 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
157 #define SMC_IRQ_FLAGS (-1) /* from resource */
158
159 /* We actually can't write halfwords properly if not word aligned */
160 static inline void
161 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
162 {
163 if (reg & 2) {
164 unsigned int v = val << 16;
165 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
166 writel(v, ioaddr + (reg & ~2));
167 } else {
168 writew(val, ioaddr + reg);
169 }
170 }
171
172 #elif defined(CONFIG_SH_SH4202_MICRODEV)
173
174 #define SMC_CAN_USE_8BIT 0
175 #define SMC_CAN_USE_16BIT 1
176 #define SMC_CAN_USE_32BIT 0
177
178 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
179 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
180 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
181 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
182 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
183 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
184 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
185 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
186 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
187 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
188
189 #define SMC_IRQ_FLAGS (0)
190
191 #elif defined(CONFIG_M32R)
192
193 #define SMC_CAN_USE_8BIT 0
194 #define SMC_CAN_USE_16BIT 1
195 #define SMC_CAN_USE_32BIT 0
196
197 #define SMC_inb(a, r) inb(((u32)a) + (r))
198 #define SMC_inw(a, r) inw(((u32)a) + (r))
199 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
200 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
201 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
202 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
203
204 #define SMC_IRQ_FLAGS (0)
205
206 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
207 #define RPC_LSB_DEFAULT RPC_LED_100_10
208
209 #elif defined(CONFIG_ARCH_VERSATILE)
210
211 #define SMC_CAN_USE_8BIT 1
212 #define SMC_CAN_USE_16BIT 1
213 #define SMC_CAN_USE_32BIT 1
214 #define SMC_NOWAIT 1
215
216 #define SMC_inb(a, r) readb((a) + (r))
217 #define SMC_inw(a, r) readw((a) + (r))
218 #define SMC_inl(a, r) readl((a) + (r))
219 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
220 #define SMC_outw(v, a, r) writew(v, (a) + (r))
221 #define SMC_outl(v, a, r) writel(v, (a) + (r))
222 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
223 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
224 #define SMC_IRQ_FLAGS (-1) /* from resource */
225
226 #elif defined(CONFIG_MN10300)
227
228 /*
229 * MN10300/AM33 configuration
230 */
231
232 #include <unit/smc91111.h>
233
234 #elif defined(CONFIG_ARCH_MSM)
235
236 #define SMC_CAN_USE_8BIT 0
237 #define SMC_CAN_USE_16BIT 1
238 #define SMC_CAN_USE_32BIT 0
239 #define SMC_NOWAIT 1
240
241 #define SMC_inw(a, r) readw((a) + (r))
242 #define SMC_outw(v, a, r) writew(v, (a) + (r))
243 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
244 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
245
246 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
247
248 #elif defined(CONFIG_COLDFIRE)
249
250 #define SMC_CAN_USE_8BIT 0
251 #define SMC_CAN_USE_16BIT 1
252 #define SMC_CAN_USE_32BIT 0
253 #define SMC_NOWAIT 1
254
255 static inline void mcf_insw(void *a, unsigned char *p, int l)
256 {
257 u16 *wp = (u16 *) p;
258 while (l-- > 0)
259 *wp++ = readw(a);
260 }
261
262 static inline void mcf_outsw(void *a, unsigned char *p, int l)
263 {
264 u16 *wp = (u16 *) p;
265 while (l-- > 0)
266 writew(*wp++, a);
267 }
268
269 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
270 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
271 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
272 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
273
274 #define SMC_IRQ_FLAGS (IRQF_DISABLED)
275
276 #else
277
278 /*
279 * Default configuration
280 */
281
282 #define SMC_CAN_USE_8BIT 1
283 #define SMC_CAN_USE_16BIT 1
284 #define SMC_CAN_USE_32BIT 1
285 #define SMC_NOWAIT 1
286
287 #define SMC_IO_SHIFT (lp->io_shift)
288
289 #define SMC_inb(a, r) readb((a) + (r))
290 #define SMC_inw(a, r) readw((a) + (r))
291 #define SMC_inl(a, r) readl((a) + (r))
292 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
293 #define SMC_outw(v, a, r) writew(v, (a) + (r))
294 #define SMC_outl(v, a, r) writel(v, (a) + (r))
295 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
296 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
297 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
298 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
299
300 #define RPC_LSA_DEFAULT RPC_LED_100_10
301 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
302
303 #endif
304
305
306 /* store this information for the driver.. */
307 struct smc_local {
308 /*
309 * If I have to wait until memory is available to send a
310 * packet, I will store the skbuff here, until I get the
311 * desired memory. Then, I'll send it out and free it.
312 */
313 struct sk_buff *pending_tx_skb;
314 struct tasklet_struct tx_task;
315
316 /* version/revision of the SMC91x chip */
317 int version;
318
319 /* Contains the current active transmission mode */
320 int tcr_cur_mode;
321
322 /* Contains the current active receive mode */
323 int rcr_cur_mode;
324
325 /* Contains the current active receive/phy mode */
326 int rpc_cur_mode;
327 int ctl_rfduplx;
328 int ctl_rspeed;
329
330 u32 msg_enable;
331 u32 phy_type;
332 struct mii_if_info mii;
333
334 /* work queue */
335 struct work_struct phy_configure;
336 struct net_device *dev;
337 int work_pending;
338
339 spinlock_t lock;
340
341 #ifdef CONFIG_ARCH_PXA
342 /* DMA needs the physical address of the chip */
343 u_long physaddr;
344 struct device *device;
345 #endif
346 void __iomem *base;
347 void __iomem *datacs;
348
349 /* the low address lines on some platforms aren't connected... */
350 int io_shift;
351
352 struct smc91x_platdata cfg;
353 };
354
355 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
356 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
357 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
358
359 #ifdef CONFIG_ARCH_PXA
360 /*
361 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
362 * always happening in irq context so no need to worry about races. TX is
363 * different and probably not worth it for that reason, and not as critical
364 * as RX which can overrun memory and lose packets.
365 */
366 #include <linux/dma-mapping.h>
367 #include <mach/dma.h>
368
369 #ifdef SMC_insl
370 #undef SMC_insl
371 #define SMC_insl(a, r, p, l) \
372 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
373 static inline void
374 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
375 u_char *buf, int len)
376 {
377 u_long physaddr = lp->physaddr;
378 dma_addr_t dmabuf;
379
380 /* fallback if no DMA available */
381 if (dma == (unsigned char)-1) {
382 readsl(ioaddr + reg, buf, len);
383 return;
384 }
385
386 /* 64 bit alignment is required for memory to memory DMA */
387 if ((long)buf & 4) {
388 *((u32 *)buf) = SMC_inl(ioaddr, reg);
389 buf += 4;
390 len--;
391 }
392
393 len *= 4;
394 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
395 DCSR(dma) = DCSR_NODESC;
396 DTADR(dma) = dmabuf;
397 DSADR(dma) = physaddr + reg;
398 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
399 DCMD_WIDTH4 | (DCMD_LENGTH & len));
400 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
401 while (!(DCSR(dma) & DCSR_STOPSTATE))
402 cpu_relax();
403 DCSR(dma) = 0;
404 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
405 }
406 #endif
407
408 #ifdef SMC_insw
409 #undef SMC_insw
410 #define SMC_insw(a, r, p, l) \
411 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
412 static inline void
413 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
414 u_char *buf, int len)
415 {
416 u_long physaddr = lp->physaddr;
417 dma_addr_t dmabuf;
418
419 /* fallback if no DMA available */
420 if (dma == (unsigned char)-1) {
421 readsw(ioaddr + reg, buf, len);
422 return;
423 }
424
425 /* 64 bit alignment is required for memory to memory DMA */
426 while ((long)buf & 6) {
427 *((u16 *)buf) = SMC_inw(ioaddr, reg);
428 buf += 2;
429 len--;
430 }
431
432 len *= 2;
433 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
434 DCSR(dma) = DCSR_NODESC;
435 DTADR(dma) = dmabuf;
436 DSADR(dma) = physaddr + reg;
437 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
438 DCMD_WIDTH2 | (DCMD_LENGTH & len));
439 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
440 while (!(DCSR(dma) & DCSR_STOPSTATE))
441 cpu_relax();
442 DCSR(dma) = 0;
443 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
444 }
445 #endif
446
447 static void
448 smc_pxa_dma_irq(int dma, void *dummy)
449 {
450 DCSR(dma) = 0;
451 }
452 #endif /* CONFIG_ARCH_PXA */
453
454
455 /*
456 * Everything a particular hardware setup needs should have been defined
457 * at this point. Add stubs for the undefined cases, mainly to avoid
458 * compilation warnings since they'll be optimized away, or to prevent buggy
459 * use of them.
460 */
461
462 #if ! SMC_CAN_USE_32BIT
463 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
464 #define SMC_outl(x, ioaddr, reg) BUG()
465 #define SMC_insl(a, r, p, l) BUG()
466 #define SMC_outsl(a, r, p, l) BUG()
467 #endif
468
469 #if !defined(SMC_insl) || !defined(SMC_outsl)
470 #define SMC_insl(a, r, p, l) BUG()
471 #define SMC_outsl(a, r, p, l) BUG()
472 #endif
473
474 #if ! SMC_CAN_USE_16BIT
475
476 /*
477 * Any 16-bit access is performed with two 8-bit accesses if the hardware
478 * can't do it directly. Most registers are 16-bit so those are mandatory.
479 */
480 #define SMC_outw(x, ioaddr, reg) \
481 do { \
482 unsigned int __val16 = (x); \
483 SMC_outb( __val16, ioaddr, reg ); \
484 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
485 } while (0)
486 #define SMC_inw(ioaddr, reg) \
487 ({ \
488 unsigned int __val16; \
489 __val16 = SMC_inb( ioaddr, reg ); \
490 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
491 __val16; \
492 })
493
494 #define SMC_insw(a, r, p, l) BUG()
495 #define SMC_outsw(a, r, p, l) BUG()
496
497 #endif
498
499 #if !defined(SMC_insw) || !defined(SMC_outsw)
500 #define SMC_insw(a, r, p, l) BUG()
501 #define SMC_outsw(a, r, p, l) BUG()
502 #endif
503
504 #if ! SMC_CAN_USE_8BIT
505 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
506 #define SMC_outb(x, ioaddr, reg) BUG()
507 #define SMC_insb(a, r, p, l) BUG()
508 #define SMC_outsb(a, r, p, l) BUG()
509 #endif
510
511 #if !defined(SMC_insb) || !defined(SMC_outsb)
512 #define SMC_insb(a, r, p, l) BUG()
513 #define SMC_outsb(a, r, p, l) BUG()
514 #endif
515
516 #ifndef SMC_CAN_USE_DATACS
517 #define SMC_CAN_USE_DATACS 0
518 #endif
519
520 #ifndef SMC_IO_SHIFT
521 #define SMC_IO_SHIFT 0
522 #endif
523
524 #ifndef SMC_IRQ_FLAGS
525 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
526 #endif
527
528 #ifndef SMC_INTERRUPT_PREAMBLE
529 #define SMC_INTERRUPT_PREAMBLE
530 #endif
531
532
533 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
534 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
535 #define SMC_DATA_EXTENT (4)
536
537 /*
538 . Bank Select Register:
539 .
540 . yyyy yyyy 0000 00xx
541 . xx = bank number
542 . yyyy yyyy = 0x33, for identification purposes.
543 */
544 #define BANK_SELECT (14 << SMC_IO_SHIFT)
545
546
547 // Transmit Control Register
548 /* BANK 0 */
549 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
550 #define TCR_ENABLE 0x0001 // When 1 we can transmit
551 #define TCR_LOOP 0x0002 // Controls output pin LBK
552 #define TCR_FORCOL 0x0004 // When 1 will force a collision
553 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
554 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
555 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
556 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
557 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
558 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
559 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
560
561 #define TCR_CLEAR 0 /* do NOTHING */
562 /* the default settings for the TCR register : */
563 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
564
565
566 // EPH Status Register
567 /* BANK 0 */
568 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
569 #define ES_TX_SUC 0x0001 // Last TX was successful
570 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
571 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
572 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
573 #define ES_16COL 0x0010 // 16 Collisions Reached
574 #define ES_SQET 0x0020 // Signal Quality Error Test
575 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
576 #define ES_TXDEFR 0x0080 // Transmit Deferred
577 #define ES_LATCOL 0x0200 // Late collision detected on last tx
578 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
579 #define ES_EXC_DEF 0x0800 // Excessive Deferral
580 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
581 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
582 #define ES_TXUNRN 0x8000 // Tx Underrun
583
584
585 // Receive Control Register
586 /* BANK 0 */
587 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
588 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
589 #define RCR_PRMS 0x0002 // Enable promiscuous mode
590 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
591 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
592 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
593 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
594 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
595 #define RCR_SOFTRST 0x8000 // resets the chip
596
597 /* the normal settings for the RCR register : */
598 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
599 #define RCR_CLEAR 0x0 // set it to a base state
600
601
602 // Counter Register
603 /* BANK 0 */
604 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
605
606
607 // Memory Information Register
608 /* BANK 0 */
609 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
610
611
612 // Receive/Phy Control Register
613 /* BANK 0 */
614 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
615 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
616 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
617 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
618 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
619 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
620
621 #ifndef RPC_LSA_DEFAULT
622 #define RPC_LSA_DEFAULT RPC_LED_100
623 #endif
624 #ifndef RPC_LSB_DEFAULT
625 #define RPC_LSB_DEFAULT RPC_LED_FD
626 #endif
627
628 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
629
630
631 /* Bank 0 0x0C is reserved */
632
633 // Bank Select Register
634 /* All Banks */
635 #define BSR_REG 0x000E
636
637
638 // Configuration Reg
639 /* BANK 1 */
640 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
641 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
642 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
643 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
644 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
645
646 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
647 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
648
649
650 // Base Address Register
651 /* BANK 1 */
652 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
653
654
655 // Individual Address Registers
656 /* BANK 1 */
657 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
658 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
659 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
660
661
662 // General Purpose Register
663 /* BANK 1 */
664 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
665
666
667 // Control Register
668 /* BANK 1 */
669 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
670 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
671 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
672 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
673 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
674 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
675 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
676 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
677 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
678
679
680 // MMU Command Register
681 /* BANK 2 */
682 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
683 #define MC_BUSY 1 // When 1 the last release has not completed
684 #define MC_NOP (0<<5) // No Op
685 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
686 #define MC_RESET (2<<5) // Reset MMU to initial state
687 #define MC_REMOVE (3<<5) // Remove the current rx packet
688 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
689 #define MC_FREEPKT (5<<5) // Release packet in PNR register
690 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
691 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
692
693
694 // Packet Number Register
695 /* BANK 2 */
696 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
697
698
699 // Allocation Result Register
700 /* BANK 2 */
701 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
702 #define AR_FAILED 0x80 // Alocation Failed
703
704
705 // TX FIFO Ports Register
706 /* BANK 2 */
707 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
708 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
709
710 // RX FIFO Ports Register
711 /* BANK 2 */
712 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
713 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
714
715 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
716
717 // Pointer Register
718 /* BANK 2 */
719 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
720 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
721 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
722 #define PTR_READ 0x2000 // When 1 the operation is a read
723
724
725 // Data Register
726 /* BANK 2 */
727 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
728
729
730 // Interrupt Status/Acknowledge Register
731 /* BANK 2 */
732 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
733
734
735 // Interrupt Mask Register
736 /* BANK 2 */
737 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
738 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
739 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
740 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
741 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
742 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
743 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
744 #define IM_TX_INT 0x02 // Transmit Interrupt
745 #define IM_RCV_INT 0x01 // Receive Interrupt
746
747
748 // Multicast Table Registers
749 /* BANK 3 */
750 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
751 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
752 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
753 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
754
755
756 // Management Interface Register (MII)
757 /* BANK 3 */
758 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
759 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
760 #define MII_MDOE 0x0008 // MII Output Enable
761 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
762 #define MII_MDI 0x0002 // MII Input, pin MDI
763 #define MII_MDO 0x0001 // MII Output, pin MDO
764
765
766 // Revision Register
767 /* BANK 3 */
768 /* ( hi: chip id low: rev # ) */
769 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
770
771
772 // Early RCV Register
773 /* BANK 3 */
774 /* this is NOT on SMC9192 */
775 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
776 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
777 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
778
779
780 // External Register
781 /* BANK 7 */
782 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
783
784
785 #define CHIP_9192 3
786 #define CHIP_9194 4
787 #define CHIP_9195 5
788 #define CHIP_9196 6
789 #define CHIP_91100 7
790 #define CHIP_91100FD 8
791 #define CHIP_91111FD 9
792
793 static const char * chip_ids[ 16 ] = {
794 NULL, NULL, NULL,
795 /* 3 */ "SMC91C90/91C92",
796 /* 4 */ "SMC91C94",
797 /* 5 */ "SMC91C95",
798 /* 6 */ "SMC91C96",
799 /* 7 */ "SMC91C100",
800 /* 8 */ "SMC91C100FD",
801 /* 9 */ "SMC91C11xFD",
802 NULL, NULL, NULL,
803 NULL, NULL, NULL};
804
805
806 /*
807 . Receive status bits
808 */
809 #define RS_ALGNERR 0x8000
810 #define RS_BRODCAST 0x4000
811 #define RS_BADCRC 0x2000
812 #define RS_ODDFRAME 0x1000
813 #define RS_TOOLONG 0x0800
814 #define RS_TOOSHORT 0x0400
815 #define RS_MULTICAST 0x0001
816 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
817
818
819 /*
820 * PHY IDs
821 * LAN83C183 == LAN91C111 Internal PHY
822 */
823 #define PHY_LAN83C183 0x0016f840
824 #define PHY_LAN83C180 0x02821c50
825
826 /*
827 * PHY Register Addresses (LAN91C111 Internal PHY)
828 *
829 * Generic PHY registers can be found in <linux/mii.h>
830 *
831 * These phy registers are specific to our on-board phy.
832 */
833
834 // PHY Configuration Register 1
835 #define PHY_CFG1_REG 0x10
836 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
837 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
838 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
839 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
840 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
841 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
842 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
843 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
844 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
845 #define PHY_CFG1_TLVL_MASK 0x003C
846 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
847
848
849 // PHY Configuration Register 2
850 #define PHY_CFG2_REG 0x11
851 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
852 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
853 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
854 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
855
856 // PHY Status Output (and Interrupt status) Register
857 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
858 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
859 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
860 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
861 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
862 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
863 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
864 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
865 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
866 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
867 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
868
869 // PHY Interrupt/Status Mask Register
870 #define PHY_MASK_REG 0x13 // Interrupt Mask
871 // Uses the same bit definitions as PHY_INT_REG
872
873
874 /*
875 * SMC91C96 ethernet config and status registers.
876 * These are in the "attribute" space.
877 */
878 #define ECOR 0x8000
879 #define ECOR_RESET 0x80
880 #define ECOR_LEVEL_IRQ 0x40
881 #define ECOR_WR_ATTRIB 0x04
882 #define ECOR_ENABLE 0x01
883
884 #define ECSR 0x8002
885 #define ECSR_IOIS8 0x20
886 #define ECSR_PWRDWN 0x04
887 #define ECSR_INT 0x02
888
889 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
890
891
892 /*
893 * Macros to abstract register access according to the data bus
894 * capabilities. Please use those and not the in/out primitives.
895 * Note: the following macros do *not* select the bank -- this must
896 * be done separately as needed in the main code. The SMC_REG() macro
897 * only uses the bank argument for debugging purposes (when enabled).
898 *
899 * Note: despite inline functions being safer, everything leading to this
900 * should preferably be macros to let BUG() display the line number in
901 * the core source code since we're interested in the top call site
902 * not in any inline function location.
903 */
904
905 #if SMC_DEBUG > 0
906 #define SMC_REG(lp, reg, bank) \
907 ({ \
908 int __b = SMC_CURRENT_BANK(lp); \
909 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
910 printk( "%s: bank reg screwed (0x%04x)\n", \
911 CARDNAME, __b ); \
912 BUG(); \
913 } \
914 reg<<SMC_IO_SHIFT; \
915 })
916 #else
917 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
918 #endif
919
920 /*
921 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
922 * aligned to a 32 bit boundary. I tell you that does exist!
923 * Fortunately the affected register accesses can be easily worked around
924 * since we can write zeroes to the preceding 16 bits without adverse
925 * effects and use a 32-bit access.
926 *
927 * Enforce it on any 32-bit capable setup for now.
928 */
929 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
930
931 #define SMC_GET_PN(lp) \
932 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
933 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
934
935 #define SMC_SET_PN(lp, x) \
936 do { \
937 if (SMC_MUST_ALIGN_WRITE(lp)) \
938 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
939 else if (SMC_8BIT(lp)) \
940 SMC_outb(x, ioaddr, PN_REG(lp)); \
941 else \
942 SMC_outw(x, ioaddr, PN_REG(lp)); \
943 } while (0)
944
945 #define SMC_GET_AR(lp) \
946 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
947 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
948
949 #define SMC_GET_TXFIFO(lp) \
950 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
951 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
952
953 #define SMC_GET_RXFIFO(lp) \
954 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
955 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
956
957 #define SMC_GET_INT(lp) \
958 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
959 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
960
961 #define SMC_ACK_INT(lp, x) \
962 do { \
963 if (SMC_8BIT(lp)) \
964 SMC_outb(x, ioaddr, INT_REG(lp)); \
965 else { \
966 unsigned long __flags; \
967 int __mask; \
968 local_irq_save(__flags); \
969 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
970 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
971 local_irq_restore(__flags); \
972 } \
973 } while (0)
974
975 #define SMC_GET_INT_MASK(lp) \
976 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
977 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
978
979 #define SMC_SET_INT_MASK(lp, x) \
980 do { \
981 if (SMC_8BIT(lp)) \
982 SMC_outb(x, ioaddr, IM_REG(lp)); \
983 else \
984 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
985 } while (0)
986
987 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
988
989 #define SMC_SELECT_BANK(lp, x) \
990 do { \
991 if (SMC_MUST_ALIGN_WRITE(lp)) \
992 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
993 else \
994 SMC_outw(x, ioaddr, BANK_SELECT); \
995 } while (0)
996
997 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
998
999 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1000
1001 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1002
1003 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1004
1005 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1006
1007 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1008
1009 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1010
1011 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1012
1013 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1014
1015 #define SMC_SET_GP(lp, x) \
1016 do { \
1017 if (SMC_MUST_ALIGN_WRITE(lp)) \
1018 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1019 else \
1020 SMC_outw(x, ioaddr, GP_REG(lp)); \
1021 } while (0)
1022
1023 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1024
1025 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1026
1027 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1028
1029 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1030
1031 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1032
1033 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1034
1035 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1036
1037 #define SMC_SET_PTR(lp, x) \
1038 do { \
1039 if (SMC_MUST_ALIGN_WRITE(lp)) \
1040 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1041 else \
1042 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1043 } while (0)
1044
1045 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1046
1047 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1048
1049 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1050
1051 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1052
1053 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1054
1055 #define SMC_SET_RPC(lp, x) \
1056 do { \
1057 if (SMC_MUST_ALIGN_WRITE(lp)) \
1058 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1059 else \
1060 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1061 } while (0)
1062
1063 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1064
1065 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1066
1067 #ifndef SMC_GET_MAC_ADDR
1068 #define SMC_GET_MAC_ADDR(lp, addr) \
1069 do { \
1070 unsigned int __v; \
1071 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1072 addr[0] = __v; addr[1] = __v >> 8; \
1073 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1074 addr[2] = __v; addr[3] = __v >> 8; \
1075 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1076 addr[4] = __v; addr[5] = __v >> 8; \
1077 } while (0)
1078 #endif
1079
1080 #define SMC_SET_MAC_ADDR(lp, addr) \
1081 do { \
1082 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1083 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1084 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1085 } while (0)
1086
1087 #define SMC_SET_MCAST(lp, x) \
1088 do { \
1089 const unsigned char *mt = (x); \
1090 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1091 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1092 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1093 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1094 } while (0)
1095
1096 #define SMC_PUT_PKT_HDR(lp, status, length) \
1097 do { \
1098 if (SMC_32BIT(lp)) \
1099 SMC_outl((status) | (length)<<16, ioaddr, \
1100 DATA_REG(lp)); \
1101 else { \
1102 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1103 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1104 } \
1105 } while (0)
1106
1107 #define SMC_GET_PKT_HDR(lp, status, length) \
1108 do { \
1109 if (SMC_32BIT(lp)) { \
1110 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1111 (status) = __val & 0xffff; \
1112 (length) = __val >> 16; \
1113 } else { \
1114 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1115 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1116 } \
1117 } while (0)
1118
1119 #define SMC_PUSH_DATA(lp, p, l) \
1120 do { \
1121 if (SMC_32BIT(lp)) { \
1122 void *__ptr = (p); \
1123 int __len = (l); \
1124 void __iomem *__ioaddr = ioaddr; \
1125 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1126 __len -= 2; \
1127 SMC_outw(*(u16 *)__ptr, ioaddr, \
1128 DATA_REG(lp)); \
1129 __ptr += 2; \
1130 } \
1131 if (SMC_CAN_USE_DATACS && lp->datacs) \
1132 __ioaddr = lp->datacs; \
1133 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1134 if (__len & 2) { \
1135 __ptr += (__len & ~3); \
1136 SMC_outw(*((u16 *)__ptr), ioaddr, \
1137 DATA_REG(lp)); \
1138 } \
1139 } else if (SMC_16BIT(lp)) \
1140 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1141 else if (SMC_8BIT(lp)) \
1142 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1143 } while (0)
1144
1145 #define SMC_PULL_DATA(lp, p, l) \
1146 do { \
1147 if (SMC_32BIT(lp)) { \
1148 void *__ptr = (p); \
1149 int __len = (l); \
1150 void __iomem *__ioaddr = ioaddr; \
1151 if ((unsigned long)__ptr & 2) { \
1152 /* \
1153 * We want 32bit alignment here. \
1154 * Since some buses perform a full \
1155 * 32bit fetch even for 16bit data \
1156 * we can't use SMC_inw() here. \
1157 * Back both source (on-chip) and \
1158 * destination pointers of 2 bytes. \
1159 * This is possible since the call to \
1160 * SMC_GET_PKT_HDR() already advanced \
1161 * the source pointer of 4 bytes, and \
1162 * the skb_reserve(skb, 2) advanced \
1163 * the destination pointer of 2 bytes. \
1164 */ \
1165 __ptr -= 2; \
1166 __len += 2; \
1167 SMC_SET_PTR(lp, \
1168 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1169 } \
1170 if (SMC_CAN_USE_DATACS && lp->datacs) \
1171 __ioaddr = lp->datacs; \
1172 __len += 2; \
1173 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1174 } else if (SMC_16BIT(lp)) \
1175 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1176 else if (SMC_8BIT(lp)) \
1177 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1178 } while (0)
1179
1180 #endif /* _SMC91X_H_ */
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