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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / sungem.c
blobade35dde5b51593638327ab5a640f995fb0c08a3
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/in.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <linux/random.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/bitops.h>
41 #include <linux/mm.h>
42 #include <linux/gfp.h>
43
44 #include <asm/system.h>
45 #include <asm/io.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
48 #include <asm/irq.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #ifdef CONFIG_PPC_PMAC
56 #include <asm/pci-bridge.h>
57 #include <asm/prom.h>
58 #include <asm/machdep.h>
59 #include <asm/pmac_feature.h>
60 #endif
61
62 #include "sungem_phy.h"
63 #include "sungem.h"
64
65 /* Stripping FCS is causing problems, disabled for now */
66 #undef STRIP_FCS
67
68 #define DEFAULT_MSG (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK)
71
72 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
73 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
74 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
75 SUPPORTED_Pause | SUPPORTED_Autoneg)
76
77 #define DRV_NAME "sungem"
78 #define DRV_VERSION "1.0"
79 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
80
81 static char version[] __devinitdata =
82 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
83
84 MODULE_AUTHOR(DRV_AUTHOR);
85 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
86 MODULE_LICENSE("GPL");
87
88 #define GEM_MODULE_NAME "gem"
89
90 static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {
91 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
93
94 /* These models only differ from the original GEM in
95 * that their tx/rx fifos are of a different size and
96 * they only support 10/100 speeds. -DaveM
97 *
98 * Apple's GMAC does support gigabit on machines with
99 * the BCM54xx PHYs. -BenH
100 */
101 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
103 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
105 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
107 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
109 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
111 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
113 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
115 {0, }
116 };
117
118 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
119
120 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
121 {
122 u32 cmd;
123 int limit = 10000;
124
125 cmd = (1 << 30);
126 cmd |= (2 << 28);
127 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
128 cmd |= (reg << 18) & MIF_FRAME_REGAD;
129 cmd |= (MIF_FRAME_TAMSB);
130 writel(cmd, gp->regs + MIF_FRAME);
131
132 while (--limit) {
133 cmd = readl(gp->regs + MIF_FRAME);
134 if (cmd & MIF_FRAME_TALSB)
135 break;
136
137 udelay(10);
138 }
139
140 if (!limit)
141 cmd = 0xffff;
142
143 return cmd & MIF_FRAME_DATA;
144 }
145
146 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
147 {
148 struct gem *gp = netdev_priv(dev);
149 return __phy_read(gp, mii_id, reg);
150 }
151
152 static inline u16 phy_read(struct gem *gp, int reg)
153 {
154 return __phy_read(gp, gp->mii_phy_addr, reg);
155 }
156
157 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
158 {
159 u32 cmd;
160 int limit = 10000;
161
162 cmd = (1 << 30);
163 cmd |= (1 << 28);
164 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
165 cmd |= (reg << 18) & MIF_FRAME_REGAD;
166 cmd |= (MIF_FRAME_TAMSB);
167 cmd |= (val & MIF_FRAME_DATA);
168 writel(cmd, gp->regs + MIF_FRAME);
169
170 while (limit--) {
171 cmd = readl(gp->regs + MIF_FRAME);
172 if (cmd & MIF_FRAME_TALSB)
173 break;
174
175 udelay(10);
176 }
177 }
178
179 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
180 {
181 struct gem *gp = netdev_priv(dev);
182 __phy_write(gp, mii_id, reg, val & 0xffff);
183 }
184
185 static inline void phy_write(struct gem *gp, int reg, u16 val)
186 {
187 __phy_write(gp, gp->mii_phy_addr, reg, val);
188 }
189
190 static inline void gem_enable_ints(struct gem *gp)
191 {
192 /* Enable all interrupts but TXDONE */
193 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
194 }
195
196 static inline void gem_disable_ints(struct gem *gp)
197 {
198 /* Disable all interrupts, including TXDONE */
199 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
200 (void)readl(gp->regs + GREG_IMASK); /* write posting */
201 }
202
203 static void gem_get_cell(struct gem *gp)
204 {
205 BUG_ON(gp->cell_enabled < 0);
206 gp->cell_enabled++;
207 #ifdef CONFIG_PPC_PMAC
208 if (gp->cell_enabled == 1) {
209 mb();
210 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
211 udelay(10);
212 }
213 #endif /* CONFIG_PPC_PMAC */
214 }
215
216 /* Turn off the chip's clock */
217 static void gem_put_cell(struct gem *gp)
218 {
219 BUG_ON(gp->cell_enabled <= 0);
220 gp->cell_enabled--;
221 #ifdef CONFIG_PPC_PMAC
222 if (gp->cell_enabled == 0) {
223 mb();
224 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
225 udelay(10);
226 }
227 #endif /* CONFIG_PPC_PMAC */
228 }
229
230 static inline void gem_netif_stop(struct gem *gp)
231 {
232 gp->dev->trans_start = jiffies; /* prevent tx timeout */
233 napi_disable(&gp->napi);
234 netif_tx_disable(gp->dev);
235 }
236
237 static inline void gem_netif_start(struct gem *gp)
238 {
239 /* NOTE: unconditional netif_wake_queue is only
240 * appropriate so long as all callers are assured to
241 * have free tx slots.
242 */
243 netif_wake_queue(gp->dev);
244 napi_enable(&gp->napi);
245 }
246
247 static void gem_schedule_reset(struct gem *gp)
248 {
249 gp->reset_task_pending = 1;
250 schedule_work(&gp->reset_task);
251 }
252
253 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
254 {
255 if (netif_msg_intr(gp))
256 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
257 }
258
259 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
260 {
261 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
262 u32 pcs_miistat;
263
264 if (netif_msg_intr(gp))
265 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
266 gp->dev->name, pcs_istat);
267
268 if (!(pcs_istat & PCS_ISTAT_LSC)) {
269 netdev_err(dev, "PCS irq but no link status change???\n");
270 return 0;
271 }
272
273 /* The link status bit latches on zero, so you must
274 * read it twice in such a case to see a transition
275 * to the link being up.
276 */
277 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
278 if (!(pcs_miistat & PCS_MIISTAT_LS))
279 pcs_miistat |=
280 (readl(gp->regs + PCS_MIISTAT) &
281 PCS_MIISTAT_LS);
282
283 if (pcs_miistat & PCS_MIISTAT_ANC) {
284 /* The remote-fault indication is only valid
285 * when autoneg has completed.
286 */
287 if (pcs_miistat & PCS_MIISTAT_RF)
288 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
289 else
290 netdev_info(dev, "PCS AutoNEG complete\n");
291 }
292
293 if (pcs_miistat & PCS_MIISTAT_LS) {
294 netdev_info(dev, "PCS link is now up\n");
295 netif_carrier_on(gp->dev);
296 } else {
297 netdev_info(dev, "PCS link is now down\n");
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307 }
308
309 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310 {
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 netdev_err(dev, "TX MAC xmit underrun\n");
326 dev->stats.tx_fifo_errors++;
327 }
328
329 if (txmac_stat & MAC_TXSTAT_MPE) {
330 netdev_err(dev, "TX MAC max packet size error\n");
331 dev->stats.tx_errors++;
332 }
333
334 /* The rest are all cases of one of the 16-bit TX
335 * counters expiring.
336 */
337 if (txmac_stat & MAC_TXSTAT_NCE)
338 dev->stats.collisions += 0x10000;
339
340 if (txmac_stat & MAC_TXSTAT_ECE) {
341 dev->stats.tx_aborted_errors += 0x10000;
342 dev->stats.collisions += 0x10000;
343 }
344
345 if (txmac_stat & MAC_TXSTAT_LCE) {
346 dev->stats.tx_aborted_errors += 0x10000;
347 dev->stats.collisions += 0x10000;
348 }
349
350 /* We do not keep track of MAC_TXSTAT_FCE and
351 * MAC_TXSTAT_PCE events.
352 */
353 return 0;
354 }
355
356 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
357 * so we do the following.
358 *
359 * If any part of the reset goes wrong, we return 1 and that causes the
360 * whole chip to be reset.
361 */
362 static int gem_rxmac_reset(struct gem *gp)
363 {
364 struct net_device *dev = gp->dev;
365 int limit, i;
366 u64 desc_dma;
367 u32 val;
368
369 /* First, reset & disable MAC RX. */
370 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
371 for (limit = 0; limit < 5000; limit++) {
372 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
373 break;
374 udelay(10);
375 }
376 if (limit == 5000) {
377 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
378 return 1;
379 }
380
381 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
382 gp->regs + MAC_RXCFG);
383 for (limit = 0; limit < 5000; limit++) {
384 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
385 break;
386 udelay(10);
387 }
388 if (limit == 5000) {
389 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
390 return 1;
391 }
392
393 /* Second, disable RX DMA. */
394 writel(0, gp->regs + RXDMA_CFG);
395 for (limit = 0; limit < 5000; limit++) {
396 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
397 break;
398 udelay(10);
399 }
400 if (limit == 5000) {
401 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
402 return 1;
403 }
404
405 udelay(5000);
406
407 /* Execute RX reset command. */
408 writel(gp->swrst_base | GREG_SWRST_RXRST,
409 gp->regs + GREG_SWRST);
410 for (limit = 0; limit < 5000; limit++) {
411 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
412 break;
413 udelay(10);
414 }
415 if (limit == 5000) {
416 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
417 return 1;
418 }
419
420 /* Refresh the RX ring. */
421 for (i = 0; i < RX_RING_SIZE; i++) {
422 struct gem_rxd *rxd = &gp->init_block->rxd[i];
423
424 if (gp->rx_skbs[i] == NULL) {
425 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
426 return 1;
427 }
428
429 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
430 }
431 gp->rx_new = gp->rx_old = 0;
432
433 /* Now we must reprogram the rest of RX unit. */
434 desc_dma = (u64) gp->gblock_dvma;
435 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
436 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
437 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
438 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
439 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
440 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
441 writel(val, gp->regs + RXDMA_CFG);
442 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
443 writel(((5 & RXDMA_BLANK_IPKTS) |
444 ((8 << 12) & RXDMA_BLANK_ITIME)),
445 gp->regs + RXDMA_BLANK);
446 else
447 writel(((5 & RXDMA_BLANK_IPKTS) |
448 ((4 << 12) & RXDMA_BLANK_ITIME)),
449 gp->regs + RXDMA_BLANK);
450 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
451 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
452 writel(val, gp->regs + RXDMA_PTHRESH);
453 val = readl(gp->regs + RXDMA_CFG);
454 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
455 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
456 val = readl(gp->regs + MAC_RXCFG);
457 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
458
459 return 0;
460 }
461
462 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
463 {
464 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
465 int ret = 0;
466
467 if (netif_msg_intr(gp))
468 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
469 gp->dev->name, rxmac_stat);
470
471 if (rxmac_stat & MAC_RXSTAT_OFLW) {
472 u32 smac = readl(gp->regs + MAC_SMACHINE);
473
474 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
475 dev->stats.rx_over_errors++;
476 dev->stats.rx_fifo_errors++;
477
478 ret = gem_rxmac_reset(gp);
479 }
480
481 if (rxmac_stat & MAC_RXSTAT_ACE)
482 dev->stats.rx_frame_errors += 0x10000;
483
484 if (rxmac_stat & MAC_RXSTAT_CCE)
485 dev->stats.rx_crc_errors += 0x10000;
486
487 if (rxmac_stat & MAC_RXSTAT_LCE)
488 dev->stats.rx_length_errors += 0x10000;
489
490 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
491 * events.
492 */
493 return ret;
494 }
495
496 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
497 {
498 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
499
500 if (netif_msg_intr(gp))
501 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
502 gp->dev->name, mac_cstat);
503
504 /* This interrupt is just for pause frame and pause
505 * tracking. It is useful for diagnostics and debug
506 * but probably by default we will mask these events.
507 */
508 if (mac_cstat & MAC_CSTAT_PS)
509 gp->pause_entered++;
510
511 if (mac_cstat & MAC_CSTAT_PRCV)
512 gp->pause_last_time_recvd = (mac_cstat >> 16);
513
514 return 0;
515 }
516
517 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
518 {
519 u32 mif_status = readl(gp->regs + MIF_STATUS);
520 u32 reg_val, changed_bits;
521
522 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
523 changed_bits = (mif_status & MIF_STATUS_STAT);
524
525 gem_handle_mif_event(gp, reg_val, changed_bits);
526
527 return 0;
528 }
529
530 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
531 {
532 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
533
534 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
535 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
536 netdev_err(dev, "PCI error [%04x]", pci_estat);
537
538 if (pci_estat & GREG_PCIESTAT_BADACK)
539 pr_cont(" <No ACK64# during ABS64 cycle>");
540 if (pci_estat & GREG_PCIESTAT_DTRTO)
541 pr_cont(" <Delayed transaction timeout>");
542 if (pci_estat & GREG_PCIESTAT_OTHER)
543 pr_cont(" <other>");
544 pr_cont("\n");
545 } else {
546 pci_estat |= GREG_PCIESTAT_OTHER;
547 netdev_err(dev, "PCI error\n");
548 }
549
550 if (pci_estat & GREG_PCIESTAT_OTHER) {
551 u16 pci_cfg_stat;
552
553 /* Interrogate PCI config space for the
554 * true cause.
555 */
556 pci_read_config_word(gp->pdev, PCI_STATUS,
557 &pci_cfg_stat);
558 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
559 pci_cfg_stat);
560 if (pci_cfg_stat & PCI_STATUS_PARITY)
561 netdev_err(dev, "PCI parity error detected\n");
562 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
563 netdev_err(dev, "PCI target abort\n");
564 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
565 netdev_err(dev, "PCI master acks target abort\n");
566 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
567 netdev_err(dev, "PCI master abort\n");
568 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
569 netdev_err(dev, "PCI system error SERR#\n");
570 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
571 netdev_err(dev, "PCI parity error\n");
572
573 /* Write the error bits back to clear them. */
574 pci_cfg_stat &= (PCI_STATUS_PARITY |
575 PCI_STATUS_SIG_TARGET_ABORT |
576 PCI_STATUS_REC_TARGET_ABORT |
577 PCI_STATUS_REC_MASTER_ABORT |
578 PCI_STATUS_SIG_SYSTEM_ERROR |
579 PCI_STATUS_DETECTED_PARITY);
580 pci_write_config_word(gp->pdev,
581 PCI_STATUS, pci_cfg_stat);
582 }
583
584 /* For all PCI errors, we should reset the chip. */
585 return 1;
586 }
587
588 /* All non-normal interrupt conditions get serviced here.
589 * Returns non-zero if we should just exit the interrupt
590 * handler right now (ie. if we reset the card which invalidates
591 * all of the other original irq status bits).
592 */
593 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
594 {
595 if (gem_status & GREG_STAT_RXNOBUF) {
596 /* Frame arrived, no free RX buffers available. */
597 if (netif_msg_rx_err(gp))
598 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
599 gp->dev->name);
600 dev->stats.rx_dropped++;
601 }
602
603 if (gem_status & GREG_STAT_RXTAGERR) {
604 /* corrupt RX tag framing */
605 if (netif_msg_rx_err(gp))
606 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
607 gp->dev->name);
608 dev->stats.rx_errors++;
609
610 return 1;
611 }
612
613 if (gem_status & GREG_STAT_PCS) {
614 if (gem_pcs_interrupt(dev, gp, gem_status))
615 return 1;
616 }
617
618 if (gem_status & GREG_STAT_TXMAC) {
619 if (gem_txmac_interrupt(dev, gp, gem_status))
620 return 1;
621 }
622
623 if (gem_status & GREG_STAT_RXMAC) {
624 if (gem_rxmac_interrupt(dev, gp, gem_status))
625 return 1;
626 }
627
628 if (gem_status & GREG_STAT_MAC) {
629 if (gem_mac_interrupt(dev, gp, gem_status))
630 return 1;
631 }
632
633 if (gem_status & GREG_STAT_MIF) {
634 if (gem_mif_interrupt(dev, gp, gem_status))
635 return 1;
636 }
637
638 if (gem_status & GREG_STAT_PCIERR) {
639 if (gem_pci_interrupt(dev, gp, gem_status))
640 return 1;
641 }
642
643 return 0;
644 }
645
646 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
647 {
648 int entry, limit;
649
650 entry = gp->tx_old;
651 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
652 while (entry != limit) {
653 struct sk_buff *skb;
654 struct gem_txd *txd;
655 dma_addr_t dma_addr;
656 u32 dma_len;
657 int frag;
658
659 if (netif_msg_tx_done(gp))
660 printk(KERN_DEBUG "%s: tx done, slot %d\n",
661 gp->dev->name, entry);
662 skb = gp->tx_skbs[entry];
663 if (skb_shinfo(skb)->nr_frags) {
664 int last = entry + skb_shinfo(skb)->nr_frags;
665 int walk = entry;
666 int incomplete = 0;
667
668 last &= (TX_RING_SIZE - 1);
669 for (;;) {
670 walk = NEXT_TX(walk);
671 if (walk == limit)
672 incomplete = 1;
673 if (walk == last)
674 break;
675 }
676 if (incomplete)
677 break;
678 }
679 gp->tx_skbs[entry] = NULL;
680 dev->stats.tx_bytes += skb->len;
681
682 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
683 txd = &gp->init_block->txd[entry];
684
685 dma_addr = le64_to_cpu(txd->buffer);
686 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
687
688 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
689 entry = NEXT_TX(entry);
690 }
691
692 dev->stats.tx_packets++;
693 dev_kfree_skb(skb);
694 }
695 gp->tx_old = entry;
696
697 /* Need to make the tx_old update visible to gem_start_xmit()
698 * before checking for netif_queue_stopped(). Without the
699 * memory barrier, there is a small possibility that gem_start_xmit()
700 * will miss it and cause the queue to be stopped forever.
701 */
702 smp_mb();
703
704 if (unlikely(netif_queue_stopped(dev) &&
705 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
706 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
707
708 __netif_tx_lock(txq, smp_processor_id());
709 if (netif_queue_stopped(dev) &&
710 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
711 netif_wake_queue(dev);
712 __netif_tx_unlock(txq);
713 }
714 }
715
716 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
717 {
718 int cluster_start, curr, count, kick;
719
720 cluster_start = curr = (gp->rx_new & ~(4 - 1));
721 count = 0;
722 kick = -1;
723 wmb();
724 while (curr != limit) {
725 curr = NEXT_RX(curr);
726 if (++count == 4) {
727 struct gem_rxd *rxd =
728 &gp->init_block->rxd[cluster_start];
729 for (;;) {
730 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
731 rxd++;
732 cluster_start = NEXT_RX(cluster_start);
733 if (cluster_start == curr)
734 break;
735 }
736 kick = curr;
737 count = 0;
738 }
739 }
740 if (kick >= 0) {
741 mb();
742 writel(kick, gp->regs + RXDMA_KICK);
743 }
744 }
745
746 #define ALIGNED_RX_SKB_ADDR(addr) \
747 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
748 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
749 gfp_t gfp_flags)
750 {
751 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
752
753 if (likely(skb)) {
754 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
755 skb_reserve(skb, offset);
756 skb->dev = dev;
757 }
758 return skb;
759 }
760
761 static int gem_rx(struct gem *gp, int work_to_do)
762 {
763 struct net_device *dev = gp->dev;
764 int entry, drops, work_done = 0;
765 u32 done;
766 __sum16 csum;
767
768 if (netif_msg_rx_status(gp))
769 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
770 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
771
772 entry = gp->rx_new;
773 drops = 0;
774 done = readl(gp->regs + RXDMA_DONE);
775 for (;;) {
776 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
777 struct sk_buff *skb;
778 u64 status = le64_to_cpu(rxd->status_word);
779 dma_addr_t dma_addr;
780 int len;
781
782 if ((status & RXDCTRL_OWN) != 0)
783 break;
784
785 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
786 break;
787
788 /* When writing back RX descriptor, GEM writes status
789 * then buffer address, possibly in separate transactions.
790 * If we don't wait for the chip to write both, we could
791 * post a new buffer to this descriptor then have GEM spam
792 * on the buffer address. We sync on the RX completion
793 * register to prevent this from happening.
794 */
795 if (entry == done) {
796 done = readl(gp->regs + RXDMA_DONE);
797 if (entry == done)
798 break;
799 }
800
801 /* We can now account for the work we're about to do */
802 work_done++;
803
804 skb = gp->rx_skbs[entry];
805
806 len = (status & RXDCTRL_BUFSZ) >> 16;
807 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
808 dev->stats.rx_errors++;
809 if (len < ETH_ZLEN)
810 dev->stats.rx_length_errors++;
811 if (len & RXDCTRL_BAD)
812 dev->stats.rx_crc_errors++;
813
814 /* We'll just return it to GEM. */
815 drop_it:
816 dev->stats.rx_dropped++;
817 goto next;
818 }
819
820 dma_addr = le64_to_cpu(rxd->buffer);
821 if (len > RX_COPY_THRESHOLD) {
822 struct sk_buff *new_skb;
823
824 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
825 if (new_skb == NULL) {
826 drops++;
827 goto drop_it;
828 }
829 pci_unmap_page(gp->pdev, dma_addr,
830 RX_BUF_ALLOC_SIZE(gp),
831 PCI_DMA_FROMDEVICE);
832 gp->rx_skbs[entry] = new_skb;
833 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
834 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
835 virt_to_page(new_skb->data),
836 offset_in_page(new_skb->data),
837 RX_BUF_ALLOC_SIZE(gp),
838 PCI_DMA_FROMDEVICE));
839 skb_reserve(new_skb, RX_OFFSET);
840
841 /* Trim the original skb for the netif. */
842 skb_trim(skb, len);
843 } else {
844 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
845
846 if (copy_skb == NULL) {
847 drops++;
848 goto drop_it;
849 }
850
851 skb_reserve(copy_skb, 2);
852 skb_put(copy_skb, len);
853 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
854 skb_copy_from_linear_data(skb, copy_skb->data, len);
855 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
856
857 /* We'll reuse the original ring buffer. */
858 skb = copy_skb;
859 }
860
861 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
862 skb->csum = csum_unfold(csum);
863 skb->ip_summed = CHECKSUM_COMPLETE;
864 skb->protocol = eth_type_trans(skb, gp->dev);
865
866 napi_gro_receive(&gp->napi, skb);
867
868 dev->stats.rx_packets++;
869 dev->stats.rx_bytes += len;
870
871 next:
872 entry = NEXT_RX(entry);
873 }
874
875 gem_post_rxds(gp, entry);
876
877 gp->rx_new = entry;
878
879 if (drops)
880 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
881
882 return work_done;
883 }
884
885 static int gem_poll(struct napi_struct *napi, int budget)
886 {
887 struct gem *gp = container_of(napi, struct gem, napi);
888 struct net_device *dev = gp->dev;
889 int work_done;
890
891 work_done = 0;
892 do {
893 /* Handle anomalies */
894 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
895 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
896 int reset;
897
898 /* We run the abnormal interrupt handling code with
899 * the Tx lock. It only resets the Rx portion of the
900 * chip, but we need to guard it against DMA being
901 * restarted by the link poll timer
902 */
903 __netif_tx_lock(txq, smp_processor_id());
904 reset = gem_abnormal_irq(dev, gp, gp->status);
905 __netif_tx_unlock(txq);
906 if (reset) {
907 gem_schedule_reset(gp);
908 napi_complete(napi);
909 return work_done;
910 }
911 }
912
913 /* Run TX completion thread */
914 gem_tx(dev, gp, gp->status);
915
916 /* Run RX thread. We don't use any locking here,
917 * code willing to do bad things - like cleaning the
918 * rx ring - must call napi_disable(), which
919 * schedule_timeout()'s if polling is already disabled.
920 */
921 work_done += gem_rx(gp, budget - work_done);
922
923 if (work_done >= budget)
924 return work_done;
925
926 gp->status = readl(gp->regs + GREG_STAT);
927 } while (gp->status & GREG_STAT_NAPI);
928
929 napi_complete(napi);
930 gem_enable_ints(gp);
931
932 return work_done;
933 }
934
935 static irqreturn_t gem_interrupt(int irq, void *dev_id)
936 {
937 struct net_device *dev = dev_id;
938 struct gem *gp = netdev_priv(dev);
939
940 if (napi_schedule_prep(&gp->napi)) {
941 u32 gem_status = readl(gp->regs + GREG_STAT);
942
943 if (unlikely(gem_status == 0)) {
944 napi_enable(&gp->napi);
945 return IRQ_NONE;
946 }
947 if (netif_msg_intr(gp))
948 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
949 gp->dev->name, gem_status);
950
951 gp->status = gem_status;
952 gem_disable_ints(gp);
953 __napi_schedule(&gp->napi);
954 }
955
956 /* If polling was disabled at the time we received that
957 * interrupt, we may return IRQ_HANDLED here while we
958 * should return IRQ_NONE. No big deal...
959 */
960 return IRQ_HANDLED;
961 }
962
963 #ifdef CONFIG_NET_POLL_CONTROLLER
964 static void gem_poll_controller(struct net_device *dev)
965 {
966 struct gem *gp = netdev_priv(dev);
967
968 disable_irq(gp->pdev->irq);
969 gem_interrupt(gp->pdev->irq, dev);
970 enable_irq(gp->pdev->irq);
971 }
972 #endif
973
974 static void gem_tx_timeout(struct net_device *dev)
975 {
976 struct gem *gp = netdev_priv(dev);
977
978 netdev_err(dev, "transmit timed out, resetting\n");
979
980 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
981 readl(gp->regs + TXDMA_CFG),
982 readl(gp->regs + MAC_TXSTAT),
983 readl(gp->regs + MAC_TXCFG));
984 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
985 readl(gp->regs + RXDMA_CFG),
986 readl(gp->regs + MAC_RXSTAT),
987 readl(gp->regs + MAC_RXCFG));
988
989 gem_schedule_reset(gp);
990 }
991
992 static __inline__ int gem_intme(int entry)
993 {
994 /* Algorithm: IRQ every 1/2 of descriptors. */
995 if (!(entry & ((TX_RING_SIZE>>1)-1)))
996 return 1;
997
998 return 0;
999 }
1000
1001 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
1002 struct net_device *dev)
1003 {
1004 struct gem *gp = netdev_priv(dev);
1005 int entry;
1006 u64 ctrl;
1007
1008 ctrl = 0;
1009 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1010 const u64 csum_start_off = skb_checksum_start_offset(skb);
1011 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1012
1013 ctrl = (TXDCTRL_CENAB |
1014 (csum_start_off << 15) |
1015 (csum_stuff_off << 21));
1016 }
1017
1018 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1019 /* This is a hard error, log it. */
1020 if (!netif_queue_stopped(dev)) {
1021 netif_stop_queue(dev);
1022 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1023 }
1024 return NETDEV_TX_BUSY;
1025 }
1026
1027 entry = gp->tx_new;
1028 gp->tx_skbs[entry] = skb;
1029
1030 if (skb_shinfo(skb)->nr_frags == 0) {
1031 struct gem_txd *txd = &gp->init_block->txd[entry];
1032 dma_addr_t mapping;
1033 u32 len;
1034
1035 len = skb->len;
1036 mapping = pci_map_page(gp->pdev,
1037 virt_to_page(skb->data),
1038 offset_in_page(skb->data),
1039 len, PCI_DMA_TODEVICE);
1040 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1041 if (gem_intme(entry))
1042 ctrl |= TXDCTRL_INTME;
1043 txd->buffer = cpu_to_le64(mapping);
1044 wmb();
1045 txd->control_word = cpu_to_le64(ctrl);
1046 entry = NEXT_TX(entry);
1047 } else {
1048 struct gem_txd *txd;
1049 u32 first_len;
1050 u64 intme;
1051 dma_addr_t first_mapping;
1052 int frag, first_entry = entry;
1053
1054 intme = 0;
1055 if (gem_intme(entry))
1056 intme |= TXDCTRL_INTME;
1057
1058 /* We must give this initial chunk to the device last.
1059 * Otherwise we could race with the device.
1060 */
1061 first_len = skb_headlen(skb);
1062 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1063 offset_in_page(skb->data),
1064 first_len, PCI_DMA_TODEVICE);
1065 entry = NEXT_TX(entry);
1066
1067 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1068 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1069 u32 len;
1070 dma_addr_t mapping;
1071 u64 this_ctrl;
1072
1073 len = this_frag->size;
1074 mapping = pci_map_page(gp->pdev,
1075 this_frag->page,
1076 this_frag->page_offset,
1077 len, PCI_DMA_TODEVICE);
1078 this_ctrl = ctrl;
1079 if (frag == skb_shinfo(skb)->nr_frags - 1)
1080 this_ctrl |= TXDCTRL_EOF;
1081
1082 txd = &gp->init_block->txd[entry];
1083 txd->buffer = cpu_to_le64(mapping);
1084 wmb();
1085 txd->control_word = cpu_to_le64(this_ctrl | len);
1086
1087 if (gem_intme(entry))
1088 intme |= TXDCTRL_INTME;
1089
1090 entry = NEXT_TX(entry);
1091 }
1092 txd = &gp->init_block->txd[first_entry];
1093 txd->buffer = cpu_to_le64(first_mapping);
1094 wmb();
1095 txd->control_word =
1096 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1097 }
1098
1099 gp->tx_new = entry;
1100 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1101 netif_stop_queue(dev);
1102
1103 /* netif_stop_queue() must be done before checking
1104 * checking tx index in TX_BUFFS_AVAIL() below, because
1105 * in gem_tx(), we update tx_old before checking for
1106 * netif_queue_stopped().
1107 */
1108 smp_mb();
1109 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1110 netif_wake_queue(dev);
1111 }
1112 if (netif_msg_tx_queued(gp))
1113 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1114 dev->name, entry, skb->len);
1115 mb();
1116 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1117
1118 return NETDEV_TX_OK;
1119 }
1120
1121 static void gem_pcs_reset(struct gem *gp)
1122 {
1123 int limit;
1124 u32 val;
1125
1126 /* Reset PCS unit. */
1127 val = readl(gp->regs + PCS_MIICTRL);
1128 val |= PCS_MIICTRL_RST;
1129 writel(val, gp->regs + PCS_MIICTRL);
1130
1131 limit = 32;
1132 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1133 udelay(100);
1134 if (limit-- <= 0)
1135 break;
1136 }
1137 if (limit < 0)
1138 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1139 }
1140
1141 static void gem_pcs_reinit_adv(struct gem *gp)
1142 {
1143 u32 val;
1144
1145 /* Make sure PCS is disabled while changing advertisement
1146 * configuration.
1147 */
1148 val = readl(gp->regs + PCS_CFG);
1149 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1150 writel(val, gp->regs + PCS_CFG);
1151
1152 /* Advertise all capabilities except asymmetric
1153 * pause.
1154 */
1155 val = readl(gp->regs + PCS_MIIADV);
1156 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1157 PCS_MIIADV_SP | PCS_MIIADV_AP);
1158 writel(val, gp->regs + PCS_MIIADV);
1159
1160 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1161 * and re-enable PCS.
1162 */
1163 val = readl(gp->regs + PCS_MIICTRL);
1164 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1165 val &= ~PCS_MIICTRL_WB;
1166 writel(val, gp->regs + PCS_MIICTRL);
1167
1168 val = readl(gp->regs + PCS_CFG);
1169 val |= PCS_CFG_ENABLE;
1170 writel(val, gp->regs + PCS_CFG);
1171
1172 /* Make sure serialink loopback is off. The meaning
1173 * of this bit is logically inverted based upon whether
1174 * you are in Serialink or SERDES mode.
1175 */
1176 val = readl(gp->regs + PCS_SCTRL);
1177 if (gp->phy_type == phy_serialink)
1178 val &= ~PCS_SCTRL_LOOP;
1179 else
1180 val |= PCS_SCTRL_LOOP;
1181 writel(val, gp->regs + PCS_SCTRL);
1182 }
1183
1184 #define STOP_TRIES 32
1185
1186 static void gem_reset(struct gem *gp)
1187 {
1188 int limit;
1189 u32 val;
1190
1191 /* Make sure we won't get any more interrupts */
1192 writel(0xffffffff, gp->regs + GREG_IMASK);
1193
1194 /* Reset the chip */
1195 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1196 gp->regs + GREG_SWRST);
1197
1198 limit = STOP_TRIES;
1199
1200 do {
1201 udelay(20);
1202 val = readl(gp->regs + GREG_SWRST);
1203 if (limit-- <= 0)
1204 break;
1205 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1206
1207 if (limit < 0)
1208 netdev_err(gp->dev, "SW reset is ghetto\n");
1209
1210 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1211 gem_pcs_reinit_adv(gp);
1212 }
1213
1214 static void gem_start_dma(struct gem *gp)
1215 {
1216 u32 val;
1217
1218 /* We are ready to rock, turn everything on. */
1219 val = readl(gp->regs + TXDMA_CFG);
1220 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1221 val = readl(gp->regs + RXDMA_CFG);
1222 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1223 val = readl(gp->regs + MAC_TXCFG);
1224 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1225 val = readl(gp->regs + MAC_RXCFG);
1226 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1227
1228 (void) readl(gp->regs + MAC_RXCFG);
1229 udelay(100);
1230
1231 gem_enable_ints(gp);
1232
1233 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1234 }
1235
1236 /* DMA won't be actually stopped before about 4ms tho ...
1237 */
1238 static void gem_stop_dma(struct gem *gp)
1239 {
1240 u32 val;
1241
1242 /* We are done rocking, turn everything off. */
1243 val = readl(gp->regs + TXDMA_CFG);
1244 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1245 val = readl(gp->regs + RXDMA_CFG);
1246 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1247 val = readl(gp->regs + MAC_TXCFG);
1248 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1249 val = readl(gp->regs + MAC_RXCFG);
1250 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1251
1252 (void) readl(gp->regs + MAC_RXCFG);
1253
1254 /* Need to wait a bit ... done by the caller */
1255 }
1256
1257
1258 // XXX dbl check what that function should do when called on PCS PHY
1259 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1260 {
1261 u32 advertise, features;
1262 int autoneg;
1263 int speed;
1264 int duplex;
1265
1266 if (gp->phy_type != phy_mii_mdio0 &&
1267 gp->phy_type != phy_mii_mdio1)
1268 goto non_mii;
1269
1270 /* Setup advertise */
1271 if (found_mii_phy(gp))
1272 features = gp->phy_mii.def->features;
1273 else
1274 features = 0;
1275
1276 advertise = features & ADVERTISE_MASK;
1277 if (gp->phy_mii.advertising != 0)
1278 advertise &= gp->phy_mii.advertising;
1279
1280 autoneg = gp->want_autoneg;
1281 speed = gp->phy_mii.speed;
1282 duplex = gp->phy_mii.duplex;
1283
1284 /* Setup link parameters */
1285 if (!ep)
1286 goto start_aneg;
1287 if (ep->autoneg == AUTONEG_ENABLE) {
1288 advertise = ep->advertising;
1289 autoneg = 1;
1290 } else {
1291 autoneg = 0;
1292 speed = ethtool_cmd_speed(ep);
1293 duplex = ep->duplex;
1294 }
1295
1296 start_aneg:
1297 /* Sanitize settings based on PHY capabilities */
1298 if ((features & SUPPORTED_Autoneg) == 0)
1299 autoneg = 0;
1300 if (speed == SPEED_1000 &&
1301 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1302 speed = SPEED_100;
1303 if (speed == SPEED_100 &&
1304 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1305 speed = SPEED_10;
1306 if (duplex == DUPLEX_FULL &&
1307 !(features & (SUPPORTED_1000baseT_Full |
1308 SUPPORTED_100baseT_Full |
1309 SUPPORTED_10baseT_Full)))
1310 duplex = DUPLEX_HALF;
1311 if (speed == 0)
1312 speed = SPEED_10;
1313
1314 /* If we are asleep, we don't try to actually setup the PHY, we
1315 * just store the settings
1316 */
1317 if (!netif_device_present(gp->dev)) {
1318 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1319 gp->phy_mii.speed = speed;
1320 gp->phy_mii.duplex = duplex;
1321 return;
1322 }
1323
1324 /* Configure PHY & start aneg */
1325 gp->want_autoneg = autoneg;
1326 if (autoneg) {
1327 if (found_mii_phy(gp))
1328 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1329 gp->lstate = link_aneg;
1330 } else {
1331 if (found_mii_phy(gp))
1332 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1333 gp->lstate = link_force_ok;
1334 }
1335
1336 non_mii:
1337 gp->timer_ticks = 0;
1338 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1339 }
1340
1341 /* A link-up condition has occurred, initialize and enable the
1342 * rest of the chip.
1343 */
1344 static int gem_set_link_modes(struct gem *gp)
1345 {
1346 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1347 int full_duplex, speed, pause;
1348 u32 val;
1349
1350 full_duplex = 0;
1351 speed = SPEED_10;
1352 pause = 0;
1353
1354 if (found_mii_phy(gp)) {
1355 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1356 return 1;
1357 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1358 speed = gp->phy_mii.speed;
1359 pause = gp->phy_mii.pause;
1360 } else if (gp->phy_type == phy_serialink ||
1361 gp->phy_type == phy_serdes) {
1362 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1363
1364 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1365 full_duplex = 1;
1366 speed = SPEED_1000;
1367 }
1368
1369 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1370 speed, (full_duplex ? "full" : "half"));
1371
1372
1373 /* We take the tx queue lock to avoid collisions between
1374 * this code, the tx path and the NAPI-driven error path
1375 */
1376 __netif_tx_lock(txq, smp_processor_id());
1377
1378 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1379 if (full_duplex) {
1380 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1381 } else {
1382 /* MAC_TXCFG_NBO must be zero. */
1383 }
1384 writel(val, gp->regs + MAC_TXCFG);
1385
1386 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1387 if (!full_duplex &&
1388 (gp->phy_type == phy_mii_mdio0 ||
1389 gp->phy_type == phy_mii_mdio1)) {
1390 val |= MAC_XIFCFG_DISE;
1391 } else if (full_duplex) {
1392 val |= MAC_XIFCFG_FLED;
1393 }
1394
1395 if (speed == SPEED_1000)
1396 val |= (MAC_XIFCFG_GMII);
1397
1398 writel(val, gp->regs + MAC_XIFCFG);
1399
1400 /* If gigabit and half-duplex, enable carrier extension
1401 * mode. Else, disable it.
1402 */
1403 if (speed == SPEED_1000 && !full_duplex) {
1404 val = readl(gp->regs + MAC_TXCFG);
1405 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1406
1407 val = readl(gp->regs + MAC_RXCFG);
1408 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1409 } else {
1410 val = readl(gp->regs + MAC_TXCFG);
1411 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1412
1413 val = readl(gp->regs + MAC_RXCFG);
1414 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1415 }
1416
1417 if (gp->phy_type == phy_serialink ||
1418 gp->phy_type == phy_serdes) {
1419 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1420
1421 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1422 pause = 1;
1423 }
1424
1425 if (!full_duplex)
1426 writel(512, gp->regs + MAC_STIME);
1427 else
1428 writel(64, gp->regs + MAC_STIME);
1429 val = readl(gp->regs + MAC_MCCFG);
1430 if (pause)
1431 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1432 else
1433 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1434 writel(val, gp->regs + MAC_MCCFG);
1435
1436 gem_start_dma(gp);
1437
1438 __netif_tx_unlock(txq);
1439
1440 if (netif_msg_link(gp)) {
1441 if (pause) {
1442 netdev_info(gp->dev,
1443 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1444 gp->rx_fifo_sz,
1445 gp->rx_pause_off,
1446 gp->rx_pause_on);
1447 } else {
1448 netdev_info(gp->dev, "Pause is disabled\n");
1449 }
1450 }
1451
1452 return 0;
1453 }
1454
1455 static int gem_mdio_link_not_up(struct gem *gp)
1456 {
1457 switch (gp->lstate) {
1458 case link_force_ret:
1459 netif_info(gp, link, gp->dev,
1460 "Autoneg failed again, keeping forced mode\n");
1461 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1462 gp->last_forced_speed, DUPLEX_HALF);
1463 gp->timer_ticks = 5;
1464 gp->lstate = link_force_ok;
1465 return 0;
1466 case link_aneg:
1467 /* We try forced modes after a failed aneg only on PHYs that don't
1468 * have "magic_aneg" bit set, which means they internally do the
1469 * while forced-mode thingy. On these, we just restart aneg
1470 */
1471 if (gp->phy_mii.def->magic_aneg)
1472 return 1;
1473 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1474 /* Try forced modes. */
1475 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1476 DUPLEX_HALF);
1477 gp->timer_ticks = 5;
1478 gp->lstate = link_force_try;
1479 return 0;
1480 case link_force_try:
1481 /* Downgrade from 100 to 10 Mbps if necessary.
1482 * If already at 10Mbps, warn user about the
1483 * situation every 10 ticks.
1484 */
1485 if (gp->phy_mii.speed == SPEED_100) {
1486 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1487 DUPLEX_HALF);
1488 gp->timer_ticks = 5;
1489 netif_info(gp, link, gp->dev,
1490 "switching to forced 10bt\n");
1491 return 0;
1492 } else
1493 return 1;
1494 default:
1495 return 0;
1496 }
1497 }
1498
1499 static void gem_link_timer(unsigned long data)
1500 {
1501 struct gem *gp = (struct gem *) data;
1502 struct net_device *dev = gp->dev;
1503 int restart_aneg = 0;
1504
1505 /* There's no point doing anything if we're going to be reset */
1506 if (gp->reset_task_pending)
1507 return;
1508
1509 if (gp->phy_type == phy_serialink ||
1510 gp->phy_type == phy_serdes) {
1511 u32 val = readl(gp->regs + PCS_MIISTAT);
1512
1513 if (!(val & PCS_MIISTAT_LS))
1514 val = readl(gp->regs + PCS_MIISTAT);
1515
1516 if ((val & PCS_MIISTAT_LS) != 0) {
1517 if (gp->lstate == link_up)
1518 goto restart;
1519
1520 gp->lstate = link_up;
1521 netif_carrier_on(dev);
1522 (void)gem_set_link_modes(gp);
1523 }
1524 goto restart;
1525 }
1526 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1527 /* Ok, here we got a link. If we had it due to a forced
1528 * fallback, and we were configured for autoneg, we do
1529 * retry a short autoneg pass. If you know your hub is
1530 * broken, use ethtool ;)
1531 */
1532 if (gp->lstate == link_force_try && gp->want_autoneg) {
1533 gp->lstate = link_force_ret;
1534 gp->last_forced_speed = gp->phy_mii.speed;
1535 gp->timer_ticks = 5;
1536 if (netif_msg_link(gp))
1537 netdev_info(dev,
1538 "Got link after fallback, retrying autoneg once...\n");
1539 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1540 } else if (gp->lstate != link_up) {
1541 gp->lstate = link_up;
1542 netif_carrier_on(dev);
1543 if (gem_set_link_modes(gp))
1544 restart_aneg = 1;
1545 }
1546 } else {
1547 /* If the link was previously up, we restart the
1548 * whole process
1549 */
1550 if (gp->lstate == link_up) {
1551 gp->lstate = link_down;
1552 netif_info(gp, link, dev, "Link down\n");
1553 netif_carrier_off(dev);
1554 gem_schedule_reset(gp);
1555 /* The reset task will restart the timer */
1556 return;
1557 } else if (++gp->timer_ticks > 10) {
1558 if (found_mii_phy(gp))
1559 restart_aneg = gem_mdio_link_not_up(gp);
1560 else
1561 restart_aneg = 1;
1562 }
1563 }
1564 if (restart_aneg) {
1565 gem_begin_auto_negotiation(gp, NULL);
1566 return;
1567 }
1568 restart:
1569 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1570 }
1571
1572 static void gem_clean_rings(struct gem *gp)
1573 {
1574 struct gem_init_block *gb = gp->init_block;
1575 struct sk_buff *skb;
1576 int i;
1577 dma_addr_t dma_addr;
1578
1579 for (i = 0; i < RX_RING_SIZE; i++) {
1580 struct gem_rxd *rxd;
1581
1582 rxd = &gb->rxd[i];
1583 if (gp->rx_skbs[i] != NULL) {
1584 skb = gp->rx_skbs[i];
1585 dma_addr = le64_to_cpu(rxd->buffer);
1586 pci_unmap_page(gp->pdev, dma_addr,
1587 RX_BUF_ALLOC_SIZE(gp),
1588 PCI_DMA_FROMDEVICE);
1589 dev_kfree_skb_any(skb);
1590 gp->rx_skbs[i] = NULL;
1591 }
1592 rxd->status_word = 0;
1593 wmb();
1594 rxd->buffer = 0;
1595 }
1596
1597 for (i = 0; i < TX_RING_SIZE; i++) {
1598 if (gp->tx_skbs[i] != NULL) {
1599 struct gem_txd *txd;
1600 int frag;
1601
1602 skb = gp->tx_skbs[i];
1603 gp->tx_skbs[i] = NULL;
1604
1605 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1606 int ent = i & (TX_RING_SIZE - 1);
1607
1608 txd = &gb->txd[ent];
1609 dma_addr = le64_to_cpu(txd->buffer);
1610 pci_unmap_page(gp->pdev, dma_addr,
1611 le64_to_cpu(txd->control_word) &
1612 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1613
1614 if (frag != skb_shinfo(skb)->nr_frags)
1615 i++;
1616 }
1617 dev_kfree_skb_any(skb);
1618 }
1619 }
1620 }
1621
1622 static void gem_init_rings(struct gem *gp)
1623 {
1624 struct gem_init_block *gb = gp->init_block;
1625 struct net_device *dev = gp->dev;
1626 int i;
1627 dma_addr_t dma_addr;
1628
1629 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1630
1631 gem_clean_rings(gp);
1632
1633 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1634 (unsigned)VLAN_ETH_FRAME_LEN);
1635
1636 for (i = 0; i < RX_RING_SIZE; i++) {
1637 struct sk_buff *skb;
1638 struct gem_rxd *rxd = &gb->rxd[i];
1639
1640 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1641 if (!skb) {
1642 rxd->buffer = 0;
1643 rxd->status_word = 0;
1644 continue;
1645 }
1646
1647 gp->rx_skbs[i] = skb;
1648 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1649 dma_addr = pci_map_page(gp->pdev,
1650 virt_to_page(skb->data),
1651 offset_in_page(skb->data),
1652 RX_BUF_ALLOC_SIZE(gp),
1653 PCI_DMA_FROMDEVICE);
1654 rxd->buffer = cpu_to_le64(dma_addr);
1655 wmb();
1656 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1657 skb_reserve(skb, RX_OFFSET);
1658 }
1659
1660 for (i = 0; i < TX_RING_SIZE; i++) {
1661 struct gem_txd *txd = &gb->txd[i];
1662
1663 txd->control_word = 0;
1664 wmb();
1665 txd->buffer = 0;
1666 }
1667 wmb();
1668 }
1669
1670 /* Init PHY interface and start link poll state machine */
1671 static void gem_init_phy(struct gem *gp)
1672 {
1673 u32 mifcfg;
1674
1675 /* Revert MIF CFG setting done on stop_phy */
1676 mifcfg = readl(gp->regs + MIF_CFG);
1677 mifcfg &= ~MIF_CFG_BBMODE;
1678 writel(mifcfg, gp->regs + MIF_CFG);
1679
1680 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1681 int i;
1682
1683 /* Those delay sucks, the HW seem to love them though, I'll
1684 * serisouly consider breaking some locks here to be able
1685 * to schedule instead
1686 */
1687 for (i = 0; i < 3; i++) {
1688 #ifdef CONFIG_PPC_PMAC
1689 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1690 msleep(20);
1691 #endif
1692 /* Some PHYs used by apple have problem getting back to us,
1693 * we do an additional reset here
1694 */
1695 phy_write(gp, MII_BMCR, BMCR_RESET);
1696 msleep(20);
1697 if (phy_read(gp, MII_BMCR) != 0xffff)
1698 break;
1699 if (i == 2)
1700 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1701 }
1702 }
1703
1704 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1705 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1706 u32 val;
1707
1708 /* Init datapath mode register. */
1709 if (gp->phy_type == phy_mii_mdio0 ||
1710 gp->phy_type == phy_mii_mdio1) {
1711 val = PCS_DMODE_MGM;
1712 } else if (gp->phy_type == phy_serialink) {
1713 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1714 } else {
1715 val = PCS_DMODE_ESM;
1716 }
1717
1718 writel(val, gp->regs + PCS_DMODE);
1719 }
1720
1721 if (gp->phy_type == phy_mii_mdio0 ||
1722 gp->phy_type == phy_mii_mdio1) {
1723 /* Reset and detect MII PHY */
1724 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1725
1726 /* Init PHY */
1727 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1728 gp->phy_mii.def->ops->init(&gp->phy_mii);
1729 } else {
1730 gem_pcs_reset(gp);
1731 gem_pcs_reinit_adv(gp);
1732 }
1733
1734 /* Default aneg parameters */
1735 gp->timer_ticks = 0;
1736 gp->lstate = link_down;
1737 netif_carrier_off(gp->dev);
1738
1739 /* Print things out */
1740 if (gp->phy_type == phy_mii_mdio0 ||
1741 gp->phy_type == phy_mii_mdio1)
1742 netdev_info(gp->dev, "Found %s PHY\n",
1743 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1744
1745 gem_begin_auto_negotiation(gp, NULL);
1746 }
1747
1748 static void gem_init_dma(struct gem *gp)
1749 {
1750 u64 desc_dma = (u64) gp->gblock_dvma;
1751 u32 val;
1752
1753 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1754 writel(val, gp->regs + TXDMA_CFG);
1755
1756 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1757 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1758 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1759
1760 writel(0, gp->regs + TXDMA_KICK);
1761
1762 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1763 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1764 writel(val, gp->regs + RXDMA_CFG);
1765
1766 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1767 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1768
1769 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1770
1771 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1772 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1773 writel(val, gp->regs + RXDMA_PTHRESH);
1774
1775 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1776 writel(((5 & RXDMA_BLANK_IPKTS) |
1777 ((8 << 12) & RXDMA_BLANK_ITIME)),
1778 gp->regs + RXDMA_BLANK);
1779 else
1780 writel(((5 & RXDMA_BLANK_IPKTS) |
1781 ((4 << 12) & RXDMA_BLANK_ITIME)),
1782 gp->regs + RXDMA_BLANK);
1783 }
1784
1785 static u32 gem_setup_multicast(struct gem *gp)
1786 {
1787 u32 rxcfg = 0;
1788 int i;
1789
1790 if ((gp->dev->flags & IFF_ALLMULTI) ||
1791 (netdev_mc_count(gp->dev) > 256)) {
1792 for (i=0; i<16; i++)
1793 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1794 rxcfg |= MAC_RXCFG_HFE;
1795 } else if (gp->dev->flags & IFF_PROMISC) {
1796 rxcfg |= MAC_RXCFG_PROM;
1797 } else {
1798 u16 hash_table[16];
1799 u32 crc;
1800 struct netdev_hw_addr *ha;
1801 int i;
1802
1803 memset(hash_table, 0, sizeof(hash_table));
1804 netdev_for_each_mc_addr(ha, gp->dev) {
1805 crc = ether_crc_le(6, ha->addr);
1806 crc >>= 24;
1807 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1808 }
1809 for (i=0; i<16; i++)
1810 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1811 rxcfg |= MAC_RXCFG_HFE;
1812 }
1813
1814 return rxcfg;
1815 }
1816
1817 static void gem_init_mac(struct gem *gp)
1818 {
1819 unsigned char *e = &gp->dev->dev_addr[0];
1820
1821 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1822
1823 writel(0x00, gp->regs + MAC_IPG0);
1824 writel(0x08, gp->regs + MAC_IPG1);
1825 writel(0x04, gp->regs + MAC_IPG2);
1826 writel(0x40, gp->regs + MAC_STIME);
1827 writel(0x40, gp->regs + MAC_MINFSZ);
1828
1829 /* Ethernet payload + header + FCS + optional VLAN tag. */
1830 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1831
1832 writel(0x07, gp->regs + MAC_PASIZE);
1833 writel(0x04, gp->regs + MAC_JAMSIZE);
1834 writel(0x10, gp->regs + MAC_ATTLIM);
1835 writel(0x8808, gp->regs + MAC_MCTYPE);
1836
1837 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1838
1839 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1840 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1841 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1842
1843 writel(0, gp->regs + MAC_ADDR3);
1844 writel(0, gp->regs + MAC_ADDR4);
1845 writel(0, gp->regs + MAC_ADDR5);
1846
1847 writel(0x0001, gp->regs + MAC_ADDR6);
1848 writel(0xc200, gp->regs + MAC_ADDR7);
1849 writel(0x0180, gp->regs + MAC_ADDR8);
1850
1851 writel(0, gp->regs + MAC_AFILT0);
1852 writel(0, gp->regs + MAC_AFILT1);
1853 writel(0, gp->regs + MAC_AFILT2);
1854 writel(0, gp->regs + MAC_AF21MSK);
1855 writel(0, gp->regs + MAC_AF0MSK);
1856
1857 gp->mac_rx_cfg = gem_setup_multicast(gp);
1858 #ifdef STRIP_FCS
1859 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1860 #endif
1861 writel(0, gp->regs + MAC_NCOLL);
1862 writel(0, gp->regs + MAC_FASUCC);
1863 writel(0, gp->regs + MAC_ECOLL);
1864 writel(0, gp->regs + MAC_LCOLL);
1865 writel(0, gp->regs + MAC_DTIMER);
1866 writel(0, gp->regs + MAC_PATMPS);
1867 writel(0, gp->regs + MAC_RFCTR);
1868 writel(0, gp->regs + MAC_LERR);
1869 writel(0, gp->regs + MAC_AERR);
1870 writel(0, gp->regs + MAC_FCSERR);
1871 writel(0, gp->regs + MAC_RXCVERR);
1872
1873 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1874 * them once a link is established.
1875 */
1876 writel(0, gp->regs + MAC_TXCFG);
1877 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1878 writel(0, gp->regs + MAC_MCCFG);
1879 writel(0, gp->regs + MAC_XIFCFG);
1880
1881 /* Setup MAC interrupts. We want to get all of the interesting
1882 * counter expiration events, but we do not want to hear about
1883 * normal rx/tx as the DMA engine tells us that.
1884 */
1885 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1886 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1887
1888 /* Don't enable even the PAUSE interrupts for now, we
1889 * make no use of those events other than to record them.
1890 */
1891 writel(0xffffffff, gp->regs + MAC_MCMASK);
1892
1893 /* Don't enable GEM's WOL in normal operations
1894 */
1895 if (gp->has_wol)
1896 writel(0, gp->regs + WOL_WAKECSR);
1897 }
1898
1899 static void gem_init_pause_thresholds(struct gem *gp)
1900 {
1901 u32 cfg;
1902
1903 /* Calculate pause thresholds. Setting the OFF threshold to the
1904 * full RX fifo size effectively disables PAUSE generation which
1905 * is what we do for 10/100 only GEMs which have FIFOs too small
1906 * to make real gains from PAUSE.
1907 */
1908 if (gp->rx_fifo_sz <= (2 * 1024)) {
1909 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1910 } else {
1911 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1912 int off = (gp->rx_fifo_sz - (max_frame * 2));
1913 int on = off - max_frame;
1914
1915 gp->rx_pause_off = off;
1916 gp->rx_pause_on = on;
1917 }
1918
1919
1920 /* Configure the chip "burst" DMA mode & enable some
1921 * HW bug fixes on Apple version
1922 */
1923 cfg = 0;
1924 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1925 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1926 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1927 cfg |= GREG_CFG_IBURST;
1928 #endif
1929 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1930 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1931 writel(cfg, gp->regs + GREG_CFG);
1932
1933 /* If Infinite Burst didn't stick, then use different
1934 * thresholds (and Apple bug fixes don't exist)
1935 */
1936 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1937 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1938 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1939 writel(cfg, gp->regs + GREG_CFG);
1940 }
1941 }
1942
1943 static int gem_check_invariants(struct gem *gp)
1944 {
1945 struct pci_dev *pdev = gp->pdev;
1946 u32 mif_cfg;
1947
1948 /* On Apple's sungem, we can't rely on registers as the chip
1949 * was been powered down by the firmware. The PHY is looked
1950 * up later on.
1951 */
1952 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1953 gp->phy_type = phy_mii_mdio0;
1954 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1955 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1956 gp->swrst_base = 0;
1957
1958 mif_cfg = readl(gp->regs + MIF_CFG);
1959 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1960 mif_cfg |= MIF_CFG_MDI0;
1961 writel(mif_cfg, gp->regs + MIF_CFG);
1962 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1963 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1964
1965 /* We hard-code the PHY address so we can properly bring it out of
1966 * reset later on, we can't really probe it at this point, though
1967 * that isn't an issue.
1968 */
1969 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1970 gp->mii_phy_addr = 1;
1971 else
1972 gp->mii_phy_addr = 0;
1973
1974 return 0;
1975 }
1976
1977 mif_cfg = readl(gp->regs + MIF_CFG);
1978
1979 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1980 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1981 /* One of the MII PHYs _must_ be present
1982 * as this chip has no gigabit PHY.
1983 */
1984 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1985 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1986 mif_cfg);
1987 return -1;
1988 }
1989 }
1990
1991 /* Determine initial PHY interface type guess. MDIO1 is the
1992 * external PHY and thus takes precedence over MDIO0.
1993 */
1994
1995 if (mif_cfg & MIF_CFG_MDI1) {
1996 gp->phy_type = phy_mii_mdio1;
1997 mif_cfg |= MIF_CFG_PSELECT;
1998 writel(mif_cfg, gp->regs + MIF_CFG);
1999 } else if (mif_cfg & MIF_CFG_MDI0) {
2000 gp->phy_type = phy_mii_mdio0;
2001 mif_cfg &= ~MIF_CFG_PSELECT;
2002 writel(mif_cfg, gp->regs + MIF_CFG);
2003 } else {
2004 #ifdef CONFIG_SPARC
2005 const char *p;
2006
2007 p = of_get_property(gp->of_node, "shared-pins", NULL);
2008 if (p && !strcmp(p, "serdes"))
2009 gp->phy_type = phy_serdes;
2010 else
2011 #endif
2012 gp->phy_type = phy_serialink;
2013 }
2014 if (gp->phy_type == phy_mii_mdio1 ||
2015 gp->phy_type == phy_mii_mdio0) {
2016 int i;
2017
2018 for (i = 0; i < 32; i++) {
2019 gp->mii_phy_addr = i;
2020 if (phy_read(gp, MII_BMCR) != 0xffff)
2021 break;
2022 }
2023 if (i == 32) {
2024 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2025 pr_err("RIO MII phy will not respond\n");
2026 return -1;
2027 }
2028 gp->phy_type = phy_serdes;
2029 }
2030 }
2031
2032 /* Fetch the FIFO configurations now too. */
2033 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2034 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2035
2036 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2037 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2038 if (gp->tx_fifo_sz != (9 * 1024) ||
2039 gp->rx_fifo_sz != (20 * 1024)) {
2040 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2041 gp->tx_fifo_sz, gp->rx_fifo_sz);
2042 return -1;
2043 }
2044 gp->swrst_base = 0;
2045 } else {
2046 if (gp->tx_fifo_sz != (2 * 1024) ||
2047 gp->rx_fifo_sz != (2 * 1024)) {
2048 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2049 gp->tx_fifo_sz, gp->rx_fifo_sz);
2050 return -1;
2051 }
2052 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2053 }
2054 }
2055
2056 return 0;
2057 }
2058
2059 static void gem_reinit_chip(struct gem *gp)
2060 {
2061 /* Reset the chip */
2062 gem_reset(gp);
2063
2064 /* Make sure ints are disabled */
2065 gem_disable_ints(gp);
2066
2067 /* Allocate & setup ring buffers */
2068 gem_init_rings(gp);
2069
2070 /* Configure pause thresholds */
2071 gem_init_pause_thresholds(gp);
2072
2073 /* Init DMA & MAC engines */
2074 gem_init_dma(gp);
2075 gem_init_mac(gp);
2076 }
2077
2078
2079 static void gem_stop_phy(struct gem *gp, int wol)
2080 {
2081 u32 mifcfg;
2082
2083 /* Let the chip settle down a bit, it seems that helps
2084 * for sleep mode on some models
2085 */
2086 msleep(10);
2087
2088 /* Make sure we aren't polling PHY status change. We
2089 * don't currently use that feature though
2090 */
2091 mifcfg = readl(gp->regs + MIF_CFG);
2092 mifcfg &= ~MIF_CFG_POLL;
2093 writel(mifcfg, gp->regs + MIF_CFG);
2094
2095 if (wol && gp->has_wol) {
2096 unsigned char *e = &gp->dev->dev_addr[0];
2097 u32 csr;
2098
2099 /* Setup wake-on-lan for MAGIC packet */
2100 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2101 gp->regs + MAC_RXCFG);
2102 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2103 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2104 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2105
2106 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2107 csr = WOL_WAKECSR_ENABLE;
2108 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2109 csr |= WOL_WAKECSR_MII;
2110 writel(csr, gp->regs + WOL_WAKECSR);
2111 } else {
2112 writel(0, gp->regs + MAC_RXCFG);
2113 (void)readl(gp->regs + MAC_RXCFG);
2114 /* Machine sleep will die in strange ways if we
2115 * dont wait a bit here, looks like the chip takes
2116 * some time to really shut down
2117 */
2118 msleep(10);
2119 }
2120
2121 writel(0, gp->regs + MAC_TXCFG);
2122 writel(0, gp->regs + MAC_XIFCFG);
2123 writel(0, gp->regs + TXDMA_CFG);
2124 writel(0, gp->regs + RXDMA_CFG);
2125
2126 if (!wol) {
2127 gem_reset(gp);
2128 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2129 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2130
2131 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2132 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2133
2134 /* According to Apple, we must set the MDIO pins to this begnign
2135 * state or we may 1) eat more current, 2) damage some PHYs
2136 */
2137 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2138 writel(0, gp->regs + MIF_BBCLK);
2139 writel(0, gp->regs + MIF_BBDATA);
2140 writel(0, gp->regs + MIF_BBOENAB);
2141 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2142 (void) readl(gp->regs + MAC_XIFCFG);
2143 }
2144 }
2145
2146 static int gem_do_start(struct net_device *dev)
2147 {
2148 struct gem *gp = netdev_priv(dev);
2149 int rc;
2150
2151 /* Enable the cell */
2152 gem_get_cell(gp);
2153
2154 /* Make sure PCI access and bus master are enabled */
2155 rc = pci_enable_device(gp->pdev);
2156 if (rc) {
2157 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2158
2159 /* Put cell and forget it for now, it will be considered as
2160 * still asleep, a new sleep cycle may bring it back
2161 */
2162 gem_put_cell(gp);
2163 return -ENXIO;
2164 }
2165 pci_set_master(gp->pdev);
2166
2167 /* Init & setup chip hardware */
2168 gem_reinit_chip(gp);
2169
2170 /* An interrupt might come in handy */
2171 rc = request_irq(gp->pdev->irq, gem_interrupt,
2172 IRQF_SHARED, dev->name, (void *)dev);
2173 if (rc) {
2174 netdev_err(dev, "failed to request irq !\n");
2175
2176 gem_reset(gp);
2177 gem_clean_rings(gp);
2178 gem_put_cell(gp);
2179 return rc;
2180 }
2181
2182 /* Mark us as attached again if we come from resume(), this has
2183 * no effect if we weren't detatched and needs to be done now.
2184 */
2185 netif_device_attach(dev);
2186
2187 /* Restart NAPI & queues */
2188 gem_netif_start(gp);
2189
2190 /* Detect & init PHY, start autoneg etc... this will
2191 * eventually result in starting DMA operations when
2192 * the link is up
2193 */
2194 gem_init_phy(gp);
2195
2196 return 0;
2197 }
2198
2199 static void gem_do_stop(struct net_device *dev, int wol)
2200 {
2201 struct gem *gp = netdev_priv(dev);
2202
2203 /* Stop NAPI and stop tx queue */
2204 gem_netif_stop(gp);
2205
2206 /* Make sure ints are disabled. We don't care about
2207 * synchronizing as NAPI is disabled, thus a stray
2208 * interrupt will do nothing bad (our irq handler
2209 * just schedules NAPI)
2210 */
2211 gem_disable_ints(gp);
2212
2213 /* Stop the link timer */
2214 del_timer_sync(&gp->link_timer);
2215
2216 /* We cannot cancel the reset task while holding the
2217 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2218 * if we did. This is not an issue however as the reset
2219 * task is synchronized vs. us (rtnl_lock) and will do
2220 * nothing if the device is down or suspended. We do
2221 * still clear reset_task_pending to avoid a spurrious
2222 * reset later on in case we do resume before it gets
2223 * scheduled.
2224 */
2225 gp->reset_task_pending = 0;
2226
2227 /* If we are going to sleep with WOL */
2228 gem_stop_dma(gp);
2229 msleep(10);
2230 if (!wol)
2231 gem_reset(gp);
2232 msleep(10);
2233
2234 /* Get rid of rings */
2235 gem_clean_rings(gp);
2236
2237 /* No irq needed anymore */
2238 free_irq(gp->pdev->irq, (void *) dev);
2239
2240 /* Shut the PHY down eventually and setup WOL */
2241 gem_stop_phy(gp, wol);
2242
2243 /* Make sure bus master is disabled */
2244 pci_disable_device(gp->pdev);
2245
2246 /* Cell not needed neither if no WOL */
2247 if (!wol)
2248 gem_put_cell(gp);
2249 }
2250
2251 static void gem_reset_task(struct work_struct *work)
2252 {
2253 struct gem *gp = container_of(work, struct gem, reset_task);
2254
2255 /* Lock out the network stack (essentially shield ourselves
2256 * against a racing open, close, control call, or suspend
2257 */
2258 rtnl_lock();
2259
2260 /* Skip the reset task if suspended or closed, or if it's
2261 * been cancelled by gem_do_stop (see comment there)
2262 */
2263 if (!netif_device_present(gp->dev) ||
2264 !netif_running(gp->dev) ||
2265 !gp->reset_task_pending) {
2266 rtnl_unlock();
2267 return;
2268 }
2269
2270 /* Stop the link timer */
2271 del_timer_sync(&gp->link_timer);
2272
2273 /* Stop NAPI and tx */
2274 gem_netif_stop(gp);
2275
2276 /* Reset the chip & rings */
2277 gem_reinit_chip(gp);
2278 if (gp->lstate == link_up)
2279 gem_set_link_modes(gp);
2280
2281 /* Restart NAPI and Tx */
2282 gem_netif_start(gp);
2283
2284 /* We are back ! */
2285 gp->reset_task_pending = 0;
2286
2287 /* If the link is not up, restart autoneg, else restart the
2288 * polling timer
2289 */
2290 if (gp->lstate != link_up)
2291 gem_begin_auto_negotiation(gp, NULL);
2292 else
2293 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2294
2295 rtnl_unlock();
2296 }
2297
2298 static int gem_open(struct net_device *dev)
2299 {
2300 /* We allow open while suspended, we just do nothing,
2301 * the chip will be initialized in resume()
2302 */
2303 if (netif_device_present(dev))
2304 return gem_do_start(dev);
2305 return 0;
2306 }
2307
2308 static int gem_close(struct net_device *dev)
2309 {
2310 if (netif_device_present(dev))
2311 gem_do_stop(dev, 0);
2312
2313 return 0;
2314 }
2315
2316 #ifdef CONFIG_PM
2317 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2318 {
2319 struct net_device *dev = pci_get_drvdata(pdev);
2320 struct gem *gp = netdev_priv(dev);
2321
2322 /* Lock the network stack first to avoid racing with open/close,
2323 * reset task and setting calls
2324 */
2325 rtnl_lock();
2326
2327 /* Not running, mark ourselves non-present, no need for
2328 * a lock here
2329 */
2330 if (!netif_running(dev)) {
2331 netif_device_detach(dev);
2332 rtnl_unlock();
2333 return 0;
2334 }
2335 netdev_info(dev, "suspending, WakeOnLan %s\n",
2336 (gp->wake_on_lan && netif_running(dev)) ?
2337 "enabled" : "disabled");
2338
2339 /* Tell the network stack we're gone. gem_do_stop() below will
2340 * synchronize with TX, stop NAPI etc...
2341 */
2342 netif_device_detach(dev);
2343
2344 /* Switch off chip, remember WOL setting */
2345 gp->asleep_wol = gp->wake_on_lan;
2346 gem_do_stop(dev, gp->asleep_wol);
2347
2348 /* Unlock the network stack */
2349 rtnl_unlock();
2350
2351 return 0;
2352 }
2353
2354 static int gem_resume(struct pci_dev *pdev)
2355 {
2356 struct net_device *dev = pci_get_drvdata(pdev);
2357 struct gem *gp = netdev_priv(dev);
2358
2359 /* See locking comment in gem_suspend */
2360 rtnl_lock();
2361
2362 /* Not running, mark ourselves present, no need for
2363 * a lock here
2364 */
2365 if (!netif_running(dev)) {
2366 netif_device_attach(dev);
2367 rtnl_unlock();
2368 return 0;
2369 }
2370
2371 /* Restart chip. If that fails there isn't much we can do, we
2372 * leave things stopped.
2373 */
2374 gem_do_start(dev);
2375
2376 /* If we had WOL enabled, the cell clock was never turned off during
2377 * sleep, so we end up beeing unbalanced. Fix that here
2378 */
2379 if (gp->asleep_wol)
2380 gem_put_cell(gp);
2381
2382 /* Unlock the network stack */
2383 rtnl_unlock();
2384
2385 return 0;
2386 }
2387 #endif /* CONFIG_PM */
2388
2389 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2390 {
2391 struct gem *gp = netdev_priv(dev);
2392
2393 /* I have seen this being called while the PM was in progress,
2394 * so we shield against this. Let's also not poke at registers
2395 * while the reset task is going on.
2396 *
2397 * TODO: Move stats collection elsewhere (link timer ?) and
2398 * make this a nop to avoid all those synchro issues
2399 */
2400 if (!netif_device_present(dev) || !netif_running(dev))
2401 goto bail;
2402
2403 /* Better safe than sorry... */
2404 if (WARN_ON(!gp->cell_enabled))
2405 goto bail;
2406
2407 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2408 writel(0, gp->regs + MAC_FCSERR);
2409
2410 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2411 writel(0, gp->regs + MAC_AERR);
2412
2413 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2414 writel(0, gp->regs + MAC_LERR);
2415
2416 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2417 dev->stats.collisions +=
2418 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2419 writel(0, gp->regs + MAC_ECOLL);
2420 writel(0, gp->regs + MAC_LCOLL);
2421 bail:
2422 return &dev->stats;
2423 }
2424
2425 static int gem_set_mac_address(struct net_device *dev, void *addr)
2426 {
2427 struct sockaddr *macaddr = (struct sockaddr *) addr;
2428 struct gem *gp = netdev_priv(dev);
2429 unsigned char *e = &dev->dev_addr[0];
2430
2431 if (!is_valid_ether_addr(macaddr->sa_data))
2432 return -EADDRNOTAVAIL;
2433
2434 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2435
2436 /* We'll just catch it later when the device is up'd or resumed */
2437 if (!netif_running(dev) || !netif_device_present(dev))
2438 return 0;
2439
2440 /* Better safe than sorry... */
2441 if (WARN_ON(!gp->cell_enabled))
2442 return 0;
2443
2444 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2445 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2446 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2447
2448 return 0;
2449 }
2450
2451 static void gem_set_multicast(struct net_device *dev)
2452 {
2453 struct gem *gp = netdev_priv(dev);
2454 u32 rxcfg, rxcfg_new;
2455 int limit = 10000;
2456
2457 if (!netif_running(dev) || !netif_device_present(dev))
2458 return;
2459
2460 /* Better safe than sorry... */
2461 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2462 return;
2463
2464 rxcfg = readl(gp->regs + MAC_RXCFG);
2465 rxcfg_new = gem_setup_multicast(gp);
2466 #ifdef STRIP_FCS
2467 rxcfg_new |= MAC_RXCFG_SFCS;
2468 #endif
2469 gp->mac_rx_cfg = rxcfg_new;
2470
2471 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2472 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2473 if (!limit--)
2474 break;
2475 udelay(10);
2476 }
2477
2478 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2479 rxcfg |= rxcfg_new;
2480
2481 writel(rxcfg, gp->regs + MAC_RXCFG);
2482 }
2483
2484 /* Jumbo-grams don't seem to work :-( */
2485 #define GEM_MIN_MTU 68
2486 #if 1
2487 #define GEM_MAX_MTU 1500
2488 #else
2489 #define GEM_MAX_MTU 9000
2490 #endif
2491
2492 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2493 {
2494 struct gem *gp = netdev_priv(dev);
2495
2496 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2497 return -EINVAL;
2498
2499 dev->mtu = new_mtu;
2500
2501 /* We'll just catch it later when the device is up'd or resumed */
2502 if (!netif_running(dev) || !netif_device_present(dev))
2503 return 0;
2504
2505 /* Better safe than sorry... */
2506 if (WARN_ON(!gp->cell_enabled))
2507 return 0;
2508
2509 gem_netif_stop(gp);
2510 gem_reinit_chip(gp);
2511 if (gp->lstate == link_up)
2512 gem_set_link_modes(gp);
2513 gem_netif_start(gp);
2514
2515 return 0;
2516 }
2517
2518 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2519 {
2520 struct gem *gp = netdev_priv(dev);
2521
2522 strcpy(info->driver, DRV_NAME);
2523 strcpy(info->version, DRV_VERSION);
2524 strcpy(info->bus_info, pci_name(gp->pdev));
2525 }
2526
2527 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2528 {
2529 struct gem *gp = netdev_priv(dev);
2530
2531 if (gp->phy_type == phy_mii_mdio0 ||
2532 gp->phy_type == phy_mii_mdio1) {
2533 if (gp->phy_mii.def)
2534 cmd->supported = gp->phy_mii.def->features;
2535 else
2536 cmd->supported = (SUPPORTED_10baseT_Half |
2537 SUPPORTED_10baseT_Full);
2538
2539 /* XXX hardcoded stuff for now */
2540 cmd->port = PORT_MII;
2541 cmd->transceiver = XCVR_EXTERNAL;
2542 cmd->phy_address = 0; /* XXX fixed PHYAD */
2543
2544 /* Return current PHY settings */
2545 cmd->autoneg = gp->want_autoneg;
2546 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);
2547 cmd->duplex = gp->phy_mii.duplex;
2548 cmd->advertising = gp->phy_mii.advertising;
2549
2550 /* If we started with a forced mode, we don't have a default
2551 * advertise set, we need to return something sensible so
2552 * userland can re-enable autoneg properly.
2553 */
2554 if (cmd->advertising == 0)
2555 cmd->advertising = cmd->supported;
2556 } else { // XXX PCS ?
2557 cmd->supported =
2558 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2559 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2560 SUPPORTED_Autoneg);
2561 cmd->advertising = cmd->supported;
2562 ethtool_cmd_speed_set(cmd, 0);
2563 cmd->duplex = cmd->port = cmd->phy_address =
2564 cmd->transceiver = cmd->autoneg = 0;
2565
2566 /* serdes means usually a Fibre connector, with most fixed */
2567 if (gp->phy_type == phy_serdes) {
2568 cmd->port = PORT_FIBRE;
2569 cmd->supported = (SUPPORTED_1000baseT_Half |
2570 SUPPORTED_1000baseT_Full |
2571 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2572 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2573 cmd->advertising = cmd->supported;
2574 cmd->transceiver = XCVR_INTERNAL;
2575 if (gp->lstate == link_up)
2576 ethtool_cmd_speed_set(cmd, SPEED_1000);
2577 cmd->duplex = DUPLEX_FULL;
2578 cmd->autoneg = 1;
2579 }
2580 }
2581 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2582
2583 return 0;
2584 }
2585
2586 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2587 {
2588 struct gem *gp = netdev_priv(dev);
2589 u32 speed = ethtool_cmd_speed(cmd);
2590
2591 /* Verify the settings we care about. */
2592 if (cmd->autoneg != AUTONEG_ENABLE &&
2593 cmd->autoneg != AUTONEG_DISABLE)
2594 return -EINVAL;
2595
2596 if (cmd->autoneg == AUTONEG_ENABLE &&
2597 cmd->advertising == 0)
2598 return -EINVAL;
2599
2600 if (cmd->autoneg == AUTONEG_DISABLE &&
2601 ((speed != SPEED_1000 &&
2602 speed != SPEED_100 &&
2603 speed != SPEED_10) ||
2604 (cmd->duplex != DUPLEX_HALF &&
2605 cmd->duplex != DUPLEX_FULL)))
2606 return -EINVAL;
2607
2608 /* Apply settings and restart link process. */
2609 if (netif_device_present(gp->dev)) {
2610 del_timer_sync(&gp->link_timer);
2611 gem_begin_auto_negotiation(gp, cmd);
2612 }
2613
2614 return 0;
2615 }
2616
2617 static int gem_nway_reset(struct net_device *dev)
2618 {
2619 struct gem *gp = netdev_priv(dev);
2620
2621 if (!gp->want_autoneg)
2622 return -EINVAL;
2623
2624 /* Restart link process */
2625 if (netif_device_present(gp->dev)) {
2626 del_timer_sync(&gp->link_timer);
2627 gem_begin_auto_negotiation(gp, NULL);
2628 }
2629
2630 return 0;
2631 }
2632
2633 static u32 gem_get_msglevel(struct net_device *dev)
2634 {
2635 struct gem *gp = netdev_priv(dev);
2636 return gp->msg_enable;
2637 }
2638
2639 static void gem_set_msglevel(struct net_device *dev, u32 value)
2640 {
2641 struct gem *gp = netdev_priv(dev);
2642 gp->msg_enable = value;
2643 }
2644
2645
2646 /* Add more when I understand how to program the chip */
2647 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2648
2649 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2650
2651 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2652 {
2653 struct gem *gp = netdev_priv(dev);
2654
2655 /* Add more when I understand how to program the chip */
2656 if (gp->has_wol) {
2657 wol->supported = WOL_SUPPORTED_MASK;
2658 wol->wolopts = gp->wake_on_lan;
2659 } else {
2660 wol->supported = 0;
2661 wol->wolopts = 0;
2662 }
2663 }
2664
2665 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2666 {
2667 struct gem *gp = netdev_priv(dev);
2668
2669 if (!gp->has_wol)
2670 return -EOPNOTSUPP;
2671 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2672 return 0;
2673 }
2674
2675 static const struct ethtool_ops gem_ethtool_ops = {
2676 .get_drvinfo = gem_get_drvinfo,
2677 .get_link = ethtool_op_get_link,
2678 .get_settings = gem_get_settings,
2679 .set_settings = gem_set_settings,
2680 .nway_reset = gem_nway_reset,
2681 .get_msglevel = gem_get_msglevel,
2682 .set_msglevel = gem_set_msglevel,
2683 .get_wol = gem_get_wol,
2684 .set_wol = gem_set_wol,
2685 };
2686
2687 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2688 {
2689 struct gem *gp = netdev_priv(dev);
2690 struct mii_ioctl_data *data = if_mii(ifr);
2691 int rc = -EOPNOTSUPP;
2692
2693 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2694 * netif_device_present() is true and holds rtnl_lock for us
2695 * so we have nothing to worry about
2696 */
2697
2698 switch (cmd) {
2699 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2700 data->phy_id = gp->mii_phy_addr;
2701 /* Fallthrough... */
2702
2703 case SIOCGMIIREG: /* Read MII PHY register. */
2704 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2705 data->reg_num & 0x1f);
2706 rc = 0;
2707 break;
2708
2709 case SIOCSMIIREG: /* Write MII PHY register. */
2710 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2711 data->val_in);
2712 rc = 0;
2713 break;
2714 }
2715 return rc;
2716 }
2717
2718 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2719 /* Fetch MAC address from vital product data of PCI ROM. */
2720 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2721 {
2722 int this_offset;
2723
2724 for (this_offset = 0x20; this_offset < len; this_offset++) {
2725 void __iomem *p = rom_base + this_offset;
2726 int i;
2727
2728 if (readb(p + 0) != 0x90 ||
2729 readb(p + 1) != 0x00 ||
2730 readb(p + 2) != 0x09 ||
2731 readb(p + 3) != 0x4e ||
2732 readb(p + 4) != 0x41 ||
2733 readb(p + 5) != 0x06)
2734 continue;
2735
2736 this_offset += 6;
2737 p += 6;
2738
2739 for (i = 0; i < 6; i++)
2740 dev_addr[i] = readb(p + i);
2741 return 1;
2742 }
2743 return 0;
2744 }
2745
2746 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2747 {
2748 size_t size;
2749 void __iomem *p = pci_map_rom(pdev, &size);
2750
2751 if (p) {
2752 int found;
2753
2754 found = readb(p) == 0x55 &&
2755 readb(p + 1) == 0xaa &&
2756 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2757 pci_unmap_rom(pdev, p);
2758 if (found)
2759 return;
2760 }
2761
2762 /* Sun MAC prefix then 3 random bytes. */
2763 dev_addr[0] = 0x08;
2764 dev_addr[1] = 0x00;
2765 dev_addr[2] = 0x20;
2766 get_random_bytes(dev_addr + 3, 3);
2767 }
2768 #endif /* not Sparc and not PPC */
2769
2770 static int __devinit gem_get_device_address(struct gem *gp)
2771 {
2772 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2773 struct net_device *dev = gp->dev;
2774 const unsigned char *addr;
2775
2776 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2777 if (addr == NULL) {
2778 #ifdef CONFIG_SPARC
2779 addr = idprom->id_ethaddr;
2780 #else
2781 printk("\n");
2782 pr_err("%s: can't get mac-address\n", dev->name);
2783 return -1;
2784 #endif
2785 }
2786 memcpy(dev->dev_addr, addr, 6);
2787 #else
2788 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2789 #endif
2790 return 0;
2791 }
2792
2793 static void gem_remove_one(struct pci_dev *pdev)
2794 {
2795 struct net_device *dev = pci_get_drvdata(pdev);
2796
2797 if (dev) {
2798 struct gem *gp = netdev_priv(dev);
2799
2800 unregister_netdev(dev);
2801
2802 /* Ensure reset task is truely gone */
2803 cancel_work_sync(&gp->reset_task);
2804
2805 /* Free resources */
2806 pci_free_consistent(pdev,
2807 sizeof(struct gem_init_block),
2808 gp->init_block,
2809 gp->gblock_dvma);
2810 iounmap(gp->regs);
2811 pci_release_regions(pdev);
2812 free_netdev(dev);
2813
2814 pci_set_drvdata(pdev, NULL);
2815 }
2816 }
2817
2818 static const struct net_device_ops gem_netdev_ops = {
2819 .ndo_open = gem_open,
2820 .ndo_stop = gem_close,
2821 .ndo_start_xmit = gem_start_xmit,
2822 .ndo_get_stats = gem_get_stats,
2823 .ndo_set_multicast_list = gem_set_multicast,
2824 .ndo_do_ioctl = gem_ioctl,
2825 .ndo_tx_timeout = gem_tx_timeout,
2826 .ndo_change_mtu = gem_change_mtu,
2827 .ndo_validate_addr = eth_validate_addr,
2828 .ndo_set_mac_address = gem_set_mac_address,
2829 #ifdef CONFIG_NET_POLL_CONTROLLER
2830 .ndo_poll_controller = gem_poll_controller,
2831 #endif
2832 };
2833
2834 static int __devinit gem_init_one(struct pci_dev *pdev,
2835 const struct pci_device_id *ent)
2836 {
2837 unsigned long gemreg_base, gemreg_len;
2838 struct net_device *dev;
2839 struct gem *gp;
2840 int err, pci_using_dac;
2841
2842 printk_once(KERN_INFO "%s", version);
2843
2844 /* Apple gmac note: during probe, the chip is powered up by
2845 * the arch code to allow the code below to work (and to let
2846 * the chip be probed on the config space. It won't stay powered
2847 * up until the interface is brought up however, so we can't rely
2848 * on register configuration done at this point.
2849 */
2850 err = pci_enable_device(pdev);
2851 if (err) {
2852 pr_err("Cannot enable MMIO operation, aborting\n");
2853 return err;
2854 }
2855 pci_set_master(pdev);
2856
2857 /* Configure DMA attributes. */
2858
2859 /* All of the GEM documentation states that 64-bit DMA addressing
2860 * is fully supported and should work just fine. However the
2861 * front end for RIO based GEMs is different and only supports
2862 * 32-bit addressing.
2863 *
2864 * For now we assume the various PPC GEMs are 32-bit only as well.
2865 */
2866 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2867 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2868 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2869 pci_using_dac = 1;
2870 } else {
2871 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2872 if (err) {
2873 pr_err("No usable DMA configuration, aborting\n");
2874 goto err_disable_device;
2875 }
2876 pci_using_dac = 0;
2877 }
2878
2879 gemreg_base = pci_resource_start(pdev, 0);
2880 gemreg_len = pci_resource_len(pdev, 0);
2881
2882 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2883 pr_err("Cannot find proper PCI device base address, aborting\n");
2884 err = -ENODEV;
2885 goto err_disable_device;
2886 }
2887
2888 dev = alloc_etherdev(sizeof(*gp));
2889 if (!dev) {
2890 pr_err("Etherdev alloc failed, aborting\n");
2891 err = -ENOMEM;
2892 goto err_disable_device;
2893 }
2894 SET_NETDEV_DEV(dev, &pdev->dev);
2895
2896 gp = netdev_priv(dev);
2897
2898 err = pci_request_regions(pdev, DRV_NAME);
2899 if (err) {
2900 pr_err("Cannot obtain PCI resources, aborting\n");
2901 goto err_out_free_netdev;
2902 }
2903
2904 gp->pdev = pdev;
2905 dev->base_addr = (long) pdev;
2906 gp->dev = dev;
2907
2908 gp->msg_enable = DEFAULT_MSG;
2909
2910 init_timer(&gp->link_timer);
2911 gp->link_timer.function = gem_link_timer;
2912 gp->link_timer.data = (unsigned long) gp;
2913
2914 INIT_WORK(&gp->reset_task, gem_reset_task);
2915
2916 gp->lstate = link_down;
2917 gp->timer_ticks = 0;
2918 netif_carrier_off(dev);
2919
2920 gp->regs = ioremap(gemreg_base, gemreg_len);
2921 if (!gp->regs) {
2922 pr_err("Cannot map device registers, aborting\n");
2923 err = -EIO;
2924 goto err_out_free_res;
2925 }
2926
2927 /* On Apple, we want a reference to the Open Firmware device-tree
2928 * node. We use it for clock control.
2929 */
2930 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2931 gp->of_node = pci_device_to_OF_node(pdev);
2932 #endif
2933
2934 /* Only Apple version supports WOL afaik */
2935 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2936 gp->has_wol = 1;
2937
2938 /* Make sure cell is enabled */
2939 gem_get_cell(gp);
2940
2941 /* Make sure everything is stopped and in init state */
2942 gem_reset(gp);
2943
2944 /* Fill up the mii_phy structure (even if we won't use it) */
2945 gp->phy_mii.dev = dev;
2946 gp->phy_mii.mdio_read = _phy_read;
2947 gp->phy_mii.mdio_write = _phy_write;
2948 #ifdef CONFIG_PPC_PMAC
2949 gp->phy_mii.platform_data = gp->of_node;
2950 #endif
2951 /* By default, we start with autoneg */
2952 gp->want_autoneg = 1;
2953
2954 /* Check fifo sizes, PHY type, etc... */
2955 if (gem_check_invariants(gp)) {
2956 err = -ENODEV;
2957 goto err_out_iounmap;
2958 }
2959
2960 /* It is guaranteed that the returned buffer will be at least
2961 * PAGE_SIZE aligned.
2962 */
2963 gp->init_block = (struct gem_init_block *)
2964 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2965 &gp->gblock_dvma);
2966 if (!gp->init_block) {
2967 pr_err("Cannot allocate init block, aborting\n");
2968 err = -ENOMEM;
2969 goto err_out_iounmap;
2970 }
2971
2972 if (gem_get_device_address(gp))
2973 goto err_out_free_consistent;
2974
2975 dev->netdev_ops = &gem_netdev_ops;
2976 netif_napi_add(dev, &gp->napi, gem_poll, 64);
2977 dev->ethtool_ops = &gem_ethtool_ops;
2978 dev->watchdog_timeo = 5 * HZ;
2979 dev->irq = pdev->irq;
2980 dev->dma = 0;
2981
2982 /* Set that now, in case PM kicks in now */
2983 pci_set_drvdata(pdev, dev);
2984
2985 /* We can do scatter/gather and HW checksum */
2986 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2987 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2988 if (pci_using_dac)
2989 dev->features |= NETIF_F_HIGHDMA;
2990
2991 /* Register with kernel */
2992 if (register_netdev(dev)) {
2993 pr_err("Cannot register net device, aborting\n");
2994 err = -ENOMEM;
2995 goto err_out_free_consistent;
2996 }
2997
2998 /* Undo the get_cell with appropriate locking (we could use
2999 * ndo_init/uninit but that would be even more clumsy imho)
3000 */
3001 rtnl_lock();
3002 gem_put_cell(gp);
3003 rtnl_unlock();
3004
3005 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3006 dev->dev_addr);
3007 return 0;
3008
3009 err_out_free_consistent:
3010 gem_remove_one(pdev);
3011 err_out_iounmap:
3012 gem_put_cell(gp);
3013 iounmap(gp->regs);
3014
3015 err_out_free_res:
3016 pci_release_regions(pdev);
3017
3018 err_out_free_netdev:
3019 free_netdev(dev);
3020 err_disable_device:
3021 pci_disable_device(pdev);
3022 return err;
3023
3024 }
3025
3026
3027 static struct pci_driver gem_driver = {
3028 .name = GEM_MODULE_NAME,
3029 .id_table = gem_pci_tbl,
3030 .probe = gem_init_one,
3031 .remove = gem_remove_one,
3032 #ifdef CONFIG_PM
3033 .suspend = gem_suspend,
3034 .resume = gem_resume,
3035 #endif /* CONFIG_PM */
3036 };
3037
3038 static int __init gem_init(void)
3039 {
3040 return pci_register_driver(&gem_driver);
3041 }
3042
3043 static void __exit gem_cleanup(void)
3044 {
3045 pci_unregister_driver(&gem_driver);
3046 }
3047
3048 module_init(gem_init);
3049 module_exit(gem_cleanup);
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