drivers/net/wireless/ath/ath9k/ar9002_mac.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18
  19 #define AR_BufLen           0x00000fff
  20
  21 static void ar9002_hw_rx_enable(struct ath_hw *ah)
  22 {
  23         REG_WRITE(ah, AR_CR, AR_CR_RXE);
  24 }
  25
  26 static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
  27 {
  28         ((struct ath_desc*) ds)->ds_link = ds_link;
  29 }
  30
  31 static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
  32 {
  33         u32 isr = 0;
  34         u32 mask2 = 0;
  35         struct ath9k_hw_capabilities *pCap = &ah->caps;
  36         u32 sync_cause = 0;
  37         bool fatal_int = false;
  38         struct ath_common *common = ath9k_hw_common(ah);
  39
  40         if (!AR_SREV_9100(ah)) {
  41                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
  42                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
  43                             == AR_RTC_STATUS_ON) {
  44                                 isr = REG_READ(ah, AR_ISR);
  45                         }
  46                 }
  47
  48                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
  49                         AR_INTR_SYNC_DEFAULT;
  50
  51                 *masked = 0;
  52
  53                 if (!isr && !sync_cause)
  54                         return false;
  55         } else {
  56                 *masked = 0;
  57                 isr = REG_READ(ah, AR_ISR);
  58         }
  59
  60         if (isr) {
  61                 if (isr & AR_ISR_BCNMISC) {
  62                         u32 isr2;
  63                         isr2 = REG_READ(ah, AR_ISR_S2);
  64                         if (isr2 & AR_ISR_S2_TIM)
  65                                 mask2 |= ATH9K_INT_TIM;
  66                         if (isr2 & AR_ISR_S2_DTIM)
  67                                 mask2 |= ATH9K_INT_DTIM;
  68                         if (isr2 & AR_ISR_S2_DTIMSYNC)
  69                                 mask2 |= ATH9K_INT_DTIMSYNC;
  70                         if (isr2 & (AR_ISR_S2_CABEND))
  71                                 mask2 |= ATH9K_INT_CABEND;
  72                         if (isr2 & AR_ISR_S2_GTT)
  73                                 mask2 |= ATH9K_INT_GTT;
  74                         if (isr2 & AR_ISR_S2_CST)
  75                                 mask2 |= ATH9K_INT_CST;
  76                         if (isr2 & AR_ISR_S2_TSFOOR)
  77                                 mask2 |= ATH9K_INT_TSFOOR;
  78                 }
  79
  80                 isr = REG_READ(ah, AR_ISR_RAC);
  81                 if (isr == 0xffffffff) {
  82                         *masked = 0;
  83                         return false;
  84                 }
  85
  86                 *masked = isr & ATH9K_INT_COMMON;
  87
  88                 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
  89                            AR_ISR_RXOK | AR_ISR_RXERR))
  90                         *masked |= ATH9K_INT_RX;
  91
  92                 if (isr &
  93                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
  94                      AR_ISR_TXEOL)) {
  95                         u32 s0_s, s1_s;
  96
  97                         *masked |= ATH9K_INT_TX;
  98
  99                         s0_s = REG_READ(ah, AR_ISR_S0_S);
 100                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
 101                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
 102
 103                         s1_s = REG_READ(ah, AR_ISR_S1_S);
 104                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
 105                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
 106                 }
 107
 108                 if (isr & AR_ISR_RXORN) {
 109                         ath_dbg(common, ATH_DBG_INTERRUPT,
 110                                 "receive FIFO overrun interrupt\n");
 111                 }
 112
 113                 *masked |= mask2;
 114         }
 115
 116         if (AR_SREV_9100(ah))
 117                 return true;
 118
 119         if (isr & AR_ISR_GENTMR) {
 120                 u32 s5_s;
 121
 122                 s5_s = REG_READ(ah, AR_ISR_S5_S);
 123                 ah->intr_gen_timer_trigger =
 124                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
 125
 126                 ah->intr_gen_timer_thresh =
 127                         MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
 128
 129                 if (ah->intr_gen_timer_trigger)
 130                         *masked |= ATH9K_INT_GENTIMER;
 131
 132                 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
 133                     !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 134                         *masked |= ATH9K_INT_TIM_TIMER;
 135         }
 136
 137         if (sync_cause) {
 138                 fatal_int =
 139                         (sync_cause &
 140                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
 141                         ? true : false;
 142
 143                 if (fatal_int) {
 144                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
 145                                 ath_dbg(common, ATH_DBG_ANY,
 146                                         "received PCI FATAL interrupt\n");
 147                         }
 148                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
 149                                 ath_dbg(common, ATH_DBG_ANY,
 150                                         "received PCI PERR interrupt\n");
 151                         }
 152                         *masked |= ATH9K_INT_FATAL;
 153                 }
 154                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 155                         ath_dbg(common, ATH_DBG_INTERRUPT,
 156                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
 157                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
 158                         REG_WRITE(ah, AR_RC, 0);
 159                         *masked |= ATH9K_INT_FATAL;
 160                 }
 161                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
 162                         ath_dbg(common, ATH_DBG_INTERRUPT,
 163                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
 164                 }
 165
 166                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
 167                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 168         }
 169
 170         return true;
 171 }
 172
 173 static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
 174                                   bool is_firstseg, bool is_lastseg,
 175                                   const void *ds0, dma_addr_t buf_addr,
 176                                   unsigned int qcu)
 177 {
 178         struct ar5416_desc *ads = AR5416DESC(ds);
 179
 180         ads->ds_data = buf_addr;
 181
 182         if (is_firstseg) {
 183                 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
 184         } else if (is_lastseg) {
 185                 ads->ds_ctl0 = 0;
 186                 ads->ds_ctl1 = seglen;
 187                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
 188                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
 189         } else {
 190                 ads->ds_ctl0 = 0;
 191                 ads->ds_ctl1 = seglen | AR_TxMore;
 192                 ads->ds_ctl2 = 0;
 193                 ads->ds_ctl3 = 0;
 194         }
 195         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
 196         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
 197         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
 198         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
 199         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
 200 }
 201
 202 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
 203                                  struct ath_tx_status *ts)
 204 {
 205         struct ar5416_desc *ads = AR5416DESC(ds);
 206         u32 status;
 207
 208         status = ACCESS_ONCE(ads->ds_txstatus9);
 209         if ((status & AR_TxDone) == 0)
 210                 return -EINPROGRESS;
 211
 212         ts->ts_tstamp = ads->AR_SendTimestamp;
 213         ts->ts_status = 0;
 214         ts->ts_flags = 0;
 215
 216         if (status & AR_TxOpExceeded)
 217                 ts->ts_status |= ATH9K_TXERR_XTXOP;
 218         ts->tid = MS(status, AR_TxTid);
 219         ts->ts_rateindex = MS(status, AR_FinalTxIdx);
 220         ts->ts_seqnum = MS(status, AR_SeqNum);
 221
 222         status = ACCESS_ONCE(ads->ds_txstatus0);
 223         ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
 224         ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
 225         ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
 226         if (status & AR_TxBaStatus) {
 227                 ts->ts_flags |= ATH9K_TX_BA;
 228                 ts->ba_low = ads->AR_BaBitmapLow;
 229                 ts->ba_high = ads->AR_BaBitmapHigh;
 230         }
 231
 232         status = ACCESS_ONCE(ads->ds_txstatus1);
 233         if (status & AR_FrmXmitOK)
 234                 ts->ts_status |= ATH9K_TX_ACKED;
 235         else {
 236                 if (status & AR_ExcessiveRetries)
 237                         ts->ts_status |= ATH9K_TXERR_XRETRY;
 238                 if (status & AR_Filtered)
 239                         ts->ts_status |= ATH9K_TXERR_FILT;
 240                 if (status & AR_FIFOUnderrun) {
 241                         ts->ts_status |= ATH9K_TXERR_FIFO;
 242                         ath9k_hw_updatetxtriglevel(ah, true);
 243                 }
 244         }
 245         if (status & AR_TxTimerExpired)
 246                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
 247         if (status & AR_DescCfgErr)
 248                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
 249         if (status & AR_TxDataUnderrun) {
 250                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
 251                 ath9k_hw_updatetxtriglevel(ah, true);
 252         }
 253         if (status & AR_TxDelimUnderrun) {
 254                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
 255                 ath9k_hw_updatetxtriglevel(ah, true);
 256         }
 257         ts->ts_shortretry = MS(status, AR_RTSFailCnt);
 258         ts->ts_longretry = MS(status, AR_DataFailCnt);
 259         ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 260
 261         status = ACCESS_ONCE(ads->ds_txstatus5);
 262         ts->ts_rssi = MS(status, AR_TxRSSICombined);
 263         ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
 264         ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
 265         ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 266
 267         ts->evm0 = ads->AR_TxEVM0;
 268         ts->evm1 = ads->AR_TxEVM1;
 269         ts->evm2 = ads->AR_TxEVM2;
 270
 271         return 0;
 272 }
 273
 274 static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
 275                                     u32 pktLen, enum ath9k_pkt_type type,
 276                                     u32 txPower, u32 keyIx,
 277                                     enum ath9k_key_type keyType, u32 flags)
 278 {
 279         struct ar5416_desc *ads = AR5416DESC(ds);
 280
 281         if (txPower > 63)
 282                 txPower = 63;
 283
 284         ads->ds_ctl0 = (pktLen & AR_FrameLen)
 285                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
 286                 | SM(txPower, AR_XmitPower)
 287                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
 288                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
 289                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
 290
 291         ads->ds_ctl1 =
 292                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
 293                 | SM(type, AR_FrameType)
 294                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
 295                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
 296                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
 297
 298         ads->ds_ctl6 = SM(keyType, AR_EncrType);
 299
 300         if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
 301                 ads->ds_ctl8 = 0;
 302                 ads->ds_ctl9 = 0;
 303                 ads->ds_ctl10 = 0;
 304                 ads->ds_ctl11 = 0;
 305         }
 306 }
 307
 308 static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
 309 {
 310         struct ar5416_desc *ads = AR5416DESC(ds);
 311
 312         if (val)
 313                 ads->ds_ctl0 |= AR_ClrDestMask;
 314         else
 315                 ads->ds_ctl0 &= ~AR_ClrDestMask;
 316 }
 317
 318 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
 319                                           void *lastds,
 320                                           u32 durUpdateEn, u32 rtsctsRate,
 321                                           u32 rtsctsDuration,
 322                                           struct ath9k_11n_rate_series series[],
 323                                           u32 nseries, u32 flags)
 324 {
 325         struct ar5416_desc *ads = AR5416DESC(ds);
 326         struct ar5416_desc *last_ads = AR5416DESC(lastds);
 327         u32 ds_ctl0;
 328
 329         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
 330                 ds_ctl0 = ads->ds_ctl0;
 331
 332                 if (flags & ATH9K_TXDESC_RTSENA) {
 333                         ds_ctl0 &= ~AR_CTSEnable;
 334                         ds_ctl0 |= AR_RTSEnable;
 335                 } else {
 336                         ds_ctl0 &= ~AR_RTSEnable;
 337                         ds_ctl0 |= AR_CTSEnable;
 338                 }
 339
 340                 ads->ds_ctl0 = ds_ctl0;
 341         } else {
 342                 ads->ds_ctl0 =
 343                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
 344         }
 345
 346         ads->ds_ctl2 = set11nTries(series, 0)
 347                 | set11nTries(series, 1)
 348                 | set11nTries(series, 2)
 349                 | set11nTries(series, 3)
 350                 | (durUpdateEn ? AR_DurUpdateEna : 0)
 351                 | SM(0, AR_BurstDur);
 352
 353         ads->ds_ctl3 = set11nRate(series, 0)
 354                 | set11nRate(series, 1)
 355                 | set11nRate(series, 2)
 356                 | set11nRate(series, 3);
 357
 358         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
 359                 | set11nPktDurRTSCTS(series, 1);
 360
 361         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
 362                 | set11nPktDurRTSCTS(series, 3);
 363
 364         ads->ds_ctl7 = set11nRateFlags(series, 0)
 365                 | set11nRateFlags(series, 1)
 366                 | set11nRateFlags(series, 2)
 367                 | set11nRateFlags(series, 3)
 368                 | SM(rtsctsRate, AR_RTSCTSRate);
 369         last_ads->ds_ctl2 = ads->ds_ctl2;
 370         last_ads->ds_ctl3 = ads->ds_ctl3;
 371 }
 372
 373 static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
 374                                         u32 aggrLen)
 375 {
 376         struct ar5416_desc *ads = AR5416DESC(ds);
 377
 378         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
 379         ads->ds_ctl6 &= ~AR_AggrLen;
 380         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
 381 }
 382
 383 static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
 384                                          u32 numDelims)
 385 {
 386         struct ar5416_desc *ads = AR5416DESC(ds);
 387         unsigned int ctl6;
 388
 389         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
 390
 391         ctl6 = ads->ds_ctl6;
 392         ctl6 &= ~AR_PadDelim;
 393         ctl6 |= SM(numDelims, AR_PadDelim);
 394         ads->ds_ctl6 = ctl6;
 395 }
 396
 397 static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
 398 {
 399         struct ar5416_desc *ads = AR5416DESC(ds);
 400
 401         ads->ds_ctl1 |= AR_IsAggr;
 402         ads->ds_ctl1 &= ~AR_MoreAggr;
 403         ads->ds_ctl6 &= ~AR_PadDelim;
 404 }
 405
 406 static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
 407 {
 408         struct ar5416_desc *ads = AR5416DESC(ds);
 409
 410         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
 411 }
 412
 413 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
 414                           u32 size, u32 flags)
 415 {
 416         struct ar5416_desc *ads = AR5416DESC(ds);
 417         struct ath9k_hw_capabilities *pCap = &ah->caps;
 418
 419         ads->ds_ctl1 = size & AR_BufLen;
 420         if (flags & ATH9K_RXDESC_INTREQ)
 421                 ads->ds_ctl1 |= AR_RxIntrReq;
 422
 423         ads->ds_rxstatus8 &= ~AR_RxDone;
 424         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 425                 memset(&(ads->u), 0, sizeof(ads->u));
 426 }
 427 EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
 428
 429 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
 430 {
 431         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 432
 433         ops->rx_enable = ar9002_hw_rx_enable;
 434         ops->set_desc_link = ar9002_hw_set_desc_link;
 435         ops->get_isr = ar9002_hw_get_isr;
 436         ops->fill_txdesc = ar9002_hw_fill_txdesc;
 437         ops->proc_txdesc = ar9002_hw_proc_txdesc;
 438         ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
 439         ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
 440         ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
 441         ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
 442         ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
 443         ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
 444         ops->set_clrdmask = ar9002_hw_set_clrdmask;
 445 }