drivers/net/wireless/ath/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #define AR_EEPROM_MODAL_SPURS   5
  21
  22 #include "../ath.h"
  23 #include <net/cfg80211.h>
  24 #include "ar9003_eeprom.h"
  25
  26 #ifdef __BIG_ENDIAN
  27 #define AR5416_EEPROM_MAGIC 0x5aa5
  28 #else
  29 #define AR5416_EEPROM_MAGIC 0xa55a
  30 #endif
  31
  32 #define CTRY_DEBUG   0x1ff
  33 #define CTRY_DEFAULT 0
  34
  35 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  36 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  37 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  38 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  39 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  40 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  41 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  42 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  43 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  44
  45 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  46 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  47 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  48 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  49 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  50 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  51
  52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  53 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  54
  55 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  56 #define AR5416_EEPROM_S             2
  57 #define AR5416_EEPROM_OFFSET        0x2000
  58 #define AR5416_EEPROM_MAX           0xae0
  59
  60 #define AR5416_EEPROM_START_ADDR \
  61         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  62
  63 #define SD_NO_CTL               0xE0
  64 #define NO_CTL                  0xff
  65 #define CTL_MODE_M              0xf
  66 #define CTL_11A                 0
  67 #define CTL_11B                 1
  68 #define CTL_11G                 2
  69 #define CTL_2GHT20              5
  70 #define CTL_5GHT20              6
  71 #define CTL_2GHT40              7
  72 #define CTL_5GHT40              8
  73
  74 #define EXT_ADDITIVE (0x8000)
  75 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  76 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  77 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  78
  79 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  80 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  81
  82 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  83 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  84
  85 /*
  86  * For AR9285 and later chipsets, the following bits are not being programmed
  87  * in EEPROM and so need to be enabled always.
  88  *
  89  * Bit 0: en_fcc_mid
  90  * Bit 1: en_jap_mid
  91  * Bit 2: en_fcc_dfs_ht40
  92  * Bit 3: en_jap_ht40
  93  * Bit 4: en_jap_dfs_ht40
  94  */
  95 #define AR9285_RDEXT_DEFAULT    0x1F
  96
  97 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  98 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  99 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
 100
 101 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 102 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
 103                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 104 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
 105                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 106
 107 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 108 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 109 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 110 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 111
 112 #define EEP_RFSILENT_ENABLED        0x0001
 113 #define EEP_RFSILENT_ENABLED_S      0
 114 #define EEP_RFSILENT_POLARITY       0x0002
 115 #define EEP_RFSILENT_POLARITY_S     1
 116 #define EEP_RFSILENT_GPIO_SEL       0x001c
 117 #define EEP_RFSILENT_GPIO_SEL_S     2
 118
 119 #define AR5416_OPFLAGS_11A           0x01
 120 #define AR5416_OPFLAGS_11G           0x02
 121 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 122 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 123 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 124 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 125
 126 #define AR5416_EEP_NO_BACK_VER       0x1
 127 #define AR5416_EEP_VER               0xE
 128 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 129 #define AR5416_EEP_MINOR_VER_2       0x2
 130 #define AR5416_EEP_MINOR_VER_3       0x3
 131 #define AR5416_EEP_MINOR_VER_7       0x7
 132 #define AR5416_EEP_MINOR_VER_9       0x9
 133 #define AR5416_EEP_MINOR_VER_16      0x10
 134 #define AR5416_EEP_MINOR_VER_17      0x11
 135 #define AR5416_EEP_MINOR_VER_19      0x13
 136 #define AR5416_EEP_MINOR_VER_20      0x14
 137 #define AR5416_EEP_MINOR_VER_21      0x15
 138 #define AR5416_EEP_MINOR_VER_22      0x16
 139
 140 #define AR5416_NUM_5G_CAL_PIERS         8
 141 #define AR5416_NUM_2G_CAL_PIERS         4
 142 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 143 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 144 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 145 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 146 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 147 #define AR5416_NUM_CTLS                 24
 148 #define AR5416_NUM_BAND_EDGES           8
 149 #define AR5416_NUM_PD_GAINS             4
 150 #define AR5416_PD_GAINS_IN_MASK         4
 151 #define AR5416_PD_GAIN_ICEPTS           5
 152 #define AR5416_NUM_PDADC_VALUES         128
 153 #define AR5416_BCHAN_UNUSED             0xFF
 154 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 155 #define AR5416_MAX_CHAINS               3
 156 #define AR9300_MAX_CHAINS               3
 157 #define AR5416_PWR_TABLE_OFFSET_DB     -5
 158
 159 /* Rx gain type values */
 160 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 161 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 162 #define AR5416_EEP_RXGAIN_ORIG             2
 163
 164 /* Tx gain type values */
 165 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 166 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 167
 168 #define AR5416_EEP4K_START_LOC                64
 169 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 170 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 171 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 172 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 173 #define AR5416_EEP4K_NUM_CTLS                 12
 174 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 175 #define AR5416_EEP4K_NUM_PD_GAINS             2
 176 #define AR5416_EEP4K_MAX_CHAINS               1
 177
 178 #define AR9280_TX_GAIN_TABLE_SIZE 22
 179
 180 #define AR9287_EEP_VER               0xE
 181 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
 182 #define AR9287_EEP_MINOR_VER_1       0x1
 183 #define AR9287_EEP_MINOR_VER_2       0x2
 184 #define AR9287_EEP_MINOR_VER_3       0x3
 185 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
 186 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
 187 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
 188
 189 #define AR9287_EEP_START_LOC            128
 190 #define AR9287_HTC_EEP_START_LOC        256
 191 #define AR9287_NUM_2G_CAL_PIERS         3
 192 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
 193 #define AR9287_NUM_2G_20_TARGET_POWERS  3
 194 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 195 #define AR9287_NUM_CTLS                 12
 196 #define AR9287_NUM_BAND_EDGES           4
 197 #define AR9287_PD_GAIN_ICEPTS           1
 198 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 199 #define AR9287_EEPMISC_WOW              0x02
 200 #define AR9287_MAX_CHAINS               2
 201 #define AR9287_ANT_16S                  32
 202
 203 #define AR9287_DATA_SZ                  32
 204
 205 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 206
 207 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 208
 209 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
 210 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
 211
 212 #define LNA_CTL_BUF_MODE        BIT(0)
 213 #define LNA_CTL_ISEL_LO         BIT(1)
 214 #define LNA_CTL_ISEL_HI         BIT(2)
 215 #define LNA_CTL_BUF_IN          BIT(3)
 216 #define LNA_CTL_FEM_BAND        BIT(4)
 217 #define LNA_CTL_LOCAL_BIAS      BIT(5)
 218 #define LNA_CTL_FORCE_XPA       BIT(6)
 219 #define LNA_CTL_USE_ANT1        BIT(7)
 220
 221 enum eeprom_param {
 222         EEP_NFTHRESH_5,
 223         EEP_NFTHRESH_2,
 224         EEP_MAC_MSW,
 225         EEP_MAC_MID,
 226         EEP_MAC_LSW,
 227         EEP_REG_0,
 228         EEP_REG_1,
 229         EEP_OP_CAP,
 230         EEP_OP_MODE,
 231         EEP_RF_SILENT,
 232         EEP_OB_5,
 233         EEP_DB_5,
 234         EEP_OB_2,
 235         EEP_DB_2,
 236         EEP_MINOR_REV,
 237         EEP_TX_MASK,
 238         EEP_RX_MASK,
 239         EEP_FSTCLK_5G,
 240         EEP_RXGAIN_TYPE,
 241         EEP_OL_PWRCTRL,
 242         EEP_TXGAIN_TYPE,
 243         EEP_RC_CHAIN_MASK,
 244         EEP_DAC_HPWR_5G,
 245         EEP_FRAC_N_5G,
 246         EEP_DEV_TYPE,
 247         EEP_TEMPSENSE_SLOPE,
 248         EEP_TEMPSENSE_SLOPE_PAL_ON,
 249         EEP_PWR_TABLE_OFFSET,
 250         EEP_DRIVE_STRENGTH,
 251         EEP_INTERNAL_REGULATOR,
 252         EEP_SWREG,
 253         EEP_PAPRD,
 254         EEP_MODAL_VER,
 255         EEP_ANT_DIV_CTL1,
 256         EEP_CHAIN_MASK_REDUCE
 257 };
 258
 259 enum ar5416_rates {
 260         rate6mb, rate9mb, rate12mb, rate18mb,
 261         rate24mb, rate36mb, rate48mb, rate54mb,
 262         rate1l, rate2l, rate2s, rate5_5l,
 263         rate5_5s, rate11l, rate11s, rateXr,
 264         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 265         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 266         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 267         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 268         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 269         Ar5416RateSize
 270 };
 271
 272 enum ath9k_hal_freq_band {
 273         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 274         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 275 };
 276
 277 struct base_eep_header {
 278         u16 length;
 279         u16 checksum;
 280         u16 version;
 281         u8 opCapFlags;
 282         u8 eepMisc;
 283         u16 regDmn[2];
 284         u8 macAddr[6];
 285         u8 rxMask;
 286         u8 txMask;
 287         u16 rfSilent;
 288         u16 blueToothOptions;
 289         u16 deviceCap;
 290         u32 binBuildNumber;
 291         u8 deviceType;
 292         u8 pwdclkind;
 293         u8 fastClk5g;
 294         u8 divChain;
 295         u8 rxGainType;
 296         u8 dacHiPwrMode_5G;
 297         u8 openLoopPwrCntl;
 298         u8 dacLpMode;
 299         u8 txGainType;
 300         u8 rcChainMask;
 301         u8 desiredScaleCCK;
 302         u8 pwr_table_offset;
 303         u8 frac_n_5g;
 304         u8 futureBase_3[21];
 305 } __packed;
 306
 307 struct base_eep_header_4k {
 308         u16 length;
 309         u16 checksum;
 310         u16 version;
 311         u8 opCapFlags;
 312         u8 eepMisc;
 313         u16 regDmn[2];
 314         u8 macAddr[6];
 315         u8 rxMask;
 316         u8 txMask;
 317         u16 rfSilent;
 318         u16 blueToothOptions;
 319         u16 deviceCap;
 320         u32 binBuildNumber;
 321         u8 deviceType;
 322         u8 txGainType;
 323 } __packed;
 324
 325
 326 struct spur_chan {
 327         u16 spurChan;
 328         u8 spurRangeLow;
 329         u8 spurRangeHigh;
 330 } __packed;
 331
 332 struct modal_eep_header {
 333         u32 antCtrlChain[AR5416_MAX_CHAINS];
 334         u32 antCtrlCommon;
 335         u8 antennaGainCh[AR5416_MAX_CHAINS];
 336         u8 switchSettling;
 337         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 338         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 339         u8 adcDesiredSize;
 340         u8 pgaDesiredSize;
 341         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 342         u8 txEndToXpaOff;
 343         u8 txEndToRxOn;
 344         u8 txFrameToXpaOn;
 345         u8 thresh62;
 346         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 347         u8 xpdGain;
 348         u8 xpd;
 349         u8 iqCalICh[AR5416_MAX_CHAINS];
 350         u8 iqCalQCh[AR5416_MAX_CHAINS];
 351         u8 pdGainOverlap;
 352         u8 ob;
 353         u8 db;
 354         u8 xpaBiasLvl;
 355         u8 pwrDecreaseFor2Chain;
 356         u8 pwrDecreaseFor3Chain;
 357         u8 txFrameToDataStart;
 358         u8 txFrameToPaOn;
 359         u8 ht40PowerIncForPdadc;
 360         u8 bswAtten[AR5416_MAX_CHAINS];
 361         u8 bswMargin[AR5416_MAX_CHAINS];
 362         u8 swSettleHt40;
 363         u8 xatten2Db[AR5416_MAX_CHAINS];
 364         u8 xatten2Margin[AR5416_MAX_CHAINS];
 365         u8 ob_ch1;
 366         u8 db_ch1;
 367         u8 lna_ctl;
 368         u8 miscBits;
 369         u16 xpaBiasLvlFreq[3];
 370         u8 futureModal[6];
 371
 372         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 373 } __packed;
 374
 375 struct calDataPerFreqOpLoop {
 376         u8 pwrPdg[2][5];
 377         u8 vpdPdg[2][5];
 378         u8 pcdac[2][5];
 379         u8 empty[2][5];
 380 } __packed;
 381
 382 struct modal_eep_4k_header {
 383         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 384         u32 antCtrlCommon;
 385         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 386         u8 switchSettling;
 387         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 388         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 389         u8 adcDesiredSize;
 390         u8 pgaDesiredSize;
 391         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 392         u8 txEndToXpaOff;
 393         u8 txEndToRxOn;
 394         u8 txFrameToXpaOn;
 395         u8 thresh62;
 396         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 397         u8 xpdGain;
 398         u8 xpd;
 399         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 400         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 401         u8 pdGainOverlap;
 402 #ifdef __BIG_ENDIAN_BITFIELD
 403         u8 ob_1:4, ob_0:4;
 404         u8 db1_1:4, db1_0:4;
 405 #else
 406         u8 ob_0:4, ob_1:4;
 407         u8 db1_0:4, db1_1:4;
 408 #endif
 409         u8 xpaBiasLvl;
 410         u8 txFrameToDataStart;
 411         u8 txFrameToPaOn;
 412         u8 ht40PowerIncForPdadc;
 413         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
 414         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
 415         u8 swSettleHt40;
 416         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 417         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 418 #ifdef __BIG_ENDIAN_BITFIELD
 419         u8 db2_1:4, db2_0:4;
 420 #else
 421         u8 db2_0:4, db2_1:4;
 422 #endif
 423         u8 version;
 424 #ifdef __BIG_ENDIAN_BITFIELD
 425         u8 ob_3:4, ob_2:4;
 426         u8 antdiv_ctl1:4, ob_4:4;
 427         u8 db1_3:4, db1_2:4;
 428         u8 antdiv_ctl2:4, db1_4:4;
 429         u8 db2_2:4, db2_3:4;
 430         u8 reserved:4, db2_4:4;
 431 #else
 432         u8 ob_2:4, ob_3:4;
 433         u8 ob_4:4, antdiv_ctl1:4;
 434         u8 db1_2:4, db1_3:4;
 435         u8 db1_4:4, antdiv_ctl2:4;
 436         u8 db2_2:4, db2_3:4;
 437         u8 db2_4:4, reserved:4;
 438 #endif
 439         u8 tx_diversity;
 440         u8 flc_pwr_thresh;
 441         u8 bb_scale_smrt_antenna;
 442 #define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
 443         u8 futureModal[1];
 444         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 445 } __packed;
 446
 447 struct base_eep_ar9287_header {
 448         u16 length;
 449         u16 checksum;
 450         u16 version;
 451         u8 opCapFlags;
 452         u8 eepMisc;
 453         u16 regDmn[2];
 454         u8 macAddr[6];
 455         u8 rxMask;
 456         u8 txMask;
 457         u16 rfSilent;
 458         u16 blueToothOptions;
 459         u16 deviceCap;
 460         u32 binBuildNumber;
 461         u8 deviceType;
 462         u8 openLoopPwrCntl;
 463         int8_t pwrTableOffset;
 464         int8_t tempSensSlope;
 465         int8_t tempSensSlopePalOn;
 466         u8 futureBase[29];
 467 } __packed;
 468
 469 struct modal_eep_ar9287_header {
 470         u32 antCtrlChain[AR9287_MAX_CHAINS];
 471         u32 antCtrlCommon;
 472         int8_t antennaGainCh[AR9287_MAX_CHAINS];
 473         u8 switchSettling;
 474         u8 txRxAttenCh[AR9287_MAX_CHAINS];
 475         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
 476         int8_t adcDesiredSize;
 477         u8 txEndToXpaOff;
 478         u8 txEndToRxOn;
 479         u8 txFrameToXpaOn;
 480         u8 thresh62;
 481         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
 482         u8 xpdGain;
 483         u8 xpd;
 484         int8_t iqCalICh[AR9287_MAX_CHAINS];
 485         int8_t iqCalQCh[AR9287_MAX_CHAINS];
 486         u8 pdGainOverlap;
 487         u8 xpaBiasLvl;
 488         u8 txFrameToDataStart;
 489         u8 txFrameToPaOn;
 490         u8 ht40PowerIncForPdadc;
 491         u8 bswAtten[AR9287_MAX_CHAINS];
 492         u8 bswMargin[AR9287_MAX_CHAINS];
 493         u8 swSettleHt40;
 494         u8 version;
 495         u8 db1;
 496         u8 db2;
 497         u8 ob_cck;
 498         u8 ob_psk;
 499         u8 ob_qam;
 500         u8 ob_pal_off;
 501         u8 futureModal[30];
 502         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 503 } __packed;
 504
 505 struct cal_data_per_freq {
 506         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 507         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 508 } __packed;
 509
 510 struct cal_data_per_freq_4k {
 511         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 512         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 513 } __packed;
 514
 515 struct cal_target_power_leg {
 516         u8 bChannel;
 517         u8 tPow2x[4];
 518 } __packed;
 519
 520 struct cal_target_power_ht {
 521         u8 bChannel;
 522         u8 tPow2x[8];
 523 } __packed;
 524
 525 struct cal_ctl_edges {
 526         u8 bChannel;
 527         u8 ctl;
 528 } __packed;
 529
 530 struct cal_data_op_loop_ar9287 {
 531         u8 pwrPdg[2][5];
 532         u8 vpdPdg[2][5];
 533         u8 pcdac[2][5];
 534         u8 empty[2][5];
 535 } __packed;
 536
 537 struct cal_data_per_freq_ar9287 {
 538         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 539         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 540 } __packed;
 541
 542 union cal_data_per_freq_ar9287_u {
 543         struct cal_data_op_loop_ar9287 calDataOpen;
 544         struct cal_data_per_freq_ar9287 calDataClose;
 545 } __packed;
 546
 547 struct cal_ctl_data_ar9287 {
 548         struct cal_ctl_edges
 549         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
 550 } __packed;
 551
 552 struct cal_ctl_data {
 553         struct cal_ctl_edges
 554         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 555 } __packed;
 556
 557 struct cal_ctl_data_4k {
 558         struct cal_ctl_edges
 559         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 560 } __packed;
 561
 562 struct ar5416_eeprom_def {
 563         struct base_eep_header baseEepHeader;
 564         u8 custData[64];
 565         struct modal_eep_header modalHeader[2];
 566         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 567         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 568         struct cal_data_per_freq
 569          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 570         struct cal_data_per_freq
 571          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 572         struct cal_target_power_leg
 573          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 574         struct cal_target_power_ht
 575          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 576         struct cal_target_power_ht
 577          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 578         struct cal_target_power_leg
 579          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 580         struct cal_target_power_leg
 581          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 582         struct cal_target_power_ht
 583          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 584         struct cal_target_power_ht
 585          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 586         u8 ctlIndex[AR5416_NUM_CTLS];
 587         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 588         u8 padding;
 589 } __packed;
 590
 591 struct ar5416_eeprom_4k {
 592         struct base_eep_header_4k baseEepHeader;
 593         u8 custData[20];
 594         struct modal_eep_4k_header modalHeader;
 595         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 596         struct cal_data_per_freq_4k
 597         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 598         struct cal_target_power_leg
 599         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 600         struct cal_target_power_leg
 601         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 602         struct cal_target_power_ht
 603         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 604         struct cal_target_power_ht
 605         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 606         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 607         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 608         u8 padding;
 609 } __packed;
 610
 611 struct ar9287_eeprom {
 612         struct base_eep_ar9287_header baseEepHeader;
 613         u8 custData[AR9287_DATA_SZ];
 614         struct modal_eep_ar9287_header modalHeader;
 615         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
 616         union cal_data_per_freq_ar9287_u
 617         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
 618         struct cal_target_power_leg
 619         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
 620         struct cal_target_power_leg
 621         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
 622         struct cal_target_power_ht
 623         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
 624         struct cal_target_power_ht
 625         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
 626         u8 ctlIndex[AR9287_NUM_CTLS];
 627         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
 628         u8 padding;
 629 } __packed;
 630
 631 enum reg_ext_bitmap {
 632         REG_EXT_FCC_MIDBAND = 0,
 633         REG_EXT_JAPAN_MIDBAND = 1,
 634         REG_EXT_FCC_DFS_HT40 = 2,
 635         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 636         REG_EXT_JAPAN_DFS_HT40 = 4
 637 };
 638
 639 struct ath9k_country_entry {
 640         u16 countryCode;
 641         u16 regDmnEnum;
 642         u16 regDmn5G;
 643         u16 regDmn2G;
 644         u8 isMultidomain;
 645         u8 iso[3];
 646 };
 647
 648 struct eeprom_ops {
 649         int (*check_eeprom)(struct ath_hw *hw);
 650         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 651         bool (*fill_eeprom)(struct ath_hw *hw);
 652         int (*get_eeprom_ver)(struct ath_hw *hw);
 653         int (*get_eeprom_rev)(struct ath_hw *hw);
 654         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 655         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 656         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 657                            u16 cfgCtl, u8 twiceAntennaReduction,
 658                            u8 twiceMaxRegulatoryPower, u8 powerLimit,
 659                            bool test);
 660         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 661 };
 662
 663 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
 664 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
 665                                u32 shift, u32 val);
 666 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 667                              int16_t targetLeft,
 668                              int16_t targetRight);
 669 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
 670                                     u16 *indexL, u16 *indexR);
 671 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
 672 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
 673                                   int eep_start_loc, int size);
 674 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
 675                              u8 *pVpdList, u16 numIntercepts,
 676                              u8 *pRetVpdList);
 677 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 678                                        struct ath9k_channel *chan,
 679                                        struct cal_target_power_leg *powInfo,
 680                                        u16 numChannels,
 681                                        struct cal_target_power_leg *pNewPower,
 682                                        u16 numRates, bool isExtTarget);
 683 void ath9k_hw_get_target_powers(struct ath_hw *ah,
 684                                 struct ath9k_channel *chan,
 685                                 struct cal_target_power_ht *powInfo,
 686                                 u16 numChannels,
 687                                 struct cal_target_power_ht *pNewPower,
 688                                 u16 numRates, bool isHt40Target);
 689 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 690                                 bool is2GHz, int num_band_edges);
 691 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 692 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 693
 694 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
 695                                 struct ath9k_channel *chan,
 696                                 void *pRawDataSet,
 697                                 u8 *bChans, u16 availPiers,
 698                                 u16 tPdGainOverlap,
 699                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 700                                 u16 numXpdGains);
 701
 702 #define ar5416_get_ntxchains(_txchainmask)                      \
 703         (((_txchainmask >> 2) & 1) +                            \
 704          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 705
 706 extern const struct eeprom_ops eep_def_ops;
 707 extern const struct eeprom_ops eep_4k_ops;
 708 extern const struct eeprom_ops eep_ar9287_ops;
 709 extern const struct eeprom_ops eep_ar9287_ops;
 710 extern const struct eeprom_ops eep_ar9300_ops;
 711
 712 #endif /* EEPROM_H */