cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / wireless / b43 / phy_ht.h
blob7ad7affc8df08b8bc9e2caa7a03f5cb4e4e8e431
1 #ifndef B43_PHY_HT_H_
2 #define B43_PHY_HT_H_
4 #include "phy_common.h"
7 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
8 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
9 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
10 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
11 #define B43_PHY_HT_BW1 0x1CE
12 #define B43_PHY_HT_BW2 0x1CF
13 #define B43_PHY_HT_BW3 0x1D0
14 #define B43_PHY_HT_BW4 0x1D1
15 #define B43_PHY_HT_BW5 0x1D2
16 #define B43_PHY_HT_BW6 0x1D3
18 #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
20 #define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110)
21 #define B43_PHY_HT_AFE_CTL2 B43_PHY_EXTG(0x111)
22 #define B43_PHY_HT_AFE_CTL3 B43_PHY_EXTG(0x114)
23 #define B43_PHY_HT_AFE_CTL4 B43_PHY_EXTG(0x115)
24 #define B43_PHY_HT_AFE_CTL5 B43_PHY_EXTG(0x118)
25 #define B43_PHY_HT_AFE_CTL6 B43_PHY_EXTG(0x119)
28 /* Values for PHY registers used on channel switching */
29 struct b43_phy_ht_channeltab_e_phy {
30 u16 bw1;
31 u16 bw2;
32 u16 bw3;
33 u16 bw4;
34 u16 bw5;
35 u16 bw6;
39 struct b43_phy_ht {
43 struct b43_phy_operations;
44 extern const struct b43_phy_operations b43_phyops_ht;
46 #endif /* B43_PHY_HT_H_ */