cris: add arch/cris/include/asm/serial.h

[linux-2.6/next.git] / drivers / net / wireless / iwlwifi / iwl-trans-rx-pcie.c

/******************************************************************************
 *
 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/gfp.h>

#include "iwl-dev.h"
#include "iwl-agn.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-trans-int-pcie.h"

/******************************************************************************
 *
 * RX path functions
 *
 ******************************************************************************/

/*
 * Rx theory of operation
 *
 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
 * each of which point to Receive Buffers to be filled by the NIC.  These get
 * used not only for Rx frames, but for any command response or notification
 * from the NIC.  The driver and NIC manage the Rx buffers by means
 * of indexes into the circular buffer.
 *
 * Rx Queue Indexes
 * The host/firmware share two index registers for managing the Rx buffers.
 *
 * The READ index maps to the first position that the firmware may be writing
 * to -- the driver can read up to (but not including) this position and get
 * good data.
 * The READ index is managed by the firmware once the card is enabled.
 *
 * The WRITE index maps to the last position the driver has read from -- the
 * position preceding WRITE is the last slot the firmware can place a packet.
 *
 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
 * WRITE = READ.
 *
 * During initialization, the host sets up the READ queue position to the first
 * INDEX position, and WRITE to the last (READ - 1 wrapped)
 *
 * When the firmware places a packet in a buffer, it will advance the READ index
 * and fire the RX interrupt.  The driver can then query the READ index and
 * process as many packets as possible, moving the WRITE index forward as it
 * resets the Rx queue buffers with new memory.
 *
 * The management in the driver is as follows:
 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
 *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
 *   to replenish the iwl->rxq->rx_free.
 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
 *   iwl->rxq is replenished and the READ INDEX is updated (updating the
 *   'processed' and 'read' driver indexes as well)
 * + A received packet is processed and handed to the kernel network stack,
 *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
 *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
 *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
 *   were enough free buffers and RX_STALLED is set it is cleared.
 *
 *
 * Driver sequence:
 *
 * iwl_rx_queue_alloc()   Allocates rx_free
 * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
 *                            iwl_rx_queue_restock
 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 *                            queue, updates firmware pointers, and updates
 *                            the WRITE index.  If insufficient rx_free buffers
 *                            are available, schedules iwl_rx_replenish
 *
 * -- enable interrupts --
 * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 *                            READ INDEX, detaching the SKB from the pool.
 *                            Moves the packet buffer from queue to rx_used.
 *                            Calls iwl_rx_queue_restock to refill any empty
 *                            slots.
 * ...
 *
 */

/**
 * iwl_rx_queue_space - Return number of free slots available in queue.
 */
static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
{
        int s = q->read - q->write;
        if (s <= 0)
                s += RX_QUEUE_SIZE;
        /* keep some buffer to not confuse full and empty queue */
        s -= 2;
        if (s < 0)
                s = 0;
        return s;
}

/**
 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 */
void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
                        struct iwl_rx_queue *q)
{
        unsigned long flags;
        u32 reg;

        spin_lock_irqsave(&q->lock, flags);

        if (q->need_update == 0)
                goto exit_unlock;

        if (priv->cfg->base_params->shadow_reg_enable) {
                /* shadow register enabled */
                /* Device expects a multiple of 8 */
                q->write_actual = (q->write & ~0x7);
                iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual);
        } else {
                /* If power-saving is in use, make sure device is awake */
                if (test_bit(STATUS_POWER_PMI, &priv->status)) {
                        reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);

                        if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
                                IWL_DEBUG_INFO(priv,
                                        "Rx queue requesting wakeup,"
                                        " GP1 = 0x%x\n", reg);
                                iwl_set_bit(priv, CSR_GP_CNTRL,
                                        CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
                                goto exit_unlock;
                        }

                        q->write_actual = (q->write & ~0x7);
                        iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
                                        q->write_actual);

                /* Else device is assumed to be awake */
                } else {
                        /* Device expects a multiple of 8 */
                        q->write_actual = (q->write & ~0x7);
                        iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
                                q->write_actual);
                }
        }
        q->need_update = 0;

 exit_unlock:
        spin_unlock_irqrestore(&q->lock, flags);
}

/**
 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 */
static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
                                          dma_addr_t dma_addr)
{
        return cpu_to_le32((u32)(dma_addr >> 8));
}

/**
 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 *
 * If there are slots in the RX queue that need to be restocked,
 * and we have free pre-allocated buffers, fill the ranks as much
 * as we can, pulling from rx_free.
 *
 * This moves the 'write' index forward to catch up with 'processed', and
 * also updates the memory address in the firmware to reference the new
 * target buffer.
 */
static void iwlagn_rx_queue_restock(struct iwl_priv *priv)
{
        struct iwl_rx_queue *rxq = &priv->rxq;
        struct list_head *element;
        struct iwl_rx_mem_buffer *rxb;
        unsigned long flags;

        spin_lock_irqsave(&rxq->lock, flags);
        while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
                /* The overwritten rxb must be a used one */
                rxb = rxq->queue[rxq->write];
                BUG_ON(rxb && rxb->page);

                /* Get next free Rx buffer, remove from free list */
                element = rxq->rx_free.next;
                rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
                list_del(element);

                /* Point to Rx buffer via next RBD in circular buffer */
                rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
                                                              rxb->page_dma);
                rxq->queue[rxq->write] = rxb;
                rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
                rxq->free_count--;
        }
        spin_unlock_irqrestore(&rxq->lock, flags);
        /* If the pre-allocated buffer pool is dropping low, schedule to
         * refill it */
        if (rxq->free_count <= RX_LOW_WATERMARK)
                queue_work(priv->workqueue, &priv->rx_replenish);


        /* If we've added more space for the firmware to place data, tell it.
         * Increment device's write pointer in multiples of 8. */
        if (rxq->write_actual != (rxq->write & ~0x7)) {
                spin_lock_irqsave(&rxq->lock, flags);
                rxq->need_update = 1;
                spin_unlock_irqrestore(&rxq->lock, flags);
                iwl_rx_queue_update_write_ptr(priv, rxq);
        }
}

/**
 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 *
 * When moving to rx_free an SKB is allocated for the slot.
 *
 * Also restock the Rx queue via iwl_rx_queue_restock.
 * This is called as a scheduled work item (except for during initialization)
 */
static void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
{
        struct iwl_rx_queue *rxq = &priv->rxq;
        struct list_head *element;
        struct iwl_rx_mem_buffer *rxb;
        struct page *page;
        unsigned long flags;
        gfp_t gfp_mask = priority;

        while (1) {
                spin_lock_irqsave(&rxq->lock, flags);
                if (list_empty(&rxq->rx_used)) {
                        spin_unlock_irqrestore(&rxq->lock, flags);
                        return;
                }
                spin_unlock_irqrestore(&rxq->lock, flags);

                if (rxq->free_count > RX_LOW_WATERMARK)
                        gfp_mask |= __GFP_NOWARN;

                if (priv->hw_params.rx_page_order > 0)
                        gfp_mask |= __GFP_COMP;

                /* Alloc a new receive buffer */
                page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
                if (!page) {
                        if (net_ratelimit())
                                IWL_DEBUG_INFO(priv, "alloc_pages failed, "
                                               "order: %d\n",
                                               priv->hw_params.rx_page_order);

                        if ((rxq->free_count <= RX_LOW_WATERMARK) &&
                            net_ratelimit())
                                IWL_CRIT(priv, "Failed to alloc_pages with %s."
                                         "Only %u free buffers remaining.\n",
                                         priority == GFP_ATOMIC ?
                                         "GFP_ATOMIC" : "GFP_KERNEL",
                                         rxq->free_count);
                        /* We don't reschedule replenish work here -- we will
                         * call the restock method and if it still needs
                         * more buffers it will schedule replenish */
                        return;
                }

                spin_lock_irqsave(&rxq->lock, flags);

                if (list_empty(&rxq->rx_used)) {
                        spin_unlock_irqrestore(&rxq->lock, flags);
                        __free_pages(page, priv->hw_params.rx_page_order);
                        return;
                }
                element = rxq->rx_used.next;
                rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
                list_del(element);

                spin_unlock_irqrestore(&rxq->lock, flags);

                BUG_ON(rxb->page);
                rxb->page = page;
                /* Get physical address of the RB */
                rxb->page_dma = dma_map_page(priv->bus->dev, page, 0,
                                PAGE_SIZE << priv->hw_params.rx_page_order,
                                DMA_FROM_DEVICE);
                /* dma address must be no more than 36 bits */
                BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
                /* and also 256 byte aligned! */
                BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));

                spin_lock_irqsave(&rxq->lock, flags);

                list_add_tail(&rxb->list, &rxq->rx_free);
                rxq->free_count++;

                spin_unlock_irqrestore(&rxq->lock, flags);
        }
}

void iwlagn_rx_replenish(struct iwl_priv *priv)
{
        unsigned long flags;

        iwlagn_rx_allocate(priv, GFP_KERNEL);

        spin_lock_irqsave(&priv->lock, flags);
        iwlagn_rx_queue_restock(priv);
        spin_unlock_irqrestore(&priv->lock, flags);
}

static void iwlagn_rx_replenish_now(struct iwl_priv *priv)
{
        iwlagn_rx_allocate(priv, GFP_ATOMIC);

        iwlagn_rx_queue_restock(priv);
}

void iwl_bg_rx_replenish(struct work_struct *data)
{
        struct iwl_priv *priv =
            container_of(data, struct iwl_priv, rx_replenish);

        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
                return;

        mutex_lock(&priv->mutex);
        iwlagn_rx_replenish(priv);
        mutex_unlock(&priv->mutex);
}

/**
 * iwl_rx_handle - Main entry function for receiving responses from uCode
 *
 * Uses the priv->rx_handlers callback function array to invoke
 * the appropriate handlers, including command responses,
 * frame-received notifications, and other notifications.
 */
static void iwl_rx_handle(struct iwl_priv *priv)
{
        struct iwl_rx_mem_buffer *rxb;
        struct iwl_rx_packet *pkt;
        struct iwl_rx_queue *rxq = &priv->rxq;
        u32 r, i;
        int reclaim;
        unsigned long flags;
        u8 fill_rx = 0;
        u32 count = 8;
        int total_empty;

        /* uCode's read index (stored in shared DRAM) indicates the last Rx
         * buffer that the driver may process (last buffer filled by ucode). */
        r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
        i = rxq->read;

        /* Rx interrupt, but nothing sent from uCode */
        if (i == r)
                IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);

        /* calculate total frames need to be restock after handling RX */
        total_empty = r - rxq->write_actual;
        if (total_empty < 0)
                total_empty += RX_QUEUE_SIZE;

        if (total_empty > (RX_QUEUE_SIZE / 2))
                fill_rx = 1;

        while (i != r) {
                int len;

                rxb = rxq->queue[i];

                /* If an RXB doesn't have a Rx queue slot associated with it,
                 * then a bug has been introduced in the queue refilling
                 * routines -- catch it here */
                if (WARN_ON(rxb == NULL)) {
                        i = (i + 1) & RX_QUEUE_MASK;
                        continue;
                }

                rxq->queue[i] = NULL;

                dma_unmap_page(priv->bus->dev, rxb->page_dma,
                               PAGE_SIZE << priv->hw_params.rx_page_order,
                               DMA_FROM_DEVICE);
                pkt = rxb_addr(rxb);

                IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
                        i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);

                len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
                len += sizeof(u32); /* account for status word */
                trace_iwlwifi_dev_rx(priv, pkt, len);

                /* Reclaim a command buffer only if this packet is a response
                 *   to a (driver-originated) command.
                 * If the packet (e.g. Rx frame) originated from uCode,
                 *   there is no command buffer to reclaim.
                 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
                 *   but apparently a few don't get set; catch them here. */
                reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
                        (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
                        (pkt->hdr.cmd != REPLY_RX) &&
                        (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
                        (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
                        (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
                        (pkt->hdr.cmd != REPLY_TX);

                iwl_rx_dispatch(priv, rxb);

                /*
                 * XXX: After here, we should always check rxb->page
                 * against NULL before touching it or its virtual
                 * memory (pkt). Because some rx_handler might have
                 * already taken or freed the pages.
                 */

                if (reclaim) {
                        /* Invoke any callbacks, transfer the buffer to caller,
                         * and fire off the (possibly) blocking
                         * trans_send_cmd()
                         * as we reclaim the driver command queue */
                        if (rxb->page)
                                iwl_tx_cmd_complete(priv, rxb);
                        else
                                IWL_WARN(priv, "Claim null rxb?\n");
                }

                /* Reuse the page if possible. For notification packets and
                 * SKBs that fail to Rx correctly, add them back into the
                 * rx_free list for reuse later. */
                spin_lock_irqsave(&rxq->lock, flags);
                if (rxb->page != NULL) {
                        rxb->page_dma = dma_map_page(priv->bus->dev, rxb->page,
                                0, PAGE_SIZE << priv->hw_params.rx_page_order,
                                DMA_FROM_DEVICE);
                        list_add_tail(&rxb->list, &rxq->rx_free);
                        rxq->free_count++;
                } else
                        list_add_tail(&rxb->list, &rxq->rx_used);

                spin_unlock_irqrestore(&rxq->lock, flags);

                i = (i + 1) & RX_QUEUE_MASK;
                /* If there are a lot of unused frames,
                 * restock the Rx queue so ucode wont assert. */
                if (fill_rx) {
                        count++;
                        if (count >= 8) {
                                rxq->read = i;
                                iwlagn_rx_replenish_now(priv);
                                count = 0;
                        }
                }
        }

        /* Backtrack one entry */
        rxq->read = i;
        if (fill_rx)
                iwlagn_rx_replenish_now(priv);
        else
                iwlagn_rx_queue_restock(priv);
}

/* tasklet for iwlagn interrupt */
void iwl_irq_tasklet(struct iwl_priv *priv)
{
        u32 inta = 0;
        u32 handled = 0;
        unsigned long flags;
        u32 i;
#ifdef CONFIG_IWLWIFI_DEBUG
        u32 inta_mask;
#endif

        spin_lock_irqsave(&priv->lock, flags);

        /* Ack/clear/reset pending uCode interrupts.
         * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
         */
        /* There is a hardware bug in the interrupt mask function that some
         * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
         * they are disabled in the CSR_INT_MASK register. Furthermore the
         * ICT interrupt handling mechanism has another bug that might cause
         * these unmasked interrupts fail to be detected. We workaround the
         * hardware bugs here by ACKing all the possible interrupts so that
         * interrupt coalescing can still be achieved.
         */
        iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask);

        inta = priv->inta;

#ifdef CONFIG_IWLWIFI_DEBUG
        if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
                /* just for debug */
                inta_mask = iwl_read32(priv, CSR_INT_MASK);
                IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
                                inta, inta_mask);
        }
#endif

        spin_unlock_irqrestore(&priv->lock, flags);

        /* saved interrupt in inta variable now we can reset priv->inta */
        priv->inta = 0;

        /* Now service all interrupt bits discovered above. */
        if (inta & CSR_INT_BIT_HW_ERR) {
                IWL_ERR(priv, "Hardware error detected.  Restarting.\n");

                /* Tell the device to stop sending interrupts */
                iwl_disable_interrupts(priv);

                priv->isr_stats.hw++;
                iwl_irq_handle_error(priv);

                handled |= CSR_INT_BIT_HW_ERR;

                return;
        }

#ifdef CONFIG_IWLWIFI_DEBUG
        if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
                /* NIC fires this, but we don't use it, redundant with WAKEUP */
                if (inta & CSR_INT_BIT_SCD) {
                        IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
                                      "the frame/frames.\n");
                        priv->isr_stats.sch++;
                }

                /* Alive notification via Rx interrupt will do the real work */
                if (inta & CSR_INT_BIT_ALIVE) {
                        IWL_DEBUG_ISR(priv, "Alive interrupt\n");
                        priv->isr_stats.alive++;
                }
        }
#endif
        /* Safely ignore these bits for debug checks below */
        inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);

        /* HW RF KILL switch toggled */
        if (inta & CSR_INT_BIT_RF_KILL) {
                int hw_rf_kill = 0;
                if (!(iwl_read32(priv, CSR_GP_CNTRL) &
                                CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
                        hw_rf_kill = 1;

                IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
                                hw_rf_kill ? "disable radio" : "enable radio");

                priv->isr_stats.rfkill++;

                /* driver only loads ucode once setting the interface up.
                 * the driver allows loading the ucode even if the radio
                 * is killed. Hence update the killswitch state here. The
                 * rfkill handler will care about restarting if needed.
                 */
                if (!test_bit(STATUS_ALIVE, &priv->status)) {
                        if (hw_rf_kill)
                                set_bit(STATUS_RF_KILL_HW, &priv->status);
                        else
                                clear_bit(STATUS_RF_KILL_HW, &priv->status);
                        wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
                }

                handled |= CSR_INT_BIT_RF_KILL;
        }

        /* Chip got too hot and stopped itself */
        if (inta & CSR_INT_BIT_CT_KILL) {
                IWL_ERR(priv, "Microcode CT kill error detected.\n");
                priv->isr_stats.ctkill++;
                handled |= CSR_INT_BIT_CT_KILL;
        }

        /* Error detected by uCode */
        if (inta & CSR_INT_BIT_SW_ERR) {
                IWL_ERR(priv, "Microcode SW error detected. "
                        " Restarting 0x%X.\n", inta);
                priv->isr_stats.sw++;
                iwl_irq_handle_error(priv);
                handled |= CSR_INT_BIT_SW_ERR;
        }

        /* uCode wakes up after power-down sleep */
        if (inta & CSR_INT_BIT_WAKEUP) {
                IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
                iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
                for (i = 0; i < priv->hw_params.max_txq_num; i++)
                        iwl_txq_update_write_ptr(priv, &priv->txq[i]);

                priv->isr_stats.wakeup++;

                handled |= CSR_INT_BIT_WAKEUP;
        }

        /* All uCode command responses, including Tx command responses,
         * Rx "responses" (frame-received notification), and other
         * notifications from uCode come through here*/
        if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
                        CSR_INT_BIT_RX_PERIODIC)) {
                IWL_DEBUG_ISR(priv, "Rx interrupt\n");
                if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
                        handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
                        iwl_write32(priv, CSR_FH_INT_STATUS,
                                        CSR_FH_INT_RX_MASK);
                }
                if (inta & CSR_INT_BIT_RX_PERIODIC) {
                        handled |= CSR_INT_BIT_RX_PERIODIC;
                        iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
                }
                /* Sending RX interrupt require many steps to be done in the
                 * the device:
                 * 1- write interrupt to current index in ICT table.
                 * 2- dma RX frame.
                 * 3- update RX shared data to indicate last write index.
                 * 4- send interrupt.
                 * This could lead to RX race, driver could receive RX interrupt
                 * but the shared data changes does not reflect this;
                 * periodic interrupt will detect any dangling Rx activity.
                 */

                /* Disable periodic interrupt; we use it as just a one-shot. */
                iwl_write8(priv, CSR_INT_PERIODIC_REG,
                            CSR_INT_PERIODIC_DIS);
                iwl_rx_handle(priv);

                /*
                 * Enable periodic interrupt in 8 msec only if we received
                 * real RX interrupt (instead of just periodic int), to catch
                 * any dangling Rx interrupt.  If it was just the periodic
                 * interrupt, there was no dangling Rx activity, and no need
                 * to extend the periodic interrupt; one-shot is enough.
                 */
                if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
                        iwl_write8(priv, CSR_INT_PERIODIC_REG,
                                    CSR_INT_PERIODIC_ENA);

                priv->isr_stats.rx++;
        }

        /* This "Tx" DMA channel is used only for loading uCode */
        if (inta & CSR_INT_BIT_FH_TX) {
                iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
                IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
                priv->isr_stats.tx++;
                handled |= CSR_INT_BIT_FH_TX;
                /* Wake up uCode load routine, now that load is complete */
                priv->ucode_write_complete = 1;
                wake_up_interruptible(&priv->wait_command_queue);
        }

        if (inta & ~handled) {
                IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
                priv->isr_stats.unhandled++;
        }

        if (inta & ~(priv->inta_mask)) {
                IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
                         inta & ~priv->inta_mask);
        }

        /* Re-enable all interrupts */
        /* only Re-enable if disabled by irq */
        if (test_bit(STATUS_INT_ENABLED, &priv->status))
                iwl_enable_interrupts(priv);
        /* Re-enable RF_KILL if it occurred */
        else if (handled & CSR_INT_BIT_RF_KILL)
                iwl_enable_rfkill_int(priv);
}

/******************************************************************************
 *
 * ICT functions
 *
 ******************************************************************************/
#define ICT_COUNT (PAGE_SIZE/sizeof(u32))

/* Free dram table */
void iwl_free_isr_ict(struct iwl_priv *priv)
{
        if (priv->ict_tbl_vir) {
                dma_free_coherent(priv->bus->dev,
                                  (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
                                  priv->ict_tbl_vir,
                                  priv->ict_tbl_dma);
                priv->ict_tbl_vir = NULL;
                memset(&priv->ict_tbl_dma, 0,
                        sizeof(priv->ict_tbl_dma));
                memset(&priv->aligned_ict_tbl_dma, 0,
                        sizeof(priv->aligned_ict_tbl_dma));
        }
}


/* allocate dram shared table it is a PAGE_SIZE aligned
 * also reset all data related to ICT table interrupt.
 */
int iwl_alloc_isr_ict(struct iwl_priv *priv)
{

        /* allocate shrared data table */
        priv->ict_tbl_vir =
                dma_alloc_coherent(priv->bus->dev,
                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
                                   &priv->ict_tbl_dma, GFP_KERNEL);
        if (!priv->ict_tbl_vir)
                return -ENOMEM;

        /* align table to PAGE_SIZE boundary */
        priv->aligned_ict_tbl_dma =
                ALIGN(priv->ict_tbl_dma, PAGE_SIZE);

        IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
                             (unsigned long long)priv->ict_tbl_dma,
                             (unsigned long long)priv->aligned_ict_tbl_dma,
                             (int)(priv->aligned_ict_tbl_dma -
                             priv->ict_tbl_dma));

        priv->ict_tbl =  priv->ict_tbl_vir +
                          (priv->aligned_ict_tbl_dma -
                          priv->ict_tbl_dma);

        IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
                             priv->ict_tbl, priv->ict_tbl_vir,
                        (int)(priv->aligned_ict_tbl_dma -
                            priv->ict_tbl_dma));

        /* reset table and index to all 0 */
        memset(priv->ict_tbl_vir, 0,
                (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
        priv->ict_index = 0;

        /* add periodic RX interrupt */
        priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
        return 0;
}

/* Device is going up inform it about using ICT interrupt table,
 * also we need to tell the driver to start using ICT interrupt.
 */
int iwl_reset_ict(struct iwl_priv *priv)
{
        u32 val;
        unsigned long flags;

        if (!priv->ict_tbl_vir)
                return 0;

        spin_lock_irqsave(&priv->lock, flags);
        iwl_disable_interrupts(priv);

        memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);

        val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;

        val |= CSR_DRAM_INT_TBL_ENABLE;
        val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;

        IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
                        "aligned dma address %Lx\n",
                        val,
                        (unsigned long long)priv->aligned_ict_tbl_dma);

        iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
        priv->use_ict = true;
        priv->ict_index = 0;
        iwl_write32(priv, CSR_INT, priv->inta_mask);
        iwl_enable_interrupts(priv);
        spin_unlock_irqrestore(&priv->lock, flags);

        return 0;
}

/* Device is going down disable ict interrupt usage */
void iwl_disable_ict(struct iwl_priv *priv)
{
        unsigned long flags;

        spin_lock_irqsave(&priv->lock, flags);
        priv->use_ict = false;
        spin_unlock_irqrestore(&priv->lock, flags);
}

static irqreturn_t iwl_isr(int irq, void *data)
{
        struct iwl_priv *priv = data;
        u32 inta, inta_mask;
        unsigned long flags;
#ifdef CONFIG_IWLWIFI_DEBUG
        u32 inta_fh;
#endif
        if (!priv)
                return IRQ_NONE;

        spin_lock_irqsave(&priv->lock, flags);

        /* Disable (but don't clear!) interrupts here to avoid
         *    back-to-back ISRs and sporadic interrupts from our NIC.
         * If we have something to service, the tasklet will re-enable ints.
         * If we *don't* have something, we'll re-enable before leaving here. */
        inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
        iwl_write32(priv, CSR_INT_MASK, 0x00000000);

        /* Discover which interrupts are active/pending */
        inta = iwl_read32(priv, CSR_INT);

        /* Ignore interrupt if there's nothing in NIC to service.
         * This may be due to IRQ shared with another device,
         * or due to sporadic interrupts thrown from our NIC. */
        if (!inta) {
                IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
                goto none;
        }

        if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
                /* Hardware disappeared. It might have already raised
                 * an interrupt */
                IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
                goto unplugged;
        }

#ifdef CONFIG_IWLWIFI_DEBUG
        if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
                inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
                IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
                              "fh 0x%08x\n", inta, inta_mask, inta_fh);
        }
#endif

        priv->inta |= inta;
        /* iwl_irq_tasklet() will service interrupts and re-enable them */
        if (likely(inta))
                tasklet_schedule(&priv->irq_tasklet);
        else if (test_bit(STATUS_INT_ENABLED, &priv->status) &&
                        !priv->inta)
                iwl_enable_interrupts(priv);

 unplugged:
        spin_unlock_irqrestore(&priv->lock, flags);
        return IRQ_HANDLED;

 none:
        /* re-enable interrupts here since we don't have anything to service. */
        /* only Re-enable if disabled by irq  and no schedules tasklet. */
        if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
                iwl_enable_interrupts(priv);

        spin_unlock_irqrestore(&priv->lock, flags);
        return IRQ_NONE;
}

/* interrupt handler using ict table, with this interrupt driver will
 * stop using INTA register to get device's interrupt, reading this register
 * is expensive, device will write interrupts in ICT dram table, increment
 * index then will fire interrupt to driver, driver will OR all ICT table
 * entries from current index up to table entry with 0 value. the result is
 * the interrupt we need to service, driver will set the entries back to 0 and
 * set index.
 */
irqreturn_t iwl_isr_ict(int irq, void *data)
{
        struct iwl_priv *priv = data;
        u32 inta, inta_mask;
        u32 val = 0;
        unsigned long flags;

        if (!priv)
                return IRQ_NONE;

        /* dram interrupt table not set yet,
         * use legacy interrupt.
         */
        if (!priv->use_ict)
                return iwl_isr(irq, data);

        spin_lock_irqsave(&priv->lock, flags);

        /* Disable (but don't clear!) interrupts here to avoid
         * back-to-back ISRs and sporadic interrupts from our NIC.
         * If we have something to service, the tasklet will re-enable ints.
         * If we *don't* have something, we'll re-enable before leaving here.
         */
        inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
        iwl_write32(priv, CSR_INT_MASK, 0x00000000);


        /* Ignore interrupt if there's nothing in NIC to service.
         * This may be due to IRQ shared with another device,
         * or due to sporadic interrupts thrown from our NIC. */
        if (!priv->ict_tbl[priv->ict_index]) {
                IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
                goto none;
        }

        /* read all entries that not 0 start with ict_index */
        while (priv->ict_tbl[priv->ict_index]) {

                val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
                IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
                                priv->ict_index,
                                le32_to_cpu(
                                    priv->ict_tbl[priv->ict_index]));
                priv->ict_tbl[priv->ict_index] = 0;
                priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
                                                     ICT_COUNT);

        }

        /* We should not get this value, just ignore it. */
        if (val == 0xffffffff)
                val = 0;

        /*
         * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
         * (bit 15 before shifting it to 31) to clear when using interrupt
         * coalescing. fortunately, bits 18 and 19 stay set when this happens
         * so we use them to decide on the real state of the Rx bit.
         * In order words, bit 15 is set if bit 18 or bit 19 are set.
         */
        if (val & 0xC0000)
                val |= 0x8000;

        inta = (0xff & val) | ((0xff00 & val) << 16);
        IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
                        inta, inta_mask, val);

        inta &= priv->inta_mask;
        priv->inta |= inta;

        /* iwl_irq_tasklet() will service interrupts and re-enable them */
        if (likely(inta))
                tasklet_schedule(&priv->irq_tasklet);
        else if (test_bit(STATUS_INT_ENABLED, &priv->status) &&
                        !priv->inta) {
                /* Allow interrupt if was disabled by this handler and
                 * no tasklet was schedules, We should not enable interrupt,
                 * tasklet will enable it.
                 */
                iwl_enable_interrupts(priv);
        }

        spin_unlock_irqrestore(&priv->lock, flags);
        return IRQ_HANDLED;

 none:
        /* re-enable interrupts here since we don't have anything to service.
         * only Re-enable if disabled by irq.
         */
        if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
                iwl_enable_interrupts(priv);

        spin_unlock_irqrestore(&priv->lock, flags);
        return IRQ_NONE;
}