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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / net / wireless / rtlwifi / rtl8192se / fw.c
blob6f91a148c2220ad2f4694c21a4f47e52822912e2
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../pci.h"
32 #include "../base.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "fw.h"
36
37 static void _rtl92s_fw_set_rqpn(struct ieee80211_hw *hw)
38 {
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40
41 rtl_write_dword(rtlpriv, RQPN, 0xffffffff);
42 rtl_write_dword(rtlpriv, RQPN + 4, 0xffffffff);
43 rtl_write_byte(rtlpriv, RQPN + 8, 0xff);
44 rtl_write_byte(rtlpriv, RQPN + 0xB, 0x80);
45 }
46
47 static bool _rtl92s_firmware_enable_cpu(struct ieee80211_hw *hw)
48 {
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 u32 ichecktime = 200;
51 u16 tmpu2b;
52 u8 tmpu1b, cpustatus = 0;
53
54 _rtl92s_fw_set_rqpn(hw);
55
56 /* Enable CPU. */
57 tmpu1b = rtl_read_byte(rtlpriv, SYS_CLKR);
58 /* AFE source */
59 rtl_write_byte(rtlpriv, SYS_CLKR, (tmpu1b | SYS_CPU_CLKSEL));
60
61 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
62 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | FEN_CPUEN));
63
64 /* Polling IMEM Ready after CPU has refilled. */
65 do {
66 cpustatus = rtl_read_byte(rtlpriv, TCR);
67 if (cpustatus & IMEM_RDY) {
68 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
69 ("IMEM Ready after CPU has refilled.\n"));
70 break;
71 }
72
73 udelay(100);
74 } while (ichecktime--);
75
76 if (!(cpustatus & IMEM_RDY))
77 return false;
78
79 return true;
80 }
81
82 static enum fw_status _rtl92s_firmware_get_nextstatus(
83 enum fw_status fw_currentstatus)
84 {
85 enum fw_status next_fwstatus = 0;
86
87 switch (fw_currentstatus) {
88 case FW_STATUS_INIT:
89 next_fwstatus = FW_STATUS_LOAD_IMEM;
90 break;
91 case FW_STATUS_LOAD_IMEM:
92 next_fwstatus = FW_STATUS_LOAD_EMEM;
93 break;
94 case FW_STATUS_LOAD_EMEM:
95 next_fwstatus = FW_STATUS_LOAD_DMEM;
96 break;
97 case FW_STATUS_LOAD_DMEM:
98 next_fwstatus = FW_STATUS_READY;
99 break;
100 default:
101 break;
102 }
103
104 return next_fwstatus;
105 }
106
107 static u8 _rtl92s_firmware_header_map_rftype(struct ieee80211_hw *hw)
108 {
109 struct rtl_priv *rtlpriv = rtl_priv(hw);
110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
111
112 switch (rtlphy->rf_type) {
113 case RF_1T1R:
114 return 0x11;
115 break;
116 case RF_1T2R:
117 return 0x12;
118 break;
119 case RF_2T2R:
120 return 0x22;
121 break;
122 default:
123 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
124 ("Unknown RF type(%x)\n",
125 rtlphy->rf_type));
126 break;
127 }
128 return 0x22;
129 }
130
131 static void _rtl92s_firmwareheader_priveupdate(struct ieee80211_hw *hw,
132 struct fw_priv *pfw_priv)
133 {
134 /* Update RF types for RATR settings. */
135 pfw_priv->rf_config = _rtl92s_firmware_header_map_rftype(hw);
136 }
137
138
139
140 static bool _rtl92s_cmd_send_packet(struct ieee80211_hw *hw,
141 struct sk_buff *skb, u8 last)
142 {
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
145 struct rtl8192_tx_ring *ring;
146 struct rtl_tx_desc *pdesc;
147 unsigned long flags;
148 u8 idx = 0;
149
150 ring = &rtlpci->tx_ring[TXCMD_QUEUE];
151
152 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
153
154 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
155 pdesc = &ring->desc[idx];
156 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
157 __skb_queue_tail(&ring->queue, skb);
158
159 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
160
161 return true;
162 }
163
164 static bool _rtl92s_firmware_downloadcode(struct ieee80211_hw *hw,
165 u8 *code_virtual_address, u32 buffer_len)
166 {
167 struct rtl_priv *rtlpriv = rtl_priv(hw);
168 struct sk_buff *skb;
169 struct rtl_tcb_desc *tcb_desc;
170 unsigned char *seg_ptr;
171 u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE;
172 u16 frag_length, frag_offset = 0;
173 u16 extra_descoffset = 0;
174 u8 last_inipkt = 0;
175
176 _rtl92s_fw_set_rqpn(hw);
177
178 if (buffer_len >= MAX_FIRMWARE_CODE_SIZE) {
179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
180 ("Size over FIRMWARE_CODE_SIZE!\n"));
181
182 return false;
183 }
184
185 extra_descoffset = 0;
186
187 do {
188 if ((buffer_len - frag_offset) > frag_threshold) {
189 frag_length = frag_threshold + extra_descoffset;
190 } else {
191 frag_length = (u16)(buffer_len - frag_offset +
192 extra_descoffset);
193 last_inipkt = 1;
194 }
195
196 /* Allocate skb buffer to contain firmware */
197 /* info and tx descriptor info. */
198 skb = dev_alloc_skb(frag_length);
199 skb_reserve(skb, extra_descoffset);
200 seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length -
201 extra_descoffset));
202 memcpy(seg_ptr, code_virtual_address + frag_offset,
203 (u32)(frag_length - extra_descoffset));
204
205 tcb_desc = (struct rtl_tcb_desc *)(skb->cb);
206 tcb_desc->queue_index = TXCMD_QUEUE;
207 tcb_desc->cmd_or_init = DESC_PACKET_TYPE_INIT;
208 tcb_desc->last_inipkt = last_inipkt;
209
210 _rtl92s_cmd_send_packet(hw, skb, last_inipkt);
211
212 frag_offset += (frag_length - extra_descoffset);
213
214 } while (frag_offset < buffer_len);
215
216 rtl_write_byte(rtlpriv, TP_POLL, TPPOLL_CQ);
217
218 return true ;
219 }
220
221 static bool _rtl92s_firmware_checkready(struct ieee80211_hw *hw,
222 u8 loadfw_status)
223 {
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
226 struct rt_firmware *firmware = (struct rt_firmware *)rtlhal->pfirmware;
227 u32 tmpu4b;
228 u8 cpustatus = 0;
229 short pollingcnt = 1000;
230 bool rtstatus = true;
231
232 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("LoadStaus(%d)\n",
233 loadfw_status));
234
235 firmware->fwstatus = (enum fw_status)loadfw_status;
236
237 switch (loadfw_status) {
238 case FW_STATUS_LOAD_IMEM:
239 /* Polling IMEM code done. */
240 do {
241 cpustatus = rtl_read_byte(rtlpriv, TCR);
242 if (cpustatus & IMEM_CODE_DONE)
243 break;
244 udelay(5);
245 } while (pollingcnt--);
246
247 if (!(cpustatus & IMEM_CHK_RPT) || (pollingcnt <= 0)) {
248 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
249 ("FW_STATUS_LOAD_IMEM"
250 " FAIL CPU, Status=%x\r\n", cpustatus));
251 goto status_check_fail;
252 }
253 break;
254
255 case FW_STATUS_LOAD_EMEM:
256 /* Check Put Code OK and Turn On CPU */
257 /* Polling EMEM code done. */
258 do {
259 cpustatus = rtl_read_byte(rtlpriv, TCR);
260 if (cpustatus & EMEM_CODE_DONE)
261 break;
262 udelay(5);
263 } while (pollingcnt--);
264
265 if (!(cpustatus & EMEM_CHK_RPT) || (pollingcnt <= 0)) {
266 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
267 ("FW_STATUS_LOAD_EMEM"
268 " FAIL CPU, Status=%x\r\n", cpustatus));
269 goto status_check_fail;
270 }
271
272 /* Turn On CPU */
273 rtstatus = _rtl92s_firmware_enable_cpu(hw);
274 if (rtstatus != true) {
275 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
276 ("Enable CPU fail!\n"));
277 goto status_check_fail;
278 }
279 break;
280
281 case FW_STATUS_LOAD_DMEM:
282 /* Polling DMEM code done */
283 do {
284 cpustatus = rtl_read_byte(rtlpriv, TCR);
285 if (cpustatus & DMEM_CODE_DONE)
286 break;
287 udelay(5);
288 } while (pollingcnt--);
289
290 if (!(cpustatus & DMEM_CODE_DONE) || (pollingcnt <= 0)) {
291 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
292 ("Polling DMEM code done"
293 " fail ! cpustatus(%#x)\n", cpustatus));
294 goto status_check_fail;
295 }
296
297 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
298 ("DMEM code download success,"
299 " cpustatus(%#x)\n", cpustatus));
300
301 /* Prevent Delay too much and being scheduled out */
302 /* Polling Load Firmware ready */
303 pollingcnt = 2000;
304 do {
305 cpustatus = rtl_read_byte(rtlpriv, TCR);
306 if (cpustatus & FWRDY)
307 break;
308 udelay(40);
309 } while (pollingcnt--);
310
311 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
312 ("Polling Load Firmware ready,"
313 " cpustatus(%x)\n", cpustatus));
314
315 if (((cpustatus & LOAD_FW_READY) != LOAD_FW_READY) ||
316 (pollingcnt <= 0)) {
317 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
318 ("Polling Load Firmware"
319 " ready fail ! cpustatus(%x)\n", cpustatus));
320 goto status_check_fail;
321 }
322
323 /* If right here, we can set TCR/RCR to desired value */
324 /* and config MAC lookback mode to normal mode */
325 tmpu4b = rtl_read_dword(rtlpriv, TCR);
326 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
327
328 tmpu4b = rtl_read_dword(rtlpriv, RCR);
329 rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS |
330 RCR_APP_ICV | RCR_APP_MIC));
331
332 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
333 ("Current RCR settings(%#x)\n", tmpu4b));
334
335 /* Set to normal mode. */
336 rtl_write_byte(rtlpriv, LBKMD_SEL, LBK_NORMAL);
337 break;
338
339 default:
340 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
341 ("Unknown status check!\n"));
342 rtstatus = false;
343 break;
344 }
345
346 status_check_fail:
347 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("loadfw_status(%d), "
348 "rtstatus(%x)\n", loadfw_status, rtstatus));
349 return rtstatus;
350 }
351
352 int rtl92s_download_fw(struct ieee80211_hw *hw)
353 {
354 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
356 struct rt_firmware *firmware = NULL;
357 struct fw_hdr *pfwheader;
358 struct fw_priv *pfw_priv = NULL;
359 u8 *puc_mappedfile = NULL;
360 u32 ul_filelength = 0;
361 u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE;
362 u8 fwstatus = FW_STATUS_INIT;
363 bool rtstatus = true;
364
365 if (!rtlhal->pfirmware)
366 return 1;
367
368 firmware = (struct rt_firmware *)rtlhal->pfirmware;
369 firmware->fwstatus = FW_STATUS_INIT;
370
371 puc_mappedfile = firmware->sz_fw_tmpbuffer;
372
373 /* 1. Retrieve FW header. */
374 firmware->pfwheader = (struct fw_hdr *) puc_mappedfile;
375 pfwheader = firmware->pfwheader;
376 firmware->firmwareversion = byte(pfwheader->version, 0);
377 firmware->pfwheader->fwpriv.hci_sel = 1;/* pcie */
378
379 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("signature:%x, version:"
380 "%x, size:%x,"
381 "imemsize:%x, sram size:%x\n", pfwheader->signature,
382 pfwheader->version, pfwheader->dmem_size,
383 pfwheader->img_imem_size, pfwheader->img_sram_size));
384
385 /* 2. Retrieve IMEM image. */
386 if ((pfwheader->img_imem_size == 0) || (pfwheader->img_imem_size >
387 sizeof(firmware->fw_imem))) {
388 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
389 ("memory for data image is less than IMEM required\n"));
390 goto fail;
391 } else {
392 puc_mappedfile += fwhdr_size;
393
394 memcpy(firmware->fw_imem, puc_mappedfile,
395 pfwheader->img_imem_size);
396 firmware->fw_imem_len = pfwheader->img_imem_size;
397 }
398
399 /* 3. Retriecve EMEM image. */
400 if (pfwheader->img_sram_size > sizeof(firmware->fw_emem)) {
401 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
402 ("memory for data image is less than EMEM required\n"));
403 goto fail;
404 } else {
405 puc_mappedfile += firmware->fw_imem_len;
406
407 memcpy(firmware->fw_emem, puc_mappedfile,
408 pfwheader->img_sram_size);
409 firmware->fw_emem_len = pfwheader->img_sram_size;
410 }
411
412 /* 4. download fw now */
413 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
414 while (fwstatus != FW_STATUS_READY) {
415 /* Image buffer redirection. */
416 switch (fwstatus) {
417 case FW_STATUS_LOAD_IMEM:
418 puc_mappedfile = firmware->fw_imem;
419 ul_filelength = firmware->fw_imem_len;
420 break;
421 case FW_STATUS_LOAD_EMEM:
422 puc_mappedfile = firmware->fw_emem;
423 ul_filelength = firmware->fw_emem_len;
424 break;
425 case FW_STATUS_LOAD_DMEM:
426 /* Partial update the content of header private. */
427 pfwheader = firmware->pfwheader;
428 pfw_priv = &pfwheader->fwpriv;
429 _rtl92s_firmwareheader_priveupdate(hw, pfw_priv);
430 puc_mappedfile = (u8 *)(firmware->pfwheader) +
431 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
432 ul_filelength = fwhdr_size -
433 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
434 break;
435 default:
436 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
437 ("Unexpected Download step!!\n"));
438 goto fail;
439 break;
440 }
441
442 /* <2> Download image file */
443 rtstatus = _rtl92s_firmware_downloadcode(hw, puc_mappedfile,
444 ul_filelength);
445
446 if (rtstatus != true) {
447 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
448 goto fail;
449 }
450
451 /* <3> Check whether load FW process is ready */
452 rtstatus = _rtl92s_firmware_checkready(hw, fwstatus);
453 if (rtstatus != true) {
454 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
455 goto fail;
456 }
457
458 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
459 }
460
461 return rtstatus;
462 fail:
463 return 0;
464 }
465
466 static u32 _rtl92s_fill_h2c_cmd(struct sk_buff *skb, u32 h2cbufferlen,
467 u32 cmd_num, u32 *pelement_id, u32 *pcmd_len,
468 u8 **pcmb_buffer, u8 *cmd_start_seq)
469 {
470 u32 totallen = 0, len = 0, tx_desclen = 0;
471 u32 pre_continueoffset = 0;
472 u8 *ph2c_buffer;
473 u8 i = 0;
474
475 do {
476 /* 8 - Byte aligment */
477 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
478
479 /* Buffer length is not enough */
480 if (h2cbufferlen < totallen + len + tx_desclen)
481 break;
482
483 /* Clear content */
484 ph2c_buffer = (u8 *)skb_put(skb, (u32)len);
485 memset((ph2c_buffer + totallen + tx_desclen), 0, len);
486
487 /* CMD len */
488 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
489 0, 16, pcmd_len[i]);
490
491 /* CMD ID */
492 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
493 16, 8, pelement_id[i]);
494
495 /* CMD Sequence */
496 *cmd_start_seq = *cmd_start_seq % 0x80;
497 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
498 24, 7, *cmd_start_seq);
499 ++*cmd_start_seq;
500
501 /* Copy memory */
502 memcpy((ph2c_buffer + totallen + tx_desclen +
503 H2C_TX_CMD_HDR_LEN), pcmb_buffer[i], pcmd_len[i]);
504
505 /* CMD continue */
506 /* set the continue in prevoius cmd. */
507 if (i < cmd_num - 1)
508 SET_BITS_TO_LE_4BYTE((ph2c_buffer + pre_continueoffset),
509 31, 1, 1);
510
511 pre_continueoffset = totallen;
512
513 totallen += len;
514 } while (++i < cmd_num);
515
516 return totallen;
517 }
518
519 static u32 _rtl92s_get_h2c_cmdlen(u32 h2cbufferlen, u32 cmd_num, u32 *pcmd_len)
520 {
521 u32 totallen = 0, len = 0, tx_desclen = 0;
522 u8 i = 0;
523
524 do {
525 /* 8 - Byte aligment */
526 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
527
528 /* Buffer length is not enough */
529 if (h2cbufferlen < totallen + len + tx_desclen)
530 break;
531
532 totallen += len;
533 } while (++i < cmd_num);
534
535 return totallen + tx_desclen;
536 }
537
538 static bool _rtl92s_firmware_set_h2c_cmd(struct ieee80211_hw *hw, u8 h2c_cmd,
539 u8 *pcmd_buffer)
540 {
541 struct rtl_priv *rtlpriv = rtl_priv(hw);
542 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
543 struct rtl_tcb_desc *cb_desc;
544 struct sk_buff *skb;
545 u32 element_id = 0;
546 u32 cmd_len = 0;
547 u32 len;
548
549 switch (h2c_cmd) {
550 case FW_H2C_SETPWRMODE:
551 element_id = H2C_SETPWRMODE_CMD ;
552 cmd_len = sizeof(struct h2c_set_pwrmode_parm);
553 break;
554 case FW_H2C_JOINBSSRPT:
555 element_id = H2C_JOINBSSRPT_CMD;
556 cmd_len = sizeof(struct h2c_joinbss_rpt_parm);
557 break;
558 case FW_H2C_WOWLAN_UPDATE_GTK:
559 element_id = H2C_WOWLAN_UPDATE_GTK_CMD;
560 cmd_len = sizeof(struct h2c_wpa_two_way_parm);
561 break;
562 case FW_H2C_WOWLAN_UPDATE_IV:
563 element_id = H2C_WOWLAN_UPDATE_IV_CMD;
564 cmd_len = sizeof(unsigned long long);
565 break;
566 case FW_H2C_WOWLAN_OFFLOAD:
567 element_id = H2C_WOWLAN_FW_OFFLOAD;
568 cmd_len = sizeof(u8);
569 break;
570 default:
571 break;
572 }
573
574 len = _rtl92s_get_h2c_cmdlen(MAX_TRANSMIT_BUFFER_SIZE, 1, &cmd_len);
575 skb = dev_alloc_skb(len);
576 cb_desc = (struct rtl_tcb_desc *)(skb->cb);
577 cb_desc->queue_index = TXCMD_QUEUE;
578 cb_desc->cmd_or_init = DESC_PACKET_TYPE_NORMAL;
579 cb_desc->last_inipkt = false;
580
581 _rtl92s_fill_h2c_cmd(skb, MAX_TRANSMIT_BUFFER_SIZE, 1, &element_id,
582 &cmd_len, &pcmd_buffer, &rtlhal->h2c_txcmd_seq);
583 _rtl92s_cmd_send_packet(hw, skb, false);
584 rtlpriv->cfg->ops->tx_polling(hw, TXCMD_QUEUE);
585
586 return true;
587 }
588
589 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 Mode)
590 {
591 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
592 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
593 struct h2c_set_pwrmode_parm pwrmode;
594 u16 max_wakeup_period = 0;
595
596 pwrmode.mode = Mode;
597 pwrmode.flag_low_traffic_en = 0;
598 pwrmode.flag_lpnav_en = 0;
599 pwrmode.flag_rf_low_snr_en = 0;
600 pwrmode.flag_dps_en = 0;
601 pwrmode.bcn_rx_en = 0;
602 pwrmode.bcn_to = 0;
603 SET_BITS_TO_LE_2BYTE((u8 *)(&pwrmode) + 8, 0, 16,
604 mac->vif->bss_conf.beacon_int);
605 pwrmode.app_itv = 0;
606 pwrmode.awake_bcn_itvl = ppsc->reg_max_lps_awakeintvl;
607 pwrmode.smart_ps = 1;
608 pwrmode.bcn_pass_period = 10;
609
610 /* Set beacon pass count */
611 if (pwrmode.mode == FW_PS_MIN_MODE)
612 max_wakeup_period = mac->vif->bss_conf.beacon_int;
613 else if (pwrmode.mode == FW_PS_MAX_MODE)
614 max_wakeup_period = mac->vif->bss_conf.beacon_int *
615 mac->vif->bss_conf.dtim_period;
616
617 if (max_wakeup_period >= 500)
618 pwrmode.bcn_pass_cnt = 1;
619 else if ((max_wakeup_period >= 300) && (max_wakeup_period < 500))
620 pwrmode.bcn_pass_cnt = 2;
621 else if ((max_wakeup_period >= 200) && (max_wakeup_period < 300))
622 pwrmode.bcn_pass_cnt = 3;
623 else if ((max_wakeup_period >= 20) && (max_wakeup_period < 200))
624 pwrmode.bcn_pass_cnt = 5;
625 else
626 pwrmode.bcn_pass_cnt = 1;
627
628 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_SETPWRMODE, (u8 *)&pwrmode);
629
630 }
631
632 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
633 u8 mstatus, u8 ps_qosinfo)
634 {
635 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
636 struct h2c_joinbss_rpt_parm joinbss_rpt;
637
638 joinbss_rpt.opmode = mstatus;
639 joinbss_rpt.ps_qos_info = ps_qosinfo;
640 joinbss_rpt.bssid[0] = mac->bssid[0];
641 joinbss_rpt.bssid[1] = mac->bssid[1];
642 joinbss_rpt.bssid[2] = mac->bssid[2];
643 joinbss_rpt.bssid[3] = mac->bssid[3];
644 joinbss_rpt.bssid[4] = mac->bssid[4];
645 joinbss_rpt.bssid[5] = mac->bssid[5];
646 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 8, 0, 16,
647 mac->vif->bss_conf.beacon_int);
648 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 10, 0, 16, mac->assoc_id);
649
650 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_JOINBSSRPT, (u8 *)&joinbss_rpt);
651 }
652
linux-next