drivers/scsi/hpsa_cmd.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_CMD_H
  22 #define HPSA_CMD_H
  23
  24 /* general boundary defintions */
  25 #define SENSEINFOBYTES          32 /* may vary between hbas */
  26 #define MAXSGENTRIES            32
  27 #define HPSA_SG_CHAIN           0x80000000
  28 #define MAXREPLYQS              256
  29
  30 /* Command Status value */
  31 #define CMD_SUCCESS             0x0000
  32 #define CMD_TARGET_STATUS       0x0001
  33 #define CMD_DATA_UNDERRUN       0x0002
  34 #define CMD_DATA_OVERRUN        0x0003
  35 #define CMD_INVALID             0x0004
  36 #define CMD_PROTOCOL_ERR        0x0005
  37 #define CMD_HARDWARE_ERR        0x0006
  38 #define CMD_CONNECTION_LOST     0x0007
  39 #define CMD_ABORTED             0x0008
  40 #define CMD_ABORT_FAILED        0x0009
  41 #define CMD_UNSOLICITED_ABORT   0x000A
  42 #define CMD_TIMEOUT             0x000B
  43 #define CMD_UNABORTABLE         0x000C
  44
  45 /* Unit Attentions ASC's as defined for the MSA2012sa */
  46 #define POWER_OR_RESET                  0x29
  47 #define STATE_CHANGED                   0x2a
  48 #define UNIT_ATTENTION_CLEARED          0x2f
  49 #define LUN_FAILED                      0x3e
  50 #define REPORT_LUNS_CHANGED             0x3f
  51
  52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  53
  54         /* These ASCQ's defined for ASC = POWER_OR_RESET */
  55 #define POWER_ON_RESET                  0x00
  56 #define POWER_ON_REBOOT                 0x01
  57 #define SCSI_BUS_RESET                  0x02
  58 #define MSA_TARGET_RESET                0x03
  59 #define CONTROLLER_FAILOVER             0x04
  60 #define TRANSCEIVER_SE                  0x05
  61 #define TRANSCEIVER_LVD                 0x06
  62
  63         /* These ASCQ's defined for ASC = STATE_CHANGED */
  64 #define RESERVATION_PREEMPTED           0x03
  65 #define ASYM_ACCESS_CHANGED             0x06
  66 #define LUN_CAPACITY_CHANGED            0x09
  67
  68 /* transfer direction */
  69 #define XFER_NONE               0x00
  70 #define XFER_WRITE              0x01
  71 #define XFER_READ               0x02
  72 #define XFER_RSVD               0x03
  73
  74 /* task attribute */
  75 #define ATTR_UNTAGGED           0x00
  76 #define ATTR_SIMPLE             0x04
  77 #define ATTR_HEADOFQUEUE        0x05
  78 #define ATTR_ORDERED            0x06
  79 #define ATTR_ACA                0x07
  80
  81 /* cdb type */
  82 #define TYPE_CMD                                0x00
  83 #define TYPE_MSG                                0x01
  84
  85 /* config space register offsets */
  86 #define CFG_VENDORID            0x00
  87 #define CFG_DEVICEID            0x02
  88 #define CFG_I2OBAR              0x10
  89 #define CFG_MEM1BAR             0x14
  90
  91 /* i2o space register offsets */
  92 #define I2O_IBDB_SET            0x20
  93 #define I2O_IBDB_CLEAR          0x70
  94 #define I2O_INT_STATUS          0x30
  95 #define I2O_INT_MASK            0x34
  96 #define I2O_IBPOST_Q            0x40
  97 #define I2O_OBPOST_Q            0x44
  98 #define I2O_DMA1_CFG            0x214
  99
 100 /* Configuration Table */
 101 #define CFGTBL_ChangeReq        0x00000001l
 102 #define CFGTBL_AccCmds          0x00000001l
 103 #define DOORBELL_CTLR_RESET     0x00000004l
 104
 105 #define CFGTBL_Trans_Simple     0x00000002l
 106 #define CFGTBL_Trans_Performant 0x00000004l
 107
 108 #define CFGTBL_BusType_Ultra2   0x00000001l
 109 #define CFGTBL_BusType_Ultra3   0x00000002l
 110 #define CFGTBL_BusType_Fibre1G  0x00000100l
 111 #define CFGTBL_BusType_Fibre2G  0x00000200l
 112 struct vals32 {
 113         u32   lower;
 114         u32   upper;
 115 };
 116
 117 union u64bit {
 118         struct vals32 val32;
 119         u64 val;
 120 };
 121
 122 /* FIXME this is a per controller value (barf!) */
 123 #define HPSA_MAX_TARGETS_PER_CTLR 16
 124 #define HPSA_MAX_LUN 256
 125 #define HPSA_MAX_PHYS_LUN 1024
 126
 127 /* SCSI-3 Commands */
 128 #pragma pack(1)
 129
 130 #define HPSA_INQUIRY 0x12
 131 struct InquiryData {
 132         u8 data_byte[36];
 133 };
 134
 135 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
 136 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
 137 struct ReportLUNdata {
 138         u8 LUNListLength[4];
 139         u32 reserved;
 140         u8 LUN[HPSA_MAX_LUN][8];
 141 };
 142
 143 struct ReportExtendedLUNdata {
 144         u8 LUNListLength[4];
 145         u8 extended_response_flag;
 146         u8 reserved[3];
 147         u8 LUN[HPSA_MAX_LUN][24];
 148 };
 149
 150 struct SenseSubsystem_info {
 151         u8 reserved[36];
 152         u8 portname[8];
 153         u8 reserved1[1108];
 154 };
 155
 156 /* BMIC commands */
 157 #define BMIC_READ 0x26
 158 #define BMIC_WRITE 0x27
 159 #define BMIC_CACHE_FLUSH 0xc2
 160 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
 161
 162 /* Command List Structure */
 163 union SCSI3Addr {
 164         struct {
 165                 u8 Dev;
 166                 u8 Bus:6;
 167                 u8 Mode:2;        /* b00 */
 168         } PeripDev;
 169         struct {
 170                 u8 DevLSB;
 171                 u8 DevMSB:6;
 172                 u8 Mode:2;        /* b01 */
 173         } LogDev;
 174         struct {
 175                 u8 Dev:5;
 176                 u8 Bus:3;
 177                 u8 Targ:6;
 178                 u8 Mode:2;        /* b10 */
 179         } LogUnit;
 180 };
 181
 182 struct PhysDevAddr {
 183         u32             TargetId:24;
 184         u32             Bus:6;
 185         u32             Mode:2;
 186         /* 2 level target device addr */
 187         union SCSI3Addr  Target[2];
 188 };
 189
 190 struct LogDevAddr {
 191         u32            VolId:30;
 192         u32            Mode:2;
 193         u8             reserved[4];
 194 };
 195
 196 union LUNAddr {
 197         u8               LunAddrBytes[8];
 198         union SCSI3Addr    SCSI3Lun[4];
 199         struct PhysDevAddr PhysDev;
 200         struct LogDevAddr  LogDev;
 201 };
 202
 203 struct CommandListHeader {
 204         u8              ReplyQueue;
 205         u8              SGList;
 206         u16             SGTotal;
 207         struct vals32     Tag;
 208         union LUNAddr     LUN;
 209 };
 210
 211 struct RequestBlock {
 212         u8   CDBLen;
 213         struct {
 214                 u8 Type:3;
 215                 u8 Attribute:3;
 216                 u8 Direction:2;
 217         } Type;
 218         u16  Timeout;
 219         u8   CDB[16];
 220 };
 221
 222 struct ErrDescriptor {
 223         struct vals32 Addr;
 224         u32  Len;
 225 };
 226
 227 struct SGDescriptor {
 228         struct vals32 Addr;
 229         u32  Len;
 230         u32  Ext;
 231 };
 232
 233 union MoreErrInfo {
 234         struct {
 235                 u8  Reserved[3];
 236                 u8  Type;
 237                 u32 ErrorInfo;
 238         } Common_Info;
 239         struct {
 240                 u8  Reserved[2];
 241                 u8  offense_size; /* size of offending entry */
 242                 u8  offense_num;  /* byte # of offense 0-base */
 243                 u32 offense_value;
 244         } Invalid_Cmd;
 245 };
 246 struct ErrorInfo {
 247         u8               ScsiStatus;
 248         u8               SenseLen;
 249         u16              CommandStatus;
 250         u32              ResidualCnt;
 251         union MoreErrInfo  MoreErrInfo;
 252         u8               SenseInfo[SENSEINFOBYTES];
 253 };
 254 /* Command types */
 255 #define CMD_IOCTL_PEND  0x01
 256 #define CMD_SCSI        0x03
 257
 258 /* This structure needs to be divisible by 32 for new
 259  * indexing method and performant mode.
 260  */
 261 #define PAD32 32
 262 #define PAD64DIFF 0
 263 #define USEEXTRA ((sizeof(void *) - 4)/4)
 264 #define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)
 265
 266 #define DIRECT_LOOKUP_SHIFT 5
 267 #define DIRECT_LOOKUP_BIT 0x10
 268
 269 #define HPSA_ERROR_BIT          0x02
 270 struct ctlr_info; /* defined in hpsa.h */
 271 /* The size of this structure needs to be divisible by 32
 272  * on all architectures because low 5 bits of the addresses
 273  * are used as follows:
 274  *
 275  * bit 0: to device, used to indicate "performant mode" command
 276  *        from device, indidcates error status.
 277  * bit 1-3: to device, indicates block fetch table entry for
 278  *          reducing DMA in fetching commands from host memory.
 279  * bit 4: used to indicate whether tag is "direct lookup" (index),
 280  *        or a bus address.
 281  */
 282
 283 struct CommandList {
 284         struct CommandListHeader Header;
 285         struct RequestBlock      Request;
 286         struct ErrDescriptor     ErrDesc;
 287         struct SGDescriptor      SG[MAXSGENTRIES];
 288         /* information associated with the command */
 289         u32                        busaddr; /* physical addr of this record */
 290         struct ErrorInfo *err_info; /* pointer to the allocated mem */
 291         struct ctlr_info           *h;
 292         int                        cmd_type;
 293         long                       cmdindex;
 294         struct hlist_node list;
 295         struct request *rq;
 296         struct completion *waiting;
 297         void   *scsi_cmd;
 298
 299 /* on 64 bit architectures, to get this to be 32-byte-aligned
 300  * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 301  * we need PAD_32 bytes of padding (see below).   This does that.
 302  * If it happens that 64 bit and 32 bit systems need different
 303  * padding, PAD_32 and PAD_64 can be set independently, and.
 304  * the code below will do the right thing.
 305  */
 306 #define IS_32_BIT ((8 - sizeof(long))/4)
 307 #define IS_64_BIT (!IS_32_BIT)
 308 #define PAD_32 (4)
 309 #define PAD_64 (4)
 310 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
 311         u8 pad[COMMANDLIST_PAD];
 312 };
 313
 314 /* Configuration Table Structure */
 315 struct HostWrite {
 316         u32 TransportRequest;
 317         u32 Reserved;
 318         u32 CoalIntDelay;
 319         u32 CoalIntCount;
 320 };
 321
 322 #define SIMPLE_MODE     0x02
 323 #define PERFORMANT_MODE 0x04
 324 #define MEMQ_MODE       0x08
 325
 326 struct CfgTable {
 327         u8            Signature[4];
 328         u32             SpecValence;
 329         u32           TransportSupport;
 330         u32           TransportActive;
 331         struct          HostWrite HostWrite;
 332         u32           CmdsOutMax;
 333         u32           BusTypes;
 334         u32           TransMethodOffset;
 335         u8            ServerName[16];
 336         u32           HeartBeat;
 337         u32           SCSI_Prefetch;
 338         u32             MaxScatterGatherElements;
 339         u32             MaxLogicalUnits;
 340         u32             MaxPhysicalDevices;
 341         u32             MaxPhysicalDrivesPerLogicalUnit;
 342         u32             MaxPerformantModeCommands;
 343         u8              reserved[0x78 - 0x58];
 344         u32             misc_fw_support; /* offset 0x78 */
 345 #define                 MISC_FW_DOORBELL_RESET (0x02)
 346 };
 347
 348 #define NUM_BLOCKFETCH_ENTRIES 8
 349 struct TransTable_struct {
 350         u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
 351         u32            RepQSize;
 352         u32            RepQCount;
 353         u32            RepQCtrAddrLow32;
 354         u32            RepQCtrAddrHigh32;
 355         u32            RepQAddr0Low32;
 356         u32            RepQAddr0High32;
 357 };
 358
 359 struct hpsa_pci_info {
 360         unsigned char   bus;
 361         unsigned char   dev_fn;
 362         unsigned short  domain;
 363         u32             board_id;
 364 };
 365
 366 #pragma pack()
 367 #endif /* HPSA_CMD_H */