drivers/ssb/driver_pcicore.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom PCI-core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/pci.h>
  13 #include <linux/delay.h>
  14 #include <linux/ssb/ssb_embedded.h>
  15
  16 #include "ssb_private.h"
  17
  18 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
  19 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
  20 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
  21 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
  22                                 u8 address, u16 data);
  23
  24 static inline
  25 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
  26 {
  27         return ssb_read32(pc->dev, offset);
  28 }
  29
  30 static inline
  31 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
  32 {
  33         ssb_write32(pc->dev, offset, value);
  34 }
  35
  36 static inline
  37 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
  38 {
  39         return ssb_read16(pc->dev, offset);
  40 }
  41
  42 static inline
  43 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
  44 {
  45         ssb_write16(pc->dev, offset, value);
  46 }
  47
  48 /**************************************************
  49  * Code for hostmode operation.
  50  **************************************************/
  51
  52 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
  53
  54 #include <asm/paccess.h>
  55 /* Probe a 32bit value on the bus and catch bus exceptions.
  56  * Returns nonzero on a bus exception.
  57  * This is MIPS specific */
  58 #define mips_busprobe32(val, addr)      get_dbe((val), ((u32 *)(addr)))
  59
  60 /* Assume one-hot slot wiring */
  61 #define SSB_PCI_SLOT_MAX        16
  62
  63 /* Global lock is OK, as we won't have more than one extpci anyway. */
  64 static DEFINE_SPINLOCK(cfgspace_lock);
  65 /* Core to access the external PCI config space. Can only have one. */
  66 static struct ssb_pcicore *extpci_core;
  67
  68
  69 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
  70                              unsigned int bus, unsigned int dev,
  71                              unsigned int func, unsigned int off)
  72 {
  73         u32 addr = 0;
  74         u32 tmp;
  75
  76         /* We do only have one cardbus device behind the bridge. */
  77         if (pc->cardbusmode && (dev >= 1))
  78                 goto out;
  79
  80         if (bus == 0) {
  81                 /* Type 0 transaction */
  82                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  83                         goto out;
  84                 /* Slide the window */
  85                 tmp = SSB_PCICORE_SBTOPCI_CFG0;
  86                 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
  87                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
  88                 /* Calculate the address */
  89                 addr = SSB_PCI_CFG;
  90                 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
  91                 addr |= (func << 8);
  92                 addr |= (off & ~3);
  93         } else {
  94                 /* Type 1 transaction */
  95                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
  96                                 SSB_PCICORE_SBTOPCI_CFG1);
  97                 /* Calculate the address */
  98                 addr = SSB_PCI_CFG;
  99                 addr |= (bus << 16);
 100                 addr |= (dev << 11);
 101                 addr |= (func << 8);
 102                 addr |= (off & ~3);
 103         }
 104 out:
 105         return addr;
 106 }
 107
 108 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
 109                                   unsigned int bus, unsigned int dev,
 110                                   unsigned int func, unsigned int off,
 111                                   void *buf, int len)
 112 {
 113         int err = -EINVAL;
 114         u32 addr, val;
 115         void __iomem *mmio;
 116
 117         SSB_WARN_ON(!pc->hostmode);
 118         if (unlikely(len != 1 && len != 2 && len != 4))
 119                 goto out;
 120         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 121         if (unlikely(!addr))
 122                 goto out;
 123         err = -ENOMEM;
 124         mmio = ioremap_nocache(addr, len);
 125         if (!mmio)
 126                 goto out;
 127
 128         if (mips_busprobe32(val, mmio)) {
 129                 val = 0xffffffff;
 130                 goto unmap;
 131         }
 132
 133         val = readl(mmio);
 134         val >>= (8 * (off & 3));
 135
 136         switch (len) {
 137         case 1:
 138                 *((u8 *)buf) = (u8)val;
 139                 break;
 140         case 2:
 141                 *((u16 *)buf) = (u16)val;
 142                 break;
 143         case 4:
 144                 *((u32 *)buf) = (u32)val;
 145                 break;
 146         }
 147         err = 0;
 148 unmap:
 149         iounmap(mmio);
 150 out:
 151         return err;
 152 }
 153
 154 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 155                                    unsigned int bus, unsigned int dev,
 156                                    unsigned int func, unsigned int off,
 157                                    const void *buf, int len)
 158 {
 159         int err = -EINVAL;
 160         u32 addr, val = 0;
 161         void __iomem *mmio;
 162
 163         SSB_WARN_ON(!pc->hostmode);
 164         if (unlikely(len != 1 && len != 2 && len != 4))
 165                 goto out;
 166         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 167         if (unlikely(!addr))
 168                 goto out;
 169         err = -ENOMEM;
 170         mmio = ioremap_nocache(addr, len);
 171         if (!mmio)
 172                 goto out;
 173
 174         if (mips_busprobe32(val, mmio)) {
 175                 val = 0xffffffff;
 176                 goto unmap;
 177         }
 178
 179         switch (len) {
 180         case 1:
 181                 val = readl(mmio);
 182                 val &= ~(0xFF << (8 * (off & 3)));
 183                 val |= *((const u8 *)buf) << (8 * (off & 3));
 184                 break;
 185         case 2:
 186                 val = readl(mmio);
 187                 val &= ~(0xFFFF << (8 * (off & 3)));
 188                 val |= *((const u16 *)buf) << (8 * (off & 3));
 189                 break;
 190         case 4:
 191                 val = *((const u32 *)buf);
 192                 break;
 193         }
 194         writel(val, mmio);
 195
 196         err = 0;
 197 unmap:
 198         iounmap(mmio);
 199 out:
 200         return err;
 201 }
 202
 203 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
 204                                    int reg, int size, u32 *val)
 205 {
 206         unsigned long flags;
 207         int err;
 208
 209         spin_lock_irqsave(&cfgspace_lock, flags);
 210         err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
 211                                      PCI_FUNC(devfn), reg, val, size);
 212         spin_unlock_irqrestore(&cfgspace_lock, flags);
 213
 214         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 215 }
 216
 217 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
 218                                     int reg, int size, u32 val)
 219 {
 220         unsigned long flags;
 221         int err;
 222
 223         spin_lock_irqsave(&cfgspace_lock, flags);
 224         err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
 225                                       PCI_FUNC(devfn), reg, &val, size);
 226         spin_unlock_irqrestore(&cfgspace_lock, flags);
 227
 228         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 229 }
 230
 231 static struct pci_ops ssb_pcicore_pciops = {
 232         .read   = ssb_pcicore_read_config,
 233         .write  = ssb_pcicore_write_config,
 234 };
 235
 236 static struct resource ssb_pcicore_mem_resource = {
 237         .name   = "SSB PCIcore external memory",
 238         .start  = SSB_PCI_DMA,
 239         .end    = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
 240         .flags  = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
 241 };
 242
 243 static struct resource ssb_pcicore_io_resource = {
 244         .name   = "SSB PCIcore external I/O",
 245         .start  = 0x100,
 246         .end    = 0x7FF,
 247         .flags  = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
 248 };
 249
 250 static struct pci_controller ssb_pcicore_controller = {
 251         .pci_ops        = &ssb_pcicore_pciops,
 252         .io_resource    = &ssb_pcicore_io_resource,
 253         .mem_resource   = &ssb_pcicore_mem_resource,
 254 };
 255
 256 /* This function is called when doing a pci_enable_device().
 257  * We must first check if the device is a device on the PCI-core bridge. */
 258 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 259 {
 260         if (d->bus->ops != &ssb_pcicore_pciops) {
 261                 /* This is not a device on the PCI-core bridge. */
 262                 return -ENODEV;
 263         }
 264
 265         ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 266                    pci_name(d));
 267
 268         /* Fix up interrupt lines */
 269         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 270         pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 271
 272         return 0;
 273 }
 274
 275 /* Early PCI fixup for a device on the PCI-core bridge. */
 276 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 277 {
 278         u8 lat;
 279
 280         if (dev->bus->ops != &ssb_pcicore_pciops) {
 281                 /* This is not a device on the PCI-core bridge. */
 282                 return;
 283         }
 284         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 285                 return;
 286
 287         ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 288
 289         /* Enable PCI bridge bus mastering and memory space */
 290         pci_set_master(dev);
 291         if (pcibios_enable_device(dev, ~0) < 0) {
 292                 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
 293                 return;
 294         }
 295
 296         /* Enable PCI bridge BAR1 prefetch and burst */
 297         pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 298
 299         /* Make sure our latency is high enough to handle the devices behind us */
 300         lat = 168;
 301         ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 302                    pci_name(dev), lat);
 303         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 304 }
 305 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 306
 307 /* PCI device IRQ mapping. */
 308 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 309 {
 310         if (dev->bus->ops != &ssb_pcicore_pciops) {
 311                 /* This is not a device on the PCI-core bridge. */
 312                 return -ENODEV;
 313         }
 314         return ssb_mips_irq(extpci_core->dev) + 2;
 315 }
 316
 317 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 318 {
 319         u32 val;
 320
 321         if (WARN_ON(extpci_core))
 322                 return;
 323         extpci_core = pc;
 324
 325         ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
 326         /* Reset devices on the external PCI bus */
 327         val = SSB_PCICORE_CTL_RST_OE;
 328         val |= SSB_PCICORE_CTL_CLK_OE;
 329         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 330         val |= SSB_PCICORE_CTL_CLK; /* Clock on */
 331         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 332         udelay(150); /* Assertion time demanded by the PCI standard */
 333         val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 334         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 335         val = SSB_PCICORE_ARBCTL_INTERN;
 336         pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
 337         udelay(1); /* Assertion time demanded by the PCI standard */
 338
 339         if (pc->dev->bus->has_cardbus_slot) {
 340                 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
 341                 pc->cardbusmode = 1;
 342                 /* GPIO 1 resets the bridge */
 343                 ssb_gpio_out(pc->dev->bus, 1, 1);
 344                 ssb_gpio_outen(pc->dev->bus, 1, 1);
 345                 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
 346                                 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
 347                                 | 0x0400);
 348         }
 349
 350         /* 64MB I/O window */
 351         pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
 352                         SSB_PCICORE_SBTOPCI_IO);
 353         /* 64MB config space */
 354         pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
 355                         SSB_PCICORE_SBTOPCI_CFG0);
 356         /* 1GB memory window */
 357         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
 358                         SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
 359
 360         /* Enable PCI bridge BAR0 prefetch and burst */
 361         val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 362         ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
 363         /* Clear error conditions */
 364         val = 0;
 365         ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
 366
 367         /* Enable PCI interrupts */
 368         pcicore_write32(pc, SSB_PCICORE_IMASK,
 369                         SSB_PCICORE_IMASK_INTA);
 370
 371         /* Ok, ready to run, register it to the system.
 372          * The following needs change, if we want to port hostmode
 373          * to non-MIPS platform. */
 374         ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
 375         set_io_port_base(ssb_pcicore_controller.io_map_base);
 376         /* Give some time to the PCI controller to configure itself with the new
 377          * values. Not waiting at this point causes crashes of the machine. */
 378         mdelay(10);
 379         register_pci_controller(&ssb_pcicore_controller);
 380 }
 381
 382 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 383 {
 384         struct ssb_bus *bus = pc->dev->bus;
 385         u16 chipid_top;
 386         u32 tmp;
 387
 388         chipid_top = (bus->chip_id & 0xFF00);
 389         if (chipid_top != 0x4700 &&
 390             chipid_top != 0x5300)
 391                 return 0;
 392
 393         if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
 394                 return 0;
 395
 396         /* The 200-pin BCM4712 package does not bond out PCI. Even when
 397          * PCI is bonded out, some boards may leave the pins floating. */
 398         if (bus->chip_id == 0x4712) {
 399                 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
 400                         return 0;
 401                 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
 402                         return 0;
 403         }
 404         if (bus->chip_id == 0x5350)
 405                 return 0;
 406
 407         return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
 408 }
 409 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 410
 411 /**************************************************
 412  * Workarounds.
 413  **************************************************/
 414
 415 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
 416 {
 417         return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
 418 }
 419
 420 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
 421 {
 422         const u8 serdes_pll_device = 0x1D;
 423         const u8 serdes_rx_device = 0x1F;
 424         u16 tmp;
 425
 426         ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
 427                             ssb_pcicore_polarity_workaround(pc));
 428         tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
 429         if (tmp & 0x4000)
 430                 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
 431 }
 432
 433 /**************************************************
 434  * Generic and Clientmode operation code.
 435  **************************************************/
 436
 437 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
 438 {
 439         /* Disable PCI interrupts. */
 440         ssb_write32(pc->dev, SSB_INTVEC, 0);
 441 }
 442
 443 void ssb_pcicore_init(struct ssb_pcicore *pc)
 444 {
 445         struct ssb_device *dev = pc->dev;
 446
 447         if (!dev)
 448                 return;
 449         if (!ssb_device_is_enabled(dev))
 450                 ssb_device_enable(dev, 0);
 451
 452 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
 453         pc->hostmode = pcicore_is_in_hostmode(pc);
 454         if (pc->hostmode)
 455                 ssb_pcicore_init_hostmode(pc);
 456 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 457         if (!pc->hostmode)
 458                 ssb_pcicore_init_clientmode(pc);
 459
 460         ssb_pcicore_serdes_workaround(pc);
 461 }
 462
 463 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
 464 {
 465         pcicore_write32(pc, 0x130, address);
 466         return pcicore_read32(pc, 0x134);
 467 }
 468
 469 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
 470 {
 471         pcicore_write32(pc, 0x130, address);
 472         pcicore_write32(pc, 0x134, data);
 473 }
 474
 475 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
 476 {
 477         const u16 mdio_control = 0x128;
 478         const u16 mdio_data = 0x12C;
 479         u32 v;
 480         int i;
 481
 482         v = (1 << 30); /* Start of Transaction */
 483         v |= (1 << 28); /* Write Transaction */
 484         v |= (1 << 17); /* Turnaround */
 485         v |= (0x1F << 18);
 486         v |= (phy << 4);
 487         pcicore_write32(pc, mdio_data, v);
 488
 489         udelay(10);
 490         for (i = 0; i < 200; i++) {
 491                 v = pcicore_read32(pc, mdio_control);
 492                 if (v & 0x100 /* Trans complete */)
 493                         break;
 494                 msleep(1);
 495         }
 496 }
 497
 498 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
 499 {
 500         const u16 mdio_control = 0x128;
 501         const u16 mdio_data = 0x12C;
 502         int max_retries = 10;
 503         u16 ret = 0;
 504         u32 v;
 505         int i;
 506
 507         v = 0x80; /* Enable Preamble Sequence */
 508         v |= 0x2; /* MDIO Clock Divisor */
 509         pcicore_write32(pc, mdio_control, v);
 510
 511         if (pc->dev->id.revision >= 10) {
 512                 max_retries = 200;
 513                 ssb_pcie_mdio_set_phy(pc, device);
 514         }
 515
 516         v = (1 << 30); /* Start of Transaction */
 517         v |= (1 << 29); /* Read Transaction */
 518         v |= (1 << 17); /* Turnaround */
 519         if (pc->dev->id.revision < 10)
 520                 v |= (u32)device << 22;
 521         v |= (u32)address << 18;
 522         pcicore_write32(pc, mdio_data, v);
 523         /* Wait for the device to complete the transaction */
 524         udelay(10);
 525         for (i = 0; i < 200; i++) {
 526                 v = pcicore_read32(pc, mdio_control);
 527                 if (v & 0x100 /* Trans complete */) {
 528                         udelay(10);
 529                         ret = pcicore_read32(pc, mdio_data);
 530                         break;
 531                 }
 532                 msleep(1);
 533         }
 534         pcicore_write32(pc, mdio_control, 0);
 535         return ret;
 536 }
 537
 538 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
 539                                 u8 address, u16 data)
 540 {
 541         const u16 mdio_control = 0x128;
 542         const u16 mdio_data = 0x12C;
 543         int max_retries = 10;
 544         u32 v;
 545         int i;
 546
 547         v = 0x80; /* Enable Preamble Sequence */
 548         v |= 0x2; /* MDIO Clock Divisor */
 549         pcicore_write32(pc, mdio_control, v);
 550
 551         if (pc->dev->id.revision >= 10) {
 552                 max_retries = 200;
 553                 ssb_pcie_mdio_set_phy(pc, device);
 554         }
 555
 556         v = (1 << 30); /* Start of Transaction */
 557         v |= (1 << 28); /* Write Transaction */
 558         v |= (1 << 17); /* Turnaround */
 559         if (pc->dev->id.revision < 10)
 560                 v |= (u32)device << 22;
 561         v |= (u32)address << 18;
 562         v |= data;
 563         pcicore_write32(pc, mdio_data, v);
 564         /* Wait for the device to complete the transaction */
 565         udelay(10);
 566         for (i = 0; i < max_retries; i++) {
 567                 v = pcicore_read32(pc, mdio_control);
 568                 if (v & 0x100 /* Trans complete */)
 569                         break;
 570                 msleep(1);
 571         }
 572         pcicore_write32(pc, mdio_control, 0);
 573 }
 574
 575 static void ssb_broadcast_value(struct ssb_device *dev,
 576                                 u32 address, u32 data)
 577 {
 578         /* This is used for both, PCI and ChipCommon core, so be careful. */
 579         BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
 580         BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
 581
 582         ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
 583         ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
 584         ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
 585         ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
 586 }
 587
 588 static void ssb_commit_settings(struct ssb_bus *bus)
 589 {
 590         struct ssb_device *dev;
 591
 592         dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
 593         if (WARN_ON(!dev))
 594                 return;
 595         /* This forces an update of the cached registers. */
 596         ssb_broadcast_value(dev, 0xFD8, 0);
 597 }
 598
 599 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 600                                    struct ssb_device *dev)
 601 {
 602         struct ssb_device *pdev = pc->dev;
 603         struct ssb_bus *bus;
 604         int err = 0;
 605         u32 tmp;
 606
 607         if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
 608                 /* This SSB device is not on a PCI host-bus. So the IRQs are
 609                  * not routed through the PCI core.
 610                  * So we must not enable routing through the PCI core. */
 611                 goto out;
 612         }
 613
 614         if (!pdev)
 615                 goto out;
 616         bus = pdev->bus;
 617
 618         might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
 619
 620         /* Enable interrupts for this device. */
 621         if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
 622                 u32 coremask;
 623
 624                 /* Calculate the "coremask" for the device. */
 625                 coremask = (1 << dev->core_index);
 626
 627                 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
 628                 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
 629                 if (err)
 630                         goto out;
 631                 tmp |= coremask << 8;
 632                 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
 633                 if (err)
 634                         goto out;
 635         } else {
 636                 u32 intvec;
 637
 638                 intvec = ssb_read32(pdev, SSB_INTVEC);
 639                 tmp = ssb_read32(dev, SSB_TPSFLAG);
 640                 tmp &= SSB_TPSFLAG_BPFLAG;
 641                 intvec |= (1 << tmp);
 642                 ssb_write32(pdev, SSB_INTVEC, intvec);
 643         }
 644
 645         /* Setup PCIcore operation. */
 646         if (pc->setup_done)
 647                 goto out;
 648         if (pdev->id.coreid == SSB_DEV_PCI) {
 649                 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 650                 tmp |= SSB_PCICORE_SBTOPCI_PREF;
 651                 tmp |= SSB_PCICORE_SBTOPCI_BURST;
 652                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 653
 654                 if (pdev->id.revision < 5) {
 655                         tmp = ssb_read32(pdev, SSB_IMCFGLO);
 656                         tmp &= ~SSB_IMCFGLO_SERTO;
 657                         tmp |= 2;
 658                         tmp &= ~SSB_IMCFGLO_REQTO;
 659                         tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
 660                         ssb_write32(pdev, SSB_IMCFGLO, tmp);
 661                         ssb_commit_settings(bus);
 662                 } else if (pdev->id.revision >= 11) {
 663                         tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 664                         tmp |= SSB_PCICORE_SBTOPCI_MRM;
 665                         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 666                 }
 667         } else {
 668                 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
 669                 //TODO: Better make defines for all these magic PCIE values.
 670                 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
 671                         /* TLP Workaround register. */
 672                         tmp = ssb_pcie_read(pc, 0x4);
 673                         tmp |= 0x8;
 674                         ssb_pcie_write(pc, 0x4, tmp);
 675                 }
 676                 if (pdev->id.revision == 0) {
 677                         const u8 serdes_rx_device = 0x1F;
 678
 679                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 680                                             2 /* Timer */, 0x8128);
 681                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 682                                             6 /* CDR */, 0x0100);
 683                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 684                                             7 /* CDR BW */, 0x1466);
 685                 } else if (pdev->id.revision == 1) {
 686                         /* DLLP Link Control register. */
 687                         tmp = ssb_pcie_read(pc, 0x100);
 688                         tmp |= 0x40;
 689                         ssb_pcie_write(pc, 0x100, tmp);
 690                 }
 691         }
 692         pc->setup_done = 1;
 693 out:
 694         return err;
 695 }
 696 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);