drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/acpi.h>
  17 #include "pci-quirks.h"
  18 #include "xhci-ext-caps.h"
  19
  20
  21 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  22 #define UHCI_USBCMD             0               /* command register */
  23 #define UHCI_USBINTR            4               /* interrupt register */
  24 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  25 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  26 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  27 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  28 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  29 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  30 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  31
  32 #define OHCI_CONTROL            0x04
  33 #define OHCI_CMDSTATUS          0x08
  34 #define OHCI_INTRSTATUS         0x0c
  35 #define OHCI_INTRENABLE         0x10
  36 #define OHCI_INTRDISABLE        0x14
  37 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  38 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  39 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  40 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  41
  42 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  43 #define EHCI_USBCMD             0               /* command register */
  44 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  45 #define EHCI_USBSTS             4               /* status register */
  46 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  47 #define EHCI_USBINTR            8               /* interrupt register */
  48 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  49 #define EHCI_USBLEGSUP          0               /* legacy support register */
  50 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  51 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  52 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  53 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  54
  55 /* AMD quirk use */
  56 #define AB_REG_BAR_LOW          0xe0
  57 #define AB_REG_BAR_HIGH         0xe1
  58 #define AB_REG_BAR_SB700        0xf0
  59 #define AB_INDX(addr)           ((addr) + 0x00)
  60 #define AB_DATA(addr)           ((addr) + 0x04)
  61 #define AX_INDXC                0x30
  62 #define AX_DATAC                0x34
  63
  64 #define NB_PCIE_INDX_ADDR       0xe0
  65 #define NB_PCIE_INDX_DATA       0xe4
  66 #define PCIE_P_CNTL             0x10040
  67 #define BIF_NB                  0x10002
  68 #define NB_PIF0_PWRDOWN_0       0x01100012
  69 #define NB_PIF0_PWRDOWN_1       0x01100013
  70
  71 static struct amd_chipset_info {
  72         struct pci_dev  *nb_dev;
  73         struct pci_dev  *smbus_dev;
  74         int nb_type;
  75         int sb_type;
  76         int isoc_reqs;
  77         int probe_count;
  78         int probe_result;
  79 } amd_chipset;
  80
  81 static DEFINE_SPINLOCK(amd_lock);
  82
  83 int usb_amd_find_chipset_info(void)
  84 {
  85         u8 rev = 0;
  86         unsigned long flags;
  87         struct amd_chipset_info info;
  88         int ret;
  89
  90         spin_lock_irqsave(&amd_lock, flags);
  91
  92         /* probe only once */
  93         if (amd_chipset.probe_count > 0) {
  94                 amd_chipset.probe_count++;
  95                 spin_unlock_irqrestore(&amd_lock, flags);
  96                 return amd_chipset.probe_result;
  97         }
  98         memset(&info, 0, sizeof(info));
  99         spin_unlock_irqrestore(&amd_lock, flags);
 100
 101         info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
 102         if (info.smbus_dev) {
 103                 rev = info.smbus_dev->revision;
 104                 if (rev >= 0x40)
 105                         info.sb_type = 1;
 106                 else if (rev >= 0x30 && rev <= 0x3b)
 107                         info.sb_type = 3;
 108         } else {
 109                 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 110                                                 0x780b, NULL);
 111                 if (!info.smbus_dev) {
 112                         ret = 0;
 113                         goto commit;
 114                 }
 115
 116                 rev = info.smbus_dev->revision;
 117                 if (rev >= 0x11 && rev <= 0x18)
 118                         info.sb_type = 2;
 119         }
 120
 121         if (info.sb_type == 0) {
 122                 if (info.smbus_dev) {
 123                         pci_dev_put(info.smbus_dev);
 124                         info.smbus_dev = NULL;
 125                 }
 126                 ret = 0;
 127                 goto commit;
 128         }
 129
 130         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
 131         if (info.nb_dev) {
 132                 info.nb_type = 1;
 133         } else {
 134                 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
 135                 if (info.nb_dev) {
 136                         info.nb_type = 2;
 137                 } else {
 138                         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 139                                                      0x9600, NULL);
 140                         if (info.nb_dev)
 141                                 info.nb_type = 3;
 142                 }
 143         }
 144
 145         ret = info.probe_result = 1;
 146         printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
 147
 148 commit:
 149
 150         spin_lock_irqsave(&amd_lock, flags);
 151         if (amd_chipset.probe_count > 0) {
 152                 /* race - someone else was faster - drop devices */
 153
 154                 /* Mark that we where here */
 155                 amd_chipset.probe_count++;
 156                 ret = amd_chipset.probe_result;
 157
 158                 spin_unlock_irqrestore(&amd_lock, flags);
 159
 160                 if (info.nb_dev)
 161                         pci_dev_put(info.nb_dev);
 162                 if (info.smbus_dev)
 163                         pci_dev_put(info.smbus_dev);
 164
 165         } else {
 166                 /* no race - commit the result */
 167                 info.probe_count++;
 168                 amd_chipset = info;
 169                 spin_unlock_irqrestore(&amd_lock, flags);
 170         }
 171
 172         return ret;
 173 }
 174 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
 175
 176 /*
 177  * The hardware normally enables the A-link power management feature, which
 178  * lets the system lower the power consumption in idle states.
 179  *
 180  * This USB quirk prevents the link going into that lower power state
 181  * during isochronous transfers.
 182  *
 183  * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
 184  * some AMD platforms may stutter or have breaks occasionally.
 185  */
 186 static void usb_amd_quirk_pll(int disable)
 187 {
 188         u32 addr, addr_low, addr_high, val;
 189         u32 bit = disable ? 0 : 1;
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&amd_lock, flags);
 193
 194         if (disable) {
 195                 amd_chipset.isoc_reqs++;
 196                 if (amd_chipset.isoc_reqs > 1) {
 197                         spin_unlock_irqrestore(&amd_lock, flags);
 198                         return;
 199                 }
 200         } else {
 201                 amd_chipset.isoc_reqs--;
 202                 if (amd_chipset.isoc_reqs > 0) {
 203                         spin_unlock_irqrestore(&amd_lock, flags);
 204                         return;
 205                 }
 206         }
 207
 208         if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
 209                 outb_p(AB_REG_BAR_LOW, 0xcd6);
 210                 addr_low = inb_p(0xcd7);
 211                 outb_p(AB_REG_BAR_HIGH, 0xcd6);
 212                 addr_high = inb_p(0xcd7);
 213                 addr = addr_high << 8 | addr_low;
 214
 215                 outl_p(0x30, AB_INDX(addr));
 216                 outl_p(0x40, AB_DATA(addr));
 217                 outl_p(0x34, AB_INDX(addr));
 218                 val = inl_p(AB_DATA(addr));
 219         } else if (amd_chipset.sb_type == 3) {
 220                 pci_read_config_dword(amd_chipset.smbus_dev,
 221                                         AB_REG_BAR_SB700, &addr);
 222                 outl(AX_INDXC, AB_INDX(addr));
 223                 outl(0x40, AB_DATA(addr));
 224                 outl(AX_DATAC, AB_INDX(addr));
 225                 val = inl(AB_DATA(addr));
 226         } else {
 227                 spin_unlock_irqrestore(&amd_lock, flags);
 228                 return;
 229         }
 230
 231         if (disable) {
 232                 val &= ~0x08;
 233                 val |= (1 << 4) | (1 << 9);
 234         } else {
 235                 val |= 0x08;
 236                 val &= ~((1 << 4) | (1 << 9));
 237         }
 238         outl_p(val, AB_DATA(addr));
 239
 240         if (!amd_chipset.nb_dev) {
 241                 spin_unlock_irqrestore(&amd_lock, flags);
 242                 return;
 243         }
 244
 245         if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
 246                 addr = PCIE_P_CNTL;
 247                 pci_write_config_dword(amd_chipset.nb_dev,
 248                                         NB_PCIE_INDX_ADDR, addr);
 249                 pci_read_config_dword(amd_chipset.nb_dev,
 250                                         NB_PCIE_INDX_DATA, &val);
 251
 252                 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
 253                 val |= bit | (bit << 3) | (bit << 12);
 254                 val |= ((!bit) << 4) | ((!bit) << 9);
 255                 pci_write_config_dword(amd_chipset.nb_dev,
 256                                         NB_PCIE_INDX_DATA, val);
 257
 258                 addr = BIF_NB;
 259                 pci_write_config_dword(amd_chipset.nb_dev,
 260                                         NB_PCIE_INDX_ADDR, addr);
 261                 pci_read_config_dword(amd_chipset.nb_dev,
 262                                         NB_PCIE_INDX_DATA, &val);
 263                 val &= ~(1 << 8);
 264                 val |= bit << 8;
 265
 266                 pci_write_config_dword(amd_chipset.nb_dev,
 267                                         NB_PCIE_INDX_DATA, val);
 268         } else if (amd_chipset.nb_type == 2) {
 269                 addr = NB_PIF0_PWRDOWN_0;
 270                 pci_write_config_dword(amd_chipset.nb_dev,
 271                                         NB_PCIE_INDX_ADDR, addr);
 272                 pci_read_config_dword(amd_chipset.nb_dev,
 273                                         NB_PCIE_INDX_DATA, &val);
 274                 if (disable)
 275                         val &= ~(0x3f << 7);
 276                 else
 277                         val |= 0x3f << 7;
 278
 279                 pci_write_config_dword(amd_chipset.nb_dev,
 280                                         NB_PCIE_INDX_DATA, val);
 281
 282                 addr = NB_PIF0_PWRDOWN_1;
 283                 pci_write_config_dword(amd_chipset.nb_dev,
 284                                         NB_PCIE_INDX_ADDR, addr);
 285                 pci_read_config_dword(amd_chipset.nb_dev,
 286                                         NB_PCIE_INDX_DATA, &val);
 287                 if (disable)
 288                         val &= ~(0x3f << 7);
 289                 else
 290                         val |= 0x3f << 7;
 291
 292                 pci_write_config_dword(amd_chipset.nb_dev,
 293                                         NB_PCIE_INDX_DATA, val);
 294         }
 295
 296         spin_unlock_irqrestore(&amd_lock, flags);
 297         return;
 298 }
 299
 300 void usb_amd_quirk_pll_disable(void)
 301 {
 302         usb_amd_quirk_pll(1);
 303 }
 304 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
 305
 306 void usb_amd_quirk_pll_enable(void)
 307 {
 308         usb_amd_quirk_pll(0);
 309 }
 310 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
 311
 312 void usb_amd_dev_put(void)
 313 {
 314         struct pci_dev *nb, *smbus;
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&amd_lock, flags);
 318
 319         amd_chipset.probe_count--;
 320         if (amd_chipset.probe_count > 0) {
 321                 spin_unlock_irqrestore(&amd_lock, flags);
 322                 return;
 323         }
 324
 325         /* save them to pci_dev_put outside of spinlock */
 326         nb    = amd_chipset.nb_dev;
 327         smbus = amd_chipset.smbus_dev;
 328
 329         amd_chipset.nb_dev = NULL;
 330         amd_chipset.smbus_dev = NULL;
 331         amd_chipset.nb_type = 0;
 332         amd_chipset.sb_type = 0;
 333         amd_chipset.isoc_reqs = 0;
 334         amd_chipset.probe_result = 0;
 335
 336         spin_unlock_irqrestore(&amd_lock, flags);
 337
 338         if (nb)
 339                 pci_dev_put(nb);
 340         if (smbus)
 341                 pci_dev_put(smbus);
 342 }
 343 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
 344
 345 /*
 346  * Make sure the controller is completely inactive, unable to
 347  * generate interrupts or do DMA.
 348  */
 349 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
 350 {
 351         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
 352          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
 353          */
 354         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
 355
 356         /* Reset the HC - this will force us to get a
 357          * new notification of any already connected
 358          * ports due to the virtual disconnect that it
 359          * implies.
 360          */
 361         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
 362         mb();
 363         udelay(5);
 364         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
 365                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
 366
 367         /* Just to be safe, disable interrupt requests and
 368          * make sure the controller is stopped.
 369          */
 370         outw(0, base + UHCI_USBINTR);
 371         outw(0, base + UHCI_USBCMD);
 372 }
 373 EXPORT_SYMBOL_GPL(uhci_reset_hc);
 374
 375 /*
 376  * Initialize a controller that was newly discovered or has just been
 377  * resumed.  In either case we can't be sure of its previous state.
 378  *
 379  * Returns: 1 if the controller was reset, 0 otherwise.
 380  */
 381 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
 382 {
 383         u16 legsup;
 384         unsigned int cmd, intr;
 385
 386         /*
 387          * When restarting a suspended controller, we expect all the
 388          * settings to be the same as we left them:
 389          *
 390          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 391          *      Controller is stopped and configured with EGSM set;
 392          *      No interrupts enabled except possibly Resume Detect.
 393          *
 394          * If any of these conditions are violated we do a complete reset.
 395          */
 396         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 397         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 398                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 399                                 __func__, legsup);
 400                 goto reset_needed;
 401         }
 402
 403         cmd = inw(base + UHCI_USBCMD);
 404         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 405                         !(cmd & UHCI_USBCMD_EGSM)) {
 406                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 407                                 __func__, cmd);
 408                 goto reset_needed;
 409         }
 410
 411         intr = inw(base + UHCI_USBINTR);
 412         if (intr & (~UHCI_USBINTR_RESUME)) {
 413                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 414                                 __func__, intr);
 415                 goto reset_needed;
 416         }
 417         return 0;
 418
 419 reset_needed:
 420         dev_dbg(&pdev->dev, "Performing full reset\n");
 421         uhci_reset_hc(pdev, base);
 422         return 1;
 423 }
 424 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 425
 426 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 427 {
 428         u16 cmd;
 429         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 430 }
 431
 432 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 433 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 434
 435 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 436 {
 437         unsigned long base = 0;
 438         int i;
 439
 440         if (!pio_enabled(pdev))
 441                 return;
 442
 443         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 444                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 445                         base = pci_resource_start(pdev, i);
 446                         break;
 447                 }
 448
 449         if (base)
 450                 uhci_check_and_reset_hc(pdev, base);
 451 }
 452
 453 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 454 {
 455         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 456 }
 457
 458 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 459 {
 460         void __iomem *base;
 461         u32 control;
 462
 463         if (!mmio_resource_enabled(pdev, 0))
 464                 return;
 465
 466         base = pci_ioremap_bar(pdev, 0);
 467         if (base == NULL)
 468                 return;
 469
 470         control = readl(base + OHCI_CONTROL);
 471
 472 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 473 #ifdef __hppa__
 474 #define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
 475 #else
 476 #define OHCI_CTRL_MASK          OHCI_CTRL_RWC
 477
 478         if (control & OHCI_CTRL_IR) {
 479                 int wait_time = 500; /* arbitrary; 5 seconds */
 480                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 481                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 482                 while (wait_time > 0 &&
 483                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 484                         wait_time -= 10;
 485                         msleep(10);
 486                 }
 487                 if (wait_time <= 0)
 488                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 489                                         " (BIOS bug?) %08x\n",
 490                                         readl(base + OHCI_CONTROL));
 491         }
 492 #endif
 493
 494         /* reset controller, preserving RWC (and possibly IR) */
 495         writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
 496
 497         /*
 498          * disable interrupts
 499          */
 500         writel(~(u32)0, base + OHCI_INTRDISABLE);
 501         writel(~(u32)0, base + OHCI_INTRSTATUS);
 502
 503         iounmap(base);
 504 }
 505
 506 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 507 {
 508         int wait_time, delta;
 509         void __iomem *base, *op_reg_base;
 510         u32     hcc_params, val;
 511         u8      offset, cap_length;
 512         int     count = 256/4;
 513         int     tried_handoff = 0;
 514
 515         if (!mmio_resource_enabled(pdev, 0))
 516                 return;
 517
 518         base = pci_ioremap_bar(pdev, 0);
 519         if (base == NULL)
 520                 return;
 521
 522         cap_length = readb(base);
 523         op_reg_base = base + cap_length;
 524
 525         /* EHCI 0.96 and later may have "extended capabilities"
 526          * spec section 5.1 explains the bios handoff, e.g. for
 527          * booting from USB disk or using a usb keyboard
 528          */
 529         hcc_params = readl(base + EHCI_HCC_PARAMS);
 530         offset = (hcc_params >> 8) & 0xff;
 531         while (offset && --count) {
 532                 u32             cap;
 533                 int             msec;
 534
 535                 pci_read_config_dword(pdev, offset, &cap);
 536                 switch (cap & 0xff) {
 537                 case 1:                 /* BIOS/SMM/... handoff support */
 538                         if ((cap & EHCI_USBLEGSUP_BIOS)) {
 539                                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 540
 541 #if 0
 542 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 543  * but that seems dubious in general (the BIOS left it off intentionally)
 544  * and is known to prevent some systems from booting.  so we won't do this
 545  * unless maybe we can determine when we're on a system that needs SMI forced.
 546  */
 547                                 /* BIOS workaround (?): be sure the
 548                                  * pre-Linux code receives the SMI
 549                                  */
 550                                 pci_read_config_dword(pdev,
 551                                                 offset + EHCI_USBLEGCTLSTS,
 552                                                 &val);
 553                                 pci_write_config_dword(pdev,
 554                                                 offset + EHCI_USBLEGCTLSTS,
 555                                                 val | EHCI_USBLEGCTLSTS_SOOE);
 556 #endif
 557
 558                                 /* some systems get upset if this semaphore is
 559                                  * set for any other reason than forcing a BIOS
 560                                  * handoff..
 561                                  */
 562                                 pci_write_config_byte(pdev, offset + 3, 1);
 563                         }
 564
 565                         /* if boot firmware now owns EHCI, spin till
 566                          * it hands it over.
 567                          */
 568                         msec = 1000;
 569                         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 570                                 tried_handoff = 1;
 571                                 msleep(10);
 572                                 msec -= 10;
 573                                 pci_read_config_dword(pdev, offset, &cap);
 574                         }
 575
 576                         if (cap & EHCI_USBLEGSUP_BIOS) {
 577                                 /* well, possibly buggy BIOS... try to shut
 578                                  * it down, and hope nothing goes too wrong
 579                                  */
 580                                 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 581                                                 " (BIOS bug?) %08x\n", cap);
 582                                 pci_write_config_byte(pdev, offset + 2, 0);
 583                         }
 584
 585                         /* just in case, always disable EHCI SMIs */
 586                         pci_write_config_dword(pdev,
 587                                         offset + EHCI_USBLEGCTLSTS,
 588                                         0);
 589
 590                         /* If the BIOS ever owned the controller then we
 591                          * can't expect any power sessions to remain intact.
 592                          */
 593                         if (tried_handoff)
 594                                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 595                         break;
 596                 case 0:                 /* illegal reserved capability */
 597                         cap = 0;
 598                         /* FALLTHROUGH */
 599                 default:
 600                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 601                                         "%02x\n", cap & 0xff);
 602                         break;
 603                 }
 604                 offset = (cap >> 8) & 0xff;
 605         }
 606         if (!count)
 607                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 608
 609         /*
 610          * halt EHCI & disable its interrupts in any case
 611          */
 612         val = readl(op_reg_base + EHCI_USBSTS);
 613         if ((val & EHCI_USBSTS_HALTED) == 0) {
 614                 val = readl(op_reg_base + EHCI_USBCMD);
 615                 val &= ~EHCI_USBCMD_RUN;
 616                 writel(val, op_reg_base + EHCI_USBCMD);
 617
 618                 wait_time = 2000;
 619                 delta = 100;
 620                 do {
 621                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 622                         udelay(delta);
 623                         wait_time -= delta;
 624                         val = readl(op_reg_base + EHCI_USBSTS);
 625                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 626                                 break;
 627                         }
 628                 } while (wait_time > 0);
 629         }
 630         writel(0, op_reg_base + EHCI_USBINTR);
 631         writel(0x3f, op_reg_base + EHCI_USBSTS);
 632
 633         iounmap(base);
 634 }
 635
 636 /*
 637  * handshake - spin reading a register until handshake completes
 638  * @ptr: address of hc register to be read
 639  * @mask: bits to look at in result of read
 640  * @done: value of those bits when handshake succeeds
 641  * @wait_usec: timeout in microseconds
 642  * @delay_usec: delay in microseconds to wait between polling
 643  *
 644  * Polls a register every delay_usec microseconds.
 645  * Returns 0 when the mask bits have the value done.
 646  * Returns -ETIMEDOUT if this condition is not true after
 647  * wait_usec microseconds have passed.
 648  */
 649 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 650                 int wait_usec, int delay_usec)
 651 {
 652         u32     result;
 653
 654         do {
 655                 result = readl(ptr);
 656                 result &= mask;
 657                 if (result == done)
 658                         return 0;
 659                 udelay(delay_usec);
 660                 wait_usec -= delay_usec;
 661         } while (wait_usec > 0);
 662         return -ETIMEDOUT;
 663 }
 664
 665 /**
 666  * PCI Quirks for xHCI.
 667  *
 668  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 669  * It signals to the BIOS that the OS wants control of the host controller,
 670  * and then waits 5 seconds for the BIOS to hand over control.
 671  * If we timeout, assume the BIOS is broken and take control anyway.
 672  */
 673 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 674 {
 675         void __iomem *base;
 676         int ext_cap_offset;
 677         void __iomem *op_reg_base;
 678         u32 val;
 679         int timeout;
 680
 681         if (!mmio_resource_enabled(pdev, 0))
 682                 return;
 683
 684         base = ioremap_nocache(pci_resource_start(pdev, 0),
 685                                 pci_resource_len(pdev, 0));
 686         if (base == NULL)
 687                 return;
 688
 689         /*
 690          * Find the Legacy Support Capability register -
 691          * this is optional for xHCI host controllers.
 692          */
 693         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 694         do {
 695                 if (!ext_cap_offset)
 696                         /* We've reached the end of the extended capabilities */
 697                         goto hc_init;
 698                 val = readl(base + ext_cap_offset);
 699                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 700                         break;
 701                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 702         } while (1);
 703
 704         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 705         if (val & XHCI_HC_BIOS_OWNED) {
 706                 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
 707
 708                 /* Wait for 5 seconds with 10 microsecond polling interval */
 709                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 710                                 0, 5000, 10);
 711
 712                 /* Assume a buggy BIOS and take HC ownership anyway */
 713                 if (timeout) {
 714                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 715                                         " (BIOS bug ?) %08x\n", val);
 716                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 717                 }
 718         }
 719
 720         /* Disable any BIOS SMIs */
 721         writel(XHCI_LEGACY_DISABLE_SMI,
 722                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 723
 724 hc_init:
 725         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 726
 727         /* Wait for the host controller to be ready before writing any
 728          * operational or runtime registers.  Wait 5 seconds and no more.
 729          */
 730         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 731                         5000, 10);
 732         /* Assume a buggy HC and start HC initialization anyway */
 733         if (timeout) {
 734                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 735                 dev_warn(&pdev->dev,
 736                                 "xHCI HW not ready after 5 sec (HC bug?) "
 737                                 "status = 0x%x\n", val);
 738         }
 739
 740         /* Send the halt and disable interrupts command */
 741         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 742         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 743         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 744
 745         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 746         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 747                         XHCI_MAX_HALT_USEC, 125);
 748         if (timeout) {
 749                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 750                 dev_warn(&pdev->dev,
 751                                 "xHCI HW did not halt within %d usec "
 752                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 753         }
 754
 755         iounmap(base);
 756 }
 757
 758 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 759 {
 760         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 761                 quirk_usb_handoff_uhci(pdev);
 762         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 763                 quirk_usb_handoff_ohci(pdev);
 764         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 765                 quirk_usb_disable_ehci(pdev);
 766         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 767                 quirk_usb_handoff_xhci(pdev);
 768 }
 769 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);