drivers/usb/musb/blackfin.c

   1 /*
   2  * MUSB OTG controller driver for Blackfin Processors
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/list.h>
  16 #include <linux/gpio.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <asm/cacheflush.h>
  22
  23 #include "musb_core.h"
  24 #include "musbhsdma.h"
  25 #include "blackfin.h"
  26
  27 struct bfin_glue {
  28         struct device           *dev;
  29         struct platform_device  *musb;
  30 };
  31 #define glue_to_musb(g)         platform_get_drvdata(g->musb)
  32
  33 /*
  34  * Load an endpoint's FIFO
  35  */
  36 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  37 {
  38         void __iomem *fifo = hw_ep->fifo;
  39         void __iomem *epio = hw_ep->regs;
  40         u8 epnum = hw_ep->epnum;
  41
  42         prefetch((u8 *)src);
  43
  44         musb_writew(epio, MUSB_TXCOUNT, len);
  45
  46         DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  47                         hw_ep->epnum, fifo, len, src, epio);
  48
  49         dump_fifo_data(src, len);
  50
  51         if (!ANOMALY_05000380 && epnum != 0) {
  52                 u16 dma_reg;
  53
  54                 flush_dcache_range((unsigned long)src,
  55                         (unsigned long)(src + len));
  56
  57                 /* Setup DMA address register */
  58                 dma_reg = (u32)src;
  59                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  60                 SSYNC();
  61
  62                 dma_reg = (u32)src >> 16;
  63                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  64                 SSYNC();
  65
  66                 /* Setup DMA count register */
  67                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  68                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  69                 SSYNC();
  70
  71                 /* Enable the DMA */
  72                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  73                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  74                 SSYNC();
  75
  76                 /* Wait for compelete */
  77                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  78                         cpu_relax();
  79
  80                 /* acknowledge dma interrupt */
  81                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  82                 SSYNC();
  83
  84                 /* Reset DMA */
  85                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  86                 SSYNC();
  87         } else {
  88                 SSYNC();
  89
  90                 if (unlikely((unsigned long)src & 0x01))
  91                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
  92                 else
  93                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
  94         }
  95 }
  96 /*
  97  * Unload an endpoint's FIFO
  98  */
  99 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 100 {
 101         void __iomem *fifo = hw_ep->fifo;
 102         u8 epnum = hw_ep->epnum;
 103
 104         if (ANOMALY_05000467 && epnum != 0) {
 105                 u16 dma_reg;
 106
 107                 invalidate_dcache_range((unsigned long)dst,
 108                         (unsigned long)(dst + len));
 109
 110                 /* Setup DMA address register */
 111                 dma_reg = (u32)dst;
 112                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 113                 SSYNC();
 114
 115                 dma_reg = (u32)dst >> 16;
 116                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 117                 SSYNC();
 118
 119                 /* Setup DMA count register */
 120                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 121                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 122                 SSYNC();
 123
 124                 /* Enable the DMA */
 125                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 126                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 127                 SSYNC();
 128
 129                 /* Wait for compelete */
 130                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 131                         cpu_relax();
 132
 133                 /* acknowledge dma interrupt */
 134                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 135                 SSYNC();
 136
 137                 /* Reset DMA */
 138                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 139                 SSYNC();
 140         } else {
 141                 SSYNC();
 142                 /* Read the last byte of packet with odd size from address fifo + 4
 143                  * to trigger 1 byte access to EP0 FIFO.
 144                  */
 145                 if (len == 1)
 146                         *dst = (u8)inw((unsigned long)fifo + 4);
 147                 else {
 148                         if (unlikely((unsigned long)dst & 0x01))
 149                                 insw_8((unsigned long)fifo, dst, len >> 1);
 150                         else
 151                                 insw((unsigned long)fifo, dst, len >> 1);
 152
 153                         if (len & 0x01)
 154                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 155                 }
 156         }
 157         DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
 158                         'R', hw_ep->epnum, fifo, len, dst);
 159
 160         dump_fifo_data(dst, len);
 161 }
 162
 163 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 164 {
 165         unsigned long   flags;
 166         irqreturn_t     retval = IRQ_NONE;
 167         struct musb     *musb = __hci;
 168
 169         spin_lock_irqsave(&musb->lock, flags);
 170
 171         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 172         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 173         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 174
 175         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 176                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 177                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 178                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 179                 retval = musb_interrupt(musb);
 180         }
 181
 182         /* Start sampling ID pin, when plug is removed from MUSB */
 183         if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
 184                 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
 185                 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
 186                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 187                 musb->a_wait_bcon = TIMER_DELAY;
 188         }
 189
 190         spin_unlock_irqrestore(&musb->lock, flags);
 191
 192         return retval;
 193 }
 194
 195 static void musb_conn_timer_handler(unsigned long _musb)
 196 {
 197         struct musb *musb = (void *)_musb;
 198         unsigned long flags;
 199         u16 val;
 200         static u8 toggle;
 201
 202         spin_lock_irqsave(&musb->lock, flags);
 203         switch (musb->xceiv->state) {
 204         case OTG_STATE_A_IDLE:
 205         case OTG_STATE_A_WAIT_BCON:
 206                 /* Start a new session */
 207                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 208                 val &= ~MUSB_DEVCTL_SESSION;
 209                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 210                 val |= MUSB_DEVCTL_SESSION;
 211                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 212                 /* Check if musb is host or peripheral. */
 213                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 214
 215                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 216                         gpio_set_value(musb->config->gpio_vrsel, 1);
 217                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 218                 } else {
 219                         gpio_set_value(musb->config->gpio_vrsel, 0);
 220                         /* Ignore VBUSERROR and SUSPEND IRQ */
 221                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 222                         val &= ~MUSB_INTR_VBUSERROR;
 223                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 224
 225                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 226                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 227                         if (is_otg_enabled(musb))
 228                                 musb->xceiv->state = OTG_STATE_B_IDLE;
 229                         else
 230                                 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
 231                 }
 232                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 233                 break;
 234         case OTG_STATE_B_IDLE:
 235
 236                 if (!is_peripheral_enabled(musb))
 237                         break;
 238                 /* Start a new session.  It seems that MUSB needs taking
 239                  * some time to recognize the type of the plug inserted?
 240                  */
 241                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 242                 val |= MUSB_DEVCTL_SESSION;
 243                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 244                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 245
 246                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 247                         gpio_set_value(musb->config->gpio_vrsel, 1);
 248                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 249                 } else {
 250                         gpio_set_value(musb->config->gpio_vrsel, 0);
 251
 252                         /* Ignore VBUSERROR and SUSPEND IRQ */
 253                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 254                         val &= ~MUSB_INTR_VBUSERROR;
 255                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 256
 257                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 258                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 259
 260                         /* Toggle the Soft Conn bit, so that we can response to
 261                          * the inserting of either A-plug or B-plug.
 262                          */
 263                         if (toggle) {
 264                                 val = musb_readb(musb->mregs, MUSB_POWER);
 265                                 val &= ~MUSB_POWER_SOFTCONN;
 266                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 267                                 toggle = 0;
 268                         } else {
 269                                 val = musb_readb(musb->mregs, MUSB_POWER);
 270                                 val |= MUSB_POWER_SOFTCONN;
 271                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 272                                 toggle = 1;
 273                         }
 274                         /* The delay time is set to 1/4 second by default,
 275                          * shortening it, if accelerating A-plug detection
 276                          * is needed in OTG mode.
 277                          */
 278                         mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
 279                 }
 280                 break;
 281         default:
 282                 DBG(1, "%s state not handled\n", otg_state_string(musb));
 283                 break;
 284         }
 285         spin_unlock_irqrestore(&musb->lock, flags);
 286
 287         DBG(4, "state is %s\n", otg_state_string(musb));
 288 }
 289
 290 static void bfin_musb_enable(struct musb *musb)
 291 {
 292         if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
 293                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 294                 musb->a_wait_bcon = TIMER_DELAY;
 295         }
 296 }
 297
 298 static void bfin_musb_disable(struct musb *musb)
 299 {
 300 }
 301
 302 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
 303 {
 304         int value = musb->config->gpio_vrsel_active;
 305         if (!is_on)
 306                 value = !value;
 307         gpio_set_value(musb->config->gpio_vrsel, value);
 308
 309         DBG(1, "VBUS %s, devctl %02x "
 310                 /* otg %3x conf %08x prcm %08x */ "\n",
 311                 otg_state_string(musb),
 312                 musb_readb(musb->mregs, MUSB_DEVCTL));
 313 }
 314
 315 static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
 316 {
 317         return 0;
 318 }
 319
 320 static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
 321 {
 322         if (!is_otg_enabled(musb) && is_host_enabled(musb))
 323                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 324 }
 325
 326 static int bfin_musb_vbus_status(struct musb *musb)
 327 {
 328         return 0;
 329 }
 330
 331 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
 332 {
 333         return -EIO;
 334 }
 335
 336 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
 337                                 u16 packet_sz, u8 *mode,
 338                                 dma_addr_t *dma_addr, u32 *len)
 339 {
 340         struct musb_dma_channel *musb_channel = channel->private_data;
 341
 342         /*
 343          * Anomaly 05000450 might cause data corruption when using DMA
 344          * MODE 1 transmits with short packet.  So to work around this,
 345          * we truncate all MODE 1 transfers down to a multiple of the
 346          * max packet size, and then do the last short packet transfer
 347          * (if there is any) using MODE 0.
 348          */
 349         if (ANOMALY_05000450) {
 350                 if (musb_channel->transmit && *mode == 1)
 351                         *len = *len - (*len % packet_sz);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void bfin_musb_reg_init(struct musb *musb)
 358 {
 359         if (ANOMALY_05000346) {
 360                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 361                 SSYNC();
 362         }
 363
 364         if (ANOMALY_05000347) {
 365                 bfin_write_USB_APHY_CNTRL(0x0);
 366                 SSYNC();
 367         }
 368
 369         /* Configure PLL oscillator register */
 370         bfin_write_USB_PLLOSC_CTRL(0x3080 |
 371                         ((480/musb->config->clkin) << 1));
 372         SSYNC();
 373
 374         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 375         SSYNC();
 376
 377         bfin_write_USB_EP_NI0_RXMAXP(64);
 378         SSYNC();
 379
 380         bfin_write_USB_EP_NI0_TXMAXP(64);
 381         SSYNC();
 382
 383         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 384         bfin_write_USB_GLOBINTR(0x7);
 385         SSYNC();
 386
 387         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 388                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 389                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 390                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 391                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 392         SSYNC();
 393 }
 394
 395 static int bfin_musb_init(struct musb *musb)
 396 {
 397
 398         /*
 399          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 400          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 401          * be low for DEVICE mode and high for HOST mode. We set it high
 402          * here because we are in host mode
 403          */
 404
 405         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 406                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
 407                         musb->config->gpio_vrsel);
 408                 return -ENODEV;
 409         }
 410         gpio_direction_output(musb->config->gpio_vrsel, 0);
 411
 412         usb_nop_xceiv_register();
 413         musb->xceiv = otg_get_transceiver();
 414         if (!musb->xceiv) {
 415                 gpio_free(musb->config->gpio_vrsel);
 416                 return -ENODEV;
 417         }
 418
 419         bfin_musb_reg_init(musb);
 420
 421         if (is_host_enabled(musb)) {
 422                 setup_timer(&musb_conn_timer,
 423                         musb_conn_timer_handler, (unsigned long) musb);
 424         }
 425         if (is_peripheral_enabled(musb))
 426                 musb->xceiv->set_power = bfin_musb_set_power;
 427
 428         musb->isr = blackfin_interrupt;
 429         musb->double_buffer_not_ok = true;
 430
 431         return 0;
 432 }
 433
 434 static int bfin_musb_exit(struct musb *musb)
 435 {
 436         gpio_free(musb->config->gpio_vrsel);
 437
 438         otg_put_transceiver(musb->xceiv);
 439         usb_nop_xceiv_unregister();
 440         return 0;
 441 }
 442
 443 static const struct musb_platform_ops bfin_ops = {
 444         .init           = bfin_musb_init,
 445         .exit           = bfin_musb_exit,
 446
 447         .enable         = bfin_musb_enable,
 448         .disable        = bfin_musb_disable,
 449
 450         .set_mode       = bfin_musb_set_mode,
 451         .try_idle       = bfin_musb_try_idle,
 452
 453         .vbus_status    = bfin_musb_vbus_status,
 454         .set_vbus       = bfin_musb_set_vbus,
 455
 456         .adjust_channel_params = bfin_musb_adjust_channel_params,
 457 };
 458
 459 static u64 bfin_dmamask = DMA_BIT_MASK(32);
 460
 461 static int __init bfin_probe(struct platform_device *pdev)
 462 {
 463         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
 464         struct platform_device          *musb;
 465         struct bfin_glue                *glue;
 466
 467         int                             ret = -ENOMEM;
 468
 469         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 470         if (!glue) {
 471                 dev_err(&pdev->dev, "failed to allocate glue context\n");
 472                 goto err0;
 473         }
 474
 475         musb = platform_device_alloc("musb-hdrc", -1);
 476         if (!musb) {
 477                 dev_err(&pdev->dev, "failed to allocate musb device\n");
 478                 goto err1;
 479         }
 480
 481         musb->dev.parent                = &pdev->dev;
 482         musb->dev.dma_mask              = &bfin_dmamask;
 483         musb->dev.coherent_dma_mask     = bfin_dmamask;
 484
 485         glue->dev                       = &pdev->dev;
 486         glue->musb                      = musb;
 487
 488         pdata->platform_ops             = &bfin_ops;
 489
 490         platform_set_drvdata(pdev, glue);
 491
 492         ret = platform_device_add_resources(musb, pdev->resource,
 493                         pdev->num_resources);
 494         if (ret) {
 495                 dev_err(&pdev->dev, "failed to add resources\n");
 496                 goto err2;
 497         }
 498
 499         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 500         if (ret) {
 501                 dev_err(&pdev->dev, "failed to add platform_data\n");
 502                 goto err2;
 503         }
 504
 505         ret = platform_device_add(musb);
 506         if (ret) {
 507                 dev_err(&pdev->dev, "failed to register musb device\n");
 508                 goto err2;
 509         }
 510
 511         return 0;
 512
 513 err2:
 514         platform_device_put(musb);
 515
 516 err1:
 517         kfree(glue);
 518
 519 err0:
 520         return ret;
 521 }
 522
 523 static int __exit bfin_remove(struct platform_device *pdev)
 524 {
 525         struct bfin_glue                *glue = platform_get_drvdata(pdev);
 526
 527         platform_device_del(glue->musb);
 528         platform_device_put(glue->musb);
 529         kfree(glue);
 530
 531         return 0;
 532 }
 533
 534 #ifdef CONFIG_PM
 535 static int bfin_suspend(struct device *dev)
 536 {
 537         struct bfin_glue        *glue = dev_get_drvdata(dev);
 538         struct musb             *musb = glue_to_musb(glue);
 539
 540         if (is_host_active(musb))
 541                 /*
 542                  * During hibernate gpio_vrsel will change from high to low
 543                  * low which will generate wakeup event resume the system
 544                  * immediately.  Set it to 0 before hibernate to avoid this
 545                  * wakeup event.
 546                  */
 547                 gpio_set_value(musb->config->gpio_vrsel, 0);
 548
 549         return 0;
 550 }
 551
 552 static int bfin_resume(struct device *dev)
 553 {
 554         struct bfin_glue        *glue = dev_get_drvdata(dev);
 555         struct musb             *musb = glue_to_musb(glue);
 556
 557         bfin_musb_reg_init(musb);
 558
 559         return 0;
 560 }
 561
 562 static struct dev_pm_ops bfin_pm_ops = {
 563         .suspend        = bfin_suspend,
 564         .resume         = bfin_resume,
 565 };
 566
 567 #define DEV_PM_OPS      &bfin_pm_ops
 568 #else
 569 #define DEV_PM_OPS      NULL
 570 #endif
 571
 572 static struct platform_driver bfin_driver = {
 573         .remove         = __exit_p(bfin_remove),
 574         .driver         = {
 575                 .name   = "musb-blackfin",
 576                 .pm     = DEV_PM_OPS,
 577         },
 578 };
 579
 580 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
 581 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
 582 MODULE_LICENSE("GPL v2");
 583
 584 static int __init bfin_init(void)
 585 {
 586         return platform_driver_probe(&bfin_driver, bfin_probe);
 587 }
 588 subsys_initcall(bfin_init);
 589
 590 static void __exit bfin_exit(void)
 591 {
 592         platform_driver_unregister(&bfin_driver);
 593 }
 594 module_exit(bfin_exit);